1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2002 Benno Rice. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 21 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 22 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 23 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 24 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 25 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/conf.h> 34 #include <sys/kernel.h> 35 #include <sys/ktr.h> 36 #include <sys/proc.h> 37 #include <sys/rman.h> 38 #include <sys/sched.h> 39 #include <sys/smp.h> 40 41 #include <machine/bus.h> 42 #include <machine/intr_machdep.h> 43 #include <machine/md_var.h> 44 #include <machine/pio.h> 45 #include <machine/resource.h> 46 47 #include <vm/vm.h> 48 #include <vm/pmap.h> 49 50 #include <machine/openpicreg.h> 51 #include <machine/openpicvar.h> 52 53 #include "pic_if.h" 54 55 #define OPENPIC_NIPIS 4 56 57 /* 58 * Local routines 59 */ 60 static int openpic_intr(void *arg); 61 62 static __inline uint32_t 63 openpic_read(struct openpic_softc *sc, u_int reg) 64 { 65 return (bus_space_read_4(sc->sc_bt, sc->sc_bh, reg)); 66 } 67 68 static __inline void 69 openpic_write(struct openpic_softc *sc, u_int reg, uint32_t val) 70 { 71 bus_space_write_4(sc->sc_bt, sc->sc_bh, reg, val); 72 } 73 74 int 75 openpic_common_attach(device_t dev, uint32_t node) 76 { 77 struct openpic_softc *sc; 78 u_int cpu, ipi, irq; 79 u_int32_t x; 80 81 sc = device_get_softc(dev); 82 sc->sc_dev = dev; 83 84 sc->sc_rid = 0; 85 sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid, 86 RF_ACTIVE); 87 88 if (sc->sc_memr == NULL) { 89 device_printf(dev, "Could not alloc mem resource!\n"); 90 return (ENXIO); 91 } 92 93 sc->sc_bt = rman_get_bustag(sc->sc_memr); 94 sc->sc_bh = rman_get_bushandle(sc->sc_memr); 95 96 /* Reset the PIC */ 97 x = openpic_read(sc, OPENPIC_CONFIG); 98 x |= OPENPIC_CONFIG_RESET; 99 openpic_write(sc, OPENPIC_CONFIG, x); 100 101 while (openpic_read(sc, OPENPIC_CONFIG) & OPENPIC_CONFIG_RESET) { 102 powerpc_sync(); 103 DELAY(100); 104 } 105 106 /* Check if this is a cascaded PIC */ 107 sc->sc_irq = 0; 108 sc->sc_intr = NULL; 109 do { 110 struct resource_list *rl; 111 112 rl = BUS_GET_RESOURCE_LIST(device_get_parent(dev), dev); 113 if (rl == NULL) 114 break; 115 if (resource_list_find(rl, SYS_RES_IRQ, 0) == NULL) 116 break; 117 118 sc->sc_intr = bus_alloc_resource_any(dev, SYS_RES_IRQ, 119 &sc->sc_irq, RF_ACTIVE); 120 121 /* XXX Cascaded PICs pass NULL trapframes! */ 122 bus_setup_intr(dev, sc->sc_intr, INTR_TYPE_MISC | INTR_MPSAFE, 123 openpic_intr, NULL, dev, &sc->sc_icookie); 124 } while (0); 125 126 /* Reset the PIC */ 127 x = openpic_read(sc, OPENPIC_CONFIG); 128 x |= OPENPIC_CONFIG_RESET; 129 openpic_write(sc, OPENPIC_CONFIG, x); 130 131 while (openpic_read(sc, OPENPIC_CONFIG) & OPENPIC_CONFIG_RESET) { 132 powerpc_sync(); 133 DELAY(100); 134 } 135 136 x = openpic_read(sc, OPENPIC_FEATURE); 137 switch (x & OPENPIC_FEATURE_VERSION_MASK) { 138 case 1: 139 sc->sc_version = "1.0"; 140 break; 141 case 2: 142 sc->sc_version = "1.2"; 143 break; 144 case 3: 145 sc->sc_version = "1.3"; 146 break; 147 default: 148 sc->sc_version = "unknown"; 149 break; 150 } 151 152 sc->sc_ncpu = ((x & OPENPIC_FEATURE_LAST_CPU_MASK) >> 153 OPENPIC_FEATURE_LAST_CPU_SHIFT) + 1; 154 sc->sc_nirq = ((x & OPENPIC_FEATURE_LAST_IRQ_MASK) >> 155 OPENPIC_FEATURE_LAST_IRQ_SHIFT) + 1; 156 157 /* 158 * PSIM seems to report 1 too many IRQs and CPUs 159 */ 160 if (sc->sc_psim) { 161 sc->sc_nirq--; 162 sc->sc_ncpu--; 163 } 164 165 if (bootverbose) 166 device_printf(dev, 167 "Version %s, supports %d CPUs and %d irqs\n", 168 sc->sc_version, sc->sc_ncpu, sc->sc_nirq); 169 170 /* 171 * Allow more IRQs than what the PIC says it handles. Some Freescale PICs 172 * have MSIs that show up above the PIC's self-described 196 IRQs 173 * (P5020 starts MSI IRQs at 224). 174 */ 175 if (sc->sc_quirks & OPENPIC_QUIRK_HIDDEN_IRQS) 176 sc->sc_nirq = OPENPIC_IRQMAX - OPENPIC_NIPIS; 177 178 for (cpu = 0; cpu < sc->sc_ncpu; cpu++) 179 openpic_write(sc, OPENPIC_PCPU_TPR(cpu), 15); 180 181 /* Reset and disable all interrupts. */ 182 for (irq = 0; irq < sc->sc_nirq; irq++) { 183 x = irq; /* irq == vector. */ 184 x |= OPENPIC_IMASK; 185 x |= OPENPIC_POLARITY_NEGATIVE; 186 x |= OPENPIC_SENSE_LEVEL; 187 x |= 8 << OPENPIC_PRIORITY_SHIFT; 188 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x); 189 } 190 191 /* Reset and disable all IPIs. */ 192 for (ipi = 0; ipi < OPENPIC_NIPIS; ipi++) { 193 x = sc->sc_nirq + ipi; 194 x |= OPENPIC_IMASK; 195 x |= 15 << OPENPIC_PRIORITY_SHIFT; 196 openpic_write(sc, OPENPIC_IPI_VECTOR(ipi), x); 197 } 198 199 /* we don't need 8259 passthrough mode */ 200 x = openpic_read(sc, OPENPIC_CONFIG); 201 x |= OPENPIC_CONFIG_8259_PASSTHRU_DISABLE; 202 openpic_write(sc, OPENPIC_CONFIG, x); 203 204 /* send all interrupts to cpu 0 */ 205 for (irq = 0; irq < sc->sc_nirq; irq++) 206 openpic_write(sc, OPENPIC_IDEST(irq), 1 << 0); 207 208 /* clear all pending interrupts from cpu 0 */ 209 for (irq = 0; irq < sc->sc_nirq; irq++) { 210 (void)openpic_read(sc, OPENPIC_PCPU_IACK(0)); 211 openpic_write(sc, OPENPIC_PCPU_EOI(0), 0); 212 } 213 214 for (cpu = 0; cpu < sc->sc_ncpu; cpu++) 215 openpic_write(sc, OPENPIC_PCPU_TPR(cpu), 0); 216 217 powerpc_register_pic(dev, node, sc->sc_nirq, OPENPIC_NIPIS, FALSE); 218 219 /* If this is not a cascaded PIC, it must be the root PIC */ 220 if (sc->sc_intr == NULL) 221 root_pic = dev; 222 223 return (0); 224 } 225 226 /* 227 * PIC I/F methods 228 */ 229 230 void 231 openpic_bind(device_t dev, u_int irq, cpuset_t cpumask, void **priv __unused) 232 { 233 struct openpic_softc *sc; 234 uint32_t mask; 235 236 /* If we aren't directly connected to the CPU, this won't work */ 237 if (dev != root_pic) 238 return; 239 240 sc = device_get_softc(dev); 241 242 /* 243 * XXX: openpic_write() is very special and just needs a 32 bits mask. 244 * For the moment, just play dirty and get the first half word. 245 */ 246 mask = cpumask.__bits[0] & 0xffffffff; 247 if (sc->sc_quirks & OPENPIC_QUIRK_SINGLE_BIND) { 248 int i = mftb() % CPU_COUNT(&cpumask); 249 int cpu, ncpu; 250 251 ncpu = 0; 252 CPU_FOREACH(cpu) { 253 if (!(mask & (1 << cpu))) 254 continue; 255 if (ncpu == i) 256 break; 257 ncpu++; 258 } 259 mask &= (1 << cpu); 260 } 261 262 openpic_write(sc, OPENPIC_IDEST(irq), mask); 263 } 264 265 void 266 openpic_config(device_t dev, u_int irq, enum intr_trigger trig, 267 enum intr_polarity pol) 268 { 269 struct openpic_softc *sc; 270 uint32_t x; 271 272 sc = device_get_softc(dev); 273 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq)); 274 if (pol == INTR_POLARITY_LOW) 275 x &= ~OPENPIC_POLARITY_POSITIVE; 276 else 277 x |= OPENPIC_POLARITY_POSITIVE; 278 if (trig == INTR_TRIGGER_EDGE) 279 x &= ~OPENPIC_SENSE_LEVEL; 280 else 281 x |= OPENPIC_SENSE_LEVEL; 282 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x); 283 } 284 285 static int 286 openpic_intr(void *arg) 287 { 288 device_t dev = (device_t)(arg); 289 290 /* XXX Cascaded PICs do not pass non-NULL trapframes! */ 291 openpic_dispatch(dev, NULL); 292 293 return (FILTER_HANDLED); 294 } 295 296 void 297 openpic_dispatch(device_t dev, struct trapframe *tf) 298 { 299 struct openpic_softc *sc; 300 u_int cpuid, vector; 301 302 CTR1(KTR_INTR, "%s: got interrupt", __func__); 303 304 cpuid = (dev == root_pic) ? PCPU_GET(cpuid) : 0; 305 306 sc = device_get_softc(dev); 307 while (1) { 308 vector = openpic_read(sc, OPENPIC_PCPU_IACK(cpuid)); 309 vector &= OPENPIC_VECTOR_MASK; 310 if (vector == 255) 311 break; 312 powerpc_dispatch_intr(vector, tf); 313 } 314 } 315 316 void 317 openpic_enable(device_t dev, u_int irq, u_int vector, void **priv __unused) 318 { 319 struct openpic_softc *sc; 320 uint32_t x; 321 322 sc = device_get_softc(dev); 323 if (irq < sc->sc_nirq) { 324 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq)); 325 x &= ~(OPENPIC_IMASK | OPENPIC_VECTOR_MASK); 326 x |= vector; 327 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x); 328 } else { 329 x = openpic_read(sc, OPENPIC_IPI_VECTOR(0)); 330 x &= ~(OPENPIC_IMASK | OPENPIC_VECTOR_MASK); 331 x |= vector; 332 openpic_write(sc, OPENPIC_IPI_VECTOR(0), x); 333 } 334 } 335 336 void 337 openpic_eoi(device_t dev, u_int irq __unused, void *priv __unused) 338 { 339 struct openpic_softc *sc; 340 u_int cpuid; 341 342 cpuid = (dev == root_pic) ? PCPU_GET(cpuid) : 0; 343 344 sc = device_get_softc(dev); 345 openpic_write(sc, OPENPIC_PCPU_EOI(cpuid), 0); 346 } 347 348 void 349 openpic_ipi(device_t dev, u_int cpu) 350 { 351 struct openpic_softc *sc; 352 353 KASSERT(dev == root_pic, ("Cannot send IPIs from non-root OpenPIC")); 354 355 sc = device_get_softc(dev); 356 sched_pin(); 357 openpic_write(sc, OPENPIC_PCPU_IPI_DISPATCH(PCPU_GET(cpuid), 0), 358 1u << cpu); 359 sched_unpin(); 360 } 361 362 void 363 openpic_mask(device_t dev, u_int irq, void *priv __unused) 364 { 365 struct openpic_softc *sc; 366 uint32_t x; 367 368 sc = device_get_softc(dev); 369 if (irq < sc->sc_nirq) { 370 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq)); 371 x |= OPENPIC_IMASK; 372 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x); 373 } else { 374 x = openpic_read(sc, OPENPIC_IPI_VECTOR(0)); 375 x |= OPENPIC_IMASK; 376 openpic_write(sc, OPENPIC_IPI_VECTOR(0), x); 377 } 378 } 379 380 void 381 openpic_unmask(device_t dev, u_int irq, void *priv __unused) 382 { 383 struct openpic_softc *sc; 384 uint32_t x; 385 386 sc = device_get_softc(dev); 387 if (irq < sc->sc_nirq) { 388 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq)); 389 x &= ~OPENPIC_IMASK; 390 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x); 391 } else { 392 x = openpic_read(sc, OPENPIC_IPI_VECTOR(0)); 393 x &= ~OPENPIC_IMASK; 394 openpic_write(sc, OPENPIC_IPI_VECTOR(0), x); 395 } 396 } 397 398 int 399 openpic_suspend(device_t dev) 400 { 401 struct openpic_softc *sc; 402 int i; 403 404 sc = device_get_softc(dev); 405 406 sc->sc_saved_config = bus_read_4(sc->sc_memr, OPENPIC_CONFIG); 407 for (i = 0; i < OPENPIC_NIPIS; i++) { 408 sc->sc_saved_ipis[i] = bus_read_4(sc->sc_memr, OPENPIC_IPI_VECTOR(i)); 409 } 410 411 for (i = 0; i < 4; i++) { 412 sc->sc_saved_prios[i] = bus_read_4(sc->sc_memr, OPENPIC_PCPU_TPR(i)); 413 } 414 415 for (i = 0; i < OPENPIC_TIMERS; i++) { 416 sc->sc_saved_timers[i].tcnt = bus_read_4(sc->sc_memr, OPENPIC_TCNT(i)); 417 sc->sc_saved_timers[i].tbase = bus_read_4(sc->sc_memr, OPENPIC_TBASE(i)); 418 sc->sc_saved_timers[i].tvec = bus_read_4(sc->sc_memr, OPENPIC_TVEC(i)); 419 sc->sc_saved_timers[i].tdst = bus_read_4(sc->sc_memr, OPENPIC_TDST(i)); 420 } 421 422 for (i = 0; i < OPENPIC_SRC_VECTOR_COUNT; i++) 423 sc->sc_saved_vectors[i] = 424 bus_read_4(sc->sc_memr, OPENPIC_SRC_VECTOR(i)) & ~OPENPIC_ACTIVITY; 425 426 return (0); 427 } 428 429 int 430 openpic_resume(device_t dev) 431 { 432 struct openpic_softc *sc; 433 int i; 434 435 sc = device_get_softc(dev); 436 437 sc->sc_saved_config = bus_read_4(sc->sc_memr, OPENPIC_CONFIG); 438 for (i = 0; i < OPENPIC_NIPIS; i++) { 439 bus_write_4(sc->sc_memr, OPENPIC_IPI_VECTOR(i), sc->sc_saved_ipis[i]); 440 } 441 442 for (i = 0; i < 4; i++) { 443 bus_write_4(sc->sc_memr, OPENPIC_PCPU_TPR(i), sc->sc_saved_prios[i]); 444 } 445 446 for (i = 0; i < OPENPIC_TIMERS; i++) { 447 bus_write_4(sc->sc_memr, OPENPIC_TCNT(i), sc->sc_saved_timers[i].tcnt); 448 bus_write_4(sc->sc_memr, OPENPIC_TBASE(i), sc->sc_saved_timers[i].tbase); 449 bus_write_4(sc->sc_memr, OPENPIC_TVEC(i), sc->sc_saved_timers[i].tvec); 450 bus_write_4(sc->sc_memr, OPENPIC_TDST(i), sc->sc_saved_timers[i].tdst); 451 } 452 453 for (i = 0; i < OPENPIC_SRC_VECTOR_COUNT; i++) 454 bus_write_4(sc->sc_memr, OPENPIC_SRC_VECTOR(i), sc->sc_saved_vectors[i]); 455 456 return (0); 457 } 458