1 /*- 2 * Copyright (c) 2008 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/ktr.h> 34 #include <sys/bus.h> 35 #include <sys/cpuset.h> 36 #include <sys/lock.h> 37 #include <sys/malloc.h> 38 #include <sys/mutex.h> 39 #include <sys/pcpu.h> 40 #include <sys/proc.h> 41 #include <sys/sched.h> 42 #include <sys/smp.h> 43 44 #include <vm/vm.h> 45 #include <vm/vm_param.h> 46 #include <vm/pmap.h> 47 #include <vm/vm_map.h> 48 #include <vm/vm_extern.h> 49 #include <vm/vm_kern.h> 50 51 #include <machine/bus.h> 52 #include <machine/cpu.h> 53 #include <machine/intr_machdep.h> 54 #include <machine/pcb.h> 55 #include <machine/platform.h> 56 #include <machine/md_var.h> 57 #include <machine/smp.h> 58 59 #include "pic_if.h" 60 61 extern struct pcpu __pcpu[MAXCPU]; 62 63 volatile static int ap_awake; 64 volatile static u_int ap_letgo; 65 volatile static u_quad_t ap_timebase; 66 static u_int ipi_msg_cnt[32]; 67 static struct mtx ap_boot_mtx; 68 struct pcb stoppcbs[MAXCPU]; 69 70 void 71 machdep_ap_bootstrap(void) 72 { 73 /* Set up important bits on the CPU (HID registers, etc.) */ 74 cpudep_ap_setup(); 75 76 /* Set PIR */ 77 PCPU_SET(pir, mfspr(SPR_PIR)); 78 PCPU_SET(awake, 1); 79 __asm __volatile("msync; isync"); 80 81 while (ap_letgo == 0) 82 ; 83 84 /* Initialize DEC and TB, sync with the BSP values */ 85 #ifdef __powerpc64__ 86 /* Writing to the time base register is hypervisor-privileged */ 87 if (mfmsr() & PSL_HV) 88 mttb(ap_timebase); 89 #else 90 mttb(ap_timebase); 91 #endif 92 decr_ap_init(); 93 94 /* Serialize console output and AP count increment */ 95 mtx_lock_spin(&ap_boot_mtx); 96 ap_awake++; 97 printf("SMP: AP CPU #%d launched\n", PCPU_GET(cpuid)); 98 mtx_unlock_spin(&ap_boot_mtx); 99 100 /* Start per-CPU event timers. */ 101 cpu_initclocks_ap(); 102 103 /* Announce ourselves awake, and enter the scheduler */ 104 sched_throw(NULL); 105 } 106 107 void 108 cpu_mp_setmaxid(void) 109 { 110 struct cpuref cpuref; 111 int error; 112 113 mp_ncpus = 0; 114 error = platform_smp_first_cpu(&cpuref); 115 while (!error) { 116 mp_ncpus++; 117 error = platform_smp_next_cpu(&cpuref); 118 } 119 /* Sanity. */ 120 if (mp_ncpus == 0) 121 mp_ncpus = 1; 122 123 /* 124 * Set the largest cpuid we're going to use. This is necessary 125 * for VM initialization. 126 */ 127 mp_maxid = min(mp_ncpus, MAXCPU) - 1; 128 } 129 130 int 131 cpu_mp_probe(void) 132 { 133 134 /* 135 * We're not going to enable SMP if there's only 1 processor. 136 */ 137 return (mp_ncpus > 1); 138 } 139 140 void 141 cpu_mp_start(void) 142 { 143 struct cpuref bsp, cpu; 144 struct pcpu *pc; 145 int error; 146 147 error = platform_smp_get_bsp(&bsp); 148 KASSERT(error == 0, ("Don't know BSP")); 149 KASSERT(bsp.cr_cpuid == 0, ("%s: cpuid != 0", __func__)); 150 151 error = platform_smp_first_cpu(&cpu); 152 while (!error) { 153 if (cpu.cr_cpuid >= MAXCPU) { 154 printf("SMP: cpu%d: skipped -- ID out of range\n", 155 cpu.cr_cpuid); 156 goto next; 157 } 158 if (CPU_ISSET(cpu.cr_cpuid, &all_cpus)) { 159 printf("SMP: cpu%d: skipped - duplicate ID\n", 160 cpu.cr_cpuid); 161 goto next; 162 } 163 if (cpu.cr_cpuid != bsp.cr_cpuid) { 164 void *dpcpu; 165 166 pc = &__pcpu[cpu.cr_cpuid]; 167 dpcpu = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE, 168 M_WAITOK | M_ZERO); 169 pcpu_init(pc, cpu.cr_cpuid, sizeof(*pc)); 170 dpcpu_init(dpcpu, cpu.cr_cpuid); 171 } else { 172 pc = pcpup; 173 pc->pc_cpuid = bsp.cr_cpuid; 174 pc->pc_bsp = 1; 175 } 176 pc->pc_hwref = cpu.cr_hwref; 177 CPU_SET(pc->pc_cpuid, &all_cpus); 178 next: 179 error = platform_smp_next_cpu(&cpu); 180 } 181 } 182 183 void 184 cpu_mp_announce(void) 185 { 186 struct pcpu *pc; 187 int i; 188 189 for (i = 0; i <= mp_maxid; i++) { 190 pc = pcpu_find(i); 191 if (pc == NULL) 192 continue; 193 printf("cpu%d: dev=%x", i, (int)pc->pc_hwref); 194 if (pc->pc_bsp) 195 printf(" (BSP)"); 196 printf("\n"); 197 } 198 } 199 200 static void 201 cpu_mp_unleash(void *dummy) 202 { 203 struct pcpu *pc; 204 int cpus, timeout; 205 206 if (mp_ncpus <= 1) 207 return; 208 209 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN); 210 211 cpus = 0; 212 smp_cpus = 0; 213 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 214 cpus++; 215 if (!pc->pc_bsp) { 216 if (bootverbose) 217 printf("Waking up CPU %d (dev=%x)\n", 218 pc->pc_cpuid, (int)pc->pc_hwref); 219 220 platform_smp_start_cpu(pc); 221 222 timeout = 2000; /* wait 2sec for the AP */ 223 while (!pc->pc_awake && --timeout > 0) 224 DELAY(1000); 225 226 } else { 227 PCPU_SET(pir, mfspr(SPR_PIR)); 228 pc->pc_awake = 1; 229 } 230 if (pc->pc_awake) { 231 if (bootverbose) 232 printf("Adding CPU %d, pir=%x, awake=%x\n", 233 pc->pc_cpuid, pc->pc_pir, pc->pc_awake); 234 smp_cpus++; 235 } else 236 CPU_SET(pc->pc_cpuid, &stopped_cpus); 237 } 238 239 ap_awake = 1; 240 241 /* Provide our current DEC and TB values for APs */ 242 ap_timebase = mftb() + 10; 243 __asm __volatile("msync; isync"); 244 245 /* Let APs continue */ 246 atomic_store_rel_int(&ap_letgo, 1); 247 248 #ifdef __powerpc64__ 249 /* Writing to the time base register is hypervisor-privileged */ 250 if (mfmsr() & PSL_HV) 251 mttb(ap_timebase); 252 #else 253 mttb(ap_timebase); 254 #endif 255 256 while (ap_awake < smp_cpus) 257 ; 258 259 if (smp_cpus != cpus || cpus != mp_ncpus) { 260 printf("SMP: %d CPUs found; %d CPUs usable; %d CPUs woken\n", 261 mp_ncpus, cpus, smp_cpus); 262 } 263 264 /* Let the APs get into the scheduler */ 265 DELAY(10000); 266 267 smp_active = 1; 268 smp_started = 1; 269 } 270 271 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, cpu_mp_unleash, NULL); 272 273 int 274 powerpc_ipi_handler(void *arg) 275 { 276 u_int cpuid; 277 uint32_t ipimask; 278 int msg; 279 280 CTR2(KTR_SMP, "%s: MSR 0x%08x", __func__, mfmsr()); 281 282 ipimask = atomic_readandclear_32(&(pcpup->pc_ipimask)); 283 if (ipimask == 0) 284 return (FILTER_STRAY); 285 while ((msg = ffs(ipimask) - 1) != -1) { 286 ipimask &= ~(1u << msg); 287 ipi_msg_cnt[msg]++; 288 switch (msg) { 289 case IPI_AST: 290 CTR1(KTR_SMP, "%s: IPI_AST", __func__); 291 break; 292 case IPI_PREEMPT: 293 CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__); 294 sched_preempt(curthread); 295 break; 296 case IPI_RENDEZVOUS: 297 CTR1(KTR_SMP, "%s: IPI_RENDEZVOUS", __func__); 298 smp_rendezvous_action(); 299 break; 300 case IPI_STOP: 301 302 /* 303 * IPI_STOP_HARD is mapped to IPI_STOP so it is not 304 * necessary to add such case in the switch. 305 */ 306 CTR1(KTR_SMP, "%s: IPI_STOP or IPI_STOP_HARD (stop)", 307 __func__); 308 cpuid = PCPU_GET(cpuid); 309 savectx(&stoppcbs[cpuid]); 310 savectx(PCPU_GET(curpcb)); 311 CPU_SET_ATOMIC(cpuid, &stopped_cpus); 312 while (!CPU_ISSET(cpuid, &started_cpus)) 313 cpu_spinwait(); 314 CPU_CLR_ATOMIC(cpuid, &stopped_cpus); 315 CPU_CLR_ATOMIC(cpuid, &started_cpus); 316 CTR1(KTR_SMP, "%s: IPI_STOP (restart)", __func__); 317 break; 318 case IPI_HARDCLOCK: 319 CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__); 320 hardclockintr(); 321 break; 322 } 323 } 324 325 return (FILTER_HANDLED); 326 } 327 328 static void 329 ipi_send(struct pcpu *pc, int ipi) 330 { 331 332 CTR4(KTR_SMP, "%s: pc=%p, targetcpu=%d, IPI=%d", __func__, 333 pc, pc->pc_cpuid, ipi); 334 335 atomic_set_32(&pc->pc_ipimask, (1 << ipi)); 336 PIC_IPI(root_pic, pc->pc_cpuid); 337 338 CTR1(KTR_SMP, "%s: sent", __func__); 339 } 340 341 /* Send an IPI to a set of cpus. */ 342 void 343 ipi_selected(cpuset_t cpus, int ipi) 344 { 345 struct pcpu *pc; 346 347 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 348 if (CPU_ISSET(pc->pc_cpuid, &cpus)) 349 ipi_send(pc, ipi); 350 } 351 } 352 353 /* Send an IPI to a specific CPU. */ 354 void 355 ipi_cpu(int cpu, u_int ipi) 356 { 357 358 ipi_send(cpuid_to_pcpu[cpu], ipi); 359 } 360 361 /* Send an IPI to all CPUs EXCEPT myself. */ 362 void 363 ipi_all_but_self(int ipi) 364 { 365 struct pcpu *pc; 366 367 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 368 if (pc != pcpup) 369 ipi_send(pc, ipi); 370 } 371 } 372