1 /*- 2 * Copyright (c) 2015-2016 Nathan Whitehorn 3 * Copyright (c) 2017-2018 Semihalf 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/module.h> 33 #include <sys/bus.h> 34 #include <sys/conf.h> 35 #include <sys/kernel.h> 36 #include <sys/pciio.h> 37 #include <sys/endian.h> 38 #include <sys/rman.h> 39 #include <sys/vmem.h> 40 41 #include <dev/ofw/openfirm.h> 42 #include <dev/ofw/ofw_pci.h> 43 #include <dev/ofw/ofw_bus.h> 44 #include <dev/ofw/ofw_bus_subr.h> 45 #include <dev/ofw/ofwpci.h> 46 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcireg.h> 49 50 #include <machine/bus.h> 51 #include <machine/intr_machdep.h> 52 #include <machine/md_var.h> 53 54 #include <vm/vm.h> 55 #include <vm/pmap.h> 56 57 #include "pcib_if.h" 58 #include "pic_if.h" 59 #include "iommu_if.h" 60 #include "opal.h" 61 62 #define OPAL_PCI_TCE_MAX_ENTRIES (1024*1024UL) 63 #define OPAL_PCI_TCE_DEFAULT_SEG_SIZE (16*1024*1024UL) 64 #define OPAL_PCI_TCE_R (1UL << 0) 65 #define OPAL_PCI_TCE_W (1UL << 1) 66 #define PHB3_TCE_KILL_INVAL_ALL (1UL << 63) 67 68 /* 69 * Device interface. 70 */ 71 static int opalpci_probe(device_t); 72 static int opalpci_attach(device_t); 73 74 /* 75 * pcib interface. 76 */ 77 static uint32_t opalpci_read_config(device_t, u_int, u_int, u_int, 78 u_int, int); 79 static void opalpci_write_config(device_t, u_int, u_int, u_int, 80 u_int, u_int32_t, int); 81 static int opalpci_alloc_msi(device_t dev, device_t child, 82 int count, int maxcount, int *irqs); 83 static int opalpci_release_msi(device_t dev, device_t child, 84 int count, int *irqs); 85 static int opalpci_alloc_msix(device_t dev, device_t child, 86 int *irq); 87 static int opalpci_release_msix(device_t dev, device_t child, 88 int irq); 89 static int opalpci_map_msi(device_t dev, device_t child, 90 int irq, uint64_t *addr, uint32_t *data); 91 static int opalpci_route_interrupt(device_t bus, device_t dev, int pin); 92 93 /* 94 * MSI PIC interface. 95 */ 96 static void opalpic_pic_enable(device_t dev, u_int irq, u_int vector); 97 static void opalpic_pic_eoi(device_t dev, u_int irq); 98 99 /* 100 * Commands 101 */ 102 #define OPAL_M32_WINDOW_TYPE 1 103 #define OPAL_M64_WINDOW_TYPE 2 104 #define OPAL_IO_WINDOW_TYPE 3 105 106 #define OPAL_RESET_PHB_COMPLETE 1 107 #define OPAL_RESET_PCI_IODA_TABLE 6 108 109 #define OPAL_DISABLE_M64 0 110 #define OPAL_ENABLE_M64_SPLIT 1 111 #define OPAL_ENABLE_M64_NON_SPLIT 2 112 113 #define OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO 1 114 #define OPAL_EEH_ACTION_CLEAR_FREEZE_DMA 2 115 #define OPAL_EEH_ACTION_CLEAR_FREEZE_ALL 3 116 117 /* 118 * Constants 119 */ 120 #define OPAL_PCI_DEFAULT_PE 1 121 122 /* 123 * Driver methods. 124 */ 125 static device_method_t opalpci_methods[] = { 126 /* Device interface */ 127 DEVMETHOD(device_probe, opalpci_probe), 128 DEVMETHOD(device_attach, opalpci_attach), 129 130 /* pcib interface */ 131 DEVMETHOD(pcib_read_config, opalpci_read_config), 132 DEVMETHOD(pcib_write_config, opalpci_write_config), 133 134 DEVMETHOD(pcib_alloc_msi, opalpci_alloc_msi), 135 DEVMETHOD(pcib_release_msi, opalpci_release_msi), 136 DEVMETHOD(pcib_alloc_msix, opalpci_alloc_msix), 137 DEVMETHOD(pcib_release_msix, opalpci_release_msix), 138 DEVMETHOD(pcib_map_msi, opalpci_map_msi), 139 DEVMETHOD(pcib_route_interrupt, opalpci_route_interrupt), 140 141 /* PIC interface for MSIs */ 142 DEVMETHOD(pic_enable, opalpic_pic_enable), 143 DEVMETHOD(pic_eoi, opalpic_pic_eoi), 144 145 DEVMETHOD_END 146 }; 147 148 struct opalpci_softc { 149 struct ofw_pci_softc ofw_sc; 150 uint64_t phb_id; 151 vmem_t *msi_vmem; 152 int msi_base; /* Base XIVE number */ 153 int base_msi_irq; /* Base IRQ assigned by FreeBSD to this PIC */ 154 uint64_t *tce; /* TCE table for 1:1 mapping */ 155 struct resource *r_reg; 156 }; 157 158 static devclass_t opalpci_devclass; 159 DEFINE_CLASS_1(pcib, opalpci_driver, opalpci_methods, 160 sizeof(struct opalpci_softc), ofw_pci_driver); 161 EARLY_DRIVER_MODULE(opalpci, ofwbus, opalpci_driver, opalpci_devclass, 0, 0, 162 BUS_PASS_BUS); 163 164 static int 165 opalpci_probe(device_t dev) 166 { 167 const char *type; 168 169 if (opal_check() != 0) 170 return (ENXIO); 171 172 type = ofw_bus_get_type(dev); 173 174 if (type == NULL || (strcmp(type, "pci") != 0 && 175 strcmp(type, "pciex") != 0)) 176 return (ENXIO); 177 178 if (!OF_hasprop(ofw_bus_get_node(dev), "ibm,opal-phbid")) 179 return (ENXIO); 180 181 device_set_desc(dev, "OPAL Host-PCI bridge"); 182 return (BUS_PROBE_GENERIC); 183 } 184 185 static void 186 pci_phb3_tce_invalidate_entire(struct opalpci_softc *sc) 187 { 188 189 mb(); 190 bus_write_8(sc->r_reg, 0x210, PHB3_TCE_KILL_INVAL_ALL); 191 mb(); 192 } 193 194 /* Simple function to round to a power of 2 */ 195 static uint64_t 196 round_pow2(uint64_t val) 197 { 198 199 return (1 << (flsl(val + (val - 1)) - 1)); 200 } 201 202 /* 203 * Starting with skiboot 5.10 PCIe nodes have a new property, 204 * "ibm,supported-tce-sizes", to denote the TCE sizes available. This allows us 205 * to avoid hard-coding the maximum TCE size allowed, and instead provide a sane 206 * default (however, the "sane" default, which works for all targets, is 64k, 207 * limiting us to 64GB if we have 1M entries. 208 */ 209 static uint64_t 210 max_tce_size(device_t dev) 211 { 212 phandle_t node; 213 cell_t sizes[64]; /* Property is a list of bit-widths, up to 64-bits */ 214 int count; 215 216 node = ofw_bus_get_node(dev); 217 218 count = OF_getencprop(node, "ibm,supported-tce-sizes", 219 sizes, sizeof(sizes)); 220 if (count < (int) sizeof(cell_t)) 221 return OPAL_PCI_TCE_DEFAULT_SEG_SIZE; 222 223 count /= sizeof(cell_t); 224 225 return (1ULL << sizes[count - 1]); 226 } 227 228 static int 229 opalpci_attach(device_t dev) 230 { 231 struct opalpci_softc *sc; 232 cell_t id[2], m64ranges[2], m64window[6], npe; 233 phandle_t node; 234 int i, err; 235 uint64_t maxmem; 236 uint64_t entries; 237 uint64_t tce_size; 238 uint64_t tce_tbl_size; 239 int m64bar; 240 int rid; 241 242 sc = device_get_softc(dev); 243 node = ofw_bus_get_node(dev); 244 245 switch (OF_getproplen(node, "ibm,opal-phbid")) { 246 case 8: 247 OF_getencprop(node, "ibm,opal-phbid", id, 8); 248 sc->phb_id = ((uint64_t)id[0] << 32) | id[1]; 249 break; 250 case 4: 251 OF_getencprop(node, "ibm,opal-phbid", id, 4); 252 sc->phb_id = id[0]; 253 break; 254 default: 255 device_printf(dev, "PHB ID property had wrong length (%zd)\n", 256 OF_getproplen(node, "ibm,opal-phbid")); 257 return (ENXIO); 258 } 259 260 if (bootverbose) 261 device_printf(dev, "OPAL ID %#lx\n", sc->phb_id); 262 263 rid = 0; 264 sc->r_reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 265 &rid, RF_ACTIVE | RF_SHAREABLE); 266 if (sc->r_reg == NULL) { 267 device_printf(dev, "Failed to allocate PHB[%jd] registers\n", 268 (uintmax_t)sc->phb_id); 269 return (ENXIO); 270 } 271 272 #if 0 273 /* 274 * Reset PCI IODA table 275 */ 276 err = opal_call(OPAL_PCI_RESET, sc->phb_id, OPAL_RESET_PCI_IODA_TABLE, 277 1); 278 if (err != 0) { 279 device_printf(dev, "IODA table reset failed: %d\n", err); 280 return (ENXIO); 281 } 282 err = opal_call(OPAL_PCI_RESET, sc->phb_id, OPAL_RESET_PHB_COMPLETE, 283 1); 284 if (err < 0) { 285 device_printf(dev, "PHB reset failed: %d\n", err); 286 return (ENXIO); 287 } 288 if (err > 0) { 289 while ((err = opal_call(OPAL_PCI_POLL, sc->phb_id)) > 0) { 290 DELAY(1000*(err + 1)); /* Returns expected delay in ms */ 291 } 292 } 293 if (err < 0) { 294 device_printf(dev, "WARNING: PHB IODA reset poll failed: %d\n", err); 295 } 296 err = opal_call(OPAL_PCI_RESET, sc->phb_id, OPAL_RESET_PHB_COMPLETE, 297 0); 298 if (err < 0) { 299 device_printf(dev, "PHB reset failed: %d\n", err); 300 return (ENXIO); 301 } 302 if (err > 0) { 303 while ((err = opal_call(OPAL_PCI_POLL, sc->phb_id)) > 0) { 304 DELAY(1000*(err + 1)); /* Returns expected delay in ms */ 305 } 306 } 307 #endif 308 309 /* 310 * Map all devices on the bus to partitionable endpoint one until 311 * such time as we start wanting to do things like bhyve. 312 */ 313 err = opal_call(OPAL_PCI_SET_PE, sc->phb_id, OPAL_PCI_DEFAULT_PE, 314 0, OPAL_PCI_BUS_ANY, OPAL_IGNORE_RID_DEVICE_NUMBER, 315 OPAL_IGNORE_RID_FUNC_NUMBER, OPAL_MAP_PE); 316 if (err != 0) { 317 device_printf(dev, "PE mapping failed: %d\n", err); 318 return (ENXIO); 319 } 320 321 /* 322 * Turn on MMIO, mapped to PE 1 323 */ 324 if (OF_getencprop(node, "ibm,opal-num-pes", &npe, 4) != 4) 325 npe = 1; 326 for (i = 0; i < npe; i++) { 327 err = opal_call(OPAL_PCI_MAP_PE_MMIO_WINDOW, sc->phb_id, 328 OPAL_PCI_DEFAULT_PE, OPAL_M32_WINDOW_TYPE, 0, i); 329 if (err != 0) 330 device_printf(dev, "MMIO %d map failed: %d\n", i, err); 331 } 332 333 if (OF_getencprop(node, "ibm,opal-available-m64-ranges", 334 m64ranges, sizeof(m64ranges)) == sizeof(m64ranges)) 335 m64bar = m64ranges[0]; 336 else 337 m64bar = 0; 338 339 /* XXX: multiple M64 windows? */ 340 if (OF_getencprop(node, "ibm,opal-m64-window", 341 m64window, sizeof(m64window)) == sizeof(m64window)) { 342 opal_call(OPAL_PCI_PHB_MMIO_ENABLE, sc->phb_id, 343 OPAL_M64_WINDOW_TYPE, m64bar, 0); 344 opal_call(OPAL_PCI_SET_PHB_MEM_WINDOW, sc->phb_id, 345 OPAL_M64_WINDOW_TYPE, m64bar /* index */, 346 ((uint64_t)m64window[2] << 32) | m64window[3], 0, 347 ((uint64_t)m64window[4] << 32) | m64window[5]); 348 opal_call(OPAL_PCI_MAP_PE_MMIO_WINDOW, sc->phb_id, 349 OPAL_PCI_DEFAULT_PE, OPAL_M64_WINDOW_TYPE, 350 m64bar /* index */, 0); 351 opal_call(OPAL_PCI_PHB_MMIO_ENABLE, sc->phb_id, 352 OPAL_M64_WINDOW_TYPE, m64bar, OPAL_ENABLE_M64_NON_SPLIT); 353 } 354 355 /* 356 * Enable IOMMU for PE1 - map everything 1:1 using 357 * segments of max_tce_size size 358 */ 359 tce_size = max_tce_size(dev); 360 maxmem = roundup2(powerpc_ptob(Maxmem), tce_size); 361 entries = round_pow2(maxmem / tce_size); 362 tce_tbl_size = max(entries * sizeof(uint64_t), 4096); 363 if (entries > OPAL_PCI_TCE_MAX_ENTRIES) 364 panic("POWERNV supports only %jdGB of memory space\n", 365 (uintmax_t)((OPAL_PCI_TCE_MAX_ENTRIES * tce_size) >> 30)); 366 if (bootverbose) 367 device_printf(dev, "Mapping 0-%#jx for DMA\n", (uintmax_t)maxmem); 368 sc->tce = contigmalloc(tce_tbl_size, 369 M_DEVBUF, M_NOWAIT | M_ZERO, 0, 370 BUS_SPACE_MAXADDR, tce_size, 0); 371 if (sc->tce == NULL) 372 panic("Failed to allocate TCE memory for PHB %jd\n", 373 (uintmax_t)sc->phb_id); 374 375 for (i = 0; i < entries; i++) 376 sc->tce[i] = (i * tce_size) | OPAL_PCI_TCE_R | OPAL_PCI_TCE_W; 377 378 /* Map TCE for every PE. It seems necessary for Power8 */ 379 for (i = 0; i < npe; i++) { 380 err = opal_call(OPAL_PCI_MAP_PE_DMA_WINDOW, sc->phb_id, 381 i, (i << 1), 382 1, pmap_kextract((uint64_t)&sc->tce[0]), 383 tce_tbl_size, tce_size); 384 if (err != 0) { 385 device_printf(dev, "DMA IOMMU mapping failed: %d\n", err); 386 return (ENXIO); 387 } 388 389 err = opal_call(OPAL_PCI_MAP_PE_DMA_WINDOW_REAL, sc->phb_id, 390 i, (i << 1) + 1, 391 (1UL << 59), maxmem); 392 if (err != 0) { 393 device_printf(dev, "DMA 64b bypass mapping failed: %d\n", err); 394 return (ENXIO); 395 } 396 } 397 398 /* 399 * Invalidate all previous TCE entries. 400 * 401 * TODO: add support for other PHBs than PHB3 402 */ 403 pci_phb3_tce_invalidate_entire(sc); 404 405 /* 406 * Get MSI properties 407 */ 408 sc->msi_vmem = NULL; 409 if (OF_getproplen(node, "ibm,opal-msi-ranges") > 0) { 410 cell_t msi_ranges[2]; 411 OF_getencprop(node, "ibm,opal-msi-ranges", 412 msi_ranges, sizeof(msi_ranges)); 413 sc->msi_base = msi_ranges[0]; 414 415 sc->msi_vmem = vmem_create("OPAL MSI", msi_ranges[0], 416 msi_ranges[1], 1, 16, M_BESTFIT | M_WAITOK); 417 418 sc->base_msi_irq = powerpc_register_pic(dev, 419 OF_xref_from_node(node), 420 msi_ranges[0] + msi_ranges[1], 0, FALSE); 421 422 if (bootverbose) 423 device_printf(dev, "Supports %d MSIs starting at %d\n", 424 msi_ranges[1], msi_ranges[0]); 425 } 426 427 /* 428 * General OFW PCI attach 429 */ 430 err = ofw_pci_init(dev); 431 if (err != 0) 432 return (err); 433 434 /* 435 * Unfreeze non-config-space PCI operations. Let this fail silently 436 * if e.g. there is no current freeze. 437 */ 438 opal_call(OPAL_PCI_EEH_FREEZE_CLEAR, sc->phb_id, OPAL_PCI_DEFAULT_PE, 439 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 440 441 /* 442 * OPAL stores 64-bit BARs in a special property rather than "ranges" 443 */ 444 if (OF_getencprop(node, "ibm,opal-m64-window", 445 m64window, sizeof(m64window)) == sizeof(m64window)) { 446 struct ofw_pci_range *rp; 447 448 sc->ofw_sc.sc_nrange++; 449 sc->ofw_sc.sc_range = realloc(sc->ofw_sc.sc_range, 450 sc->ofw_sc.sc_nrange * sizeof(sc->ofw_sc.sc_range[0]), 451 M_DEVBUF, M_WAITOK); 452 rp = &sc->ofw_sc.sc_range[sc->ofw_sc.sc_nrange-1]; 453 rp->pci_hi = OFW_PCI_PHYS_HI_SPACE_MEM64 | 454 OFW_PCI_PHYS_HI_PREFETCHABLE; 455 rp->pci = ((uint64_t)m64window[0] << 32) | m64window[1]; 456 rp->host = ((uint64_t)m64window[2] << 32) | m64window[3]; 457 rp->size = ((uint64_t)m64window[4] << 32) | m64window[5]; 458 rman_manage_region(&sc->ofw_sc.sc_mem_rman, rp->pci, 459 rp->pci + rp->size - 1); 460 } 461 462 return (ofw_pci_attach(dev)); 463 } 464 465 static uint32_t 466 opalpci_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 467 int width) 468 { 469 struct opalpci_softc *sc; 470 uint64_t config_addr; 471 uint8_t byte; 472 uint16_t half; 473 uint32_t word; 474 int error; 475 476 sc = device_get_softc(dev); 477 478 config_addr = (bus << 8) | ((slot & 0x1f) << 3) | (func & 0x7); 479 480 switch (width) { 481 case 1: 482 error = opal_call(OPAL_PCI_CONFIG_READ_BYTE, sc->phb_id, 483 config_addr, reg, vtophys(&byte)); 484 word = byte; 485 break; 486 case 2: 487 error = opal_call(OPAL_PCI_CONFIG_READ_HALF_WORD, sc->phb_id, 488 config_addr, reg, vtophys(&half)); 489 word = half; 490 break; 491 case 4: 492 error = opal_call(OPAL_PCI_CONFIG_READ_WORD, sc->phb_id, 493 config_addr, reg, vtophys(&word)); 494 break; 495 default: 496 error = OPAL_SUCCESS; 497 word = 0xffffffff; 498 } 499 500 /* 501 * Poking config state for non-existant devices can make 502 * the host bridge hang up. Clear any errors. 503 * 504 * XXX: Make this conditional on the existence of a freeze 505 */ 506 opal_call(OPAL_PCI_EEH_FREEZE_CLEAR, sc->phb_id, OPAL_PCI_DEFAULT_PE, 507 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 508 509 if (error != OPAL_SUCCESS) 510 word = 0xffffffff; 511 512 return (word); 513 } 514 515 static void 516 opalpci_write_config(device_t dev, u_int bus, u_int slot, u_int func, 517 u_int reg, uint32_t val, int width) 518 { 519 struct opalpci_softc *sc; 520 uint64_t config_addr; 521 int error = OPAL_SUCCESS; 522 523 sc = device_get_softc(dev); 524 525 config_addr = (bus << 8) | ((slot & 0x1f) << 3) | (func & 0x7); 526 527 switch (width) { 528 case 1: 529 error = opal_call(OPAL_PCI_CONFIG_WRITE_BYTE, sc->phb_id, 530 config_addr, reg, val); 531 break; 532 case 2: 533 error = opal_call(OPAL_PCI_CONFIG_WRITE_HALF_WORD, sc->phb_id, 534 config_addr, reg, val); 535 break; 536 case 4: 537 error = opal_call(OPAL_PCI_CONFIG_WRITE_WORD, sc->phb_id, 538 config_addr, reg, val); 539 break; 540 } 541 542 if (error != OPAL_SUCCESS) { 543 /* 544 * Poking config state for non-existant devices can make 545 * the host bridge hang up. Clear any errors. 546 */ 547 opal_call(OPAL_PCI_EEH_FREEZE_CLEAR, sc->phb_id, 548 OPAL_PCI_DEFAULT_PE, OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 549 } 550 } 551 552 static int 553 opalpci_route_interrupt(device_t bus, device_t dev, int pin) 554 { 555 556 return (pin); 557 } 558 559 static int 560 opalpci_alloc_msi(device_t dev, device_t child, int count, int maxcount, 561 int *irqs) 562 { 563 struct opalpci_softc *sc; 564 vmem_addr_t start; 565 phandle_t xref; 566 int err, i; 567 568 sc = device_get_softc(dev); 569 if (sc->msi_vmem == NULL) 570 return (ENODEV); 571 572 err = vmem_xalloc(sc->msi_vmem, count, powerof2(count), 0, 0, 573 VMEM_ADDR_MIN, VMEM_ADDR_MAX, M_BESTFIT | M_WAITOK, &start); 574 575 if (err) 576 return (err); 577 578 xref = OF_xref_from_node(ofw_bus_get_node(dev)); 579 for (i = 0; i < count; i++) 580 irqs[i] = MAP_IRQ(xref, start + i); 581 582 return (0); 583 } 584 585 static int 586 opalpci_release_msi(device_t dev, device_t child, int count, int *irqs) 587 { 588 struct opalpci_softc *sc; 589 590 sc = device_get_softc(dev); 591 if (sc->msi_vmem == NULL) 592 return (ENODEV); 593 594 vmem_xfree(sc->msi_vmem, irqs[0] - sc->base_msi_irq, count); 595 return (0); 596 } 597 598 static int 599 opalpci_alloc_msix(device_t dev, device_t child, int *irq) 600 { 601 return (opalpci_alloc_msi(dev, child, 1, 1, irq)); 602 } 603 604 static int 605 opalpci_release_msix(device_t dev, device_t child, int irq) 606 { 607 return (opalpci_release_msi(dev, child, 1, &irq)); 608 } 609 610 static int 611 opalpci_map_msi(device_t dev, device_t child, int irq, uint64_t *addr, 612 uint32_t *data) 613 { 614 struct opalpci_softc *sc; 615 struct pci_devinfo *dinfo; 616 int err, xive; 617 618 sc = device_get_softc(dev); 619 if (sc->msi_vmem == NULL) 620 return (ENODEV); 621 622 xive = irq - sc->base_msi_irq - sc->msi_base; 623 opal_call(OPAL_PCI_SET_XIVE_PE, sc->phb_id, OPAL_PCI_DEFAULT_PE, xive); 624 625 dinfo = device_get_ivars(child); 626 if (dinfo->cfg.msi.msi_alloc > 0 && 627 (dinfo->cfg.msi.msi_ctrl & PCIM_MSICTRL_64BIT) == 0) { 628 uint32_t msi32; 629 err = opal_call(OPAL_GET_MSI_32, sc->phb_id, 630 OPAL_PCI_DEFAULT_PE, xive, 1, vtophys(&msi32), 631 vtophys(data)); 632 *addr = be32toh(msi32); 633 } else { 634 err = opal_call(OPAL_GET_MSI_64, sc->phb_id, 635 OPAL_PCI_DEFAULT_PE, xive, 1, vtophys(addr), vtophys(data)); 636 *addr = be64toh(*addr); 637 } 638 *data = be32toh(*data); 639 640 if (bootverbose && err != 0) 641 device_printf(child, "OPAL MSI mapping error: %d\n", err); 642 643 return ((err == 0) ? 0 : ENXIO); 644 } 645 646 static void 647 opalpic_pic_enable(device_t dev, u_int irq, u_int vector) 648 { 649 struct opalpci_softc *sc = device_get_softc(dev); 650 651 PIC_ENABLE(root_pic, irq, vector); 652 opal_call(OPAL_PCI_MSI_EOI, sc->phb_id, irq); 653 } 654 655 static void opalpic_pic_eoi(device_t dev, u_int irq) 656 { 657 struct opalpci_softc *sc; 658 659 sc = device_get_softc(dev); 660 opal_call(OPAL_PCI_MSI_EOI, sc->phb_id, irq); 661 662 PIC_EOI(root_pic, irq); 663 } 664