Revert "powernv: Add RF_BIGENDIAN resource flag"

After further thinking, the nexus bus mappings are for the immediate
peripherals, not downstream. Given this, and that historically PowerPC
platform

Revert "powernv: Add RF_BIGENDIAN resource flag"

After further thinking, the nexus bus mappings are for the immediate
peripherals, not downstream. Given this, and that historically PowerPC
platforms have been big-endian by default, it makes sense to default
mappings to BE always. If this changes in the future, the platform
devices can explicitly mark their mappings with the RF_LITTLEENDIAN flag
instead.

This reverts commit 86d20eaadfd1a03e19d8bc8333c689b820299d52.

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powernv: Add RF_BIGENDIAN resource flag

The big-endian analogue to the RF_LITTLEENDIAN flag, if this flag is set
on a memory resource it's always mapped big endian.

This is needed by the PowerNV OP

powernv: Add RF_BIGENDIAN resource flag

The big-endian analogue to the RF_LITTLEENDIAN flag, if this flag is set
on a memory resource it's always mapped big endian.

This is needed by the PowerNV OPAL resources (XIVE and PCI), as these
top-level peripherals are always big-endian.

Tested by: pkubaj
Fixes: c4921a0f("powerpc: Always use BE tag in nexus_map_resource")
MFC after: 1 day
X-MFC-with: c4921a0f

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sys: Automated cleanup of cdefs and other formatting

Apply the following automated changes to try to eliminate
no-longer-needed sys/cdefs.h includes as well as now-empty
blank lines in a row.

Remov

sys: Automated cleanup of cdefs and other formatting

Apply the following automated changes to try to eliminate
no-longer-needed sys/cdefs.h includes as well as now-empty
blank lines in a row.

Remove /^#if.*\n#endif.*\n#include\s+<sys/cdefs.h>.*\n/
Remove /\n+#include\s+<sys/cdefs.h>.*\n+#if.*\n#endif.*\n+/
Remove /\n+#if.*\n#endif.*\n+/
Remove /^#if.*\n#endif.*\n/
Remove /\n+#include\s+<sys/cdefs.h>\n#include\s+<sys/types.h>/
Remove /\n+#include\s+<sys/cdefs.h>\n#include\s+<sys/param.h>/
Remove /\n+#include\s+<sys/cdefs.h>\n#include\s+<sys/capsicum.h>/

Sponsored by: Netflix

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sys: Remove $FreeBSD$: one-line .c pattern

Remove /^[\s*]*__FBSDID\("\$FreeBSD\$"\);?\s*\n/

powerpc powernv: Remove unused devclass arguments to DRIVER_MODULE.

Rename ofwpci.c to ofw_pcib.c

It's a class0 driver that implements some pcib methods and creates
a pci bus as its children.
The "ofw_pci" name will be used by a new driver that will be a subclass
of

Rename ofwpci.c to ofw_pcib.c

It's a class0 driver that implements some pcib methods and creates
a pci bus as its children.
The "ofw_pci" name will be used by a new driver that will be a subclass
of the pci bus.
No functional changes intended.

Submitted by: Kornel Duleba <mindal@semihalf.com>
Reviewed by: andrew
Obtained from: Semihalf
Sponsored by: Alstom Group
Differential Revision: https://reviews.freebsd.org/D30226

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[PowerPC64LE] Get XIVE up and running.

More endian conversion.

* Install TCEs correctly (i.e. in big endian)

* Convert to big endian and back when setting up queue pages and IRQs.

Sponsored by: T

[PowerPC64LE] Get XIVE up and running.

More endian conversion.

* Install TCEs correctly (i.e. in big endian)

* Convert to big endian and back when setting up queue pages and IRQs.

Sponsored by: Tag1 Consulting, Inc.

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[PowerPC64LE] Endian fixes for opal_pci.c.

Since OPAL runs in big endian, any data being passed back and forth
via memory instead of registers needs to be byteswapped.

From my notes during developm

[PowerPC64LE] Endian fixes for opal_pci.c.

Since OPAL runs in big endian, any data being passed back and forth
via memory instead of registers needs to be byteswapped.

From my notes during development:

"A good way to find candidates is to look for vtophys() in opal_call()
parameters. The memory being passed will be written into in BE."

Sponsored by: Tag1 Consulting, Inc.

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powerpc: clean up empty lines in .c and .h files

powerpc/powernv: Don't use the vmem quantum cache for OPAL PCI MSI allocations

vmem quantum cache is only needed when doing a lot of concurrent allocations,
which doesn't happen when allocating MSIs

powerpc/powernv: Don't use the vmem quantum cache for OPAL PCI MSI allocations

vmem quantum cache is only needed when doing a lot of concurrent allocations,
which doesn't happen when allocating MSIs. This wastes memory for the cache
zones. Avoid this waste and don't use the quantum cache.

Reported by: markj

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powerpc64/powernv: Use OPAL call for non-POWER8 PCI TCE reset

According to the OPAL documentation, only the POWER8 (PHB3) should use
the register write TCE reset method. All others should use the O

powerpc64/powernv: Use OPAL call for non-POWER8 PCI TCE reset

According to the OPAL documentation, only the POWER8 (PHB3) should use
the register write TCE reset method. All others should use the OPAL
call.

On POWER9 the call is semantically identical to the register write, with
a wait for completion.

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powerpc/powernv: Fix OPAL cfgread/cfgwrite error handling

Freeze clearing needs to heppen any time OPAL reads return either an error
(except OPAL_HARDWARE), AND any time it returns 0xff for all byte

powerpc/powernv: Fix OPAL cfgread/cfgwrite error handling

Freeze clearing needs to heppen any time OPAL reads return either an error
(except OPAL_HARDWARE), AND any time it returns 0xff for all bytes.

For cfgwrite, any error that's not OPAL_HARDWARE should be cleaned up.

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powerpc/powernv: Only clear EEH freeze for some errors

Only clear an EEH freeze if an error occurs. However, if an OPAL_HARDWARE
error is returned, this indicates a hardware failure which cannot be

powerpc/powernv: Only clear EEH freeze for some errors

Only clear an EEH freeze if an error occurs. However, if an OPAL_HARDWARE
error is returned, this indicates a hardware failure which cannot be
unfrozen, and instead needs a hardware reset. Attempting to unfreeze a
broken PCH will result in console spam for each attempt. To avoid the spam,
just don't do it.

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MFHead @347527

Sponsored by: The FreeBSD Foundation

Add NUMA support to powerpc

Summary:
Initial NUMA support:
- associate CPU with domain
- associate memory ranges with domain
- identify domain for devices
- limit device interrupt bi

Add NUMA support to powerpc

Summary:
Initial NUMA support:
- associate CPU with domain
- associate memory ranges with domain
- identify domain for devices
- limit device interrupt binding to appropriate domain

- Additionally fixes a bug in the setting of Maxmem which led to
only memory attached to the first socket being enabled for DMA

A pmap variant can opt in to numa support by by calling `numa_mem_regions`
at the end of pmap_bootstrap - registering the corresponding ranges with the
VM.

This yields a ~20% improvement in build times of llvm on dual socket POWER9
over non-NUMA.

Original patch by mmacy.

Differential Revision: https://reviews.freebsd.org/D17933

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powerpc: Add opaque 'private data' to interrupt vectors

The XICS and XIVE need extra data beyond irq and vector. Rather than
performing a separate search, it's better for the general interrupt faci

powerpc: Add opaque 'private data' to interrupt vectors

The XICS and XIVE need extra data beyond irq and vector. Rather than
performing a separate search, it's better for the general interrupt facility
to hold a private pointer, since the search already must be done anyway at
that level.

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Merge ^/head r340235 through r340367.

powerpc/powernv: Restrict the busdma tag to only POWER8

It seems this tag is causing problems on POWER9 systems. Since no POWER9 user
has encountered the problem fixed by r339589 just restrict it t

powerpc/powernv: Restrict the busdma tag to only POWER8

It seems this tag is causing problems on POWER9 systems. Since no POWER9 user
has encountered the problem fixed by r339589 just restrict it to POWER8 for now.
A better fix will likely be to update powerpc/busdma_machdep.c to handle the
window correctly.

Reported by: mmacy, others

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Merge ^/head r339015 through r339669.

ppc64: limited 32-bit DMA address range

Further investigation of issues with 32-bit DMA on PowerNV revealed that
its window is hardcoded by OPAL (at least in skiboot version 5.4.9) and
cannot be cha

ppc64: limited 32-bit DMA address range

Further investigation of issues with 32-bit DMA on PowerNV revealed that
its window is hardcoded by OPAL (at least in skiboot version 5.4.9) and
cannot be changed by the OS.
Thus, now jhb suggestion of limiting the range in PCI DMA tag seems
the best way to deal with it.

Reviewed by: jhibbits, nwhitehorn, sbruno
Approved by: jhibbits(mentor)
Differential Revision: https://reviews.freebsd.org/D17601

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powerpc64/powernv:opal_pci: Fix the alignment of the TCE table

The TCE table need only be aligned to the size of the table, not the size of
the TCE segment.

MFH r339206-r339212, r339215-r339239

Sponsored by: The FreeBSD Foundation

powerpc64/powernv: Don't mask MSIs in OPAL

Summary:
Discussing with Benjamin Herrenschmidt, MSIs, and edge-triggered
interrupts in general, must not be masked in XICS and XIVE, else
subsequent inter

powerpc64/powernv: Don't mask MSIs in OPAL

Summary:
Discussing with Benjamin Herrenschmidt, MSIs, and edge-triggered
interrupts in general, must not be masked in XICS and XIVE, else
subsequent interrupts may be ignored.

Testing locally on my Talos II (single CPU, 18-core POWER9), NVMe now
works with MSI, improving read throughput by ~70% (900MB/s -> 1.67GB/s,
with 64MB block size) over INTx interrupts, and snd_hda(4) now will
actually play music with MSI. Previously, snd_hda(4) would not receive
interrupts, timing out, and declaring the channels dead.

This has also been tested by Kevin Bowling, and others, with great
success. Kevin reported NVMe unusable on his Talos II prior to this
patch.

Reviewed by: nwhitehorn, kbowling
Approved by: re(rgrimes)
Differential Revision: https://reviews.freebsd.org/D17356

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powerpc64/powernv: Avoid type promotion

There is a type promotion that transform count = -1 into a unsigned int causing
the default TCE SEG SIZE not being returned on a Boston POWER9 machine.

This

powerpc64/powernv: Avoid type promotion

There is a type promotion that transform count = -1 into a unsigned int causing
the default TCE SEG SIZE not being returned on a Boston POWER9 machine.

This machine does not have the 'ibm,supported-tce-sizes' entries, thus, count
is set to -1, and the function continue to execute instead of returning.

Reviewed by: jhibbits, wma
Approved by: jhibbits (mentor)
Differential Revision: https://reviews.freebsd.org/D15763

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Remove a debug printf from opal_pci driver