1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $NetBSD: spr.h,v 1.25 2002/08/14 15:38:40 matt Exp $ 29 * $FreeBSD$ 30 */ 31 #ifndef _POWERPC_SPR_H_ 32 #define _POWERPC_SPR_H_ 33 34 #ifndef _LOCORE 35 #define mtspr(reg, val) \ 36 __asm __volatile("mtspr %0,%1" : : "K"(reg), "r"(val)) 37 #define mfspr(reg) \ 38 ( { register_t val; \ 39 __asm __volatile("mfspr %0,%1" : "=r"(val) : "K"(reg)); \ 40 val; } ) 41 42 43 #ifndef __powerpc64__ 44 45 /* The following routines allow manipulation of the full 64-bit width 46 * of SPRs on 64 bit CPUs in bridge mode */ 47 48 #define mtspr64(reg,valhi,vallo,scratch) \ 49 __asm __volatile(" \ 50 mfmsr %0; \ 51 insrdi %0,%5,1,0; \ 52 mtmsrd %0; \ 53 isync; \ 54 \ 55 sld %1,%1,%4; \ 56 or %1,%1,%2; \ 57 mtspr %3,%1; \ 58 srd %1,%1,%4; \ 59 \ 60 clrldi %0,%0,1; \ 61 mtmsrd %0; \ 62 isync;" \ 63 : "=r"(scratch), "=r"(valhi) : "r"(vallo), "K"(reg), "r"(32), "r"(1)) 64 65 #define mfspr64upper(reg,scratch) \ 66 ( { register_t val; \ 67 __asm __volatile(" \ 68 mfmsr %0; \ 69 insrdi %0,%4,1,0; \ 70 mtmsrd %0; \ 71 isync; \ 72 \ 73 mfspr %1,%2; \ 74 srd %1,%1,%3; \ 75 \ 76 clrldi %0,%0,1; \ 77 mtmsrd %0; \ 78 isync;" \ 79 : "=r"(scratch), "=r"(val) : "K"(reg), "r"(32), "r"(1)); \ 80 val; } ) 81 82 #endif 83 84 #endif /* _LOCORE */ 85 86 /* 87 * Special Purpose Register declarations. 88 * 89 * The first column in the comments indicates which PowerPC 90 * architectures the SPR is valid on - 4 for 4xx series, 91 * 6 for 6xx/7xx series and 8 for 8xx and 8xxx series. 92 */ 93 94 #define SPR_MQ 0x000 /* .6. 601 MQ register */ 95 #define SPR_XER 0x001 /* 468 Fixed Point Exception Register */ 96 #define SPR_DSCR 0x003 /* .6. Data Stream Control Register (Unprivileged) */ 97 #define SPR_RTCU_R 0x004 /* .6. 601 RTC Upper - Read */ 98 #define SPR_RTCL_R 0x005 /* .6. 601 RTC Lower - Read */ 99 #define SPR_LR 0x008 /* 468 Link Register */ 100 #define SPR_CTR 0x009 /* 468 Count Register */ 101 #define SPR_DSCRP 0x011 /* Data Stream Control Register (Privileged) */ 102 #define SPR_DSISR 0x012 /* .68 DSI exception source */ 103 #define DSISR_DIRECT 0x80000000 /* Direct-store error exception */ 104 #define DSISR_NOTFOUND 0x40000000 /* Translation not found */ 105 #define DSISR_PROTECT 0x08000000 /* Memory access not permitted */ 106 #define DSISR_INVRX 0x04000000 /* Reserve-indexed insn direct-store access */ 107 #define DSISR_STORE 0x02000000 /* Store operation */ 108 #define DSISR_DABR 0x00400000 /* DABR match */ 109 #define DSISR_SEGMENT 0x00200000 /* XXX; not in 6xx PEM */ 110 #define DSISR_EAR 0x00100000 /* eciwx/ecowx && EAR[E] == 0 */ 111 #define DSISR_MC_UE_DEFERRED 0x00008000 /* UE deferred error */ 112 #define DSISR_MC_UE_TABLEWALK 0x00004000 /* UE deferred error during tablewalk */ 113 #define DSISR_MC_DERAT_MULTIHIT 0x00000800 /* D-ERAT multi-hit */ 114 #define DSISR_MC_TLB_MULTIHIT 0x00000400 /* TLB multi-hit */ 115 #define DSISR_MC_TLBIE_ERR 0x00000200 /* TLBIE or TLBIEL programming error */ 116 #define DSISR_MC_SLB_PARITY 0x00000100 /* SLB parity error */ 117 #define DSISR_MC_SLB_MULTIHIT 0x00000080 /* SLB Multi-hit detected (D-side) */ 118 #define DSISR_MC_BAD_REAL_LD 0x00000040 /* Bad real address for load. */ 119 #define DSISR_MC_BAD_ADDR 0x00000020 /* Bad address for load or store tablewalk */ 120 #define SPR_DAR 0x013 /* .68 Data Address Register */ 121 #define SPR_RTCU_W 0x014 /* .6. 601 RTC Upper - Write */ 122 #define SPR_RTCL_W 0x015 /* .6. 601 RTC Lower - Write */ 123 #define SPR_DEC 0x016 /* .68 DECrementer register */ 124 #define SPR_SDR1 0x019 /* .68 Page table base address register */ 125 #define SPR_SRR0 0x01a /* 468 Save/Restore Register 0 */ 126 #define SPR_SRR1 0x01b /* 468 Save/Restore Register 1 */ 127 #define SRR1_ISI_PFAULT 0x40000000 /* ISI page not found */ 128 #define SRR1_ISI_NOEXECUTE 0x10000000 /* Memory marked no-execute */ 129 #define SRR1_ISI_PP 0x08000000 /* PP bits forbid access */ 130 #define SRR1_MCHK_DATA 0x00200000 /* Machine check data in DSISR */ 131 #define SRR1_MCHK_IFETCH_M 0x081c0000 /* Machine check instr fetch mask */ 132 #define SRR1_MCHK_IFETCH_SLBMH 0x000c0000 /* SLB multihit */ 133 #define SPR_CFAR 0x01c /* Come From Address Register */ 134 #define SPR_AMR 0x01d /* Authority Mask Register */ 135 136 #define SPR_PID 0x030 /* 4.. Process ID */ 137 138 #define SPR_DECAR 0x036 /* ..8 Decrementer auto reload */ 139 #define SPR_IAMR 0x03d /* Instr. Authority Mask Reg */ 140 141 #define SPR_EIE 0x050 /* ..8 Exception Interrupt ??? */ 142 #define SPR_EID 0x051 /* ..8 Exception Interrupt ??? */ 143 #define SPR_NRI 0x052 /* ..8 Exception Interrupt ??? */ 144 #define SPR_FSCR 0x099 /* Facility Status and Control Register */ 145 #define FSCR_IC_MASK 0xFF00000000000000ULL /* FSCR[0:7] is Interrupt Cause */ 146 #define FSCR_IC_FP 0x0000000000000000ULL /* FP unavailable */ 147 #define FSCR_IC_VSX 0x0100000000000000ULL /* VSX unavailable */ 148 #define FSCR_IC_DSCR 0x0200000000000000ULL /* Access to the DSCR at SPRs 3 or 17 */ 149 #define FSCR_IC_PM 0x0300000000000000ULL /* Read or write access of a Performance Monitor SPR in group A */ 150 #define FSCR_IC_BHRB 0x0400000000000000ULL /* Execution of a BHRB Instruction */ 151 #define FSCR_IC_HTM 0x0500000000000000ULL /* Access to a Transactional Memory */ 152 /* Reserved 0x0600000000000000ULL */ 153 #define FSCR_IC_EBB 0x0700000000000000ULL /* Access to Event-Based Branch */ 154 #define FSCR_IC_TAR 0x0800000000000000ULL /* Access to Target Address Register */ 155 #define FSCR_IC_STOP 0x0900000000000000ULL /* Access to the 'stop' instruction in privileged non-hypervisor state */ 156 #define FSCR_IC_MSG 0x0A00000000000000ULL /* Access to 'msgsndp' or 'msgclrp' instructions */ 157 #define FSCR_IC_LM 0x0A00000000000000ULL /* Access to load monitored facility */ 158 #define FSCR_IC_SCV 0x0C00000000000000ULL /* Execution of a 'scv' instruction */ 159 #define FSCR_SCV 0x0000000000001000 /* scv instruction available */ 160 #define FSCR_LM 0x0000000000000800 /* Load monitored facilities available */ 161 #define FSCR_MSGP 0x0000000000000400 /* msgsndp and SPRs available */ 162 #define FSCR_TAR 0x0000000000000100 /* TAR register available */ 163 #define FSCR_EBB 0x0000000000000080 /* Event-based branch available */ 164 #define FSCR_DSCR 0x0000000000000004 /* DSCR available in PR state */ 165 #define SPR_UAMOR 0x09d /* User Authority Mask Override Register */ 166 #define SPR_DPDES 0x0b0 /* .6. Directed Privileged Doorbell Exception State Register */ 167 #define SPR_USPRG0 0x100 /* 4.8 User SPR General 0 */ 168 #define SPR_VRSAVE 0x100 /* .6. AltiVec VRSAVE */ 169 #define SPR_SPRG0 0x110 /* 468 SPR General 0 */ 170 #define SPR_SPRG1 0x111 /* 468 SPR General 1 */ 171 #define SPR_SPRG2 0x112 /* 468 SPR General 2 */ 172 #define SPR_SPRG3 0x113 /* 468 SPR General 3 */ 173 #define SPR_SPRG4 0x114 /* 4.8 SPR General 4 */ 174 #define SPR_SPRG5 0x115 /* 4.8 SPR General 5 */ 175 #define SPR_SPRG6 0x116 /* 4.8 SPR General 6 */ 176 #define SPR_SPRG7 0x117 /* 4.8 SPR General 7 */ 177 #define SPR_SCOMC 0x114 /* ... SCOM Address Register (970) */ 178 #define SPR_SCOMD 0x115 /* ... SCOM Data Register (970) */ 179 #define SPR_ASR 0x118 /* ... Address Space Register (PPC64) */ 180 #define SPR_EAR 0x11a /* .68 External Access Register */ 181 #define SPR_PVR 0x11f /* 468 Processor Version Register */ 182 #define MPC601 0x0001 183 #define MPC603 0x0003 184 #define MPC604 0x0004 185 #define MPC602 0x0005 186 #define MPC603e 0x0006 187 #define MPC603ev 0x0007 188 #define MPC750 0x0008 189 #define MPC750CL 0x7000 /* Nintendo Wii's Broadway */ 190 #define MPC604ev 0x0009 191 #define MPC7400 0x000c 192 #define MPC620 0x0014 193 #define IBM403 0x0020 194 #define IBM401A1 0x0021 195 #define IBM401B2 0x0022 196 #define IBM401C2 0x0023 197 #define IBM401D2 0x0024 198 #define IBM401E2 0x0025 199 #define IBM401F2 0x0026 200 #define IBM401G2 0x0027 201 #define IBMRS64II 0x0033 202 #define IBMRS64III 0x0034 203 #define IBMPOWER4 0x0035 204 #define IBMRS64III_2 0x0036 205 #define IBMRS64IV 0x0037 206 #define IBMPOWER4PLUS 0x0038 207 #define IBM970 0x0039 208 #define IBMPOWER5 0x003a 209 #define IBMPOWER5PLUS 0x003b 210 #define IBM970FX 0x003c 211 #define IBMPOWER6 0x003e 212 #define IBMPOWER7 0x003f 213 #define IBMPOWER3 0x0040 214 #define IBMPOWER3PLUS 0x0041 215 #define IBM970MP 0x0044 216 #define IBM970GX 0x0045 217 #define IBMPOWERPCA2 0x0049 218 #define IBMPOWER7PLUS 0x004a 219 #define IBMPOWER8E 0x004b 220 #define IBMPOWER8NVL 0x004c 221 #define IBMPOWER8 0x004d 222 #define IBMPOWER9 0x004e 223 #define MPC860 0x0050 224 #define IBMCELLBE 0x0070 225 #define MPC8240 0x0081 226 #define PA6T 0x0090 227 #define IBM405GP 0x4011 228 #define IBM405L 0x4161 229 #define IBM750FX 0x7000 230 #define MPC745X_P(v) ((v & 0xFFF8) == 0x8000) 231 #define MPC7450 0x8000 232 #define MPC7455 0x8001 233 #define MPC7457 0x8002 234 #define MPC7447A 0x8003 235 #define MPC7448 0x8004 236 #define MPC7410 0x800c 237 #define MPC8245 0x8081 238 #define FSL_E500v1 0x8020 239 #define FSL_E500v2 0x8021 240 #define FSL_E500mc 0x8023 241 #define FSL_E5500 0x8024 242 #define FSL_E6500 0x8040 243 #define FSL_E300C1 0x8083 244 #define FSL_E300C2 0x8084 245 #define FSL_E300C3 0x8085 246 #define FSL_E300C4 0x8086 247 248 #define LPCR_PECE_WAKESET (LPCR_PECE_EXT | LPCR_PECE_DECR | LPCR_PECE_ME) 249 250 #define SPR_DBSR 0x130 /* ..8 Debug Status Register */ 251 #define DBSR_IDE 0x80000000 /* Imprecise debug event. */ 252 #define DBSR_UDE 0x40000000 /* Unconditional debug event. */ 253 #define DBSR_MRR 0x30000000 /* Most recent Reset (mask). */ 254 #define DBSR_ICMP 0x08000000 /* Instr. complete debug event. */ 255 #define DBSR_BRT 0x04000000 /* Branch taken debug event. */ 256 #define DBSR_IRPT 0x02000000 /* Interrupt taken debug event. */ 257 #define DBSR_TRAP 0x01000000 /* Trap instr. debug event. */ 258 #define DBSR_IAC1 0x00800000 /* Instr. address compare #1. */ 259 #define DBSR_IAC2 0x00400000 /* Instr. address compare #2. */ 260 #define DBSR_IAC3 0x00200000 /* Instr. address compare #3. */ 261 #define DBSR_IAC4 0x00100000 /* Instr. address compare #4. */ 262 #define DBSR_DAC1R 0x00080000 /* Data addr. read compare #1. */ 263 #define DBSR_DAC1W 0x00040000 /* Data addr. write compare #1. */ 264 #define DBSR_DAC2R 0x00020000 /* Data addr. read compare #2. */ 265 #define DBSR_DAC2W 0x00010000 /* Data addr. write compare #2. */ 266 #define DBSR_RET 0x00008000 /* Return debug event. */ 267 #define SPR_EPCR 0x133 268 #define EPCR_EXTGS 0x80000000 269 #define EPCR_DTLBGS 0x40000000 270 #define EPCR_ITLBGS 0x20000000 271 #define EPCR_DSIGS 0x10000000 272 #define EPCR_ISIGS 0x08000000 273 #define EPCR_DUVGS 0x04000000 274 #define EPCR_ICM 0x02000000 275 #define EPCR_GICMGS 0x01000000 276 #define EPCR_DGTMI 0x00800000 277 #define EPCR_DMIUH 0x00400000 278 #define EPCR_PMGS 0x00200000 279 #define SPR_DBCR0 0x134 /* ..8 Debug Control Register 0 */ 280 #define SPR_DBCR1 0x135 /* ..8 Debug Control Register 1 */ 281 #define SPR_IAC1 0x138 /* ..8 Instruction Address Compare 1 */ 282 #define SPR_IAC2 0x139 /* ..8 Instruction Address Compare 2 */ 283 #define SPR_IAC3 0x13a /* ..8 Instruction Address Compare 3 */ 284 #define SPR_IAC4 0x13b /* ..8 Instruction Address Compare 4 */ 285 286 #define SPR_HSRR0 0x13a 287 #define SPR_HSRR1 0x13b 288 #define SPR_DAC1 0x13c /* ..8 Data Address Compare 1 */ 289 #define SPR_DAC2 0x13d /* ..8 Data Address Compare 2 */ 290 #define SPR_DVC1 0x13e /* ..8 Data Value Compare 1 */ 291 #define SPR_DVC2 0x13f /* ..8 Data Value Compare 2 */ 292 293 #define SPR_LPCR 0x13e /* .6. Logical Partitioning Control */ 294 #define LPCR_LPES 0x008 /* Bit 60 */ 295 #define LPCR_HVICE 0x002 /* Hypervisor Virtualization Interrupt (Arch 3.0) */ 296 #define LPCR_UPRT (1ULL << 22) /* Use Process Table (ISA 3) */ 297 #define LPCR_HR (1ULL << 20) /* Host Radix mode */ 298 #define LPCR_PECE_DRBL (1ULL << 16) /* Directed Privileged Doorbell */ 299 #define LPCR_PECE_HDRBL (1ULL << 15) /* Directed Hypervisor Doorbell */ 300 #define LPCR_PECE_EXT (1ULL << 14) /* External exceptions */ 301 #define LPCR_PECE_DECR (1ULL << 13) /* Decrementer exceptions */ 302 #define LPCR_PECE_ME (1ULL << 12) /* Machine Check and Hypervisor */ 303 /* Maintenance exceptions */ 304 #define SPR_LPID 0x13f /* .6. Logical Partitioning Control */ 305 #define SPR_HMER 0x150 /* Hypervisor Maintenance Exception Register */ 306 #define SPR_HMEER 0x151 /* Hypervisor Maintenance Exception Enable Register */ 307 #define SPR_AMOR 0x15d /* Authority Mask Override Register */ 308 309 #define SPR_TIR 0x1be /* .6. Thread Identification Register */ 310 #define SPR_PTCR 0x1d0 /* Partition Table Control Register */ 311 #define SPR_SPEFSCR 0x200 /* ..8 Signal Processing Engine FSCR. */ 312 #define SPEFSCR_SOVH 0x80000000 313 #define SPEFSCR_OVH 0x40000000 314 #define SPEFSCR_FGH 0x20000000 315 #define SPEFSCR_FXH 0x10000000 316 #define SPEFSCR_FINVH 0x08000000 317 #define SPEFSCR_FDBZH 0x04000000 318 #define SPEFSCR_FUNFH 0x02000000 319 #define SPEFSCR_FOVFH 0x01000000 320 #define SPEFSCR_FINXS 0x00200000 321 #define SPEFSCR_FINVS 0x00100000 322 #define SPEFSCR_FDBZS 0x00080000 323 #define SPEFSCR_FUNFS 0x00040000 324 #define SPEFSCR_FOVFS 0x00020000 325 #define SPEFSCR_SOV 0x00008000 326 #define SPEFSCR_OV 0x00004000 327 #define SPEFSCR_FG 0x00002000 328 #define SPEFSCR_FX 0x00001000 329 #define SPEFSCR_FINV 0x00000800 330 #define SPEFSCR_FDBZ 0x00000400 331 #define SPEFSCR_FUNF 0x00000200 332 #define SPEFSCR_FOVF 0x00000100 333 #define SPEFSCR_FINXE 0x00000040 334 #define SPEFSCR_FINVE 0x00000020 335 #define SPEFSCR_FDBZE 0x00000010 336 #define SPEFSCR_FUNFE 0x00000008 337 #define SPEFSCR_FOVFE 0x00000004 338 #define SPEFSCR_FRMC_M 0x00000003 339 #define SPR_IBAT0U 0x210 /* .6. Instruction BAT Reg 0 Upper */ 340 #define SPR_IBAT0L 0x211 /* .6. Instruction BAT Reg 0 Lower */ 341 #define SPR_IBAT1U 0x212 /* .6. Instruction BAT Reg 1 Upper */ 342 #define SPR_IBAT1L 0x213 /* .6. Instruction BAT Reg 1 Lower */ 343 #define SPR_IBAT2U 0x214 /* .6. Instruction BAT Reg 2 Upper */ 344 #define SPR_IBAT2L 0x215 /* .6. Instruction BAT Reg 2 Lower */ 345 #define SPR_IBAT3U 0x216 /* .6. Instruction BAT Reg 3 Upper */ 346 #define SPR_IBAT3L 0x217 /* .6. Instruction BAT Reg 3 Lower */ 347 #define SPR_DBAT0U 0x218 /* .6. Data BAT Reg 0 Upper */ 348 #define SPR_DBAT0L 0x219 /* .6. Data BAT Reg 0 Lower */ 349 #define SPR_DBAT1U 0x21a /* .6. Data BAT Reg 1 Upper */ 350 #define SPR_DBAT1L 0x21b /* .6. Data BAT Reg 1 Lower */ 351 #define SPR_DBAT2U 0x21c /* .6. Data BAT Reg 2 Upper */ 352 #define SPR_DBAT2L 0x21d /* .6. Data BAT Reg 2 Lower */ 353 #define SPR_DBAT3U 0x21e /* .6. Data BAT Reg 3 Upper */ 354 #define SPR_DBAT3L 0x21f /* .6. Data BAT Reg 3 Lower */ 355 #define SPR_IC_CST 0x230 /* ..8 Instruction Cache CSR */ 356 #define IC_CST_IEN 0x80000000 /* I cache is ENabled (RO) */ 357 #define IC_CST_CMD_INVALL 0x0c000000 /* I cache invalidate all */ 358 #define IC_CST_CMD_UNLOCKALL 0x0a000000 /* I cache unlock all */ 359 #define IC_CST_CMD_UNLOCK 0x08000000 /* I cache unlock block */ 360 #define IC_CST_CMD_LOADLOCK 0x06000000 /* I cache load & lock block */ 361 #define IC_CST_CMD_DISABLE 0x04000000 /* I cache disable */ 362 #define IC_CST_CMD_ENABLE 0x02000000 /* I cache enable */ 363 #define IC_CST_CCER1 0x00200000 /* I cache error type 1 (RO) */ 364 #define IC_CST_CCER2 0x00100000 /* I cache error type 2 (RO) */ 365 #define IC_CST_CCER3 0x00080000 /* I cache error type 3 (RO) */ 366 #define SPR_IBAT4U 0x230 /* .6. Instruction BAT Reg 4 Upper */ 367 #define SPR_IC_ADR 0x231 /* ..8 Instruction Cache Address */ 368 #define SPR_IBAT4L 0x231 /* .6. Instruction BAT Reg 4 Lower */ 369 #define SPR_IC_DAT 0x232 /* ..8 Instruction Cache Data */ 370 #define SPR_IBAT5U 0x232 /* .6. Instruction BAT Reg 5 Upper */ 371 #define SPR_IBAT5L 0x233 /* .6. Instruction BAT Reg 5 Lower */ 372 #define SPR_IBAT6U 0x234 /* .6. Instruction BAT Reg 6 Upper */ 373 #define SPR_IBAT6L 0x235 /* .6. Instruction BAT Reg 6 Lower */ 374 #define SPR_IBAT7U 0x236 /* .6. Instruction BAT Reg 7 Upper */ 375 #define SPR_IBAT7L 0x237 /* .6. Instruction BAT Reg 7 Lower */ 376 #define SPR_DC_CST 0x230 /* ..8 Data Cache CSR */ 377 #define DC_CST_DEN 0x80000000 /* D cache ENabled (RO) */ 378 #define DC_CST_DFWT 0x40000000 /* D cache Force Write-Thru (RO) */ 379 #define DC_CST_LES 0x20000000 /* D cache Little Endian Swap (RO) */ 380 #define DC_CST_CMD_FLUSH 0x0e000000 /* D cache invalidate all */ 381 #define DC_CST_CMD_INVALL 0x0c000000 /* D cache invalidate all */ 382 #define DC_CST_CMD_UNLOCKALL 0x0a000000 /* D cache unlock all */ 383 #define DC_CST_CMD_UNLOCK 0x08000000 /* D cache unlock block */ 384 #define DC_CST_CMD_CLRLESWAP 0x07000000 /* D cache clr little-endian swap */ 385 #define DC_CST_CMD_LOADLOCK 0x06000000 /* D cache load & lock block */ 386 #define DC_CST_CMD_SETLESWAP 0x05000000 /* D cache set little-endian swap */ 387 #define DC_CST_CMD_DISABLE 0x04000000 /* D cache disable */ 388 #define DC_CST_CMD_CLRFWT 0x03000000 /* D cache clear forced write-thru */ 389 #define DC_CST_CMD_ENABLE 0x02000000 /* D cache enable */ 390 #define DC_CST_CMD_SETFWT 0x01000000 /* D cache set forced write-thru */ 391 #define DC_CST_CCER1 0x00200000 /* D cache error type 1 (RO) */ 392 #define DC_CST_CCER2 0x00100000 /* D cache error type 2 (RO) */ 393 #define DC_CST_CCER3 0x00080000 /* D cache error type 3 (RO) */ 394 #define SPR_DBAT4U 0x238 /* .6. Data BAT Reg 4 Upper */ 395 #define SPR_DC_ADR 0x231 /* ..8 Data Cache Address */ 396 #define SPR_DBAT4L 0x239 /* .6. Data BAT Reg 4 Lower */ 397 #define SPR_DC_DAT 0x232 /* ..8 Data Cache Data */ 398 #define SPR_DBAT5U 0x23a /* .6. Data BAT Reg 5 Upper */ 399 #define SPR_DBAT5L 0x23b /* .6. Data BAT Reg 5 Lower */ 400 #define SPR_DBAT6U 0x23c /* .6. Data BAT Reg 6 Upper */ 401 #define SPR_DBAT6L 0x23d /* .6. Data BAT Reg 6 Lower */ 402 #define SPR_DBAT7U 0x23e /* .6. Data BAT Reg 7 Upper */ 403 #define SPR_DBAT7L 0x23f /* .6. Data BAT Reg 7 Lower */ 404 #define SPR_SPRG8 0x25c /* ..8 SPR General 8 */ 405 #define SPR_MI_CTR 0x310 /* ..8 IMMU control */ 406 #define Mx_CTR_GPM 0x80000000 /* Group Protection Mode */ 407 #define Mx_CTR_PPM 0x40000000 /* Page Protection Mode */ 408 #define Mx_CTR_CIDEF 0x20000000 /* Cache-Inhibit DEFault */ 409 #define MD_CTR_WTDEF 0x20000000 /* Write-Through DEFault */ 410 #define Mx_CTR_RSV4 0x08000000 /* Reserve 4 TLB entries */ 411 #define MD_CTR_TWAM 0x04000000 /* TableWalk Assist Mode */ 412 #define Mx_CTR_PPCS 0x02000000 /* Priv/user state compare mode */ 413 #define Mx_CTR_TLB_INDX 0x000001f0 /* TLB index mask */ 414 #define Mx_CTR_TLB_INDX_BITPOS 8 /* TLB index shift */ 415 #define SPR_MI_AP 0x312 /* ..8 IMMU access protection */ 416 #define Mx_GP_SUPER(n) (0 << (2*(15-(n)))) /* access is supervisor */ 417 #define Mx_GP_PAGE (1 << (2*(15-(n)))) /* access is page protect */ 418 #define Mx_GP_SWAPPED (2 << (2*(15-(n)))) /* access is swapped */ 419 #define Mx_GP_USER (3 << (2*(15-(n)))) /* access is user */ 420 #define SPR_MI_EPN 0x313 /* ..8 IMMU effective number */ 421 #define Mx_EPN_EPN 0xfffff000 /* Effective Page Number mask */ 422 #define Mx_EPN_EV 0x00000020 /* Entry Valid */ 423 #define Mx_EPN_ASID 0x0000000f /* Address Space ID */ 424 #define SPR_MI_TWC 0x315 /* ..8 IMMU tablewalk control */ 425 #define MD_TWC_L2TB 0xfffff000 /* Level-2 Tablewalk Base */ 426 #define Mx_TWC_APG 0x000001e0 /* Access Protection Group */ 427 #define Mx_TWC_G 0x00000010 /* Guarded memory */ 428 #define Mx_TWC_PS 0x0000000c /* Page Size (L1) */ 429 #define MD_TWC_WT 0x00000002 /* Write-Through */ 430 #define Mx_TWC_V 0x00000001 /* Entry Valid */ 431 #define SPR_MI_RPN 0x316 /* ..8 IMMU real (phys) page number */ 432 #define Mx_RPN_RPN 0xfffff000 /* Real Page Number */ 433 #define Mx_RPN_PP 0x00000ff0 /* Page Protection */ 434 #define Mx_RPN_SPS 0x00000008 /* Small Page Size */ 435 #define Mx_RPN_SH 0x00000004 /* SHared page */ 436 #define Mx_RPN_CI 0x00000002 /* Cache Inhibit */ 437 #define Mx_RPN_V 0x00000001 /* Valid */ 438 #define SPR_MD_CTR 0x318 /* ..8 DMMU control */ 439 #define SPR_M_CASID 0x319 /* ..8 CASID */ 440 #define M_CASID 0x0000000f /* Current AS Id */ 441 #define SPR_MD_AP 0x31a /* ..8 DMMU access protection */ 442 #define SPR_MD_EPN 0x31b /* ..8 DMMU effective number */ 443 444 #define SPR_970MMCR0 0x31b /* ... Monitor Mode Control Register 0 (PPC 970) */ 445 #define SPR_970MMCR0_PMC1SEL(x) ((x) << 8) /* PMC1 selector (970) */ 446 #define SPR_970MMCR0_PMC2SEL(x) ((x) << 1) /* PMC2 selector (970) */ 447 #define SPR_970MMCR1 0x31e /* ... Monitor Mode Control Register 1 (PPC 970) */ 448 #define SPR_970MMCR1_PMC3SEL(x) (((x) & 0x1f) << 27) /* PMC 3 selector */ 449 #define SPR_970MMCR1_PMC4SEL(x) (((x) & 0x1f) << 22) /* PMC 4 selector */ 450 #define SPR_970MMCR1_PMC5SEL(x) (((x) & 0x1f) << 17) /* PMC 5 selector */ 451 #define SPR_970MMCR1_PMC6SEL(x) (((x) & 0x1f) << 12) /* PMC 6 selector */ 452 #define SPR_970MMCR1_PMC7SEL(x) (((x) & 0x1f) << 7) /* PMC 7 selector */ 453 #define SPR_970MMCR1_PMC8SEL(x) (((x) & 0x1f) << 2) /* PMC 8 selector */ 454 #define SPR_970MMCRA 0x312 /* ... Monitor Mode Control Register 2 (PPC 970) */ 455 #define SPR_970PMC1 0x313 /* ... PMC 1 */ 456 #define SPR_970PMC2 0x314 /* ... PMC 2 */ 457 #define SPR_970PMC3 0x315 /* ... PMC 3 */ 458 #define SPR_970PMC4 0x316 /* ... PMC 4 */ 459 #define SPR_970PMC5 0x317 /* ... PMC 5 */ 460 #define SPR_970PMC6 0x318 /* ... PMC 6 */ 461 #define SPR_970PMC7 0x319 /* ... PMC 7 */ 462 #define SPR_970PMC8 0x31a /* ... PMC 8 */ 463 464 #define SPR_M_TWB 0x31c /* ..8 MMU tablewalk base */ 465 #define M_TWB_L1TB 0xfffff000 /* level-1 translation base */ 466 #define M_TWB_L1INDX 0x00000ffc /* level-1 index */ 467 #define SPR_MD_TWC 0x31d /* ..8 DMMU tablewalk control */ 468 #define SPR_MD_RPN 0x31e /* ..8 DMMU real (phys) page number */ 469 #define SPR_MD_TW 0x31f /* ..8 MMU tablewalk scratch */ 470 #define SPR_BESCRS 0x320 /* .6. Branch Event Status and Control Set Register */ 471 #define SPR_BESCRSU 0x321 /* .6. Branch Event Status and Control Set Register (upper 32-bit) */ 472 #define SPR_BESCRR 0x322 /* .6. Branch Event Status and Control Reset Register */ 473 #define SPR_BESCRRU 0x323 /* .6. Branch Event Status and Control Register (upper 32-bit) */ 474 #define SPR_EBBHR 0x324 /* .6. Event-based Branch Handler Register */ 475 #define SPR_EBBRR 0x325 /* .6. Event-based Branch Return Register */ 476 #define SPR_BESCR 0x326 /* .6. Branch Event Status and Control Register */ 477 #define SPR_LMRR 0x32d /* .6. Load Monitored Region Register */ 478 #define SPR_LMSER 0x32e /* .6. Load Monitored Section Enable Register */ 479 #define SPR_TAR 0x32f /* .6. Branch Target Address Register */ 480 #define SPR_MI_CAM 0x330 /* ..8 IMMU CAM entry read */ 481 #define SPR_MI_RAM0 0x331 /* ..8 IMMU RAM entry read reg 0 */ 482 #define SPR_MI_RAM1 0x332 /* ..8 IMMU RAM entry read reg 1 */ 483 #define SPR_MD_CAM 0x338 /* ..8 IMMU CAM entry read */ 484 #define SPR_MD_RAM0 0x339 /* ..8 IMMU RAM entry read reg 0 */ 485 #define SPR_MD_RAM1 0x33a /* ..8 IMMU RAM entry read reg 1 */ 486 #define SPR_PSSCR 0x357 /* Processor Stop Status and Control Register (ISA 3.0) */ 487 #define PSSCR_PLS_S 60 488 #define PSSCR_PLS_M (0xf << PSSCR_PLS_S) 489 #define PSSCR_SD (1 << 22) 490 #define PSSCR_ESL (1 << 21) 491 #define PSSCR_EC (1 << 20) 492 #define PSSCR_PSLL_S 16 493 #define PSSCR_PSLL_M (0xf << PSSCR_PSLL_S) 494 #define PSSCR_TR_S 8 495 #define PSSCR_TR_M (0x3 << PSSCR_TR_S) 496 #define PSSCR_MTL_S 4 497 #define PSSCR_MTL_M (0xf << PSSCR_MTL_S) 498 #define PSSCR_RL_S 0 499 #define PSSCR_RL_M (0xf << PSSCR_RL_S) 500 #define SPR_PMCR 0x374 /* Processor Management Control Register */ 501 #define SPR_UMMCR2 0x3a0 /* .6. User Monitor Mode Control Register 2 */ 502 #define SPR_UMMCR0 0x3a8 /* .6. User Monitor Mode Control Register 0 */ 503 #define SPR_USIA 0x3ab /* .6. User Sampled Instruction Address */ 504 #define SPR_UMMCR1 0x3ac /* .6. User Monitor Mode Control Register 1 */ 505 #define SPR_MMCR2 0x3b0 /* .6. Monitor Mode Control Register 2 */ 506 #define SPR_MMCR2_THRESHMULT_32 0x80000000 /* Multiply MMCR0 threshold by 32 */ 507 #define SPR_MMCR2_THRESHMULT_2 0x00000000 /* Multiply MMCR0 threshold by 2 */ 508 #define SPR_PMC5 0x3b1 /* .6. Performance Counter Register 5 */ 509 #define SPR_PMC6 0x3b2 /* .6. Performance Counter Register 6 */ 510 #define SPR_MMCR0 0x3b8 /* .6. Monitor Mode Control Register 0 */ 511 #define SPR_MMCR0_FC 0x80000000 /* Freeze counters */ 512 #define SPR_MMCR0_FCS 0x40000000 /* Freeze counters in supervisor mode */ 513 #define SPR_MMCR0_FCP 0x20000000 /* Freeze counters in user mode */ 514 #define SPR_MMCR0_FCM1 0x10000000 /* Freeze counters when mark=1 */ 515 #define SPR_MMCR0_FCM0 0x08000000 /* Freeze counters when mark=0 */ 516 #define SPR_MMCR0_PMXE 0x04000000 /* Enable PM interrupt */ 517 #define SPR_MMCR0_FCECE 0x02000000 /* Freeze counters after event */ 518 #define SPR_MMCR0_TBSEL_15 0x01800000 /* Count bit 15 of TBL */ 519 #define SPR_MMCR0_TBSEL_19 0x01000000 /* Count bit 19 of TBL */ 520 #define SPR_MMCR0_TBSEL_23 0x00800000 /* Count bit 23 of TBL */ 521 #define SPR_MMCR0_TBSEL_31 0x00000000 /* Count bit 31 of TBL */ 522 #define SPR_MMCR0_TBEE 0x00400000 /* Time-base event enable */ 523 #define SPR_MMCRO_THRESHOLD(x) ((x) << 16) /* Threshold value */ 524 #define SPR_MMCR0_PMC1CE 0x00008000 /* PMC1 condition enable */ 525 #define SPR_MMCR0_PMCNCE 0x00004000 /* PMCn condition enable */ 526 #define SPR_MMCR0_TRIGGER 0x00002000 /* Trigger */ 527 #define SPR_MMCR0_PMC1SEL(x) (((x) & 0x3f) << 6) /* PMC1 selector */ 528 #define SPR_MMCR0_PMC2SEL(x) (((x) & 0x3f) << 0) /* PMC2 selector */ 529 #define SPR_PMC1 0x3b9 /* .6. Performance Counter Register 1 */ 530 #define SPR_PMC2 0x3ba /* .6. Performance Counter Register 2 */ 531 #define SPR_SIA 0x3bb /* .6. Sampled Instruction Address */ 532 #define SPR_MMCR1 0x3bc /* .6. Monitor Mode Control Register 2 */ 533 #define SPR_MMCR1_PMC3SEL(x) (((x) & 0x1f) << 27) /* PMC 3 selector */ 534 #define SPR_MMCR1_PMC4SEL(x) (((x) & 0x1f) << 22) /* PMC 4 selector */ 535 #define SPR_MMCR1_PMC5SEL(x) (((x) & 0x1f) << 17) /* PMC 5 selector */ 536 #define SPR_MMCR1_PMC6SEL(x) (((x) & 0x3f) << 11) /* PMC 6 selector */ 537 538 #define SPR_PMC3 0x3bd /* .6. Performance Counter Register 3 */ 539 #define SPR_PMC4 0x3be /* .6. Performance Counter Register 4 */ 540 #define SPR_DMISS 0x3d0 /* .68 Data TLB Miss Address Register */ 541 #define SPR_DCMP 0x3d1 /* .68 Data TLB Compare Register */ 542 #define SPR_HASH1 0x3d2 /* .68 Primary Hash Address Register */ 543 #define SPR_HASH2 0x3d3 /* .68 Secondary Hash Address Register */ 544 #define SPR_IMISS 0x3d4 /* .68 Instruction TLB Miss Address Register */ 545 #define SPR_TLBMISS 0x3d4 /* .6. TLB Miss Address Register */ 546 #define SPR_DEAR 0x03d /* ..8 Data Exception Address Register */ 547 #define SPR_ICMP 0x3d5 /* .68 Instruction TLB Compare Register */ 548 #define SPR_PTEHI 0x3d5 /* .6. Instruction TLB Compare Register */ 549 #define SPR_RPA 0x3d6 /* .68 Required Physical Address Register */ 550 #define SPR_PTELO 0x3d6 /* .6. Required Physical Address Register */ 551 552 #define SPR_TSR 0x150 /* ..8 Timer Status Register */ 553 #define SPR_TCR 0x154 /* ..8 Timer Control Register */ 554 555 #define TSR_ENW 0x80000000 /* Enable Next Watchdog */ 556 #define TSR_WIS 0x40000000 /* Watchdog Interrupt Status */ 557 #define TSR_WRS_MASK 0x30000000 /* Watchdog Reset Status */ 558 #define TSR_WRS_NONE 0x00000000 /* No watchdog reset has occurred */ 559 #define TSR_WRS_CORE 0x10000000 /* Core reset was forced by the watchdog */ 560 #define TSR_WRS_CHIP 0x20000000 /* Chip reset was forced by the watchdog */ 561 #define TSR_WRS_SYSTEM 0x30000000 /* System reset was forced by the watchdog */ 562 #define TSR_PIS 0x08000000 /* PIT Interrupt Status */ 563 #define TSR_DIS 0x08000000 /* Decrementer Interrupt Status */ 564 #define TSR_FIS 0x04000000 /* FIT Interrupt Status */ 565 566 #define TCR_WP_MASK 0xc0000000 /* Watchdog Period mask */ 567 #define TCR_WP_2_17 0x00000000 /* 2**17 clocks */ 568 #define TCR_WP_2_21 0x40000000 /* 2**21 clocks */ 569 #define TCR_WP_2_25 0x80000000 /* 2**25 clocks */ 570 #define TCR_WP_2_29 0xc0000000 /* 2**29 clocks */ 571 #define TCR_WRC_MASK 0x30000000 /* Watchdog Reset Control mask */ 572 #define TCR_WRC_NONE 0x00000000 /* No watchdog reset */ 573 #define TCR_WRC_CORE 0x10000000 /* Core reset */ 574 #define TCR_WRC_CHIP 0x20000000 /* Chip reset */ 575 #define TCR_WRC_SYSTEM 0x30000000 /* System reset */ 576 #define TCR_WIE 0x08000000 /* Watchdog Interrupt Enable */ 577 #define TCR_PIE 0x04000000 /* PIT Interrupt Enable */ 578 #define TCR_DIE 0x04000000 /* Pecrementer Interrupt Enable */ 579 #define TCR_FP_MASK 0x03000000 /* FIT Period */ 580 #define TCR_FP_2_9 0x00000000 /* 2**9 clocks */ 581 #define TCR_FP_2_13 0x01000000 /* 2**13 clocks */ 582 #define TCR_FP_2_17 0x02000000 /* 2**17 clocks */ 583 #define TCR_FP_2_21 0x03000000 /* 2**21 clocks */ 584 #define TCR_FIE 0x00800000 /* FIT Interrupt Enable */ 585 #define TCR_ARE 0x00400000 /* Auto Reload Enable */ 586 587 #define SPR_HID0 0x3f0 /* ..8 Hardware Implementation Register 0 */ 588 #define SPR_HID1 0x3f1 /* ..8 Hardware Implementation Register 1 */ 589 #define SPR_HID2 0x3f3 /* ..8 Hardware Implementation Register 2 */ 590 #define SPR_HID4 0x3f4 /* ..8 Hardware Implementation Register 4 */ 591 #define SPR_HID5 0x3f6 /* ..8 Hardware Implementation Register 5 */ 592 #define SPR_HID6 0x3f9 /* ..8 Hardware Implementation Register 6 */ 593 594 #define SPR_CELL_TSRL 0x380 /* ... Cell BE Thread Status Register */ 595 #define SPR_CELL_TSCR 0x399 /* ... Cell BE Thread Switch Register */ 596 597 #if defined(AIM) 598 #define SPR_PIR 0x3ff /* .6. Processor Identification Register */ 599 #elif defined(BOOKE) 600 #define SPR_PIR 0x11e /* ..8 Processor Identification Register */ 601 #endif 602 603 #define DBCR0_EDM 0x80000000 /* External Debug Mode */ 604 #define DBCR0_IDM 0x40000000 /* Internal Debug Mode */ 605 #define DBCR0_RST_MASK 0x30000000 /* ReSeT */ 606 #define DBCR0_RST_NONE 0x00000000 /* No action */ 607 #define DBCR0_RST_CORE 0x10000000 /* Core reset */ 608 #define DBCR0_RST_CHIP 0x20000000 /* Chip reset */ 609 #define DBCR0_RST_SYSTEM 0x30000000 /* System reset */ 610 #define DBCR0_IC 0x08000000 /* Instruction Completion debug event */ 611 #define DBCR0_BT 0x04000000 /* Branch Taken debug event */ 612 #define DBCR0_EDE 0x02000000 /* Exception Debug Event */ 613 #define DBCR0_TDE 0x01000000 /* Trap Debug Event */ 614 #define DBCR0_IA1 0x00800000 /* IAC (Instruction Address Compare) 1 debug event */ 615 #define DBCR0_IA2 0x00400000 /* IAC 2 debug event */ 616 #define DBCR0_IA12 0x00200000 /* Instruction Address Range Compare 1-2 */ 617 #define DBCR0_IA12X 0x00100000 /* IA12 eXclusive */ 618 #define DBCR0_IA3 0x00080000 /* IAC 3 debug event */ 619 #define DBCR0_IA4 0x00040000 /* IAC 4 debug event */ 620 #define DBCR0_IA34 0x00020000 /* Instruction Address Range Compare 3-4 */ 621 #define DBCR0_IA34X 0x00010000 /* IA34 eXclusive */ 622 #define DBCR0_IA12T 0x00008000 /* Instruction Address Range Compare 1-2 range Toggle */ 623 #define DBCR0_IA34T 0x00004000 /* Instruction Address Range Compare 3-4 range Toggle */ 624 #define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */ 625 626 #define SPR_IABR 0x3f2 /* ..8 Instruction Address Breakpoint Register 0 */ 627 #define SPR_DABR 0x3f5 /* .6. Data Address Breakpoint Register */ 628 #define SPR_MSSCR0 0x3f6 /* .6. Memory SubSystem Control Register */ 629 #define MSSCR0_SHDEN 0x80000000 /* 0: Shared-state enable */ 630 #define MSSCR0_SHDPEN3 0x40000000 /* 1: ~SHD[01] signal enable in MEI mode */ 631 #define MSSCR0_L1INTVEN 0x38000000 /* 2-4: L1 data cache ~HIT intervention enable */ 632 #define MSSCR0_L2INTVEN 0x07000000 /* 5-7: L2 data cache ~HIT intervention enable*/ 633 #define MSSCR0_DL1HWF 0x00800000 /* 8: L1 data cache hardware flush */ 634 #define MSSCR0_MBO 0x00400000 /* 9: must be one */ 635 #define MSSCR0_EMODE 0x00200000 /* 10: MPX bus mode (read-only) */ 636 #define MSSCR0_ABD 0x00100000 /* 11: address bus driven (read-only) */ 637 #define MSSCR0_MBZ 0x000fffff /* 12-31: must be zero */ 638 #define MSSCR0_L2PFE 0x00000003 /* 30-31: L2 prefetch enable */ 639 #define SPR_MSSSR0 0x3f7 /* .6. Memory Subsystem Status Register (MPC745x) */ 640 #define MSSSR0_L2TAG 0x00040000 /* 13: L2 tag parity error */ 641 #define MSSSR0_L2DAT 0x00020000 /* 14: L2 data parity error */ 642 #define MSSSR0_L3TAG 0x00010000 /* 15: L3 tag parity error */ 643 #define MSSSR0_L3DAT 0x00008000 /* 16: L3 data parity error */ 644 #define MSSSR0_APE 0x00004000 /* 17: Address parity error */ 645 #define MSSSR0_DPE 0x00002000 /* 18: Data parity error */ 646 #define MSSSR0_TEA 0x00001000 /* 19: Bus transfer error acknowledge */ 647 #define SPR_LDSTCR 0x3f8 /* .6. Load/Store Control Register */ 648 #define SPR_L2PM 0x3f8 /* .6. L2 Private Memory Control Register */ 649 #define SPR_L2CR 0x3f9 /* .6. L2 Control Register */ 650 #define L2CR_L2E 0x80000000 /* 0: L2 enable */ 651 #define L2CR_L2PE 0x40000000 /* 1: L2 data parity enable */ 652 #define L2CR_L2SIZ 0x30000000 /* 2-3: L2 size */ 653 #define L2SIZ_2M 0x00000000 654 #define L2SIZ_256K 0x10000000 655 #define L2SIZ_512K 0x20000000 656 #define L2SIZ_1M 0x30000000 657 #define L2CR_L2CLK 0x0e000000 /* 4-6: L2 clock ratio */ 658 #define L2CLK_DIS 0x00000000 /* disable L2 clock */ 659 #define L2CLK_10 0x02000000 /* core clock / 1 */ 660 #define L2CLK_15 0x04000000 /* / 1.5 */ 661 #define L2CLK_20 0x08000000 /* / 2 */ 662 #define L2CLK_25 0x0a000000 /* / 2.5 */ 663 #define L2CLK_30 0x0c000000 /* / 3 */ 664 #define L2CR_L2RAM 0x01800000 /* 7-8: L2 RAM type */ 665 #define L2RAM_FLOWTHRU_BURST 0x00000000 666 #define L2RAM_PIPELINE_BURST 0x01000000 667 #define L2RAM_PIPELINE_LATE 0x01800000 668 #define L2CR_L2DO 0x00400000 /* 9: L2 data-only. 669 Setting this bit disables instruction 670 caching. */ 671 #define L2CR_L2I 0x00200000 /* 10: L2 global invalidate. */ 672 #define L2CR_L2IO_7450 0x00010000 /* 11: L2 instruction-only (MPC745x). */ 673 #define L2CR_L2CTL 0x00100000 /* 11: L2 RAM control (ZZ enable). 674 Enables automatic operation of the 675 L2ZZ (low-power mode) signal. */ 676 #define L2CR_L2WT 0x00080000 /* 12: L2 write-through. */ 677 #define L2CR_L2TS 0x00040000 /* 13: L2 test support. */ 678 #define L2CR_L2OH 0x00030000 /* 14-15: L2 output hold. */ 679 #define L2CR_L2DO_7450 0x00010000 /* 15: L2 data-only (MPC745x). */ 680 #define L2CR_L2SL 0x00008000 /* 16: L2 DLL slow. */ 681 #define L2CR_L2DF 0x00004000 /* 17: L2 differential clock. */ 682 #define L2CR_L2BYP 0x00002000 /* 18: L2 DLL bypass. */ 683 #define L2CR_L2FA 0x00001000 /* 19: L2 flush assist (for software flush). */ 684 #define L2CR_L2HWF 0x00000800 /* 20: L2 hardware flush. */ 685 #define L2CR_L2IO 0x00000400 /* 21: L2 instruction-only. */ 686 #define L2CR_L2CLKSTP 0x00000200 /* 22: L2 clock stop. */ 687 #define L2CR_L2DRO 0x00000100 /* 23: L2DLL rollover checkstop enable. */ 688 #define L2CR_L2IP 0x00000001 /* 31: L2 global invalidate in */ 689 /* progress (read only). */ 690 #define SPR_L3CR 0x3fa /* .6. L3 Control Register */ 691 #define L3CR_L3E 0x80000000 /* 0: L3 enable */ 692 #define L3CR_L3PE 0x40000000 /* 1: L3 data parity enable */ 693 #define L3CR_L3APE 0x20000000 694 #define L3CR_L3SIZ 0x10000000 /* 3: L3 size (0=1MB, 1=2MB) */ 695 #define L3CR_L3CLKEN 0x08000000 /* 4: Enables L3_CLK[0:1] */ 696 #define L3CR_L3CLK 0x03800000 697 #define L3CR_L3IO 0x00400000 698 #define L3CR_L3CLKEXT 0x00200000 699 #define L3CR_L3CKSPEXT 0x00100000 700 #define L3CR_L3OH1 0x00080000 701 #define L3CR_L3SPO 0x00040000 702 #define L3CR_L3CKSP 0x00030000 703 #define L3CR_L3PSP 0x0000e000 704 #define L3CR_L3REP 0x00001000 705 #define L3CR_L3HWF 0x00000800 706 #define L3CR_L3I 0x00000400 /* 21: L3 global invalidate */ 707 #define L3CR_L3RT 0x00000300 708 #define L3CR_L3NIRCA 0x00000080 709 #define L3CR_L3DO 0x00000040 710 #define L3CR_PMEN 0x00000004 711 #define L3CR_PMSIZ 0x00000003 712 713 #define SPR_THRM1 0x3fc /* .6. Thermal Management Register */ 714 #define SPR_THRM2 0x3fd /* .6. Thermal Management Register */ 715 #define SPR_THRM_TIN 0x80000000 /* Thermal interrupt bit (RO) */ 716 #define SPR_THRM_TIV 0x40000000 /* Thermal interrupt valid (RO) */ 717 #define SPR_THRM_THRESHOLD(x) ((x) << 23) /* Thermal sensor threshold */ 718 #define SPR_THRM_TID 0x00000004 /* Thermal interrupt direction */ 719 #define SPR_THRM_TIE 0x00000002 /* Thermal interrupt enable */ 720 #define SPR_THRM_VALID 0x00000001 /* Valid bit */ 721 #define SPR_THRM3 0x3fe /* .6. Thermal Management Register */ 722 #define SPR_THRM_TIMER(x) ((x) << 1) /* Sampling interval timer */ 723 #define SPR_THRM_ENABLE 0x00000001 /* TAU Enable */ 724 #define SPR_FPECR 0x3fe /* .6. Floating-Point Exception Cause Register */ 725 726 /* Time Base Register declarations */ 727 #define TBR_TBL 0x10c /* 468 Time Base Lower - read */ 728 #define TBR_TBU 0x10d /* 468 Time Base Upper - read */ 729 #define TBR_TBWL 0x11c /* 468 Time Base Lower - supervisor, write */ 730 #define TBR_TBWU 0x11d /* 468 Time Base Upper - supervisor, write */ 731 732 /* Performance counter declarations */ 733 #define PMC_OVERFLOW 0x80000000 /* Counter has overflowed */ 734 735 /* The first five countable [non-]events are common to many PMC's */ 736 #define PMCN_NONE 0 /* Count nothing */ 737 #define PMCN_CYCLES 1 /* Processor cycles */ 738 #define PMCN_ICOMP 2 /* Instructions completed */ 739 #define PMCN_TBLTRANS 3 /* TBL bit transitions */ 740 #define PCMN_IDISPATCH 4 /* Instructions dispatched */ 741 742 /* Similar things for the 970 PMC direct counters */ 743 #define PMC970N_NONE 0x8 /* Count nothing */ 744 #define PMC970N_CYCLES 0xf /* Processor cycles */ 745 #define PMC970N_ICOMP 0x9 /* Instructions completed */ 746 747 #if defined(BOOKE) 748 749 #define SPR_MCARU 0x239 /* ..8 Machine Check Address register upper bits */ 750 #define SPR_MCSR 0x23c /* ..8 Machine Check Syndrome register */ 751 #define MCSR_MCP 0x80000000 /* Machine check input signal to core */ 752 #define MCSR_L2MMU_MHIT 0x08000000 /* L2 MMU simultaneous hit */ 753 #define MCSR_NMI 0x00100000 /* Non-maskable interrupt */ 754 #define MCSR_MAV 0x00080000 /* MCAR address valid */ 755 #define MCSR_MEA 0x00040000 /* MCAR effective address */ 756 #define MCSR_IF 0x00010000 /* Instruction fetch error report */ 757 #define MCSR_LD 0x00008000 /* Load instruction error report */ 758 #define MCSR_ST 0x00004000 /* Store instruction error report */ 759 #define MCSR_LDG 0x00002000 /* Guarded load instruction error report */ 760 #define MCSR_TLBSYNC 0x00000002 /* Simultaneous TLBSYNC detected */ 761 #define SPR_MCAR 0x23d /* ..8 Machine Check Address register */ 762 763 #define SPR_ESR 0x003e /* ..8 Exception Syndrome Register */ 764 #define ESR_PIL 0x08000000 /* Program interrupt - illegal */ 765 #define ESR_PPR 0x04000000 /* Program interrupt - privileged */ 766 #define ESR_PTR 0x02000000 /* Program interrupt - trap */ 767 #define ESR_ST 0x00800000 /* Store operation */ 768 #define ESR_DLK 0x00200000 /* Data storage, D cache locking */ 769 #define ESR_ILK 0x00100000 /* Data storage, I cache locking */ 770 #define ESR_BO 0x00020000 /* Data/instruction storage, byte ordering */ 771 #define ESR_SPE 0x00000080 /* SPE exception bit */ 772 773 #define SPR_CSRR0 0x03a /* ..8 58 Critical SRR0 */ 774 #define SPR_CSRR1 0x03b /* ..8 59 Critical SRR1 */ 775 #define SPR_MCSRR0 0x23a /* ..8 570 Machine check SRR0 */ 776 #define SPR_MCSRR1 0x23b /* ..8 571 Machine check SRR1 */ 777 #define SPR_DSRR0 0x23e /* ..8 574 Debug SRR0<E.ED> */ 778 #define SPR_DSRR1 0x23f /* ..8 575 Debug SRR1<E.ED> */ 779 780 #define SPR_MMUCSR0 0x3f4 /* ..8 1012 MMU Control and Status Register 0 */ 781 #define MMUCSR0_L2TLB0_FI 0x04 /* TLB0 flash invalidate */ 782 #define MMUCSR0_L2TLB1_FI 0x02 /* TLB1 flash invalidate */ 783 784 #define SPR_SVR 0x3ff /* ..8 1023 System Version Register */ 785 #define SVR_MPC8533 0x8034 786 #define SVR_MPC8533E 0x803c 787 #define SVR_MPC8541 0x8072 788 #define SVR_MPC8541E 0x807a 789 #define SVR_MPC8548 0x8031 790 #define SVR_MPC8548E 0x8039 791 #define SVR_MPC8555 0x8071 792 #define SVR_MPC8555E 0x8079 793 #define SVR_MPC8572 0x80e0 794 #define SVR_MPC8572E 0x80e8 795 #define SVR_P1011 0x80e5 796 #define SVR_P1011E 0x80ed 797 #define SVR_P1013 0x80e7 798 #define SVR_P1013E 0x80ef 799 #define SVR_P1020 0x80e4 800 #define SVR_P1020E 0x80ec 801 #define SVR_P1022 0x80e6 802 #define SVR_P1022E 0x80ee 803 #define SVR_P2010 0x80e3 804 #define SVR_P2010E 0x80eb 805 #define SVR_P2020 0x80e2 806 #define SVR_P2020E 0x80ea 807 #define SVR_P2041 0x8210 808 #define SVR_P2041E 0x8218 809 #define SVR_P3041 0x8211 810 #define SVR_P3041E 0x8219 811 #define SVR_P4040 0x8200 812 #define SVR_P4040E 0x8208 813 #define SVR_P4080 0x8201 814 #define SVR_P4080E 0x8209 815 #define SVR_P5010 0x8221 816 #define SVR_P5010E 0x8229 817 #define SVR_P5020 0x8220 818 #define SVR_P5020E 0x8228 819 #define SVR_P5021 0x8205 820 #define SVR_P5021E 0x820d 821 #define SVR_P5040 0x8204 822 #define SVR_P5040E 0x820c 823 #define SVR_VER(svr) (((svr) >> 16) & 0xffff) 824 825 #define SPR_PID0 0x030 /* ..8 Process ID Register 0 */ 826 #define SPR_PID1 0x279 /* ..8 Process ID Register 1 */ 827 #define SPR_PID2 0x27a /* ..8 Process ID Register 2 */ 828 829 #define SPR_TLB0CFG 0x2B0 /* ..8 TLB 0 Config Register */ 830 #define SPR_TLB1CFG 0x2B1 /* ..8 TLB 1 Config Register */ 831 #define TLBCFG_ASSOC_MASK 0xff000000 /* Associativity of TLB */ 832 #define TLBCFG_ASSOC_SHIFT 24 833 #define TLBCFG_NENTRY_MASK 0x00000fff /* Number of entries in TLB */ 834 835 #define SPR_IVPR 0x03f /* ..8 Interrupt Vector Prefix Register */ 836 #define SPR_IVOR0 0x190 /* ..8 Critical input */ 837 #define SPR_IVOR1 0x191 /* ..8 Machine check */ 838 #define SPR_IVOR2 0x192 839 #define SPR_IVOR3 0x193 840 #define SPR_IVOR4 0x194 841 #define SPR_IVOR5 0x195 842 #define SPR_IVOR6 0x196 843 #define SPR_IVOR7 0x197 844 #define SPR_IVOR8 0x198 845 #define SPR_IVOR9 0x199 846 #define SPR_IVOR10 0x19a 847 #define SPR_IVOR11 0x19b 848 #define SPR_IVOR12 0x19c 849 #define SPR_IVOR13 0x19d 850 #define SPR_IVOR14 0x19e 851 #define SPR_IVOR15 0x19f 852 #define SPR_IVOR32 0x210 853 #define SPR_IVOR33 0x211 854 #define SPR_IVOR34 0x212 855 #define SPR_IVOR35 0x213 856 857 #define SPR_MAS0 0x270 /* ..8 MMU Assist Register 0 Book-E/e500 */ 858 #define SPR_MAS1 0x271 /* ..8 MMU Assist Register 1 Book-E/e500 */ 859 #define SPR_MAS2 0x272 /* ..8 MMU Assist Register 2 Book-E/e500 */ 860 #define SPR_MAS3 0x273 /* ..8 MMU Assist Register 3 Book-E/e500 */ 861 #define SPR_MAS4 0x274 /* ..8 MMU Assist Register 4 Book-E/e500 */ 862 #define SPR_MAS5 0x275 /* ..8 MMU Assist Register 5 Book-E */ 863 #define SPR_MAS6 0x276 /* ..8 MMU Assist Register 6 Book-E/e500 */ 864 #define SPR_MAS7 0x3B0 /* ..8 MMU Assist Register 7 Book-E/e500 */ 865 #define SPR_MAS8 0x155 /* ..8 MMU Assist Register 8 Book-E/e500 */ 866 867 #define SPR_L1CFG0 0x203 /* ..8 L1 cache configuration register 0 */ 868 #define SPR_L1CFG1 0x204 /* ..8 L1 cache configuration register 1 */ 869 870 #define SPR_CCR1 0x378 871 #define CCR1_L2COBE 0x00000040 872 873 #define DCR_L2DCDCRAI 0x0000 /* L2 D-Cache DCR Address Pointer */ 874 #define DCR_L2DCDCRDI 0x0001 /* L2 D-Cache DCR Data Indirect */ 875 #define DCR_L2CR0 0x00 /* L2 Cache Configuration Register 0 */ 876 #define L2CR0_AS 0x30000000 877 878 #define SPR_L1CSR0 0x3F2 /* ..8 L1 Cache Control and Status Register 0 */ 879 #define L1CSR0_DCPE 0x00010000 /* Data Cache Parity Enable */ 880 #define L1CSR0_DCLFR 0x00000100 /* Data Cache Lock Bits Flash Reset */ 881 #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ 882 #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ 883 #define SPR_L1CSR1 0x3F3 /* ..8 L1 Cache Control and Status Register 1 */ 884 #define L1CSR1_ICPE 0x00010000 /* Instruction Cache Parity Enable */ 885 #define L1CSR1_ICUL 0x00000400 /* Instr Cache Unable to Lock */ 886 #define L1CSR1_ICLFR 0x00000100 /* Instruction Cache Lock Bits Flash Reset */ 887 #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */ 888 #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ 889 890 #define SPR_L2CFG0 0x207 /* ..8 L2 Configuration Register 0 */ 891 #define SPR_L2CSR0 0x3F9 /* ..8 L2 Cache Control and Status Register 0 */ 892 #define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */ 893 #define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity Enable */ 894 #define L2CSR0_L2FI 0x00200000 /* L2 Cache Flash Invalidate */ 895 #define L2CSR0_L2LFC 0x00000400 /* L2 Cache Lock Flags Clear */ 896 897 #define SPR_BUCSR 0x3F5 /* ..8 Branch Unit Control and Status Register */ 898 #define BUCSR_BPEN 0x00000001 /* Branch Prediction Enable */ 899 #define BUCSR_BBFI 0x00000200 /* Branch Buffer Flash Invalidate */ 900 901 #endif /* BOOKE */ 902 #endif /* !_POWERPC_SPR_H_ */ 903