1 /*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 15 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 16 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 18 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 22 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 23 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 24 * POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $NetBSD: spr.h,v 1.25 2002/08/14 15:38:40 matt Exp $ 27 * $FreeBSD$ 28 */ 29 #ifndef _POWERPC_SPR_H_ 30 #define _POWERPC_SPR_H_ 31 32 #ifndef _LOCORE 33 #define mtspr(reg, val) \ 34 __asm __volatile("mtspr %0,%1" : : "K"(reg), "r"(val)) 35 #define mfspr(reg) \ 36 ( { register_t val; \ 37 __asm __volatile("mfspr %0,%1" : "=r"(val) : "K"(reg)); \ 38 val; } ) 39 40 41 #ifndef __powerpc64__ 42 43 /* The following routines allow manipulation of the full 64-bit width 44 * of SPRs on 64 bit CPUs in bridge mode */ 45 46 #define mtspr64(reg,valhi,vallo,scratch) \ 47 __asm __volatile(" \ 48 mfmsr %0; \ 49 insrdi %0,%5,1,0; \ 50 mtmsrd %0; \ 51 isync; \ 52 \ 53 sld %1,%1,%4; \ 54 or %1,%1,%2; \ 55 mtspr %3,%1; \ 56 srd %1,%1,%4; \ 57 \ 58 clrldi %0,%0,1; \ 59 mtmsrd %0; \ 60 isync;" \ 61 : "=r"(scratch), "=r"(valhi) : "r"(vallo), "K"(reg), "r"(32), "r"(1)) 62 63 #define mfspr64upper(reg,scratch) \ 64 ( { register_t val; \ 65 __asm __volatile(" \ 66 mfmsr %0; \ 67 insrdi %0,%4,1,0; \ 68 mtmsrd %0; \ 69 isync; \ 70 \ 71 mfspr %1,%2; \ 72 srd %1,%1,%3; \ 73 \ 74 clrldi %0,%0,1; \ 75 mtmsrd %0; \ 76 isync;" \ 77 : "=r"(scratch), "=r"(val) : "K"(reg), "r"(32), "r"(1)); \ 78 val; } ) 79 80 #endif 81 82 #endif /* _LOCORE */ 83 84 /* 85 * Special Purpose Register declarations. 86 * 87 * The first column in the comments indicates which PowerPC 88 * architectures the SPR is valid on - 4 for 4xx series, 89 * 6 for 6xx/7xx series and 8 for 8xx and 8xxx series. 90 */ 91 92 #define SPR_MQ 0x000 /* .6. 601 MQ register */ 93 #define SPR_XER 0x001 /* 468 Fixed Point Exception Register */ 94 #define SPR_RTCU_R 0x004 /* .6. 601 RTC Upper - Read */ 95 #define SPR_RTCL_R 0x005 /* .6. 601 RTC Lower - Read */ 96 #define SPR_LR 0x008 /* 468 Link Register */ 97 #define SPR_CTR 0x009 /* 468 Count Register */ 98 #define SPR_DSISR 0x012 /* .68 DSI exception source */ 99 #define DSISR_DIRECT 0x80000000 /* Direct-store error exception */ 100 #define DSISR_NOTFOUND 0x40000000 /* Translation not found */ 101 #define DSISR_PROTECT 0x08000000 /* Memory access not permitted */ 102 #define DSISR_INVRX 0x04000000 /* Reserve-indexed insn direct-store access */ 103 #define DSISR_STORE 0x02000000 /* Store operation */ 104 #define DSISR_DABR 0x00400000 /* DABR match */ 105 #define DSISR_SEGMENT 0x00200000 /* XXX; not in 6xx PEM */ 106 #define DSISR_EAR 0x00100000 /* eciwx/ecowx && EAR[E] == 0 */ 107 #define SPR_DAR 0x013 /* .68 Data Address Register */ 108 #define SPR_RTCU_W 0x014 /* .6. 601 RTC Upper - Write */ 109 #define SPR_RTCL_W 0x015 /* .6. 601 RTC Lower - Write */ 110 #define SPR_DEC 0x016 /* .68 DECrementer register */ 111 #define SPR_SDR1 0x019 /* .68 Page table base address register */ 112 #define SPR_SRR0 0x01a /* 468 Save/Restore Register 0 */ 113 #define SPR_SRR1 0x01b /* 468 Save/Restore Register 1 */ 114 #define SRR1_ISI_PFAULT 0x40000000 /* ISI page not found */ 115 #define SRR1_ISI_NOEXECUTE 0x10000000 /* Memory marked no-execute */ 116 #define SRR1_ISI_PP 0x08000000 /* PP bits forbid access */ 117 #define SPR_DECAR 0x036 /* ..8 Decrementer auto reload */ 118 #define SPR_EIE 0x050 /* ..8 Exception Interrupt ??? */ 119 #define SPR_EID 0x051 /* ..8 Exception Interrupt ??? */ 120 #define SPR_NRI 0x052 /* ..8 Exception Interrupt ??? */ 121 #define SPR_USPRG0 0x100 /* 4.. User SPR General 0 */ 122 #define SPR_VRSAVE 0x100 /* .6. AltiVec VRSAVE */ 123 #define SPR_SPRG0 0x110 /* 468 SPR General 0 */ 124 #define SPR_SPRG1 0x111 /* 468 SPR General 1 */ 125 #define SPR_SPRG2 0x112 /* 468 SPR General 2 */ 126 #define SPR_SPRG3 0x113 /* 468 SPR General 3 */ 127 #define SPR_SPRG4 0x114 /* 4.. SPR General 4 */ 128 #define SPR_SPRG5 0x115 /* 4.. SPR General 5 */ 129 #define SPR_SPRG6 0x116 /* 4.. SPR General 6 */ 130 #define SPR_SPRG7 0x117 /* 4.. SPR General 7 */ 131 #define SPR_SCOMC 0x114 /* ... SCOM Address Register (970) */ 132 #define SPR_SCOMD 0x115 /* ... SCOM Data Register (970) */ 133 #define SPR_ASR 0x118 /* ... Address Space Register (PPC64) */ 134 #define SPR_EAR 0x11a /* .68 External Access Register */ 135 #define SPR_PVR 0x11f /* 468 Processor Version Register */ 136 #define MPC601 0x0001 137 #define MPC603 0x0003 138 #define MPC604 0x0004 139 #define MPC602 0x0005 140 #define MPC603e 0x0006 141 #define MPC603ev 0x0007 142 #define MPC750 0x0008 143 #define MPC750CL 0x7000 /* Nintendo Wii's Broadway */ 144 #define MPC604ev 0x0009 145 #define MPC7400 0x000c 146 #define MPC620 0x0014 147 #define IBM403 0x0020 148 #define IBM401A1 0x0021 149 #define IBM401B2 0x0022 150 #define IBM401C2 0x0023 151 #define IBM401D2 0x0024 152 #define IBM401E2 0x0025 153 #define IBM401F2 0x0026 154 #define IBM401G2 0x0027 155 #define IBMRS64II 0x0033 156 #define IBMRS64III 0x0034 157 #define IBMPOWER4 0x0035 158 #define IBMRS64III_2 0x0036 159 #define IBMRS64IV 0x0037 160 #define IBMPOWER4PLUS 0x0038 161 #define IBM970 0x0039 162 #define IBMPOWER5 0x003a 163 #define IBMPOWER5PLUS 0x003b 164 #define IBM970FX 0x003c 165 #define IBMPOWER6 0x003e 166 #define IBMPOWER7 0x003f 167 #define IBMPOWER3 0x0040 168 #define IBMPOWER3PLUS 0x0041 169 #define IBM970MP 0x0044 170 #define IBM970GX 0x0045 171 #define IBMPOWER7PLUS 0x004a 172 #define IBMPOWER8E 0x004b 173 #define IBMPOWER8 0x004d 174 #define MPC860 0x0050 175 #define IBMCELLBE 0x0070 176 #define MPC8240 0x0081 177 #define PA6T 0x0090 178 #define IBM405GP 0x4011 179 #define IBM405L 0x4161 180 #define IBM750FX 0x7000 181 #define MPC745X_P(v) ((v & 0xFFF8) == 0x8000) 182 #define MPC7450 0x8000 183 #define MPC7455 0x8001 184 #define MPC7457 0x8002 185 #define MPC7447A 0x8003 186 #define MPC7448 0x8004 187 #define MPC7410 0x800c 188 #define MPC8245 0x8081 189 #define FSL_E500v1 0x8020 190 #define FSL_E500v2 0x8021 191 #define FSL_E500mc 0x8023 192 #define FSL_E5500 0x8024 193 194 #define SPR_IBAT0U 0x210 /* .68 Instruction BAT Reg 0 Upper */ 195 #define SPR_IBAT0U 0x210 /* .6. Instruction BAT Reg 0 Upper */ 196 #define SPR_IBAT0L 0x211 /* .6. Instruction BAT Reg 0 Lower */ 197 #define SPR_IBAT1U 0x212 /* .6. Instruction BAT Reg 1 Upper */ 198 #define SPR_IBAT1L 0x213 /* .6. Instruction BAT Reg 1 Lower */ 199 #define SPR_IBAT2U 0x214 /* .6. Instruction BAT Reg 2 Upper */ 200 #define SPR_IBAT2L 0x215 /* .6. Instruction BAT Reg 2 Lower */ 201 #define SPR_IBAT3U 0x216 /* .6. Instruction BAT Reg 3 Upper */ 202 #define SPR_IBAT3L 0x217 /* .6. Instruction BAT Reg 3 Lower */ 203 #define SPR_DBAT0U 0x218 /* .6. Data BAT Reg 0 Upper */ 204 #define SPR_DBAT0L 0x219 /* .6. Data BAT Reg 0 Lower */ 205 #define SPR_DBAT1U 0x21a /* .6. Data BAT Reg 1 Upper */ 206 #define SPR_DBAT1L 0x21b /* .6. Data BAT Reg 1 Lower */ 207 #define SPR_DBAT2U 0x21c /* .6. Data BAT Reg 2 Upper */ 208 #define SPR_DBAT2L 0x21d /* .6. Data BAT Reg 2 Lower */ 209 #define SPR_DBAT3U 0x21e /* .6. Data BAT Reg 3 Upper */ 210 #define SPR_DBAT3L 0x21f /* .6. Data BAT Reg 3 Lower */ 211 #define SPR_IC_CST 0x230 /* ..8 Instruction Cache CSR */ 212 #define IC_CST_IEN 0x80000000 /* I cache is ENabled (RO) */ 213 #define IC_CST_CMD_INVALL 0x0c000000 /* I cache invalidate all */ 214 #define IC_CST_CMD_UNLOCKALL 0x0a000000 /* I cache unlock all */ 215 #define IC_CST_CMD_UNLOCK 0x08000000 /* I cache unlock block */ 216 #define IC_CST_CMD_LOADLOCK 0x06000000 /* I cache load & lock block */ 217 #define IC_CST_CMD_DISABLE 0x04000000 /* I cache disable */ 218 #define IC_CST_CMD_ENABLE 0x02000000 /* I cache enable */ 219 #define IC_CST_CCER1 0x00200000 /* I cache error type 1 (RO) */ 220 #define IC_CST_CCER2 0x00100000 /* I cache error type 2 (RO) */ 221 #define IC_CST_CCER3 0x00080000 /* I cache error type 3 (RO) */ 222 #define SPR_IBAT4U 0x230 /* .6. Instruction BAT Reg 4 Upper */ 223 #define SPR_IC_ADR 0x231 /* ..8 Instruction Cache Address */ 224 #define SPR_IBAT4L 0x231 /* .6. Instruction BAT Reg 4 Lower */ 225 #define SPR_IC_DAT 0x232 /* ..8 Instruction Cache Data */ 226 #define SPR_IBAT5U 0x232 /* .6. Instruction BAT Reg 5 Upper */ 227 #define SPR_IBAT5L 0x233 /* .6. Instruction BAT Reg 5 Lower */ 228 #define SPR_IBAT6U 0x234 /* .6. Instruction BAT Reg 6 Upper */ 229 #define SPR_IBAT6L 0x235 /* .6. Instruction BAT Reg 6 Lower */ 230 #define SPR_IBAT7U 0x236 /* .6. Instruction BAT Reg 7 Upper */ 231 #define SPR_IBAT7L 0x237 /* .6. Instruction BAT Reg 7 Lower */ 232 #define SPR_DC_CST 0x230 /* ..8 Data Cache CSR */ 233 #define DC_CST_DEN 0x80000000 /* D cache ENabled (RO) */ 234 #define DC_CST_DFWT 0x40000000 /* D cache Force Write-Thru (RO) */ 235 #define DC_CST_LES 0x20000000 /* D cache Little Endian Swap (RO) */ 236 #define DC_CST_CMD_FLUSH 0x0e000000 /* D cache invalidate all */ 237 #define DC_CST_CMD_INVALL 0x0c000000 /* D cache invalidate all */ 238 #define DC_CST_CMD_UNLOCKALL 0x0a000000 /* D cache unlock all */ 239 #define DC_CST_CMD_UNLOCK 0x08000000 /* D cache unlock block */ 240 #define DC_CST_CMD_CLRLESWAP 0x07000000 /* D cache clr little-endian swap */ 241 #define DC_CST_CMD_LOADLOCK 0x06000000 /* D cache load & lock block */ 242 #define DC_CST_CMD_SETLESWAP 0x05000000 /* D cache set little-endian swap */ 243 #define DC_CST_CMD_DISABLE 0x04000000 /* D cache disable */ 244 #define DC_CST_CMD_CLRFWT 0x03000000 /* D cache clear forced write-thru */ 245 #define DC_CST_CMD_ENABLE 0x02000000 /* D cache enable */ 246 #define DC_CST_CMD_SETFWT 0x01000000 /* D cache set forced write-thru */ 247 #define DC_CST_CCER1 0x00200000 /* D cache error type 1 (RO) */ 248 #define DC_CST_CCER2 0x00100000 /* D cache error type 2 (RO) */ 249 #define DC_CST_CCER3 0x00080000 /* D cache error type 3 (RO) */ 250 #define SPR_DBAT4U 0x238 /* .6. Data BAT Reg 4 Upper */ 251 #define SPR_DC_ADR 0x231 /* ..8 Data Cache Address */ 252 #define SPR_DBAT4L 0x239 /* .6. Data BAT Reg 4 Lower */ 253 #define SPR_DC_DAT 0x232 /* ..8 Data Cache Data */ 254 #define SPR_DBAT5U 0x23a /* .6. Data BAT Reg 5 Upper */ 255 #define SPR_DBAT5L 0x23b /* .6. Data BAT Reg 5 Lower */ 256 #define SPR_DBAT6U 0x23c /* .6. Data BAT Reg 6 Upper */ 257 #define SPR_DBAT6L 0x23d /* .6. Data BAT Reg 6 Lower */ 258 #define SPR_DBAT7U 0x23e /* .6. Data BAT Reg 7 Upper */ 259 #define SPR_DBAT7L 0x23f /* .6. Data BAT Reg 7 Lower */ 260 #define SPR_MI_CTR 0x310 /* ..8 IMMU control */ 261 #define Mx_CTR_GPM 0x80000000 /* Group Protection Mode */ 262 #define Mx_CTR_PPM 0x40000000 /* Page Protection Mode */ 263 #define Mx_CTR_CIDEF 0x20000000 /* Cache-Inhibit DEFault */ 264 #define MD_CTR_WTDEF 0x20000000 /* Write-Through DEFault */ 265 #define Mx_CTR_RSV4 0x08000000 /* Reserve 4 TLB entries */ 266 #define MD_CTR_TWAM 0x04000000 /* TableWalk Assist Mode */ 267 #define Mx_CTR_PPCS 0x02000000 /* Priv/user state compare mode */ 268 #define Mx_CTR_TLB_INDX 0x000001f0 /* TLB index mask */ 269 #define Mx_CTR_TLB_INDX_BITPOS 8 /* TLB index shift */ 270 #define SPR_MI_AP 0x312 /* ..8 IMMU access protection */ 271 #define Mx_GP_SUPER(n) (0 << (2*(15-(n)))) /* access is supervisor */ 272 #define Mx_GP_PAGE (1 << (2*(15-(n)))) /* access is page protect */ 273 #define Mx_GP_SWAPPED (2 << (2*(15-(n)))) /* access is swapped */ 274 #define Mx_GP_USER (3 << (2*(15-(n)))) /* access is user */ 275 #define SPR_MI_EPN 0x313 /* ..8 IMMU effective number */ 276 #define Mx_EPN_EPN 0xfffff000 /* Effective Page Number mask */ 277 #define Mx_EPN_EV 0x00000020 /* Entry Valid */ 278 #define Mx_EPN_ASID 0x0000000f /* Address Space ID */ 279 #define SPR_MI_TWC 0x315 /* ..8 IMMU tablewalk control */ 280 #define MD_TWC_L2TB 0xfffff000 /* Level-2 Tablewalk Base */ 281 #define Mx_TWC_APG 0x000001e0 /* Access Protection Group */ 282 #define Mx_TWC_G 0x00000010 /* Guarded memory */ 283 #define Mx_TWC_PS 0x0000000c /* Page Size (L1) */ 284 #define MD_TWC_WT 0x00000002 /* Write-Through */ 285 #define Mx_TWC_V 0x00000001 /* Entry Valid */ 286 #define SPR_MI_RPN 0x316 /* ..8 IMMU real (phys) page number */ 287 #define Mx_RPN_RPN 0xfffff000 /* Real Page Number */ 288 #define Mx_RPN_PP 0x00000ff0 /* Page Protection */ 289 #define Mx_RPN_SPS 0x00000008 /* Small Page Size */ 290 #define Mx_RPN_SH 0x00000004 /* SHared page */ 291 #define Mx_RPN_CI 0x00000002 /* Cache Inhibit */ 292 #define Mx_RPN_V 0x00000001 /* Valid */ 293 #define SPR_MD_CTR 0x318 /* ..8 DMMU control */ 294 #define SPR_M_CASID 0x319 /* ..8 CASID */ 295 #define M_CASID 0x0000000f /* Current AS Id */ 296 #define SPR_MD_AP 0x31a /* ..8 DMMU access protection */ 297 #define SPR_MD_EPN 0x31b /* ..8 DMMU effective number */ 298 299 #define SPR_970MMCR0 0x31b /* ... Monitor Mode Control Register 0 (PPC 970) */ 300 #define SPR_970MMCR0_PMC1SEL(x) ((x) << 8) /* PMC1 selector (970) */ 301 #define SPR_970MMCR0_PMC2SEL(x) ((x) << 1) /* PMC2 selector (970) */ 302 #define SPR_970MMCR1 0x31e /* ... Monitor Mode Control Register 1 (PPC 970) */ 303 #define SPR_970MMCR1_PMC3SEL(x) (((x) & 0x1f) << 27) /* PMC 3 selector */ 304 #define SPR_970MMCR1_PMC4SEL(x) (((x) & 0x1f) << 22) /* PMC 4 selector */ 305 #define SPR_970MMCR1_PMC5SEL(x) (((x) & 0x1f) << 17) /* PMC 5 selector */ 306 #define SPR_970MMCR1_PMC6SEL(x) (((x) & 0x1f) << 12) /* PMC 6 selector */ 307 #define SPR_970MMCR1_PMC7SEL(x) (((x) & 0x1f) << 7) /* PMC 7 selector */ 308 #define SPR_970MMCR1_PMC8SEL(x) (((x) & 0x1f) << 2) /* PMC 8 selector */ 309 #define SPR_970MMCRA 0x312 /* ... Monitor Mode Control Register 2 (PPC 970) */ 310 #define SPR_970PMC1 0x313 /* ... PMC 1 */ 311 #define SPR_970PMC2 0x314 /* ... PMC 2 */ 312 #define SPR_970PMC3 0x315 /* ... PMC 3 */ 313 #define SPR_970PMC4 0x316 /* ... PMC 4 */ 314 #define SPR_970PMC5 0x317 /* ... PMC 5 */ 315 #define SPR_970PMC6 0x318 /* ... PMC 6 */ 316 #define SPR_970PMC7 0x319 /* ... PMC 7 */ 317 #define SPR_970PMC8 0x31a /* ... PMC 8 */ 318 319 #define SPR_M_TWB 0x31c /* ..8 MMU tablewalk base */ 320 #define M_TWB_L1TB 0xfffff000 /* level-1 translation base */ 321 #define M_TWB_L1INDX 0x00000ffc /* level-1 index */ 322 #define SPR_MD_TWC 0x31d /* ..8 DMMU tablewalk control */ 323 #define SPR_MD_RPN 0x31e /* ..8 DMMU real (phys) page number */ 324 #define SPR_MD_TW 0x31f /* ..8 MMU tablewalk scratch */ 325 #define SPR_MI_CAM 0x330 /* ..8 IMMU CAM entry read */ 326 #define SPR_MI_RAM0 0x331 /* ..8 IMMU RAM entry read reg 0 */ 327 #define SPR_MI_RAM1 0x332 /* ..8 IMMU RAM entry read reg 1 */ 328 #define SPR_MD_CAM 0x338 /* ..8 IMMU CAM entry read */ 329 #define SPR_MD_RAM0 0x339 /* ..8 IMMU RAM entry read reg 0 */ 330 #define SPR_MD_RAM1 0x33a /* ..8 IMMU RAM entry read reg 1 */ 331 #define SPR_UMMCR2 0x3a0 /* .6. User Monitor Mode Control Register 2 */ 332 #define SPR_UMMCR0 0x3a8 /* .6. User Monitor Mode Control Register 0 */ 333 #define SPR_USIA 0x3ab /* .6. User Sampled Instruction Address */ 334 #define SPR_UMMCR1 0x3ac /* .6. User Monitor Mode Control Register 1 */ 335 #define SPR_ZPR 0x3b0 /* 4.. Zone Protection Register */ 336 #define SPR_MMCR2 0x3b0 /* .6. Monitor Mode Control Register 2 */ 337 #define SPR_MMCR2_THRESHMULT_32 0x80000000 /* Multiply MMCR0 threshold by 32 */ 338 #define SPR_MMCR2_THRESHMULT_2 0x00000000 /* Multiply MMCR0 threshold by 2 */ 339 #define SPR_PID 0x3b1 /* 4.. Process ID */ 340 #define SPR_PMC5 0x3b1 /* .6. Performance Counter Register 5 */ 341 #define SPR_PMC6 0x3b2 /* .6. Performance Counter Register 6 */ 342 #define SPR_CCR0 0x3b3 /* 4.. Core Configuration Register 0 */ 343 #define SPR_IAC3 0x3b4 /* 4.. Instruction Address Compare 3 */ 344 #define SPR_IAC4 0x3b5 /* 4.. Instruction Address Compare 4 */ 345 #define SPR_DVC1 0x3b6 /* 4.. Data Value Compare 1 */ 346 #define SPR_DVC2 0x3b7 /* 4.. Data Value Compare 2 */ 347 #define SPR_MMCR0 0x3b8 /* .6. Monitor Mode Control Register 0 */ 348 #define SPR_MMCR0_FC 0x80000000 /* Freeze counters */ 349 #define SPR_MMCR0_FCS 0x40000000 /* Freeze counters in supervisor mode */ 350 #define SPR_MMCR0_FCP 0x20000000 /* Freeze counters in user mode */ 351 #define SPR_MMCR0_FCM1 0x10000000 /* Freeze counters when mark=1 */ 352 #define SPR_MMCR0_FCM0 0x08000000 /* Freeze counters when mark=0 */ 353 #define SPR_MMCR0_PMXE 0x04000000 /* Enable PM interrupt */ 354 #define SPR_MMCR0_FCECE 0x02000000 /* Freeze counters after event */ 355 #define SPR_MMCR0_TBSEL_15 0x01800000 /* Count bit 15 of TBL */ 356 #define SPR_MMCR0_TBSEL_19 0x01000000 /* Count bit 19 of TBL */ 357 #define SPR_MMCR0_TBSEL_23 0x00800000 /* Count bit 23 of TBL */ 358 #define SPR_MMCR0_TBSEL_31 0x00000000 /* Count bit 31 of TBL */ 359 #define SPR_MMCR0_TBEE 0x00400000 /* Time-base event enable */ 360 #define SPR_MMCRO_THRESHOLD(x) ((x) << 16) /* Threshold value */ 361 #define SPR_MMCR0_PMC1CE 0x00008000 /* PMC1 condition enable */ 362 #define SPR_MMCR0_PMCNCE 0x00004000 /* PMCn condition enable */ 363 #define SPR_MMCR0_TRIGGER 0x00002000 /* Trigger */ 364 #define SPR_MMCR0_PMC1SEL(x) (((x) & 0x3f) << 6) /* PMC1 selector */ 365 #define SPR_MMCR0_PMC2SEL(x) (((x) & 0x3f) << 0) /* PMC2 selector */ 366 #define SPR_SGR 0x3b9 /* 4.. Storage Guarded Register */ 367 #define SPR_PMC1 0x3b9 /* .6. Performance Counter Register 1 */ 368 #define SPR_DCWR 0x3ba /* 4.. Data Cache Write-through Register */ 369 #define SPR_PMC2 0x3ba /* .6. Performance Counter Register 2 */ 370 #define SPR_SLER 0x3bb /* 4.. Storage Little Endian Register */ 371 #define SPR_SIA 0x3bb /* .6. Sampled Instruction Address */ 372 #define SPR_MMCR1 0x3bc /* .6. Monitor Mode Control Register 2 */ 373 #define SPR_MMCR1_PMC3SEL(x) (((x) & 0x1f) << 27) /* PMC 3 selector */ 374 #define SPR_MMCR1_PMC4SEL(x) (((x) & 0x1f) << 22) /* PMC 4 selector */ 375 #define SPR_MMCR1_PMC5SEL(x) (((x) & 0x1f) << 17) /* PMC 5 selector */ 376 #define SPR_MMCR1_PMC6SEL(x) (((x) & 0x3f) << 11) /* PMC 6 selector */ 377 378 #define SPR_SU0R 0x3bc /* 4.. Storage User-defined 0 Register */ 379 #define SPR_PMC3 0x3bd /* .6. Performance Counter Register 3 */ 380 #define SPR_PMC4 0x3be /* .6. Performance Counter Register 4 */ 381 #define SPR_DMISS 0x3d0 /* .68 Data TLB Miss Address Register */ 382 #define SPR_DCMP 0x3d1 /* .68 Data TLB Compare Register */ 383 #define SPR_HASH1 0x3d2 /* .68 Primary Hash Address Register */ 384 #define SPR_ICDBDR 0x3d3 /* 4.. Instruction Cache Debug Data Register */ 385 #define SPR_HASH2 0x3d3 /* .68 Secondary Hash Address Register */ 386 #define SPR_IMISS 0x3d4 /* .68 Instruction TLB Miss Address Register */ 387 #define SPR_TLBMISS 0x3d4 /* .6. TLB Miss Address Register */ 388 #define SPR_DEAR 0x3d5 /* 4.. Data Error Address Register */ 389 #define SPR_ICMP 0x3d5 /* .68 Instruction TLB Compare Register */ 390 #define SPR_PTEHI 0x3d5 /* .6. Instruction TLB Compare Register */ 391 #define SPR_EVPR 0x3d6 /* 4.. Exception Vector Prefix Register */ 392 #define SPR_RPA 0x3d6 /* .68 Required Physical Address Register */ 393 #define SPR_PTELO 0x3d6 /* .6. Required Physical Address Register */ 394 395 #define SPR_TSR 0x150 /* ..8 Timer Status Register */ 396 #define SPR_TCR 0x154 /* ..8 Timer Control Register */ 397 398 #define TSR_ENW 0x80000000 /* Enable Next Watchdog */ 399 #define TSR_WIS 0x40000000 /* Watchdog Interrupt Status */ 400 #define TSR_WRS_MASK 0x30000000 /* Watchdog Reset Status */ 401 #define TSR_WRS_NONE 0x00000000 /* No watchdog reset has occurred */ 402 #define TSR_WRS_CORE 0x10000000 /* Core reset was forced by the watchdog */ 403 #define TSR_WRS_CHIP 0x20000000 /* Chip reset was forced by the watchdog */ 404 #define TSR_WRS_SYSTEM 0x30000000 /* System reset was forced by the watchdog */ 405 #define TSR_PIS 0x08000000 /* PIT Interrupt Status */ 406 #define TSR_DIS 0x08000000 /* Decrementer Interrupt Status */ 407 #define TSR_FIS 0x04000000 /* FIT Interrupt Status */ 408 409 #define TCR_WP_MASK 0xc0000000 /* Watchdog Period mask */ 410 #define TCR_WP_2_17 0x00000000 /* 2**17 clocks */ 411 #define TCR_WP_2_21 0x40000000 /* 2**21 clocks */ 412 #define TCR_WP_2_25 0x80000000 /* 2**25 clocks */ 413 #define TCR_WP_2_29 0xc0000000 /* 2**29 clocks */ 414 #define TCR_WRC_MASK 0x30000000 /* Watchdog Reset Control mask */ 415 #define TCR_WRC_NONE 0x00000000 /* No watchdog reset */ 416 #define TCR_WRC_CORE 0x10000000 /* Core reset */ 417 #define TCR_WRC_CHIP 0x20000000 /* Chip reset */ 418 #define TCR_WRC_SYSTEM 0x30000000 /* System reset */ 419 #define TCR_WIE 0x08000000 /* Watchdog Interrupt Enable */ 420 #define TCR_PIE 0x04000000 /* PIT Interrupt Enable */ 421 #define TCR_DIE 0x04000000 /* Pecrementer Interrupt Enable */ 422 #define TCR_FP_MASK 0x03000000 /* FIT Period */ 423 #define TCR_FP_2_9 0x00000000 /* 2**9 clocks */ 424 #define TCR_FP_2_13 0x01000000 /* 2**13 clocks */ 425 #define TCR_FP_2_17 0x02000000 /* 2**17 clocks */ 426 #define TCR_FP_2_21 0x03000000 /* 2**21 clocks */ 427 #define TCR_FIE 0x00800000 /* FIT Interrupt Enable */ 428 #define TCR_ARE 0x00400000 /* Auto Reload Enable */ 429 430 #define SPR_PIT 0x3db /* 4.. Programmable Interval Timer */ 431 #define SPR_SRR2 0x3de /* 4.. Save/Restore Register 2 */ 432 #define SPR_SRR3 0x3df /* 4.. Save/Restore Register 3 */ 433 #define SPR_HID0 0x3f0 /* ..8 Hardware Implementation Register 0 */ 434 #define SPR_HID1 0x3f1 /* ..8 Hardware Implementation Register 1 */ 435 #define SPR_HID2 0x3f3 /* ..8 Hardware Implementation Register 2 */ 436 #define SPR_HID4 0x3f4 /* ..8 Hardware Implementation Register 4 */ 437 #define SPR_HID5 0x3f6 /* ..8 Hardware Implementation Register 5 */ 438 #define SPR_HID6 0x3f9 /* ..8 Hardware Implementation Register 6 */ 439 440 #define SPR_CELL_TSRL 0x380 /* ... Cell BE Thread Status Register */ 441 #define SPR_CELL_TSCR 0x399 /* ... Cell BE Thread Switch Register */ 442 443 #if defined(AIM) 444 #define SPR_DBSR 0x3f0 /* 4.. Debug Status Register */ 445 #define DBSR_IC 0x80000000 /* Instruction completion debug event */ 446 #define DBSR_BT 0x40000000 /* Branch Taken debug event */ 447 #define DBSR_EDE 0x20000000 /* Exception debug event */ 448 #define DBSR_TIE 0x10000000 /* Trap Instruction debug event */ 449 #define DBSR_UDE 0x08000000 /* Unconditional debug event */ 450 #define DBSR_IA1 0x04000000 /* IAC1 debug event */ 451 #define DBSR_IA2 0x02000000 /* IAC2 debug event */ 452 #define DBSR_DR1 0x01000000 /* DAC1 Read debug event */ 453 #define DBSR_DW1 0x00800000 /* DAC1 Write debug event */ 454 #define DBSR_DR2 0x00400000 /* DAC2 Read debug event */ 455 #define DBSR_DW2 0x00200000 /* DAC2 Write debug event */ 456 #define DBSR_IDE 0x00100000 /* Imprecise debug event */ 457 #define DBSR_IA3 0x00080000 /* IAC3 debug event */ 458 #define DBSR_IA4 0x00040000 /* IAC4 debug event */ 459 #define DBSR_MRR 0x00000300 /* Most recent reset */ 460 #define SPR_DBCR0 0x3f2 /* 4.. Debug Control Register 0 */ 461 #define SPR_DBCR1 0x3bd /* 4.. Debug Control Register 1 */ 462 #define SPR_IAC1 0x3f4 /* 4.. Instruction Address Compare 1 */ 463 #define SPR_IAC2 0x3f5 /* 4.. Instruction Address Compare 2 */ 464 #define SPR_DAC1 0x3f6 /* 4.. Data Address Compare 1 */ 465 #define SPR_DAC2 0x3f7 /* 4.. Data Address Compare 2 */ 466 #define SPR_PIR 0x3ff /* .6. Processor Identification Register */ 467 #elif defined(BOOKE) 468 #define SPR_PIR 0x11e /* ..8 Processor Identification Register */ 469 #define SPR_DBSR 0x130 /* ..8 Debug Status Register */ 470 #define DBSR_IDE 0x80000000 /* Imprecise debug event. */ 471 #define DBSR_UDE 0x40000000 /* Unconditional debug event. */ 472 #define DBSR_MRR 0x30000000 /* Most recent Reset (mask). */ 473 #define DBSR_ICMP 0x08000000 /* Instr. complete debug event. */ 474 #define DBSR_BRT 0x04000000 /* Branch taken debug event. */ 475 #define DBSR_IRPT 0x02000000 /* Interrupt taken debug event. */ 476 #define DBSR_TRAP 0x01000000 /* Trap instr. debug event. */ 477 #define DBSR_IAC1 0x00800000 /* Instr. address compare #1. */ 478 #define DBSR_IAC2 0x00400000 /* Instr. address compare #2. */ 479 #define DBSR_IAC3 0x00200000 /* Instr. address compare #3. */ 480 #define DBSR_IAC4 0x00100000 /* Instr. address compare #4. */ 481 #define DBSR_DAC1R 0x00080000 /* Data addr. read compare #1. */ 482 #define DBSR_DAC1W 0x00040000 /* Data addr. write compare #1. */ 483 #define DBSR_DAC2R 0x00020000 /* Data addr. read compare #2. */ 484 #define DBSR_DAC2W 0x00010000 /* Data addr. write compare #2. */ 485 #define DBSR_RET 0x00008000 /* Return debug event. */ 486 #define SPR_DBCR0 0x134 /* ..8 Debug Control Register 0 */ 487 #define SPR_DBCR1 0x135 /* ..8 Debug Control Register 1 */ 488 #define SPR_IAC1 0x138 /* ..8 Instruction Address Compare 1 */ 489 #define SPR_IAC2 0x139 /* ..8 Instruction Address Compare 2 */ 490 #define SPR_DAC1 0x13c /* ..8 Data Address Compare 1 */ 491 #define SPR_DAC2 0x13d /* ..8 Data Address Compare 2 */ 492 #endif 493 494 #define DBCR0_EDM 0x80000000 /* External Debug Mode */ 495 #define DBCR0_IDM 0x40000000 /* Internal Debug Mode */ 496 #define DBCR0_RST_MASK 0x30000000 /* ReSeT */ 497 #define DBCR0_RST_NONE 0x00000000 /* No action */ 498 #define DBCR0_RST_CORE 0x10000000 /* Core reset */ 499 #define DBCR0_RST_CHIP 0x20000000 /* Chip reset */ 500 #define DBCR0_RST_SYSTEM 0x30000000 /* System reset */ 501 #define DBCR0_IC 0x08000000 /* Instruction Completion debug event */ 502 #define DBCR0_BT 0x04000000 /* Branch Taken debug event */ 503 #define DBCR0_EDE 0x02000000 /* Exception Debug Event */ 504 #define DBCR0_TDE 0x01000000 /* Trap Debug Event */ 505 #define DBCR0_IA1 0x00800000 /* IAC (Instruction Address Compare) 1 debug event */ 506 #define DBCR0_IA2 0x00400000 /* IAC 2 debug event */ 507 #define DBCR0_IA12 0x00200000 /* Instruction Address Range Compare 1-2 */ 508 #define DBCR0_IA12X 0x00100000 /* IA12 eXclusive */ 509 #define DBCR0_IA3 0x00080000 /* IAC 3 debug event */ 510 #define DBCR0_IA4 0x00040000 /* IAC 4 debug event */ 511 #define DBCR0_IA34 0x00020000 /* Instruction Address Range Compare 3-4 */ 512 #define DBCR0_IA34X 0x00010000 /* IA34 eXclusive */ 513 #define DBCR0_IA12T 0x00008000 /* Instruction Address Range Compare 1-2 range Toggle */ 514 #define DBCR0_IA34T 0x00004000 /* Instruction Address Range Compare 3-4 range Toggle */ 515 #define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */ 516 517 #define SPR_IABR 0x3f2 /* ..8 Instruction Address Breakpoint Register 0 */ 518 #define SPR_DABR 0x3f5 /* .6. Data Address Breakpoint Register */ 519 #define SPR_MSSCR0 0x3f6 /* .6. Memory SubSystem Control Register */ 520 #define MSSCR0_SHDEN 0x80000000 /* 0: Shared-state enable */ 521 #define MSSCR0_SHDPEN3 0x40000000 /* 1: ~SHD[01] signal enable in MEI mode */ 522 #define MSSCR0_L1INTVEN 0x38000000 /* 2-4: L1 data cache ~HIT intervention enable */ 523 #define MSSCR0_L2INTVEN 0x07000000 /* 5-7: L2 data cache ~HIT intervention enable*/ 524 #define MSSCR0_DL1HWF 0x00800000 /* 8: L1 data cache hardware flush */ 525 #define MSSCR0_MBO 0x00400000 /* 9: must be one */ 526 #define MSSCR0_EMODE 0x00200000 /* 10: MPX bus mode (read-only) */ 527 #define MSSCR0_ABD 0x00100000 /* 11: address bus driven (read-only) */ 528 #define MSSCR0_MBZ 0x000fffff /* 12-31: must be zero */ 529 #define MSSCR0_L2PFE 0x00000003 /* 30-31: L2 prefetch enable */ 530 #define SPR_MSSSR0 0x3f7 /* .6. Memory Subsystem Status Register (MPC745x) */ 531 #define MSSSR0_L2TAG 0x00040000 /* 13: L2 tag parity error */ 532 #define MSSSR0_L2DAT 0x00020000 /* 14: L2 data parity error */ 533 #define MSSSR0_L3TAG 0x00010000 /* 15: L3 tag parity error */ 534 #define MSSSR0_L3DAT 0x00008000 /* 16: L3 data parity error */ 535 #define MSSSR0_APE 0x00004000 /* 17: Address parity error */ 536 #define MSSSR0_DPE 0x00002000 /* 18: Data parity error */ 537 #define MSSSR0_TEA 0x00001000 /* 19: Bus transfer error acknowledge */ 538 #define SPR_LDSTCR 0x3f8 /* .6. Load/Store Control Register */ 539 #define SPR_L2PM 0x3f8 /* .6. L2 Private Memory Control Register */ 540 #define SPR_L2CR 0x3f9 /* .6. L2 Control Register */ 541 #define L2CR_L2E 0x80000000 /* 0: L2 enable */ 542 #define L2CR_L2PE 0x40000000 /* 1: L2 data parity enable */ 543 #define L2CR_L2SIZ 0x30000000 /* 2-3: L2 size */ 544 #define L2SIZ_2M 0x00000000 545 #define L2SIZ_256K 0x10000000 546 #define L2SIZ_512K 0x20000000 547 #define L2SIZ_1M 0x30000000 548 #define L2CR_L2CLK 0x0e000000 /* 4-6: L2 clock ratio */ 549 #define L2CLK_DIS 0x00000000 /* disable L2 clock */ 550 #define L2CLK_10 0x02000000 /* core clock / 1 */ 551 #define L2CLK_15 0x04000000 /* / 1.5 */ 552 #define L2CLK_20 0x08000000 /* / 2 */ 553 #define L2CLK_25 0x0a000000 /* / 2.5 */ 554 #define L2CLK_30 0x0c000000 /* / 3 */ 555 #define L2CR_L2RAM 0x01800000 /* 7-8: L2 RAM type */ 556 #define L2RAM_FLOWTHRU_BURST 0x00000000 557 #define L2RAM_PIPELINE_BURST 0x01000000 558 #define L2RAM_PIPELINE_LATE 0x01800000 559 #define L2CR_L2DO 0x00400000 /* 9: L2 data-only. 560 Setting this bit disables instruction 561 caching. */ 562 #define L2CR_L2I 0x00200000 /* 10: L2 global invalidate. */ 563 #define L2CR_L2IO_7450 0x00010000 /* 11: L2 instruction-only (MPC745x). */ 564 #define L2CR_L2CTL 0x00100000 /* 11: L2 RAM control (ZZ enable). 565 Enables automatic operation of the 566 L2ZZ (low-power mode) signal. */ 567 #define L2CR_L2WT 0x00080000 /* 12: L2 write-through. */ 568 #define L2CR_L2TS 0x00040000 /* 13: L2 test support. */ 569 #define L2CR_L2OH 0x00030000 /* 14-15: L2 output hold. */ 570 #define L2CR_L2DO_7450 0x00010000 /* 15: L2 data-only (MPC745x). */ 571 #define L2CR_L2SL 0x00008000 /* 16: L2 DLL slow. */ 572 #define L2CR_L2DF 0x00004000 /* 17: L2 differential clock. */ 573 #define L2CR_L2BYP 0x00002000 /* 18: L2 DLL bypass. */ 574 #define L2CR_L2FA 0x00001000 /* 19: L2 flush assist (for software flush). */ 575 #define L2CR_L2HWF 0x00000800 /* 20: L2 hardware flush. */ 576 #define L2CR_L2IO 0x00000400 /* 21: L2 instruction-only. */ 577 #define L2CR_L2CLKSTP 0x00000200 /* 22: L2 clock stop. */ 578 #define L2CR_L2DRO 0x00000100 /* 23: L2DLL rollover checkstop enable. */ 579 #define L2CR_L2IP 0x00000001 /* 31: L2 global invalidate in */ 580 /* progress (read only). */ 581 #define SPR_L3CR 0x3fa /* .6. L3 Control Register */ 582 #define L3CR_L3E 0x80000000 /* 0: L3 enable */ 583 #define L3CR_L3PE 0x40000000 /* 1: L3 data parity enable */ 584 #define L3CR_L3APE 0x20000000 585 #define L3CR_L3SIZ 0x10000000 /* 3: L3 size (0=1MB, 1=2MB) */ 586 #define L3CR_L3CLKEN 0x08000000 /* 4: Enables L3_CLK[0:1] */ 587 #define L3CR_L3CLK 0x03800000 588 #define L3CR_L3IO 0x00400000 589 #define L3CR_L3CLKEXT 0x00200000 590 #define L3CR_L3CKSPEXT 0x00100000 591 #define L3CR_L3OH1 0x00080000 592 #define L3CR_L3SPO 0x00040000 593 #define L3CR_L3CKSP 0x00030000 594 #define L3CR_L3PSP 0x0000e000 595 #define L3CR_L3REP 0x00001000 596 #define L3CR_L3HWF 0x00000800 597 #define L3CR_L3I 0x00000400 /* 21: L3 global invalidate */ 598 #define L3CR_L3RT 0x00000300 599 #define L3CR_L3NIRCA 0x00000080 600 #define L3CR_L3DO 0x00000040 601 #define L3CR_PMEN 0x00000004 602 #define L3CR_PMSIZ 0x00000003 603 604 #define SPR_DCCR 0x3fa /* 4.. Data Cache Cachability Register */ 605 #define SPR_ICCR 0x3fb /* 4.. Instruction Cache Cachability Register */ 606 #define SPR_THRM1 0x3fc /* .6. Thermal Management Register */ 607 #define SPR_THRM2 0x3fd /* .6. Thermal Management Register */ 608 #define SPR_THRM_TIN 0x80000000 /* Thermal interrupt bit (RO) */ 609 #define SPR_THRM_TIV 0x40000000 /* Thermal interrupt valid (RO) */ 610 #define SPR_THRM_THRESHOLD(x) ((x) << 23) /* Thermal sensor threshold */ 611 #define SPR_THRM_TID 0x00000004 /* Thermal interrupt direction */ 612 #define SPR_THRM_TIE 0x00000002 /* Thermal interrupt enable */ 613 #define SPR_THRM_VALID 0x00000001 /* Valid bit */ 614 #define SPR_THRM3 0x3fe /* .6. Thermal Management Register */ 615 #define SPR_THRM_TIMER(x) ((x) << 1) /* Sampling interval timer */ 616 #define SPR_THRM_ENABLE 0x00000001 /* TAU Enable */ 617 #define SPR_FPECR 0x3fe /* .6. Floating-Point Exception Cause Register */ 618 619 /* Time Base Register declarations */ 620 #define TBR_TBL 0x10c /* 468 Time Base Lower - read */ 621 #define TBR_TBU 0x10d /* 468 Time Base Upper - read */ 622 #define TBR_TBWL 0x11c /* 468 Time Base Lower - supervisor, write */ 623 #define TBR_TBWU 0x11d /* 468 Time Base Upper - supervisor, write */ 624 625 /* Performance counter declarations */ 626 #define PMC_OVERFLOW 0x80000000 /* Counter has overflowed */ 627 628 /* The first five countable [non-]events are common to many PMC's */ 629 #define PMCN_NONE 0 /* Count nothing */ 630 #define PMCN_CYCLES 1 /* Processor cycles */ 631 #define PMCN_ICOMP 2 /* Instructions completed */ 632 #define PMCN_TBLTRANS 3 /* TBL bit transitions */ 633 #define PCMN_IDISPATCH 4 /* Instructions dispatched */ 634 635 /* Similar things for the 970 PMC direct counters */ 636 #define PMC970N_NONE 0x8 /* Count nothing */ 637 #define PMC970N_CYCLES 0xf /* Processor cycles */ 638 #define PMC970N_ICOMP 0x9 /* Instructions completed */ 639 640 #if defined(AIM) 641 642 #define SPR_ESR 0x3d4 /* 4.. Exception Syndrome Register */ 643 #define ESR_MCI 0x80000000 /* Machine check - instruction */ 644 #define ESR_PIL 0x08000000 /* Program interrupt - illegal */ 645 #define ESR_PPR 0x04000000 /* Program interrupt - privileged */ 646 #define ESR_PTR 0x02000000 /* Program interrupt - trap */ 647 #define ESR_ST 0x01000000 /* Store operation */ 648 #define ESR_DST 0x00800000 /* Data storage interrupt - store fault */ 649 #define ESR_DIZ 0x00800000 /* Data/instruction storage interrupt - zone fault */ 650 #define ESR_U0F 0x00008000 /* Data storage interrupt - U0 fault */ 651 652 #elif defined(BOOKE) 653 654 #define SPR_MCSR 0x23c /* ..8 Machine Check Syndrome register */ 655 656 #define SPR_ESR 0x003e /* ..8 Exception Syndrome Register */ 657 #define ESR_PIL 0x08000000 /* Program interrupt - illegal */ 658 #define ESR_PPR 0x04000000 /* Program interrupt - privileged */ 659 #define ESR_PTR 0x02000000 /* Program interrupt - trap */ 660 #define ESR_ST 0x00800000 /* Store operation */ 661 #define ESR_DLK 0x00200000 /* Data storage, D cache locking */ 662 #define ESR_ILK 0x00100000 /* Data storage, I cache locking */ 663 #define ESR_BO 0x00020000 /* Data/instruction storage, byte ordering */ 664 #define ESR_SPE 0x00000080 /* SPE exception bit */ 665 666 #define SPR_CSRR0 0x03a /* ..8 58 Critical SRR0 */ 667 #define SPR_CSRR1 0x03b /* ..8 59 Critical SRR1 */ 668 #define SPR_MCSRR0 0x23a /* ..8 570 Machine check SRR0 */ 669 #define SPR_MCSRR1 0x23b /* ..8 571 Machine check SRR1 */ 670 671 #define SPR_MMUCR 0x3b2 /* 4.. MMU Control Register */ 672 #define MMUCR_SWOA (0x80000000 >> 7) 673 #define MMUCR_U1TE (0x80000000 >> 9) 674 #define MMUCR_U2SWOAE (0x80000000 >> 10) 675 #define MMUCR_DULXE (0x80000000 >> 12) 676 #define MMUCR_IULXE (0x80000000 >> 13) 677 #define MMUCR_STS (0x80000000 >> 15) 678 #define MMUCR_STID_MASK (0xFF000000 >> 24) 679 680 #define SPR_MMUCSR0 0x3f4 /* ..8 1012 MMU Control and Status Register 0 */ 681 #define MMUCSR0_L2TLB0_FI 0x04 /* TLB0 flash invalidate */ 682 #define MMUCSR0_L2TLB1_FI 0x02 /* TLB1 flash invalidate */ 683 684 #define SPR_SVR 0x3ff /* ..8 1023 System Version Register */ 685 #define SVR_MPC8533 0x8034 686 #define SVR_MPC8533E 0x803c 687 #define SVR_MPC8541 0x8072 688 #define SVR_MPC8541E 0x807a 689 #define SVR_MPC8548 0x8031 690 #define SVR_MPC8548E 0x8039 691 #define SVR_MPC8555 0x8071 692 #define SVR_MPC8555E 0x8079 693 #define SVR_MPC8572 0x80e0 694 #define SVR_MPC8572E 0x80e8 695 #define SVR_P1011 0x80e5 696 #define SVR_P1011E 0x80ed 697 #define SVR_P1020 0x80e4 698 #define SVR_P1020E 0x80ec 699 #define SVR_P2010 0x80e3 700 #define SVR_P2010E 0x80eb 701 #define SVR_P2020 0x80e2 702 #define SVR_P2020E 0x80ea 703 #define SVR_P2041 0x8210 704 #define SVR_P2041E 0x8218 705 #define SVR_P3041 0x8211 706 #define SVR_P3041E 0x8219 707 #define SVR_P4040 0x8200 708 #define SVR_P4040E 0x8208 709 #define SVR_P4080 0x8201 710 #define SVR_P4080E 0x8209 711 #define SVR_P5020 0x8220 712 #define SVR_P5020E 0x8228 713 #define SVR_VER(svr) (((svr) >> 16) & 0xffff) 714 715 #define SPR_PID0 0x030 /* ..8 Process ID Register 0 */ 716 #define SPR_PID1 0x279 /* ..8 Process ID Register 1 */ 717 #define SPR_PID2 0x27a /* ..8 Process ID Register 2 */ 718 719 #define SPR_TLB0CFG 0x2B0 /* ..8 TLB 0 Config Register */ 720 #define SPR_TLB1CFG 0x2B1 /* ..8 TLB 1 Config Register */ 721 #define TLBCFG_ASSOC_MASK 0xff000000 /* Associativity of TLB */ 722 #define TLBCFG_ASSOC_SHIFT 24 723 #define TLBCFG_NENTRY_MASK 0x00000fff /* Number of entries in TLB */ 724 725 #define SPR_IVPR 0x03f /* ..8 Interrupt Vector Prefix Register */ 726 #define SPR_IVOR0 0x190 /* ..8 Critical input */ 727 #define SPR_IVOR1 0x191 /* ..8 Machine check */ 728 #define SPR_IVOR2 0x192 729 #define SPR_IVOR3 0x193 730 #define SPR_IVOR4 0x194 731 #define SPR_IVOR5 0x195 732 #define SPR_IVOR6 0x196 733 #define SPR_IVOR7 0x197 734 #define SPR_IVOR8 0x198 735 #define SPR_IVOR9 0x199 736 #define SPR_IVOR10 0x19a 737 #define SPR_IVOR11 0x19b 738 #define SPR_IVOR12 0x19c 739 #define SPR_IVOR13 0x19d 740 #define SPR_IVOR14 0x19e 741 #define SPR_IVOR15 0x19f 742 #define SPR_IVOR32 0x210 743 #define SPR_IVOR33 0x211 744 #define SPR_IVOR34 0x212 745 #define SPR_IVOR35 0x213 746 747 #define SPR_MAS0 0x270 /* ..8 MMU Assist Register 0 Book-E/e500 */ 748 #define SPR_MAS1 0x271 /* ..8 MMU Assist Register 1 Book-E/e500 */ 749 #define SPR_MAS2 0x272 /* ..8 MMU Assist Register 2 Book-E/e500 */ 750 #define SPR_MAS3 0x273 /* ..8 MMU Assist Register 3 Book-E/e500 */ 751 #define SPR_MAS4 0x274 /* ..8 MMU Assist Register 4 Book-E/e500 */ 752 #define SPR_MAS5 0x275 /* ..8 MMU Assist Register 5 Book-E */ 753 #define SPR_MAS6 0x276 /* ..8 MMU Assist Register 6 Book-E/e500 */ 754 #define SPR_MAS7 0x3B0 /* ..8 MMU Assist Register 7 Book-E/e500 */ 755 #define SPR_MAS8 0x155 /* ..8 MMU Assist Register 8 Book-E/e500 */ 756 757 #define SPR_L1CFG0 0x203 /* ..8 L1 cache configuration register 0 */ 758 #define SPR_L1CFG1 0x204 /* ..8 L1 cache configuration register 1 */ 759 760 #define SPR_CCR1 0x378 761 #define CCR1_L2COBE 0x00000040 762 763 #define DCR_L2DCDCRAI 0x0000 /* L2 D-Cache DCR Address Pointer */ 764 #define DCR_L2DCDCRDI 0x0001 /* L2 D-Cache DCR Data Indirect */ 765 #define DCR_L2CR0 0x00 /* L2 Cache Configuration Register 0 */ 766 #define L2CR0_AS 0x30000000 767 768 #define SPR_L1CSR0 0x3F2 /* ..8 L1 Cache Control and Status Register 0 */ 769 #define L1CSR0_DCPE 0x00010000 /* Data Cache Parity Enable */ 770 #define L1CSR0_DCLFR 0x00000100 /* Data Cache Lock Bits Flash Reset */ 771 #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ 772 #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ 773 #define SPR_L1CSR1 0x3F3 /* ..8 L1 Cache Control and Status Register 1 */ 774 #define L1CSR1_ICPE 0x00010000 /* Instruction Cache Parity Enable */ 775 #define L1CSR1_ICUL 0x00000400 /* Instr Cache Unable to Lock */ 776 #define L1CSR1_ICLFR 0x00000100 /* Instruction Cache Lock Bits Flash Reset */ 777 #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */ 778 #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ 779 780 #define SPR_L2CSR0 0x3F9 /* ..8 L2 Cache Control and Status Register 0 */ 781 #define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */ 782 #define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity Enable */ 783 #define L2CSR0_L2FI 0x00200000 /* L2 Cache Flash Invalidate */ 784 #define L2CSR0_L2LFC 0x00000400 /* L2 Cache Lock Flags Clear */ 785 786 #define SPR_BUCSR 0x3F5 /* ..8 Branch Unit Control and Status Register */ 787 #define BUCSR_BPEN 0x00000001 /* Branch Prediction Enable */ 788 #define BUCSR_BBFI 0x00000200 /* Branch Buffer Flash Invalidate */ 789 790 #endif /* BOOKE */ 791 #endif /* !_POWERPC_SPR_H_ */ 792