xref: /freebsd/sys/powerpc/include/spr.h (revision 2971d3bb6eef91dc41d91b354625c81a5bff9257)
160727d8bSWarner Losh /*-
2b57e802aSBenno Rice  * Copyright (c) 2001 The NetBSD Foundation, Inc.
3b57e802aSBenno Rice  * All rights reserved.
4b57e802aSBenno Rice  *
5b57e802aSBenno Rice  * Redistribution and use in source and binary forms, with or without
6b57e802aSBenno Rice  * modification, are permitted provided that the following conditions
7b57e802aSBenno Rice  * are met:
8b57e802aSBenno Rice  * 1. Redistributions of source code must retain the above copyright
9b57e802aSBenno Rice  *    notice, this list of conditions and the following disclaimer.
10b57e802aSBenno Rice  * 2. Redistributions in binary form must reproduce the above copyright
11b57e802aSBenno Rice  *    notice, this list of conditions and the following disclaimer in the
12b57e802aSBenno Rice  *    documentation and/or other materials provided with the distribution.
13b57e802aSBenno Rice  *
14b57e802aSBenno Rice  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
15b57e802aSBenno Rice  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
16b57e802aSBenno Rice  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17b57e802aSBenno Rice  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
18b57e802aSBenno Rice  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
19b57e802aSBenno Rice  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
20b57e802aSBenno Rice  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
21b57e802aSBenno Rice  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
22b57e802aSBenno Rice  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
23b57e802aSBenno Rice  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
24b57e802aSBenno Rice  * POSSIBILITY OF SUCH DAMAGE.
25b57e802aSBenno Rice  *
2619ca68d9SBenno Rice  * $NetBSD: spr.h,v 1.25 2002/08/14 15:38:40 matt Exp $
27b57e802aSBenno Rice  * $FreeBSD$
28b57e802aSBenno Rice  */
29b57e802aSBenno Rice #ifndef _POWERPC_SPR_H_
30b57e802aSBenno Rice #define	_POWERPC_SPR_H_
31b57e802aSBenno Rice 
32b57e802aSBenno Rice #ifndef _LOCORE
33b57e802aSBenno Rice #define	mtspr(reg, val)							\
34b57e802aSBenno Rice 	__asm __volatile("mtspr %0,%1" : : "K"(reg), "r"(val))
35b57e802aSBenno Rice #define	mfspr(reg)							\
3619ca68d9SBenno Rice 	( { register_t val;						\
37b57e802aSBenno Rice 	  __asm __volatile("mfspr %0,%1" : "=r"(val) : "K"(reg));	\
38b57e802aSBenno Rice 	  val; } )
391c96bdd1SNathan Whitehorn 
40c3e289e1SNathan Whitehorn 
41c3e289e1SNathan Whitehorn #ifndef __powerpc64__
42c3e289e1SNathan Whitehorn 
431c96bdd1SNathan Whitehorn /* The following routines allow manipulation of the full 64-bit width
441c96bdd1SNathan Whitehorn  * of SPRs on 64 bit CPUs in bridge mode */
451c96bdd1SNathan Whitehorn 
461c96bdd1SNathan Whitehorn #define mtspr64(reg,valhi,vallo,scratch)				\
471c96bdd1SNathan Whitehorn 	__asm __volatile("						\
481c96bdd1SNathan Whitehorn 		mfmsr %0; 						\
49999987e5SNathan Whitehorn 		insrdi %0,%5,1,0; 					\
501c96bdd1SNathan Whitehorn 		mtmsrd %0; 						\
511c96bdd1SNathan Whitehorn 		isync; 							\
521c96bdd1SNathan Whitehorn 									\
531c96bdd1SNathan Whitehorn 		sld %1,%1,%4;						\
541c96bdd1SNathan Whitehorn 		or %1,%1,%2;						\
551c96bdd1SNathan Whitehorn 		mtspr %3,%1;						\
561c96bdd1SNathan Whitehorn 		srd %1,%1,%4;						\
571c96bdd1SNathan Whitehorn 									\
581c96bdd1SNathan Whitehorn 		clrldi %0,%0,1; 					\
591c96bdd1SNathan Whitehorn 		mtmsrd %0; 						\
601c96bdd1SNathan Whitehorn 		isync;"							\
61999987e5SNathan Whitehorn 	: "=r"(scratch), "=r"(valhi) : "r"(vallo), "K"(reg), "r"(32), "r"(1))
621c96bdd1SNathan Whitehorn 
631c96bdd1SNathan Whitehorn #define mfspr64upper(reg,scratch)					\
641c96bdd1SNathan Whitehorn 	( { register_t val;						\
651c96bdd1SNathan Whitehorn 	    __asm __volatile("						\
661c96bdd1SNathan Whitehorn 		mfmsr %0; 						\
67999987e5SNathan Whitehorn 		insrdi %0,%4,1,0; 					\
681c96bdd1SNathan Whitehorn 		mtmsrd %0; 						\
691c96bdd1SNathan Whitehorn 		isync; 							\
701c96bdd1SNathan Whitehorn 									\
711c96bdd1SNathan Whitehorn 		mfspr %1,%2;						\
721c96bdd1SNathan Whitehorn 		srd %1,%1,%3;						\
731c96bdd1SNathan Whitehorn 									\
741c96bdd1SNathan Whitehorn 		clrldi %0,%0,1; 					\
751c96bdd1SNathan Whitehorn 		mtmsrd %0; 						\
761c96bdd1SNathan Whitehorn 		isync;" 						\
77999987e5SNathan Whitehorn 	    : "=r"(scratch), "=r"(val) : "K"(reg), "r"(32), "r"(1));	\
781c96bdd1SNathan Whitehorn 	    val; } )
791c96bdd1SNathan Whitehorn 
80c3e289e1SNathan Whitehorn #endif
81c3e289e1SNathan Whitehorn 
82b57e802aSBenno Rice #endif /* _LOCORE */
83b57e802aSBenno Rice 
84b57e802aSBenno Rice /*
85b57e802aSBenno Rice  * Special Purpose Register declarations.
86b57e802aSBenno Rice  *
87b57e802aSBenno Rice  * The first column in the comments indicates which PowerPC
88b57e802aSBenno Rice  * architectures the SPR is valid on - 4 for 4xx series,
89b57e802aSBenno Rice  * 6 for 6xx/7xx series and 8 for 8xx and 8xxx series.
90b57e802aSBenno Rice  */
91b57e802aSBenno Rice 
92b57e802aSBenno Rice #define	SPR_MQ			0x000	/* .6. 601 MQ register */
93b57e802aSBenno Rice #define	SPR_XER			0x001	/* 468 Fixed Point Exception Register */
94b57e802aSBenno Rice #define	SPR_RTCU_R		0x004	/* .6. 601 RTC Upper - Read */
95b57e802aSBenno Rice #define	SPR_RTCL_R		0x005	/* .6. 601 RTC Lower - Read */
96b57e802aSBenno Rice #define	SPR_LR			0x008	/* 468 Link Register */
97b57e802aSBenno Rice #define	SPR_CTR			0x009	/* 468 Count Register */
98b57e802aSBenno Rice #define	SPR_DSISR		0x012	/* .68 DSI exception source */
99b57e802aSBenno Rice #define	  DSISR_DIRECT		  0x80000000 /* Direct-store error exception */
100b57e802aSBenno Rice #define	  DSISR_NOTFOUND	  0x40000000 /* Translation not found */
101b57e802aSBenno Rice #define	  DSISR_PROTECT		  0x08000000 /* Memory access not permitted */
102b57e802aSBenno Rice #define	  DSISR_INVRX		  0x04000000 /* Reserve-indexed insn direct-store access */
103b57e802aSBenno Rice #define	  DSISR_STORE		  0x02000000 /* Store operation */
104b57e802aSBenno Rice #define	  DSISR_DABR		  0x00400000 /* DABR match */
105b57e802aSBenno Rice #define	  DSISR_SEGMENT		  0x00200000 /* XXX; not in 6xx PEM */
106b57e802aSBenno Rice #define	  DSISR_EAR		  0x00100000 /* eciwx/ecowx && EAR[E] == 0 */
107b57e802aSBenno Rice #define	SPR_DAR			0x013	/* .68 Data Address Register */
108b57e802aSBenno Rice #define	SPR_RTCU_W		0x014	/* .6. 601 RTC Upper - Write */
109b57e802aSBenno Rice #define	SPR_RTCL_W		0x015	/* .6. 601 RTC Lower - Write */
110b57e802aSBenno Rice #define	SPR_DEC			0x016	/* .68 DECrementer register */
111b57e802aSBenno Rice #define	SPR_SDR1		0x019	/* .68 Page table base address register */
112b57e802aSBenno Rice #define	SPR_SRR0		0x01a	/* 468 Save/Restore Register 0 */
113b57e802aSBenno Rice #define	SPR_SRR1		0x01b	/* 468 Save/Restore Register 1 */
114ffb56695SRafal Jaworowski #define	SPR_DECAR		0x036	/* ..8 Decrementer auto reload */
11519ca68d9SBenno Rice #define SPR_EIE			0x050	/* ..8 Exception Interrupt ??? */
11619ca68d9SBenno Rice #define SPR_EID			0x051	/* ..8 Exception Interrupt ??? */
11719ca68d9SBenno Rice #define SPR_NRI			0x052	/* ..8 Exception Interrupt ??? */
118b57e802aSBenno Rice #define	SPR_USPRG0		0x100	/* 4.. User SPR General 0 */
11919ca68d9SBenno Rice #define	SPR_VRSAVE		0x100	/* .6. AltiVec VRSAVE */
120b57e802aSBenno Rice #define	SPR_SPRG0		0x110	/* 468 SPR General 0 */
121b57e802aSBenno Rice #define	SPR_SPRG1		0x111	/* 468 SPR General 1 */
122b57e802aSBenno Rice #define	SPR_SPRG2		0x112	/* 468 SPR General 2 */
123b57e802aSBenno Rice #define	SPR_SPRG3		0x113	/* 468 SPR General 3 */
124b57e802aSBenno Rice #define	SPR_SPRG4		0x114	/* 4.. SPR General 4 */
125b57e802aSBenno Rice #define	SPR_SPRG5		0x115	/* 4.. SPR General 5 */
126b57e802aSBenno Rice #define	SPR_SPRG6		0x116	/* 4.. SPR General 6 */
127b57e802aSBenno Rice #define	SPR_SPRG7		0x117	/* 4.. SPR General 7 */
12830a2bd2fSNathan Whitehorn #define	SPR_SCOMC		0x114	/* ... SCOM Address Register (970) */
12930a2bd2fSNathan Whitehorn #define	SPR_SCOMD		0x115	/* ... SCOM Data Register (970) */
13019ca68d9SBenno Rice #define	SPR_ASR			0x118	/* ... Address Space Register (PPC64) */
131b57e802aSBenno Rice #define	SPR_EAR			0x11a	/* .68 External Access Register */
132b57e802aSBenno Rice #define	SPR_PVR			0x11f	/* 468 Processor Version Register */
13319ca68d9SBenno Rice #define	  MPC601		  0x0001
13419ca68d9SBenno Rice #define	  MPC603		  0x0003
13519ca68d9SBenno Rice #define	  MPC604		  0x0004
13619ca68d9SBenno Rice #define	  MPC602		  0x0005
13719ca68d9SBenno Rice #define	  MPC603e		  0x0006
13819ca68d9SBenno Rice #define	  MPC603ev		  0x0007
13919ca68d9SBenno Rice #define	  MPC750		  0x0008
14019ca68d9SBenno Rice #define	  MPC604ev		  0x0009
14119ca68d9SBenno Rice #define	  MPC7400		  0x000c
14219ca68d9SBenno Rice #define	  MPC620		  0x0014
14319ca68d9SBenno Rice #define	  IBM403		  0x0020
14419ca68d9SBenno Rice #define	  IBM401A1		  0x0021
14519ca68d9SBenno Rice #define	  IBM401B2		  0x0022
14619ca68d9SBenno Rice #define	  IBM401C2		  0x0023
14719ca68d9SBenno Rice #define	  IBM401D2		  0x0024
14819ca68d9SBenno Rice #define	  IBM401E2		  0x0025
14919ca68d9SBenno Rice #define	  IBM401F2		  0x0026
15019ca68d9SBenno Rice #define	  IBM401G2		  0x0027
151c3e289e1SNathan Whitehorn #define	  IBMRS64II		  0x0033
152c3e289e1SNathan Whitehorn #define	  IBMRS64III		  0x0034
153c3e289e1SNathan Whitehorn #define	  IBMPOWER4		  0x0035
154c3e289e1SNathan Whitehorn #define	  IBMRS64III_2		  0x0036
155c3e289e1SNathan Whitehorn #define	  IBMRS64IV		  0x0037
156c3e289e1SNathan Whitehorn #define	  IBMPOWER4PLUS		  0x0038
1571c96bdd1SNathan Whitehorn #define	  IBM970		  0x0039
158c3e289e1SNathan Whitehorn #define	  IBMPOWER5		  0x003a
159c3e289e1SNathan Whitehorn #define	  IBMPOWER5PLUS		  0x003b
1601c96bdd1SNathan Whitehorn #define	  IBM970FX		  0x003c
161c3e289e1SNathan Whitehorn #define	  IBMPOWER6		  0x003e
162c3e289e1SNathan Whitehorn #define	  IBMPOWER7		  0x003f
163c3e289e1SNathan Whitehorn #define	  IBMPOWER3		  0x0040
164c3e289e1SNathan Whitehorn #define	  IBMPOWER3PLUS		  0x0041
1651c96bdd1SNathan Whitehorn #define	  IBM970MP		  0x0044
1661c96bdd1SNathan Whitehorn #define	  IBM970GX		  0x0045
16719ca68d9SBenno Rice #define	  MPC860		  0x0050
168c3e289e1SNathan Whitehorn #define	  IBMCELLBE		  0x0070
16919ca68d9SBenno Rice #define	  MPC8240		  0x0081
170c3e289e1SNathan Whitehorn #define	  PA6T			  0x0090
17119ca68d9SBenno Rice #define	  IBM405GP		  0x4011
17219ca68d9SBenno Rice #define	  IBM405L		  0x4161
17319ca68d9SBenno Rice #define	  IBM750FX		  0x7000
1744e895c54SPeter Grehan #define	MPC745X_P(v)	((v & 0xFFF8) == 0x8000)
17519ca68d9SBenno Rice #define	  MPC7450		  0x8000
17619ca68d9SBenno Rice #define	  MPC7455		  0x8001
177e6d3e1c2SPeter Grehan #define	  MPC7457		  0x8002
1784e895c54SPeter Grehan #define	  MPC7447A		  0x8003
1794e895c54SPeter Grehan #define	  MPC7448		  0x8004
18019ca68d9SBenno Rice #define	  MPC7410		  0x800c
18119ca68d9SBenno Rice #define	  MPC8245		  0x8081
182cb9bdc64SRafal Jaworowski #define	  FSL_E500v1		  0x8020
183cb9bdc64SRafal Jaworowski #define	  FSL_E500v2		  0x8021
18419ca68d9SBenno Rice 
185b57e802aSBenno Rice #define	SPR_IBAT0U		0x210	/* .68 Instruction BAT Reg 0 Upper */
18619ca68d9SBenno Rice #define	SPR_IBAT0U		0x210	/* .6. Instruction BAT Reg 0 Upper */
18719ca68d9SBenno Rice #define	SPR_IBAT0L		0x211	/* .6. Instruction BAT Reg 0 Lower */
18819ca68d9SBenno Rice #define	SPR_IBAT1U		0x212	/* .6. Instruction BAT Reg 1 Upper */
18919ca68d9SBenno Rice #define	SPR_IBAT1L		0x213	/* .6. Instruction BAT Reg 1 Lower */
19019ca68d9SBenno Rice #define	SPR_IBAT2U		0x214	/* .6. Instruction BAT Reg 2 Upper */
19119ca68d9SBenno Rice #define	SPR_IBAT2L		0x215	/* .6. Instruction BAT Reg 2 Lower */
19219ca68d9SBenno Rice #define	SPR_IBAT3U		0x216	/* .6. Instruction BAT Reg 3 Upper */
19319ca68d9SBenno Rice #define	SPR_IBAT3L		0x217	/* .6. Instruction BAT Reg 3 Lower */
19419ca68d9SBenno Rice #define	SPR_DBAT0U		0x218	/* .6. Data BAT Reg 0 Upper */
19519ca68d9SBenno Rice #define	SPR_DBAT0L		0x219	/* .6. Data BAT Reg 0 Lower */
19619ca68d9SBenno Rice #define	SPR_DBAT1U		0x21a	/* .6. Data BAT Reg 1 Upper */
19719ca68d9SBenno Rice #define	SPR_DBAT1L		0x21b	/* .6. Data BAT Reg 1 Lower */
19819ca68d9SBenno Rice #define	SPR_DBAT2U		0x21c	/* .6. Data BAT Reg 2 Upper */
19919ca68d9SBenno Rice #define	SPR_DBAT2L		0x21d	/* .6. Data BAT Reg 2 Lower */
20019ca68d9SBenno Rice #define	SPR_DBAT3U		0x21e	/* .6. Data BAT Reg 3 Upper */
20119ca68d9SBenno Rice #define	SPR_DBAT3L		0x21f	/* .6. Data BAT Reg 3 Lower */
20219ca68d9SBenno Rice #define SPR_IC_CST		0x230	/* ..8 Instruction Cache CSR */
20319ca68d9SBenno Rice #define  IC_CST_IEN		0x80000000 /* I cache is ENabled   (RO) */
20419ca68d9SBenno Rice #define  IC_CST_CMD_INVALL	0x0c000000 /* I cache invalidate all */
20519ca68d9SBenno Rice #define  IC_CST_CMD_UNLOCKALL	0x0a000000 /* I cache unlock all */
20619ca68d9SBenno Rice #define  IC_CST_CMD_UNLOCK	0x08000000 /* I cache unlock block */
20719ca68d9SBenno Rice #define  IC_CST_CMD_LOADLOCK	0x06000000 /* I cache load & lock block */
20819ca68d9SBenno Rice #define  IC_CST_CMD_DISABLE	0x04000000 /* I cache disable */
20919ca68d9SBenno Rice #define  IC_CST_CMD_ENABLE	0x02000000 /* I cache enable */
21019ca68d9SBenno Rice #define  IC_CST_CCER1		0x00200000 /* I cache error type 1 (RO) */
21119ca68d9SBenno Rice #define  IC_CST_CCER2		0x00100000 /* I cache error type 2 (RO) */
21219ca68d9SBenno Rice #define  IC_CST_CCER3		0x00080000 /* I cache error type 3 (RO) */
21319ca68d9SBenno Rice #define	SPR_IBAT4U		0x230	/* .6. Instruction BAT Reg 4 Upper */
21419ca68d9SBenno Rice #define SPR_IC_ADR		0x231	/* ..8 Instruction Cache Address */
21519ca68d9SBenno Rice #define	SPR_IBAT4L		0x231	/* .6. Instruction BAT Reg 4 Lower */
21619ca68d9SBenno Rice #define SPR_IC_DAT		0x232	/* ..8 Instruction Cache Data */
21719ca68d9SBenno Rice #define	SPR_IBAT5U		0x232	/* .6. Instruction BAT Reg 5 Upper */
21819ca68d9SBenno Rice #define	SPR_IBAT5L		0x233	/* .6. Instruction BAT Reg 5 Lower */
21919ca68d9SBenno Rice #define	SPR_IBAT6U		0x234	/* .6. Instruction BAT Reg 6 Upper */
22019ca68d9SBenno Rice #define	SPR_IBAT6L		0x235	/* .6. Instruction BAT Reg 6 Lower */
22119ca68d9SBenno Rice #define	SPR_IBAT7U		0x236	/* .6. Instruction BAT Reg 7 Upper */
22219ca68d9SBenno Rice #define	SPR_IBAT7L		0x237	/* .6. Instruction BAT Reg 7 Lower */
22319ca68d9SBenno Rice #define SPR_DC_CST		0x230	/* ..8 Data Cache CSR */
22419ca68d9SBenno Rice #define  DC_CST_DEN		0x80000000 /* D cache ENabled (RO) */
22519ca68d9SBenno Rice #define  DC_CST_DFWT		0x40000000 /* D cache Force Write-Thru (RO) */
22619ca68d9SBenno Rice #define  DC_CST_LES		0x20000000 /* D cache Little Endian Swap (RO) */
22719ca68d9SBenno Rice #define  DC_CST_CMD_FLUSH	0x0e000000 /* D cache invalidate all */
22819ca68d9SBenno Rice #define  DC_CST_CMD_INVALL	0x0c000000 /* D cache invalidate all */
22919ca68d9SBenno Rice #define  DC_CST_CMD_UNLOCKALL	0x0a000000 /* D cache unlock all */
23019ca68d9SBenno Rice #define  DC_CST_CMD_UNLOCK	0x08000000 /* D cache unlock block */
23119ca68d9SBenno Rice #define  DC_CST_CMD_CLRLESWAP	0x07000000 /* D cache clr little-endian swap */
23219ca68d9SBenno Rice #define  DC_CST_CMD_LOADLOCK	0x06000000 /* D cache load & lock block */
23319ca68d9SBenno Rice #define  DC_CST_CMD_SETLESWAP	0x05000000 /* D cache set little-endian swap */
23419ca68d9SBenno Rice #define  DC_CST_CMD_DISABLE	0x04000000 /* D cache disable */
23519ca68d9SBenno Rice #define  DC_CST_CMD_CLRFWT	0x03000000 /* D cache clear forced write-thru */
23619ca68d9SBenno Rice #define  DC_CST_CMD_ENABLE	0x02000000 /* D cache enable */
23719ca68d9SBenno Rice #define  DC_CST_CMD_SETFWT	0x01000000 /* D cache set forced write-thru */
23819ca68d9SBenno Rice #define  DC_CST_CCER1		0x00200000 /* D cache error type 1 (RO) */
23919ca68d9SBenno Rice #define  DC_CST_CCER2		0x00100000 /* D cache error type 2 (RO) */
24019ca68d9SBenno Rice #define  DC_CST_CCER3		0x00080000 /* D cache error type 3 (RO) */
24119ca68d9SBenno Rice #define	SPR_DBAT4U		0x238	/* .6. Data BAT Reg 4 Upper */
24219ca68d9SBenno Rice #define SPR_DC_ADR		0x231	/* ..8 Data Cache Address */
24319ca68d9SBenno Rice #define	SPR_DBAT4L		0x239	/* .6. Data BAT Reg 4 Lower */
24419ca68d9SBenno Rice #define SPR_DC_DAT		0x232	/* ..8 Data Cache Data */
24519ca68d9SBenno Rice #define	SPR_DBAT5U		0x23a	/* .6. Data BAT Reg 5 Upper */
24619ca68d9SBenno Rice #define	SPR_DBAT5L		0x23b	/* .6. Data BAT Reg 5 Lower */
24719ca68d9SBenno Rice #define	SPR_DBAT6U		0x23c	/* .6. Data BAT Reg 6 Upper */
24819ca68d9SBenno Rice #define	SPR_DBAT6L		0x23d	/* .6. Data BAT Reg 6 Lower */
24919ca68d9SBenno Rice #define	SPR_DBAT7U		0x23e	/* .6. Data BAT Reg 7 Upper */
25019ca68d9SBenno Rice #define	SPR_DBAT7L		0x23f	/* .6. Data BAT Reg 7 Lower */
25119ca68d9SBenno Rice #define	SPR_MI_CTR		0x310	/* ..8 IMMU control */
25219ca68d9SBenno Rice #define  Mx_CTR_GPM		0x80000000 /* Group Protection Mode */
25319ca68d9SBenno Rice #define  Mx_CTR_PPM		0x40000000 /* Page Protection Mode */
25419ca68d9SBenno Rice #define  Mx_CTR_CIDEF		0x20000000 /* Cache-Inhibit DEFault */
25519ca68d9SBenno Rice #define  MD_CTR_WTDEF		0x20000000 /* Write-Through DEFault */
25619ca68d9SBenno Rice #define  Mx_CTR_RSV4		0x08000000 /* Reserve 4 TLB entries */
25719ca68d9SBenno Rice #define  MD_CTR_TWAM		0x04000000 /* TableWalk Assist Mode */
25819ca68d9SBenno Rice #define  Mx_CTR_PPCS		0x02000000 /* Priv/user state compare mode */
25919ca68d9SBenno Rice #define  Mx_CTR_TLB_INDX	0x000001f0 /* TLB index mask */
26019ca68d9SBenno Rice #define  Mx_CTR_TLB_INDX_BITPOS	8	  /* TLB index shift */
26119ca68d9SBenno Rice #define	SPR_MI_AP		0x312	/* ..8 IMMU access protection */
26219ca68d9SBenno Rice #define  Mx_GP_SUPER(n)		(0 << (2*(15-(n)))) /* access is supervisor */
26319ca68d9SBenno Rice #define  Mx_GP_PAGE		(1 << (2*(15-(n)))) /* access is page protect */
26419ca68d9SBenno Rice #define  Mx_GP_SWAPPED		(2 << (2*(15-(n)))) /* access is swapped */
26519ca68d9SBenno Rice #define  Mx_GP_USER		(3 << (2*(15-(n)))) /* access is user */
26619ca68d9SBenno Rice #define	SPR_MI_EPN		0x313	/* ..8 IMMU effective number */
26719ca68d9SBenno Rice #define  Mx_EPN_EPN		0xfffff000 /* Effective Page Number mask */
26819ca68d9SBenno Rice #define  Mx_EPN_EV		0x00000020 /* Entry Valid */
26919ca68d9SBenno Rice #define  Mx_EPN_ASID		0x0000000f /* Address Space ID */
27019ca68d9SBenno Rice #define	SPR_MI_TWC		0x315	/* ..8 IMMU tablewalk control */
27119ca68d9SBenno Rice #define  MD_TWC_L2TB		0xfffff000 /* Level-2 Tablewalk Base */
27219ca68d9SBenno Rice #define  Mx_TWC_APG		0x000001e0 /* Access Protection Group */
27319ca68d9SBenno Rice #define  Mx_TWC_G		0x00000010 /* Guarded memory */
27419ca68d9SBenno Rice #define  Mx_TWC_PS		0x0000000c /* Page Size (L1) */
27519ca68d9SBenno Rice #define  MD_TWC_WT		0x00000002 /* Write-Through */
27619ca68d9SBenno Rice #define  Mx_TWC_V		0x00000001 /* Entry Valid */
27719ca68d9SBenno Rice #define	SPR_MI_RPN		0x316	/* ..8 IMMU real (phys) page number */
27819ca68d9SBenno Rice #define  Mx_RPN_RPN		0xfffff000 /* Real Page Number */
27919ca68d9SBenno Rice #define  Mx_RPN_PP		0x00000ff0 /* Page Protection */
28019ca68d9SBenno Rice #define  Mx_RPN_SPS		0x00000008 /* Small Page Size */
28119ca68d9SBenno Rice #define  Mx_RPN_SH		0x00000004 /* SHared page */
28219ca68d9SBenno Rice #define  Mx_RPN_CI		0x00000002 /* Cache Inhibit */
28319ca68d9SBenno Rice #define  Mx_RPN_V		0x00000001 /* Valid */
28419ca68d9SBenno Rice #define	SPR_MD_CTR		0x318	/* ..8 DMMU control */
28519ca68d9SBenno Rice #define	SPR_M_CASID		0x319	/* ..8 CASID */
28619ca68d9SBenno Rice #define  M_CASID		0x0000000f /* Current AS Id */
28719ca68d9SBenno Rice #define	SPR_MD_AP		0x31a	/* ..8 DMMU access protection */
28819ca68d9SBenno Rice #define	SPR_MD_EPN		0x31b	/* ..8 DMMU effective number */
28919ca68d9SBenno Rice #define	SPR_M_TWB		0x31c	/* ..8 MMU tablewalk base */
29019ca68d9SBenno Rice #define  M_TWB_L1TB		0xfffff000 /* level-1 translation base */
29119ca68d9SBenno Rice #define  M_TWB_L1INDX		0x00000ffc /* level-1 index */
29219ca68d9SBenno Rice #define	SPR_MD_TWC		0x31d	/* ..8 DMMU tablewalk control */
29319ca68d9SBenno Rice #define	SPR_MD_RPN		0x31e	/* ..8 DMMU real (phys) page number */
29419ca68d9SBenno Rice #define	SPR_MD_TW		0x31f	/* ..8 MMU tablewalk scratch */
29519ca68d9SBenno Rice #define	SPR_MI_CAM		0x330	/* ..8 IMMU CAM entry read */
29619ca68d9SBenno Rice #define	SPR_MI_RAM0		0x331	/* ..8 IMMU RAM entry read reg 0 */
29719ca68d9SBenno Rice #define	SPR_MI_RAM1		0x332	/* ..8 IMMU RAM entry read reg 1 */
29819ca68d9SBenno Rice #define	SPR_MD_CAM		0x338	/* ..8 IMMU CAM entry read */
29919ca68d9SBenno Rice #define	SPR_MD_RAM0		0x339	/* ..8 IMMU RAM entry read reg 0 */
30019ca68d9SBenno Rice #define	SPR_MD_RAM1		0x33a	/* ..8 IMMU RAM entry read reg 1 */
301b57e802aSBenno Rice #define	SPR_UMMCR2		0x3a0	/* .6. User Monitor Mode Control Register 2 */
302b57e802aSBenno Rice #define	SPR_UMMCR0		0x3a8	/* .6. User Monitor Mode Control Register 0 */
303b57e802aSBenno Rice #define	SPR_USIA		0x3ab	/* .6. User Sampled Instruction Address */
304b57e802aSBenno Rice #define	SPR_UMMCR1		0x3ac	/* .6. User Monitor Mode Control Register 1 */
305b57e802aSBenno Rice #define	SPR_ZPR			0x3b0	/* 4.. Zone Protection Register */
306b57e802aSBenno Rice #define	SPR_MMCR2		0x3b0	/* .6. Monitor Mode Control Register 2 */
307b57e802aSBenno Rice #define	 SPR_MMCR2_THRESHMULT_32  0x80000000 /* Multiply MMCR0 threshold by 32 */
308b57e802aSBenno Rice #define	 SPR_MMCR2_THRESHMULT_2	  0x00000000 /* Multiply MMCR0 threshold by 2 */
309b57e802aSBenno Rice #define	SPR_PID			0x3b1	/* 4.. Process ID */
310b57e802aSBenno Rice #define	SPR_PMC5		0x3b1	/* .6. Performance Counter Register 5 */
311b57e802aSBenno Rice #define	SPR_PMC6		0x3b2	/* .6. Performance Counter Register 6 */
312b57e802aSBenno Rice #define	SPR_CCR0		0x3b3	/* 4.. Core Configuration Register 0 */
313b57e802aSBenno Rice #define	SPR_IAC3		0x3b4	/* 4.. Instruction Address Compare 3 */
314b57e802aSBenno Rice #define	SPR_IAC4		0x3b5	/* 4.. Instruction Address Compare 4 */
315b57e802aSBenno Rice #define	SPR_DVC1		0x3b6	/* 4.. Data Value Compare 1 */
316b57e802aSBenno Rice #define	SPR_DVC2		0x3b7	/* 4.. Data Value Compare 2 */
317b57e802aSBenno Rice #define	SPR_MMCR0		0x3b8	/* .6. Monitor Mode Control Register 0 */
31830a2bd2fSNathan Whitehorn 
31930a2bd2fSNathan Whitehorn #define	SPR_970MMCR0		0x31b	/* ... Monitor Mode Control Register 0 (PPC 970) */
32030a2bd2fSNathan Whitehorn #define	SPR_970MMCR1		0x31e	/* ... Monitor Mode Control Register 1 (PPC 970) */
32130a2bd2fSNathan Whitehorn #define	SPR_970MMCRA		0x312	/* ... Monitor Mode Control Register 2 (PPC 970) */
32230a2bd2fSNathan Whitehorn #define	SPR_970MMCR0		0x31b	/* ... Monitor Mode Control Register 0 (PPC 970) */
32330a2bd2fSNathan Whitehorn #define SPR_970PMC1		0x313	/* ... PMC 1 */
32430a2bd2fSNathan Whitehorn #define SPR_970PMC2		0x314	/* ... PMC 2 */
32530a2bd2fSNathan Whitehorn #define SPR_970PMC3		0x315	/* ... PMC 3 */
32630a2bd2fSNathan Whitehorn #define SPR_970PMC4		0x316	/* ... PMC 4 */
32730a2bd2fSNathan Whitehorn #define SPR_970PMC5		0x317	/* ... PMC 5 */
32830a2bd2fSNathan Whitehorn #define SPR_970PMC6		0x318	/* ... PMC 6 */
32930a2bd2fSNathan Whitehorn #define SPR_970PMC7		0x319	/* ... PMC 7 */
33030a2bd2fSNathan Whitehorn #define SPR_970PMC8		0x31a	/* ... PMC 8 */
33130a2bd2fSNathan Whitehorn 
332b57e802aSBenno Rice #define	  SPR_MMCR0_FC		  0x80000000 /* Freeze counters */
333b57e802aSBenno Rice #define	  SPR_MMCR0_FCS		  0x40000000 /* Freeze counters in supervisor mode */
334b57e802aSBenno Rice #define	  SPR_MMCR0_FCP		  0x20000000 /* Freeze counters in user mode */
335b57e802aSBenno Rice #define	  SPR_MMCR0_FCM1	  0x10000000 /* Freeze counters when mark=1 */
336b57e802aSBenno Rice #define	  SPR_MMCR0_FCM0	  0x08000000 /* Freeze counters when mark=0 */
337b57e802aSBenno Rice #define	  SPR_MMCR0_PMXE	  0x04000000 /* Enable PM interrupt */
338b57e802aSBenno Rice #define	  SPR_MMCR0_FCECE	  0x02000000 /* Freeze counters after event */
339b57e802aSBenno Rice #define	  SPR_MMCR0_TBSEL_15	  0x01800000 /* Count bit 15 of TBL */
340b57e802aSBenno Rice #define	  SPR_MMCR0_TBSEL_19	  0x01000000 /* Count bit 19 of TBL */
341b57e802aSBenno Rice #define	  SPR_MMCR0_TBSEL_23	  0x00800000 /* Count bit 23 of TBL */
342b57e802aSBenno Rice #define	  SPR_MMCR0_TBSEL_31	  0x00000000 /* Count bit 31 of TBL */
343b57e802aSBenno Rice #define	  SPR_MMCR0_TBEE	  0x00400000 /* Time-base event enable */
344b57e802aSBenno Rice #define	  SPR_MMCRO_THRESHOLD(x)  ((x) << 16) /* Threshold value */
345b57e802aSBenno Rice #define	  SPR_MMCR0_PMC1CE	  0x00008000 /* PMC1 condition enable */
346b57e802aSBenno Rice #define	  SPR_MMCR0_PMCNCE	  0x00004000 /* PMCn condition enable */
347b57e802aSBenno Rice #define	  SPR_MMCR0_TRIGGER	  0x00002000 /* Trigger */
348b57e802aSBenno Rice #define	  SPR_MMCR0_PMC1SEL(x)	  ((x) << 6) /* PMC1 selector */
349b57e802aSBenno Rice #define	  SPR_MMCR0_PMC2SEL(x)	  ((x) << 0) /* PMC2 selector */
3507f0ad28fSNathan Whitehorn #define	  SPR_970MMCR0_PMC1SEL(x) ((x) << 8) /* PMC1 selector (970) */
35130a2bd2fSNathan Whitehorn #define	  SPR_970MMCR0_PMC2SEL(x) ((x) << 1) /* PMC2 selector (970) */
352b57e802aSBenno Rice #define	SPR_SGR			0x3b9	/* 4.. Storage Guarded Register */
353b57e802aSBenno Rice #define	SPR_PMC1		0x3b9	/* .6. Performance Counter Register 1 */
354b57e802aSBenno Rice #define	SPR_DCWR		0x3ba	/* 4.. Data Cache Write-through Register */
355b57e802aSBenno Rice #define	SPR_PMC2		0x3ba	/* .6. Performance Counter Register 2 */
356b57e802aSBenno Rice #define	SPR_SLER		0x3bb	/* 4.. Storage Little Endian Register */
357b57e802aSBenno Rice #define	SPR_SIA			0x3bb	/* .6. Sampled Instruction Address */
358b57e802aSBenno Rice #define	SPR_MMCR1		0x3bc	/* .6. Monitor Mode Control Register 2 */
359b57e802aSBenno Rice #define	  SPR_MMCR1_PMC3SEL(x)	  ((x) << 27) /* PMC 3 selector */
360b57e802aSBenno Rice #define	  SPR_MMCR1_PMC4SEL(x)	  ((x) << 22) /* PMC 4 selector */
361b57e802aSBenno Rice #define	  SPR_MMCR1_PMC5SEL(x)	  ((x) << 17) /* PMC 5 selector */
362b57e802aSBenno Rice #define	  SPR_MMCR1_PMC6SEL(x)	  ((x) << 11) /* PMC 6 selector */
363b57e802aSBenno Rice 
364b57e802aSBenno Rice #define	SPR_SU0R		0x3bc	/* 4.. Storage User-defined 0 Register */
365b57e802aSBenno Rice #define	SPR_PMC3		0x3bd	/* .6. Performance Counter Register 3 */
366b57e802aSBenno Rice #define	SPR_PMC4		0x3be	/* .6. Performance Counter Register 4 */
367b57e802aSBenno Rice #define	SPR_DMISS		0x3d0	/* .68 Data TLB Miss Address Register */
368b57e802aSBenno Rice #define	SPR_DCMP		0x3d1	/* .68 Data TLB Compare Register */
369b57e802aSBenno Rice #define	SPR_HASH1		0x3d2	/* .68 Primary Hash Address Register */
370b57e802aSBenno Rice #define	SPR_ICDBDR		0x3d3	/* 4.. Instruction Cache Debug Data Register */
371b57e802aSBenno Rice #define	SPR_HASH2		0x3d3	/* .68 Secondary Hash Address Register */
372b57e802aSBenno Rice #define	SPR_IMISS		0x3d4	/* .68 Instruction TLB Miss Address Register */
373b57e802aSBenno Rice #define	SPR_TLBMISS		0x3d4	/* .6. TLB Miss Address Register */
374b57e802aSBenno Rice #define	SPR_DEAR		0x3d5	/* 4.. Data Error Address Register */
375b57e802aSBenno Rice #define	SPR_ICMP		0x3d5	/* .68 Instruction TLB Compare Register */
376b57e802aSBenno Rice #define	SPR_PTEHI		0x3d5	/* .6. Instruction TLB Compare Register */
377b57e802aSBenno Rice #define	SPR_EVPR		0x3d6	/* 4.. Exception Vector Prefix Register */
378b57e802aSBenno Rice #define	SPR_RPA			0x3d6	/* .68 Required Physical Address Register */
379b57e802aSBenno Rice #define	SPR_PTELO		0x3d6	/* .6. Required Physical Address Register */
380ffb56695SRafal Jaworowski 
381ffb56695SRafal Jaworowski #define	SPR_TSR			0x150	/* ..8 Timer Status Register */
382ffb56695SRafal Jaworowski #define	SPR_TCR			0x154	/* ..8 Timer Control Register */
383ffb56695SRafal Jaworowski 
384b57e802aSBenno Rice #define	  TSR_ENW		  0x80000000 /* Enable Next Watchdog */
385b57e802aSBenno Rice #define	  TSR_WIS		  0x40000000 /* Watchdog Interrupt Status */
386b57e802aSBenno Rice #define	  TSR_WRS_MASK		  0x30000000 /* Watchdog Reset Status */
387b57e802aSBenno Rice #define	  TSR_WRS_NONE		  0x00000000 /* No watchdog reset has occurred */
388b57e802aSBenno Rice #define	  TSR_WRS_CORE		  0x10000000 /* Core reset was forced by the watchdog */
389b57e802aSBenno Rice #define	  TSR_WRS_CHIP		  0x20000000 /* Chip reset was forced by the watchdog */
390b57e802aSBenno Rice #define	  TSR_WRS_SYSTEM	  0x30000000 /* System reset was forced by the watchdog */
391b57e802aSBenno Rice #define	  TSR_PIS		  0x08000000 /* PIT Interrupt Status */
392ffb56695SRafal Jaworowski #define	  TSR_DIS		  0x08000000 /* Decrementer Interrupt Status */
393b57e802aSBenno Rice #define	  TSR_FIS		  0x04000000 /* FIT Interrupt Status */
394ffb56695SRafal Jaworowski 
395b57e802aSBenno Rice #define	  TCR_WP_MASK		  0xc0000000 /* Watchdog Period mask */
396b57e802aSBenno Rice #define	  TCR_WP_2_17		  0x00000000 /* 2**17 clocks */
397b57e802aSBenno Rice #define	  TCR_WP_2_21		  0x40000000 /* 2**21 clocks */
398b57e802aSBenno Rice #define	  TCR_WP_2_25		  0x80000000 /* 2**25 clocks */
399b57e802aSBenno Rice #define	  TCR_WP_2_29		  0xc0000000 /* 2**29 clocks */
400b57e802aSBenno Rice #define	  TCR_WRC_MASK		  0x30000000 /* Watchdog Reset Control mask */
401b57e802aSBenno Rice #define	  TCR_WRC_NONE		  0x00000000 /* No watchdog reset */
402b57e802aSBenno Rice #define	  TCR_WRC_CORE		  0x10000000 /* Core reset */
403b57e802aSBenno Rice #define	  TCR_WRC_CHIP		  0x20000000 /* Chip reset */
404b57e802aSBenno Rice #define	  TCR_WRC_SYSTEM	  0x30000000 /* System reset */
405b57e802aSBenno Rice #define	  TCR_WIE		  0x08000000 /* Watchdog Interrupt Enable */
406b57e802aSBenno Rice #define	  TCR_PIE		  0x04000000 /* PIT Interrupt Enable */
407ffb56695SRafal Jaworowski #define	  TCR_DIE		  0x04000000 /* Pecrementer Interrupt Enable */
408b57e802aSBenno Rice #define	  TCR_FP_MASK		  0x03000000 /* FIT Period */
409b57e802aSBenno Rice #define	  TCR_FP_2_9		  0x00000000 /* 2**9 clocks */
410b57e802aSBenno Rice #define	  TCR_FP_2_13		  0x01000000 /* 2**13 clocks */
411b57e802aSBenno Rice #define	  TCR_FP_2_17		  0x02000000 /* 2**17 clocks */
412b57e802aSBenno Rice #define	  TCR_FP_2_21		  0x03000000 /* 2**21 clocks */
413b57e802aSBenno Rice #define	  TCR_FIE		  0x00800000 /* FIT Interrupt Enable */
414b57e802aSBenno Rice #define	  TCR_ARE		  0x00400000 /* Auto Reload Enable */
415ffb56695SRafal Jaworowski 
416b57e802aSBenno Rice #define	SPR_PIT			0x3db	/* 4.. Programmable Interval Timer */
417b57e802aSBenno Rice #define	SPR_SRR2		0x3de	/* 4.. Save/Restore Register 2 */
418b57e802aSBenno Rice #define	SPR_SRR3		0x3df	/* 4.. Save/Restore Register 3 */
419ffb56695SRafal Jaworowski #define	SPR_HID0		0x3f0	/* ..8 Hardware Implementation Register 0 */
420ffb56695SRafal Jaworowski #define	SPR_HID1		0x3f1	/* ..8 Hardware Implementation Register 1 */
4218cf9d6cdSNathan Whitehorn #define	SPR_HID4		0x3f4	/* ..8 Hardware Implementation Register 4 */
4228cf9d6cdSNathan Whitehorn #define	SPR_HID5		0x3f6	/* ..8 Hardware Implementation Register 5 */
423*2971d3bbSNathan Whitehorn #define	SPR_HID6		0x3f9	/* ..8 Hardware Implementation Register 6 */
424*2971d3bbSNathan Whitehorn 
425*2971d3bbSNathan Whitehorn #define	SPR_CELL_TSRL		0x380	/* ... Cell BE Thread Status Register */
426*2971d3bbSNathan Whitehorn #define	SPR_CELL_TSCR		0x399	/* ... Cell BE Thread Switch Register */
427ffb56695SRafal Jaworowski 
428ffb56695SRafal Jaworowski #if defined(AIM)
429b57e802aSBenno Rice #define	SPR_DBSR		0x3f0	/* 4.. Debug Status Register */
430b57e802aSBenno Rice #define	  DBSR_IC		  0x80000000 /* Instruction completion debug event */
431b57e802aSBenno Rice #define	  DBSR_BT		  0x40000000 /* Branch Taken debug event */
432b57e802aSBenno Rice #define	  DBSR_EDE		  0x20000000 /* Exception debug event */
433b57e802aSBenno Rice #define	  DBSR_TIE		  0x10000000 /* Trap Instruction debug event */
434b57e802aSBenno Rice #define	  DBSR_UDE		  0x08000000 /* Unconditional debug event */
435b57e802aSBenno Rice #define	  DBSR_IA1		  0x04000000 /* IAC1 debug event */
436b57e802aSBenno Rice #define	  DBSR_IA2		  0x02000000 /* IAC2 debug event */
437b57e802aSBenno Rice #define	  DBSR_DR1		  0x01000000 /* DAC1 Read debug event */
438b57e802aSBenno Rice #define	  DBSR_DW1		  0x00800000 /* DAC1 Write debug event */
439b57e802aSBenno Rice #define	  DBSR_DR2		  0x00400000 /* DAC2 Read debug event */
440b57e802aSBenno Rice #define	  DBSR_DW2		  0x00200000 /* DAC2 Write debug event */
441b57e802aSBenno Rice #define	  DBSR_IDE		  0x00100000 /* Imprecise debug event */
442b57e802aSBenno Rice #define	  DBSR_IA3		  0x00080000 /* IAC3 debug event */
443b57e802aSBenno Rice #define	  DBSR_IA4		  0x00040000 /* IAC4 debug event */
444b57e802aSBenno Rice #define	  DBSR_MRR		  0x00000300 /* Most recent reset */
445b57e802aSBenno Rice #define	SPR_DBCR0		0x3f2	/* 4.. Debug Control Register 0 */
446ffb56695SRafal Jaworowski #define	SPR_DBCR1		0x3bd	/* 4.. Debug Control Register 1 */
447ffb56695SRafal Jaworowski #define	SPR_IAC1		0x3f4	/* 4.. Instruction Address Compare 1 */
448ffb56695SRafal Jaworowski #define	SPR_IAC2		0x3f5	/* 4.. Instruction Address Compare 2 */
449ffb56695SRafal Jaworowski #define	SPR_DAC1		0x3f6	/* 4.. Data Address Compare 1 */
450ffb56695SRafal Jaworowski #define	SPR_DAC2		0x3f7	/* 4.. Data Address Compare 2 */
451ffb56695SRafal Jaworowski #define	SPR_PIR			0x3ff	/* .6. Processor Identification Register */
452ffb56695SRafal Jaworowski #elif defined(E500)
453b40ce02aSNathan Whitehorn #define	SPR_PIR			0x11e	/* ..8 Processor Identification Register */
454ffb56695SRafal Jaworowski #define	SPR_DBSR		0x130	/* ..8 Debug Status Register */
455ffb56695SRafal Jaworowski #define	  DBSR_IDE		  0x80000000 /* Imprecise debug event. */
456ffb56695SRafal Jaworowski #define	  DBSR_UDE		  0x40000000 /* Unconditional debug event. */
457ffb56695SRafal Jaworowski #define	  DBSR_MRR		  0x30000000 /* Most recent Reset (mask). */
458ffb56695SRafal Jaworowski #define	  DBSR_ICMP		  0x08000000 /* Instr. complete debug event. */
459ffb56695SRafal Jaworowski #define	  DBSR_BRT		  0x04000000 /* Branch taken debug event. */
460ffb56695SRafal Jaworowski #define	  DBSR_IRPT		  0x02000000 /* Interrupt taken debug event. */
461ffb56695SRafal Jaworowski #define	  DBSR_TRAP		  0x01000000 /* Trap instr. debug event. */
462ffb56695SRafal Jaworowski #define	  DBSR_IAC1		  0x00800000 /* Instr. address compare #1. */
463ffb56695SRafal Jaworowski #define	  DBSR_IAC2		  0x00400000 /* Instr. address compare #2. */
464ffb56695SRafal Jaworowski #define	  DBSR_IAC3		  0x00200000 /* Instr. address compare #3. */
465ffb56695SRafal Jaworowski #define	  DBSR_IAC4		  0x00100000 /* Instr. address compare #4. */
466ffb56695SRafal Jaworowski #define	  DBSR_DAC1R		  0x00080000 /* Data addr. read compare #1. */
467ffb56695SRafal Jaworowski #define	  DBSR_DAC1W		  0x00040000 /* Data addr. write compare #1. */
468ffb56695SRafal Jaworowski #define	  DBSR_DAC2R		  0x00020000 /* Data addr. read compare #2. */
469ffb56695SRafal Jaworowski #define	  DBSR_DAC2W		  0x00010000 /* Data addr. write compare #2. */
470ffb56695SRafal Jaworowski #define	  DBSR_RET		  0x00008000 /* Return debug event. */
471ffb56695SRafal Jaworowski #define	SPR_DBCR0		0x134	/* ..8 Debug Control Register 0 */
472ffb56695SRafal Jaworowski #define	SPR_DBCR1		0x135	/* ..8 Debug Control Register 1 */
473ffb56695SRafal Jaworowski #define	SPR_IAC1		0x138	/* ..8 Instruction Address Compare 1 */
474ffb56695SRafal Jaworowski #define	SPR_IAC2		0x139	/* ..8 Instruction Address Compare 2 */
475ffb56695SRafal Jaworowski #define	SPR_DAC1		0x13c	/* ..8 Data Address Compare 1 */
476ffb56695SRafal Jaworowski #define	SPR_DAC2		0x13d	/* ..8 Data Address Compare 2 */
477ffb56695SRafal Jaworowski #endif
478ffb56695SRafal Jaworowski 
479b57e802aSBenno Rice #define	  DBCR0_EDM		  0x80000000 /* External Debug Mode */
480b57e802aSBenno Rice #define	  DBCR0_IDM		  0x40000000 /* Internal Debug Mode */
481b57e802aSBenno Rice #define	  DBCR0_RST_MASK	  0x30000000 /* ReSeT */
482b57e802aSBenno Rice #define	  DBCR0_RST_NONE	  0x00000000 /*   No action */
483b57e802aSBenno Rice #define	  DBCR0_RST_CORE	  0x10000000 /*   Core reset */
484b57e802aSBenno Rice #define	  DBCR0_RST_CHIP	  0x20000000 /*   Chip reset */
485b57e802aSBenno Rice #define	  DBCR0_RST_SYSTEM	  0x30000000 /*   System reset */
486b57e802aSBenno Rice #define	  DBCR0_IC		  0x08000000 /* Instruction Completion debug event */
487b57e802aSBenno Rice #define	  DBCR0_BT		  0x04000000 /* Branch Taken debug event */
488b57e802aSBenno Rice #define	  DBCR0_EDE		  0x02000000 /* Exception Debug Event */
489b57e802aSBenno Rice #define	  DBCR0_TDE		  0x01000000 /* Trap Debug Event */
490b57e802aSBenno Rice #define	  DBCR0_IA1		  0x00800000 /* IAC (Instruction Address Compare) 1 debug event */
491b57e802aSBenno Rice #define	  DBCR0_IA2		  0x00400000 /* IAC 2 debug event */
492b57e802aSBenno Rice #define	  DBCR0_IA12		  0x00200000 /* Instruction Address Range Compare 1-2 */
493b57e802aSBenno Rice #define	  DBCR0_IA12X		  0x00100000 /* IA12 eXclusive */
494b57e802aSBenno Rice #define	  DBCR0_IA3		  0x00080000 /* IAC 3 debug event */
495b57e802aSBenno Rice #define	  DBCR0_IA4		  0x00040000 /* IAC 4 debug event */
496b57e802aSBenno Rice #define	  DBCR0_IA34		  0x00020000 /* Instruction Address Range Compare 3-4 */
497b57e802aSBenno Rice #define	  DBCR0_IA34X		  0x00010000 /* IA34 eXclusive */
498b57e802aSBenno Rice #define	  DBCR0_IA12T		  0x00008000 /* Instruction Address Range Compare 1-2 range Toggle */
499b57e802aSBenno Rice #define	  DBCR0_IA34T		  0x00004000 /* Instruction Address Range Compare 3-4 range Toggle */
500b57e802aSBenno Rice #define	  DBCR0_FT		  0x00000001 /* Freeze Timers on debug event */
501ffb56695SRafal Jaworowski 
502b57e802aSBenno Rice #define	SPR_IABR		0x3f2	/* ..8 Instruction Address Breakpoint Register 0 */
503b57e802aSBenno Rice #define	SPR_DABR		0x3f5	/* .6. Data Address Breakpoint Register */
50419ca68d9SBenno Rice #define	SPR_MSSCR0		0x3f6	/* .6. Memory SubSystem Control Register */
50519ca68d9SBenno Rice #define	  MSSCR0_SHDEN		  0x80000000 /* 0: Shared-state enable */
50619ca68d9SBenno Rice #define	  MSSCR0_SHDPEN3	  0x40000000 /* 1: ~SHD[01] signal enable in MEI mode */
50719ca68d9SBenno Rice #define	  MSSCR0_L1INTVEN	  0x38000000 /* 2-4: L1 data cache ~HIT intervention enable */
50819ca68d9SBenno Rice #define	  MSSCR0_L2INTVEN	  0x07000000 /* 5-7: L2 data cache ~HIT intervention enable*/
50919ca68d9SBenno Rice #define	  MSSCR0_DL1HWF		  0x00800000 /* 8: L1 data cache hardware flush */
51019ca68d9SBenno Rice #define	  MSSCR0_MBO		  0x00400000 /* 9: must be one */
51119ca68d9SBenno Rice #define	  MSSCR0_EMODE		  0x00200000 /* 10: MPX bus mode (read-only) */
51219ca68d9SBenno Rice #define	  MSSCR0_ABD		  0x00100000 /* 11: address bus driven (read-only) */
51319ca68d9SBenno Rice #define	  MSSCR0_MBZ		  0x000fffff /* 12-31: must be zero */
514b57e802aSBenno Rice #define	SPR_L2PM		0x3f8	/* .6. L2 Private Memory Control Register */
515b57e802aSBenno Rice #define	SPR_L2CR		0x3f9	/* .6. L2 Control Register */
516b57e802aSBenno Rice #define	  L2CR_L2E		  0x80000000 /* 0: L2 enable */
517b57e802aSBenno Rice #define	  L2CR_L2PE		  0x40000000 /* 1: L2 data parity enable */
518b57e802aSBenno Rice #define	  L2CR_L2SIZ		  0x30000000 /* 2-3: L2 size */
519b57e802aSBenno Rice #define	   L2SIZ_2M		  0x00000000
520b57e802aSBenno Rice #define	   L2SIZ_256K		  0x10000000
521b57e802aSBenno Rice #define	   L2SIZ_512K		  0x20000000
522b57e802aSBenno Rice #define	   L2SIZ_1M		  0x30000000
523b57e802aSBenno Rice #define	  L2CR_L2CLK		  0x0e000000 /* 4-6: L2 clock ratio */
524b57e802aSBenno Rice #define	   L2CLK_DIS		  0x00000000 /* disable L2 clock */
525b57e802aSBenno Rice #define	   L2CLK_10		  0x02000000 /* core clock / 1   */
526b57e802aSBenno Rice #define	   L2CLK_15		  0x04000000 /*            / 1.5 */
527b57e802aSBenno Rice #define	   L2CLK_20		  0x08000000 /*            / 2   */
528b57e802aSBenno Rice #define	   L2CLK_25		  0x0a000000 /*            / 2.5 */
529b57e802aSBenno Rice #define	   L2CLK_30		  0x0c000000 /*            / 3   */
530b57e802aSBenno Rice #define	  L2CR_L2RAM		  0x01800000 /* 7-8: L2 RAM type */
531b57e802aSBenno Rice #define	   L2RAM_FLOWTHRU_BURST	  0x00000000
532b57e802aSBenno Rice #define	   L2RAM_PIPELINE_BURST	  0x01000000
533b57e802aSBenno Rice #define	   L2RAM_PIPELINE_LATE	  0x01800000
534b57e802aSBenno Rice #define	  L2CR_L2DO		  0x00400000 /* 9: L2 data-only.
535b57e802aSBenno Rice 				      Setting this bit disables instruction
536b57e802aSBenno Rice 				      caching. */
537b57e802aSBenno Rice #define	  L2CR_L2I		  0x00200000 /* 10: L2 global invalidate. */
538b57e802aSBenno Rice #define	  L2CR_L2CTL		  0x00100000 /* 11: L2 RAM control (ZZ enable).
539b57e802aSBenno Rice 				      Enables automatic operation of the
540b57e802aSBenno Rice 				      L2ZZ (low-power mode) signal. */
541b57e802aSBenno Rice #define	  L2CR_L2WT		  0x00080000 /* 12: L2 write-through. */
542b57e802aSBenno Rice #define	  L2CR_L2TS		  0x00040000 /* 13: L2 test support. */
543b57e802aSBenno Rice #define	  L2CR_L2OH		  0x00030000 /* 14-15: L2 output hold. */
544b57e802aSBenno Rice #define	  L2CR_L2SL		  0x00008000 /* 16: L2 DLL slow. */
545b57e802aSBenno Rice #define	  L2CR_L2DF		  0x00004000 /* 17: L2 differential clock. */
546b57e802aSBenno Rice #define	  L2CR_L2BYP		  0x00002000 /* 18: L2 DLL bypass. */
54719ca68d9SBenno Rice #define	  L2CR_L2FA		  0x00001000 /* 19: L2 flush assist (for software flush). */
54819ca68d9SBenno Rice #define	  L2CR_L2HWF		  0x00000800 /* 20: L2 hardware flush. */
54919ca68d9SBenno Rice #define	  L2CR_L2IO		  0x00000400 /* 21: L2 instruction-only. */
55019ca68d9SBenno Rice #define	  L2CR_L2CLKSTP		  0x00000200 /* 22: L2 clock stop. */
55119ca68d9SBenno Rice #define	  L2CR_L2DRO		  0x00000100 /* 23: L2DLL rollover checkstop enable. */
552b57e802aSBenno Rice #define	  L2CR_L2IP		  0x00000001 /* 31: L2 global invalidate in */
553b57e802aSBenno Rice 					     /*     progress (read only). */
554cf0c3004SMarcel Moolenaar 
555b57e802aSBenno Rice #define	SPR_L3CR		0x3fa	/* .6. L3 Control Register */
556b57e802aSBenno Rice #define	  L3CR_L3E		  0x80000000 /* 0: L3 enable */
557cf0c3004SMarcel Moolenaar #define	  L3CR_L3PE		  0x40000000 /* 1: L3 data parity enable */
558cf0c3004SMarcel Moolenaar #define	  L3CR_L3APE		  0x20000000
559b57e802aSBenno Rice #define	  L3CR_L3SIZ		  0x10000000 /* 3: L3 size (0=1MB, 1=2MB) */
560cf0c3004SMarcel Moolenaar #define	  L3CR_L3CLKEN		  0x08000000 /* 4: Enables L3_CLK[0:1] */
561cf0c3004SMarcel Moolenaar #define	  L3CR_L3CLK		  0x03800000
562cf0c3004SMarcel Moolenaar #define	  L3CR_L3IO		  0x00400000
563cf0c3004SMarcel Moolenaar #define	  L3CR_L3CLKEXT		  0x00200000
564cf0c3004SMarcel Moolenaar #define	  L3CR_L3CKSPEXT	  0x00100000
565cf0c3004SMarcel Moolenaar #define	  L3CR_L3OH1		  0x00080000
566cf0c3004SMarcel Moolenaar #define	  L3CR_L3SPO		  0x00040000
567cf0c3004SMarcel Moolenaar #define	  L3CR_L3CKSP		  0x00030000
568cf0c3004SMarcel Moolenaar #define	  L3CR_L3PSP		  0x0000e000
569cf0c3004SMarcel Moolenaar #define	  L3CR_L3REP		  0x00001000
570cf0c3004SMarcel Moolenaar #define	  L3CR_L3HWF		  0x00000800
571cf0c3004SMarcel Moolenaar #define	  L3CR_L3I		  0x00000400 /* 21: L3 global invalidate */
572cf0c3004SMarcel Moolenaar #define	  L3CR_L3RT		  0x00000300
573cf0c3004SMarcel Moolenaar #define	  L3CR_L3NIRCA		  0x00000080
574cf0c3004SMarcel Moolenaar #define	  L3CR_L3DO		  0x00000040
575cf0c3004SMarcel Moolenaar #define	  L3CR_PMEN		  0x00000004
576cf0c3004SMarcel Moolenaar #define	  L3CR_PMSIZ		  0x00000003
577cf0c3004SMarcel Moolenaar 
578b57e802aSBenno Rice #define	SPR_DCCR		0x3fa	/* 4.. Data Cache Cachability Register */
579b57e802aSBenno Rice #define	SPR_ICCR		0x3fb	/* 4.. Instruction Cache Cachability Register */
580b57e802aSBenno Rice #define	SPR_THRM1		0x3fc	/* .6. Thermal Management Register */
581b57e802aSBenno Rice #define	SPR_THRM2		0x3fd	/* .6. Thermal Management Register */
582b57e802aSBenno Rice #define	 SPR_THRM_TIN		  0x80000000 /* Thermal interrupt bit (RO) */
583b57e802aSBenno Rice #define	 SPR_THRM_TIV		  0x40000000 /* Thermal interrupt valid (RO) */
584b57e802aSBenno Rice #define	 SPR_THRM_THRESHOLD(x)	  ((x) << 23) /* Thermal sensor threshold */
585b57e802aSBenno Rice #define	 SPR_THRM_TID		  0x00000004 /* Thermal interrupt direction */
586b57e802aSBenno Rice #define	 SPR_THRM_TIE		  0x00000002 /* Thermal interrupt enable */
587b57e802aSBenno Rice #define	 SPR_THRM_VALID		  0x00000001 /* Valid bit */
588b57e802aSBenno Rice #define	SPR_THRM3		0x3fe	/* .6. Thermal Management Register */
589b57e802aSBenno Rice #define	 SPR_THRM_TIMER(x)	  ((x) << 1) /* Sampling interval timer */
590b57e802aSBenno Rice #define	 SPR_THRM_ENABLE       	  0x00000001 /* TAU Enable */
591b57e802aSBenno Rice #define	SPR_FPECR		0x3fe	/* .6. Floating-Point Exception Cause Register */
592b57e802aSBenno Rice 
593b57e802aSBenno Rice /* Time Base Register declarations */
594ffb56695SRafal Jaworowski #define	TBR_TBL			0x10c	/* 468 Time Base Lower - read */
595ffb56695SRafal Jaworowski #define	TBR_TBU			0x10d	/* 468 Time Base Upper - read */
596ffb56695SRafal Jaworowski #define	TBR_TBWL		0x11c	/* 468 Time Base Lower - supervisor, write */
597ffb56695SRafal Jaworowski #define	TBR_TBWU		0x11d	/* 468 Time Base Upper - supervisor, write */
598b57e802aSBenno Rice 
599b57e802aSBenno Rice /* Performance counter declarations */
600b57e802aSBenno Rice #define	PMC_OVERFLOW	  	0x80000000 /* Counter has overflowed */
601b57e802aSBenno Rice 
60230a2bd2fSNathan Whitehorn /* The first five countable [non-]events are common to many PMC's */
603b57e802aSBenno Rice #define	PMCN_NONE		 0 /* Count nothing */
604b57e802aSBenno Rice #define	PMCN_CYCLES		 1 /* Processor cycles */
605b57e802aSBenno Rice #define	PMCN_ICOMP		 2 /* Instructions completed */
606b57e802aSBenno Rice #define	PMCN_TBLTRANS		 3 /* TBL bit transitions */
607b57e802aSBenno Rice #define	PCMN_IDISPATCH		 4 /* Instructions dispatched */
608b57e802aSBenno Rice 
60930a2bd2fSNathan Whitehorn /* Similar things for the 970 PMC direct counters */
61030a2bd2fSNathan Whitehorn #define	PMC970N_NONE		0x8 /* Count nothing */
61130a2bd2fSNathan Whitehorn #define	PMC970N_CYCLES		0xf /* Processor cycles */
61230a2bd2fSNathan Whitehorn #define	PMC970N_ICOMP		0x9 /* Instructions completed */
61330a2bd2fSNathan Whitehorn 
614ffb56695SRafal Jaworowski #if defined(AIM)
615ffb56695SRafal Jaworowski 
616ffb56695SRafal Jaworowski #define SPR_ESR			0x3d4	/* 4.. Exception Syndrome Register */
617ffb56695SRafal Jaworowski #define	  ESR_MCI		  0x80000000 /* Machine check - instruction */
618ffb56695SRafal Jaworowski #define	  ESR_PIL		  0x08000000 /* Program interrupt - illegal */
619ffb56695SRafal Jaworowski #define	  ESR_PPR		  0x04000000 /* Program interrupt - privileged */
620ffb56695SRafal Jaworowski #define	  ESR_PTR		  0x02000000 /* Program interrupt - trap */
621ffb56695SRafal Jaworowski #define	  ESR_ST		  0x01000000 /* Store operation */
622ffb56695SRafal Jaworowski #define	  ESR_DST		  0x00800000 /* Data storage interrupt - store fault */
623ffb56695SRafal Jaworowski #define	  ESR_DIZ		  0x00800000 /* Data/instruction storage interrupt - zone fault */
624ffb56695SRafal Jaworowski #define	  ESR_U0F		  0x00008000 /* Data storage interrupt - U0 fault */
625ffb56695SRafal Jaworowski 
626ffb56695SRafal Jaworowski #elif defined(E500)
627ffb56695SRafal Jaworowski 
628ffb56695SRafal Jaworowski #define	SPR_ESR			0x003e	/* ..8 Exception Syndrome Register */
629ffb56695SRafal Jaworowski #define	  ESR_PIL		  0x08000000 /* Program interrupt - illegal */
630ffb56695SRafal Jaworowski #define	  ESR_PPR		  0x04000000 /* Program interrupt - privileged */
631ffb56695SRafal Jaworowski #define	  ESR_PTR		  0x02000000 /* Program interrupt - trap */
632ffb56695SRafal Jaworowski #define	  ESR_ST		  0x00800000 /* Store operation */
633ffb56695SRafal Jaworowski #define	  ESR_DLK		  0x00200000 /* Data storage, D cache locking */
634ffb56695SRafal Jaworowski #define	  ESR_ILK		  0x00100000 /* Data storage, I cache locking */
635ffb56695SRafal Jaworowski #define	  ESR_BO		  0x00020000 /* Data/instruction storage, byte ordering */
636ffb56695SRafal Jaworowski #define	  ESR_SPE		  0x00000080 /* SPE exception bit */
637ffb56695SRafal Jaworowski 
638ffb56695SRafal Jaworowski #define	SPR_CSRR0		0x03a	/* ..8 58 Critical SRR0 */
639ffb56695SRafal Jaworowski #define	SPR_CSRR1		0x03b	/* ..8 59 Critical SRR1 */
640ffb56695SRafal Jaworowski #define	SPR_MCSRR0		0x23a	/* ..8 570 Machine check SRR0 */
641ffb56695SRafal Jaworowski #define	SPR_MCSRR1		0x23b	/* ..8 571 Machine check SRR1 */
642ffb56695SRafal Jaworowski 
643ffb56695SRafal Jaworowski #define	SPR_SVR			0x3ff	/* ..8 1023 System Version Register */
644fe48da3fSRafal Jaworowski #define	  SVR_MPC8533		  0x803c
645fe48da3fSRafal Jaworowski #define	  SVR_MPC8533E		  0x8034
646fe48da3fSRafal Jaworowski #define	  SVR_MPC8541		  0x8072
647fe48da3fSRafal Jaworowski #define	  SVR_MPC8541E		  0x807a
648389e4721SRafal Jaworowski #define	  SVR_MPC8548		  0x8031
649389e4721SRafal Jaworowski #define	  SVR_MPC8548E		  0x8039
650fe48da3fSRafal Jaworowski #define	  SVR_MPC8555		  0x8071
651fe48da3fSRafal Jaworowski #define	  SVR_MPC8555E		  0x8079
652fe48da3fSRafal Jaworowski #define	  SVR_MPC8572		  0x80e0
653fe48da3fSRafal Jaworowski #define	  SVR_MPC8572E		  0x80e8
654fe48da3fSRafal Jaworowski #define	SVR_VER(svr)		(((svr) >> 16) & 0xffff)
655653b7b49SRafal Jaworowski 
656ffb56695SRafal Jaworowski #define	SPR_PID0		0x030	/* ..8 Process ID Register 0 */
657ffb56695SRafal Jaworowski #define	SPR_PID1		0x279	/* ..8 Process ID Register 1 */
658ffb56695SRafal Jaworowski #define	SPR_PID2		0x27a	/* ..8 Process ID Register 2 */
659ffb56695SRafal Jaworowski 
660ffb56695SRafal Jaworowski #define	SPR_TLB0CFG		0x2B0	/* ..8 TLB 0 Config Register */
661ffb56695SRafal Jaworowski #define	SPR_TLB1CFG		0x2B1	/* ..8 TLB 1 Config Register */
662ffb56695SRafal Jaworowski #define	  TLBCFG_ASSOC_MASK	0xff000000 /* Associativity of TLB */
663ffb56695SRafal Jaworowski #define	  TLBCFG_ASSOC_SHIFT	24
664ffb56695SRafal Jaworowski #define	  TLBCFG_NENTRY_MASK	0x00000fff /* Number of entries in TLB */
665ffb56695SRafal Jaworowski 
666ffb56695SRafal Jaworowski #define	SPR_IVPR		0x03f	/* ..8 Interrupt Vector Prefix Register */
667ffb56695SRafal Jaworowski #define	SPR_IVOR0		0x190	/* ..8 Critical input */
668ffb56695SRafal Jaworowski #define	SPR_IVOR1		0x191	/* ..8 Machine check */
669ffb56695SRafal Jaworowski #define	SPR_IVOR2		0x192
670ffb56695SRafal Jaworowski #define	SPR_IVOR3		0x193
671ffb56695SRafal Jaworowski #define	SPR_IVOR4		0x194
672ffb56695SRafal Jaworowski #define	SPR_IVOR5		0x195
673ffb56695SRafal Jaworowski #define	SPR_IVOR6		0x196
674ffb56695SRafal Jaworowski #define	SPR_IVOR7		0x197
675ffb56695SRafal Jaworowski #define	SPR_IVOR8		0x198
676ffb56695SRafal Jaworowski #define	SPR_IVOR9		0x199
677ffb56695SRafal Jaworowski #define	SPR_IVOR10		0x19a
678ffb56695SRafal Jaworowski #define	SPR_IVOR11		0x19b
679ffb56695SRafal Jaworowski #define	SPR_IVOR12		0x19c
680ffb56695SRafal Jaworowski #define	SPR_IVOR13		0x19d
681ffb56695SRafal Jaworowski #define	SPR_IVOR14		0x19e
682ffb56695SRafal Jaworowski #define	SPR_IVOR15		0x19f
683ffb56695SRafal Jaworowski #define	SPR_IVOR32		0x210
684ffb56695SRafal Jaworowski #define	SPR_IVOR33		0x211
685ffb56695SRafal Jaworowski #define	SPR_IVOR34		0x212
686ffb56695SRafal Jaworowski #define	SPR_IVOR35		0x213
687ffb56695SRafal Jaworowski 
688ffb56695SRafal Jaworowski #define	SPR_MAS0		0x270	/* ..8 MMU Assist Register 0 Book-E/e500 */
689ffb56695SRafal Jaworowski #define	SPR_MAS1		0x271	/* ..8 MMU Assist Register 1 Book-E/e500 */
690ffb56695SRafal Jaworowski #define	SPR_MAS2		0x272	/* ..8 MMU Assist Register 2 Book-E/e500 */
691ffb56695SRafal Jaworowski #define	SPR_MAS3		0x273	/* ..8 MMU Assist Register 3 Book-E/e500 */
692ffb56695SRafal Jaworowski #define	SPR_MAS4		0x274	/* ..8 MMU Assist Register 4 Book-E/e500 */
693ffb56695SRafal Jaworowski #define	SPR_MAS5		0x275	/* ..8 MMU Assist Register 5 Book-E */
694ffb56695SRafal Jaworowski #define	SPR_MAS6		0x276	/* ..8 MMU Assist Register 6 Book-E/e500 */
695ffb56695SRafal Jaworowski #define	SPR_MAS7		0x3B0	/* ..8 MMU Assist Register 7 Book-E/e500 */
696ffb56695SRafal Jaworowski 
697ffb56695SRafal Jaworowski #define	SPR_L1CSR0		0x3F2	/* ..8 L1 Cache Control and Status Register 0 */
698ffb56695SRafal Jaworowski #define	  L1CSR0_DCPE		0x00010000	/* Data Cache Parity Enable */
699ffb56695SRafal Jaworowski #define	  L1CSR0_DCLFR		0x00000100	/* Data Cache Lock Bits Flash Reset */
700ffb56695SRafal Jaworowski #define	  L1CSR0_DCFI		0x00000002	/* Data Cache Flash Invalidate */
701ffb56695SRafal Jaworowski #define	  L1CSR0_DCE		0x00000001	/* Data Cache Enable */
702ffb56695SRafal Jaworowski #define	SPR_L1CSR1		0x3F3	/* ..8 L1 Cache Control and Status Register 1 */
703ffb56695SRafal Jaworowski #define	  L1CSR1_ICPE		0x00010000	/* Instruction Cache Parity Enable */
704ffb56695SRafal Jaworowski #define	  L1CSR1_ICLFR		0x00000100	/* Instruction Cache Lock Bits Flash Reset */
705ffb56695SRafal Jaworowski #define	  L1CSR1_ICFI		0x00000002	/* Instruction Cache Flash Invalidate */
706ffb56695SRafal Jaworowski #define	  L1CSR1_ICE		0x00000001	/* Instruction Cache Enable */
707ffb56695SRafal Jaworowski 
70828bb01e5SRafal Jaworowski #define	SPR_BUCSR		0x3F5	/* ..8 Branch Unit Control and Status Register */
70928bb01e5SRafal Jaworowski #define	  BUCSR_BPEN		0x00000001	/* Branch Prediction Enable */
71028bb01e5SRafal Jaworowski 
711ffb56695SRafal Jaworowski #endif /* #elif defined(E500) */
712ffb56695SRafal Jaworowski 
713b57e802aSBenno Rice #endif /* !_POWERPC_SPR_H_ */
714