1 /*- 2 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com> 3 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * Some hw specific parts of this pmap were derived or influenced 27 * by NetBSD's ibm4xx pmap module. More generic code is shared with 28 * a few other pmap modules from the FreeBSD tree. 29 */ 30 31 /* 32 * VM layout notes: 33 * 34 * Kernel and user threads run within one common virtual address space 35 * defined by AS=0. 36 * 37 * Virtual address space layout: 38 * ----------------------------- 39 * 0x0000_0000 - 0xafff_ffff : user process 40 * 0xb000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.) 41 * 0xc000_0000 - 0xc0ff_ffff : kernel reserved 42 * 0xc000_0000 - data_end : kernel code+data, env, metadata etc. 43 * 0xc100_0000 - 0xfeef_ffff : KVA 44 * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy 45 * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs 46 * 0xc200_4000 - 0xc200_8fff : guard page + kstack0 47 * 0xc200_9000 - 0xfeef_ffff : actual free KVA space 48 * 0xfef0_0000 - 0xffff_ffff : I/O devices region 49 */ 50 51 #include <sys/cdefs.h> 52 __FBSDID("$FreeBSD$"); 53 54 #include "opt_kstack_pages.h" 55 56 #include <sys/param.h> 57 #include <sys/conf.h> 58 #include <sys/malloc.h> 59 #include <sys/ktr.h> 60 #include <sys/proc.h> 61 #include <sys/user.h> 62 #include <sys/queue.h> 63 #include <sys/systm.h> 64 #include <sys/kernel.h> 65 #include <sys/kerneldump.h> 66 #include <sys/linker.h> 67 #include <sys/msgbuf.h> 68 #include <sys/lock.h> 69 #include <sys/mutex.h> 70 #include <sys/rwlock.h> 71 #include <sys/sched.h> 72 #include <sys/smp.h> 73 #include <sys/vmmeter.h> 74 75 #include <vm/vm.h> 76 #include <vm/vm_page.h> 77 #include <vm/vm_kern.h> 78 #include <vm/vm_pageout.h> 79 #include <vm/vm_extern.h> 80 #include <vm/vm_object.h> 81 #include <vm/vm_param.h> 82 #include <vm/vm_map.h> 83 #include <vm/vm_pager.h> 84 #include <vm/uma.h> 85 86 #include <machine/cpu.h> 87 #include <machine/pcb.h> 88 #include <machine/platform.h> 89 90 #include <machine/tlb.h> 91 #include <machine/spr.h> 92 #include <machine/md_var.h> 93 #include <machine/mmuvar.h> 94 #include <machine/pmap.h> 95 #include <machine/pte.h> 96 97 #include "mmu_if.h" 98 99 #define SPARSE_MAPDEV 100 #ifdef DEBUG 101 #define debugf(fmt, args...) printf(fmt, ##args) 102 #else 103 #define debugf(fmt, args...) 104 #endif 105 106 #define TODO panic("%s: not implemented", __func__); 107 108 extern unsigned char _etext[]; 109 extern unsigned char _end[]; 110 111 extern uint32_t *bootinfo; 112 113 vm_paddr_t kernload; 114 vm_offset_t kernstart; 115 vm_size_t kernsize; 116 117 /* Message buffer and tables. */ 118 static vm_offset_t data_start; 119 static vm_size_t data_end; 120 121 /* Phys/avail memory regions. */ 122 static struct mem_region *availmem_regions; 123 static int availmem_regions_sz; 124 static struct mem_region *physmem_regions; 125 static int physmem_regions_sz; 126 127 /* Reserved KVA space and mutex for mmu_booke_zero_page. */ 128 static vm_offset_t zero_page_va; 129 static struct mtx zero_page_mutex; 130 131 static struct mtx tlbivax_mutex; 132 133 /* Reserved KVA space and mutex for mmu_booke_copy_page. */ 134 static vm_offset_t copy_page_src_va; 135 static vm_offset_t copy_page_dst_va; 136 static struct mtx copy_page_mutex; 137 138 /**************************************************************************/ 139 /* PMAP */ 140 /**************************************************************************/ 141 142 static int mmu_booke_enter_locked(mmu_t, pmap_t, vm_offset_t, vm_page_t, 143 vm_prot_t, u_int flags, int8_t psind); 144 145 unsigned int kptbl_min; /* Index of the first kernel ptbl. */ 146 unsigned int kernel_ptbls; /* Number of KVA ptbls. */ 147 148 /* 149 * If user pmap is processed with mmu_booke_remove and the resident count 150 * drops to 0, there are no more pages to remove, so we need not continue. 151 */ 152 #define PMAP_REMOVE_DONE(pmap) \ 153 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0) 154 155 extern int elf32_nxstack; 156 157 /**************************************************************************/ 158 /* TLB and TID handling */ 159 /**************************************************************************/ 160 161 /* Translation ID busy table */ 162 static volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1]; 163 164 /* 165 * TLB0 capabilities (entry, way numbers etc.). These can vary between e500 166 * core revisions and should be read from h/w registers during early config. 167 */ 168 uint32_t tlb0_entries; 169 uint32_t tlb0_ways; 170 uint32_t tlb0_entries_per_way; 171 uint32_t tlb1_entries; 172 173 #define TLB0_ENTRIES (tlb0_entries) 174 #define TLB0_WAYS (tlb0_ways) 175 #define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way) 176 177 #define TLB1_ENTRIES (tlb1_entries) 178 #define TLB1_MAXENTRIES 64 179 180 static vm_offset_t tlb1_map_base = VM_MAXUSER_ADDRESS + PAGE_SIZE; 181 182 static tlbtid_t tid_alloc(struct pmap *); 183 static void tid_flush(tlbtid_t tid); 184 185 static void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t); 186 187 static void tlb1_read_entry(tlb_entry_t *, unsigned int); 188 static void tlb1_write_entry(tlb_entry_t *, unsigned int); 189 static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *); 190 static vm_size_t tlb1_mapin_region(vm_offset_t, vm_paddr_t, vm_size_t); 191 192 static vm_size_t tsize2size(unsigned int); 193 static unsigned int size2tsize(vm_size_t); 194 static unsigned int ilog2(unsigned int); 195 196 static void set_mas4_defaults(void); 197 198 static inline void tlb0_flush_entry(vm_offset_t); 199 static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int); 200 201 /**************************************************************************/ 202 /* Page table management */ 203 /**************************************************************************/ 204 205 static struct rwlock_padalign pvh_global_lock; 206 207 /* Data for the pv entry allocation mechanism */ 208 static uma_zone_t pvzone; 209 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 210 211 #define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */ 212 213 #ifndef PMAP_SHPGPERPROC 214 #define PMAP_SHPGPERPROC 200 215 #endif 216 217 static void ptbl_init(void); 218 static struct ptbl_buf *ptbl_buf_alloc(void); 219 static void ptbl_buf_free(struct ptbl_buf *); 220 static void ptbl_free_pmap_ptbl(pmap_t, pte_t *); 221 222 static pte_t *ptbl_alloc(mmu_t, pmap_t, unsigned int, boolean_t); 223 static void ptbl_free(mmu_t, pmap_t, unsigned int); 224 static void ptbl_hold(mmu_t, pmap_t, unsigned int); 225 static int ptbl_unhold(mmu_t, pmap_t, unsigned int); 226 227 static vm_paddr_t pte_vatopa(mmu_t, pmap_t, vm_offset_t); 228 static pte_t *pte_find(mmu_t, pmap_t, vm_offset_t); 229 static int pte_enter(mmu_t, pmap_t, vm_page_t, vm_offset_t, uint32_t, boolean_t); 230 static int pte_remove(mmu_t, pmap_t, vm_offset_t, uint8_t); 231 static void kernel_pte_alloc(vm_offset_t data_end, vm_offset_t addr, 232 vm_offset_t pdir); 233 234 static pv_entry_t pv_alloc(void); 235 static void pv_free(pv_entry_t); 236 static void pv_insert(pmap_t, vm_offset_t, vm_page_t); 237 static void pv_remove(pmap_t, vm_offset_t, vm_page_t); 238 239 static void booke_pmap_init_qpages(void); 240 241 /* Number of kva ptbl buffers, each covering one ptbl (PTBL_PAGES). */ 242 #define PTBL_BUFS (128 * 16) 243 244 struct ptbl_buf { 245 TAILQ_ENTRY(ptbl_buf) link; /* list link */ 246 vm_offset_t kva; /* va of mapping */ 247 }; 248 249 /* ptbl free list and a lock used for access synchronization. */ 250 static TAILQ_HEAD(, ptbl_buf) ptbl_buf_freelist; 251 static struct mtx ptbl_buf_freelist_lock; 252 253 /* Base address of kva space allocated fot ptbl bufs. */ 254 static vm_offset_t ptbl_buf_pool_vabase; 255 256 /* Pointer to ptbl_buf structures. */ 257 static struct ptbl_buf *ptbl_bufs; 258 259 #ifdef SMP 260 extern tlb_entry_t __boot_tlb1[]; 261 void pmap_bootstrap_ap(volatile uint32_t *); 262 #endif 263 264 /* 265 * Kernel MMU interface 266 */ 267 static void mmu_booke_clear_modify(mmu_t, vm_page_t); 268 static void mmu_booke_copy(mmu_t, pmap_t, pmap_t, vm_offset_t, 269 vm_size_t, vm_offset_t); 270 static void mmu_booke_copy_page(mmu_t, vm_page_t, vm_page_t); 271 static void mmu_booke_copy_pages(mmu_t, vm_page_t *, 272 vm_offset_t, vm_page_t *, vm_offset_t, int); 273 static int mmu_booke_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, 274 vm_prot_t, u_int flags, int8_t psind); 275 static void mmu_booke_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 276 vm_page_t, vm_prot_t); 277 static void mmu_booke_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, 278 vm_prot_t); 279 static vm_paddr_t mmu_booke_extract(mmu_t, pmap_t, vm_offset_t); 280 static vm_page_t mmu_booke_extract_and_hold(mmu_t, pmap_t, vm_offset_t, 281 vm_prot_t); 282 static void mmu_booke_init(mmu_t); 283 static boolean_t mmu_booke_is_modified(mmu_t, vm_page_t); 284 static boolean_t mmu_booke_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 285 static boolean_t mmu_booke_is_referenced(mmu_t, vm_page_t); 286 static int mmu_booke_ts_referenced(mmu_t, vm_page_t); 287 static vm_offset_t mmu_booke_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, 288 int); 289 static int mmu_booke_mincore(mmu_t, pmap_t, vm_offset_t, 290 vm_paddr_t *); 291 static void mmu_booke_object_init_pt(mmu_t, pmap_t, vm_offset_t, 292 vm_object_t, vm_pindex_t, vm_size_t); 293 static boolean_t mmu_booke_page_exists_quick(mmu_t, pmap_t, vm_page_t); 294 static void mmu_booke_page_init(mmu_t, vm_page_t); 295 static int mmu_booke_page_wired_mappings(mmu_t, vm_page_t); 296 static void mmu_booke_pinit(mmu_t, pmap_t); 297 static void mmu_booke_pinit0(mmu_t, pmap_t); 298 static void mmu_booke_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 299 vm_prot_t); 300 static void mmu_booke_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 301 static void mmu_booke_qremove(mmu_t, vm_offset_t, int); 302 static void mmu_booke_release(mmu_t, pmap_t); 303 static void mmu_booke_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 304 static void mmu_booke_remove_all(mmu_t, vm_page_t); 305 static void mmu_booke_remove_write(mmu_t, vm_page_t); 306 static void mmu_booke_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 307 static void mmu_booke_zero_page(mmu_t, vm_page_t); 308 static void mmu_booke_zero_page_area(mmu_t, vm_page_t, int, int); 309 static void mmu_booke_activate(mmu_t, struct thread *); 310 static void mmu_booke_deactivate(mmu_t, struct thread *); 311 static void mmu_booke_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 312 static void *mmu_booke_mapdev(mmu_t, vm_paddr_t, vm_size_t); 313 static void *mmu_booke_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t); 314 static void mmu_booke_unmapdev(mmu_t, vm_offset_t, vm_size_t); 315 static vm_paddr_t mmu_booke_kextract(mmu_t, vm_offset_t); 316 static void mmu_booke_kenter(mmu_t, vm_offset_t, vm_paddr_t); 317 static void mmu_booke_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t); 318 static void mmu_booke_kremove(mmu_t, vm_offset_t); 319 static boolean_t mmu_booke_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 320 static void mmu_booke_sync_icache(mmu_t, pmap_t, vm_offset_t, 321 vm_size_t); 322 static void mmu_booke_dumpsys_map(mmu_t, vm_paddr_t pa, size_t, 323 void **); 324 static void mmu_booke_dumpsys_unmap(mmu_t, vm_paddr_t pa, size_t, 325 void *); 326 static void mmu_booke_scan_init(mmu_t); 327 static vm_offset_t mmu_booke_quick_enter_page(mmu_t mmu, vm_page_t m); 328 static void mmu_booke_quick_remove_page(mmu_t mmu, vm_offset_t addr); 329 static int mmu_booke_change_attr(mmu_t mmu, vm_offset_t addr, 330 vm_size_t sz, vm_memattr_t mode); 331 332 static mmu_method_t mmu_booke_methods[] = { 333 /* pmap dispatcher interface */ 334 MMUMETHOD(mmu_clear_modify, mmu_booke_clear_modify), 335 MMUMETHOD(mmu_copy, mmu_booke_copy), 336 MMUMETHOD(mmu_copy_page, mmu_booke_copy_page), 337 MMUMETHOD(mmu_copy_pages, mmu_booke_copy_pages), 338 MMUMETHOD(mmu_enter, mmu_booke_enter), 339 MMUMETHOD(mmu_enter_object, mmu_booke_enter_object), 340 MMUMETHOD(mmu_enter_quick, mmu_booke_enter_quick), 341 MMUMETHOD(mmu_extract, mmu_booke_extract), 342 MMUMETHOD(mmu_extract_and_hold, mmu_booke_extract_and_hold), 343 MMUMETHOD(mmu_init, mmu_booke_init), 344 MMUMETHOD(mmu_is_modified, mmu_booke_is_modified), 345 MMUMETHOD(mmu_is_prefaultable, mmu_booke_is_prefaultable), 346 MMUMETHOD(mmu_is_referenced, mmu_booke_is_referenced), 347 MMUMETHOD(mmu_ts_referenced, mmu_booke_ts_referenced), 348 MMUMETHOD(mmu_map, mmu_booke_map), 349 MMUMETHOD(mmu_mincore, mmu_booke_mincore), 350 MMUMETHOD(mmu_object_init_pt, mmu_booke_object_init_pt), 351 MMUMETHOD(mmu_page_exists_quick,mmu_booke_page_exists_quick), 352 MMUMETHOD(mmu_page_init, mmu_booke_page_init), 353 MMUMETHOD(mmu_page_wired_mappings, mmu_booke_page_wired_mappings), 354 MMUMETHOD(mmu_pinit, mmu_booke_pinit), 355 MMUMETHOD(mmu_pinit0, mmu_booke_pinit0), 356 MMUMETHOD(mmu_protect, mmu_booke_protect), 357 MMUMETHOD(mmu_qenter, mmu_booke_qenter), 358 MMUMETHOD(mmu_qremove, mmu_booke_qremove), 359 MMUMETHOD(mmu_release, mmu_booke_release), 360 MMUMETHOD(mmu_remove, mmu_booke_remove), 361 MMUMETHOD(mmu_remove_all, mmu_booke_remove_all), 362 MMUMETHOD(mmu_remove_write, mmu_booke_remove_write), 363 MMUMETHOD(mmu_sync_icache, mmu_booke_sync_icache), 364 MMUMETHOD(mmu_unwire, mmu_booke_unwire), 365 MMUMETHOD(mmu_zero_page, mmu_booke_zero_page), 366 MMUMETHOD(mmu_zero_page_area, mmu_booke_zero_page_area), 367 MMUMETHOD(mmu_activate, mmu_booke_activate), 368 MMUMETHOD(mmu_deactivate, mmu_booke_deactivate), 369 MMUMETHOD(mmu_quick_enter_page, mmu_booke_quick_enter_page), 370 MMUMETHOD(mmu_quick_remove_page, mmu_booke_quick_remove_page), 371 372 /* Internal interfaces */ 373 MMUMETHOD(mmu_bootstrap, mmu_booke_bootstrap), 374 MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped), 375 MMUMETHOD(mmu_mapdev, mmu_booke_mapdev), 376 MMUMETHOD(mmu_mapdev_attr, mmu_booke_mapdev_attr), 377 MMUMETHOD(mmu_kenter, mmu_booke_kenter), 378 MMUMETHOD(mmu_kenter_attr, mmu_booke_kenter_attr), 379 MMUMETHOD(mmu_kextract, mmu_booke_kextract), 380 MMUMETHOD(mmu_kremove, mmu_booke_kremove), 381 MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev), 382 MMUMETHOD(mmu_change_attr, mmu_booke_change_attr), 383 384 /* dumpsys() support */ 385 MMUMETHOD(mmu_dumpsys_map, mmu_booke_dumpsys_map), 386 MMUMETHOD(mmu_dumpsys_unmap, mmu_booke_dumpsys_unmap), 387 MMUMETHOD(mmu_scan_init, mmu_booke_scan_init), 388 389 { 0, 0 } 390 }; 391 392 MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods, 0); 393 394 static __inline uint32_t 395 tlb_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 396 { 397 uint32_t attrib; 398 int i; 399 400 if (ma != VM_MEMATTR_DEFAULT) { 401 switch (ma) { 402 case VM_MEMATTR_UNCACHEABLE: 403 return (MAS2_I | MAS2_G); 404 case VM_MEMATTR_WRITE_COMBINING: 405 case VM_MEMATTR_WRITE_BACK: 406 case VM_MEMATTR_PREFETCHABLE: 407 return (MAS2_I); 408 case VM_MEMATTR_WRITE_THROUGH: 409 return (MAS2_W | MAS2_M); 410 case VM_MEMATTR_CACHEABLE: 411 return (MAS2_M); 412 } 413 } 414 415 /* 416 * Assume the page is cache inhibited and access is guarded unless 417 * it's in our available memory array. 418 */ 419 attrib = _TLB_ENTRY_IO; 420 for (i = 0; i < physmem_regions_sz; i++) { 421 if ((pa >= physmem_regions[i].mr_start) && 422 (pa < (physmem_regions[i].mr_start + 423 physmem_regions[i].mr_size))) { 424 attrib = _TLB_ENTRY_MEM; 425 break; 426 } 427 } 428 429 return (attrib); 430 } 431 432 static inline void 433 tlb_miss_lock(void) 434 { 435 #ifdef SMP 436 struct pcpu *pc; 437 438 if (!smp_started) 439 return; 440 441 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 442 if (pc != pcpup) { 443 444 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, " 445 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke_tlb_lock); 446 447 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)), 448 ("tlb_miss_lock: tried to lock self")); 449 450 tlb_lock(pc->pc_booke_tlb_lock); 451 452 CTR1(KTR_PMAP, "%s: locked", __func__); 453 } 454 } 455 #endif 456 } 457 458 static inline void 459 tlb_miss_unlock(void) 460 { 461 #ifdef SMP 462 struct pcpu *pc; 463 464 if (!smp_started) 465 return; 466 467 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 468 if (pc != pcpup) { 469 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d", 470 __func__, pc->pc_cpuid); 471 472 tlb_unlock(pc->pc_booke_tlb_lock); 473 474 CTR1(KTR_PMAP, "%s: unlocked", __func__); 475 } 476 } 477 #endif 478 } 479 480 /* Return number of entries in TLB0. */ 481 static __inline void 482 tlb0_get_tlbconf(void) 483 { 484 uint32_t tlb0_cfg; 485 486 tlb0_cfg = mfspr(SPR_TLB0CFG); 487 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK; 488 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT; 489 tlb0_entries_per_way = tlb0_entries / tlb0_ways; 490 } 491 492 /* Return number of entries in TLB1. */ 493 static __inline void 494 tlb1_get_tlbconf(void) 495 { 496 uint32_t tlb1_cfg; 497 498 tlb1_cfg = mfspr(SPR_TLB1CFG); 499 tlb1_entries = tlb1_cfg & TLBCFG_NENTRY_MASK; 500 } 501 502 /**************************************************************************/ 503 /* Page table related */ 504 /**************************************************************************/ 505 506 /* Initialize pool of kva ptbl buffers. */ 507 static void 508 ptbl_init(void) 509 { 510 int i; 511 512 CTR3(KTR_PMAP, "%s: s (ptbl_bufs = 0x%08x size 0x%08x)", __func__, 513 (uint32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS); 514 CTR3(KTR_PMAP, "%s: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)", 515 __func__, ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE); 516 517 mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF); 518 TAILQ_INIT(&ptbl_buf_freelist); 519 520 for (i = 0; i < PTBL_BUFS; i++) { 521 ptbl_bufs[i].kva = ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE; 522 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link); 523 } 524 } 525 526 /* Get a ptbl_buf from the freelist. */ 527 static struct ptbl_buf * 528 ptbl_buf_alloc(void) 529 { 530 struct ptbl_buf *buf; 531 532 mtx_lock(&ptbl_buf_freelist_lock); 533 buf = TAILQ_FIRST(&ptbl_buf_freelist); 534 if (buf != NULL) 535 TAILQ_REMOVE(&ptbl_buf_freelist, buf, link); 536 mtx_unlock(&ptbl_buf_freelist_lock); 537 538 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 539 540 return (buf); 541 } 542 543 /* Return ptbl buff to free pool. */ 544 static void 545 ptbl_buf_free(struct ptbl_buf *buf) 546 { 547 548 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 549 550 mtx_lock(&ptbl_buf_freelist_lock); 551 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link); 552 mtx_unlock(&ptbl_buf_freelist_lock); 553 } 554 555 /* 556 * Search the list of allocated ptbl bufs and find on list of allocated ptbls 557 */ 558 static void 559 ptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl) 560 { 561 struct ptbl_buf *pbuf; 562 563 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 564 565 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 566 567 TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link) 568 if (pbuf->kva == (vm_offset_t)ptbl) { 569 /* Remove from pmap ptbl buf list. */ 570 TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link); 571 572 /* Free corresponding ptbl buf. */ 573 ptbl_buf_free(pbuf); 574 break; 575 } 576 } 577 578 /* Allocate page table. */ 579 static pte_t * 580 ptbl_alloc(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx, boolean_t nosleep) 581 { 582 vm_page_t mtbl[PTBL_PAGES]; 583 vm_page_t m; 584 struct ptbl_buf *pbuf; 585 unsigned int pidx; 586 pte_t *ptbl; 587 int i, j; 588 589 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 590 (pmap == kernel_pmap), pdir_idx); 591 592 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 593 ("ptbl_alloc: invalid pdir_idx")); 594 KASSERT((pmap->pm_pdir[pdir_idx] == NULL), 595 ("pte_alloc: valid ptbl entry exists!")); 596 597 pbuf = ptbl_buf_alloc(); 598 if (pbuf == NULL) 599 panic("pte_alloc: couldn't alloc kernel virtual memory"); 600 601 ptbl = (pte_t *)pbuf->kva; 602 603 CTR2(KTR_PMAP, "%s: ptbl kva = %p", __func__, ptbl); 604 605 /* Allocate ptbl pages, this will sleep! */ 606 for (i = 0; i < PTBL_PAGES; i++) { 607 pidx = (PTBL_PAGES * pdir_idx) + i; 608 while ((m = vm_page_alloc(NULL, pidx, 609 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 610 PMAP_UNLOCK(pmap); 611 rw_wunlock(&pvh_global_lock); 612 if (nosleep) { 613 ptbl_free_pmap_ptbl(pmap, ptbl); 614 for (j = 0; j < i; j++) 615 vm_page_free(mtbl[j]); 616 atomic_subtract_int(&vm_cnt.v_wire_count, i); 617 return (NULL); 618 } 619 VM_WAIT; 620 rw_wlock(&pvh_global_lock); 621 PMAP_LOCK(pmap); 622 } 623 mtbl[i] = m; 624 } 625 626 /* Map allocated pages into kernel_pmap. */ 627 mmu_booke_qenter(mmu, (vm_offset_t)ptbl, mtbl, PTBL_PAGES); 628 629 /* Zero whole ptbl. */ 630 bzero((caddr_t)ptbl, PTBL_PAGES * PAGE_SIZE); 631 632 /* Add pbuf to the pmap ptbl bufs list. */ 633 TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link); 634 635 return (ptbl); 636 } 637 638 /* Free ptbl pages and invalidate pdir entry. */ 639 static void 640 ptbl_free(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 641 { 642 pte_t *ptbl; 643 vm_paddr_t pa; 644 vm_offset_t va; 645 vm_page_t m; 646 int i; 647 648 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 649 (pmap == kernel_pmap), pdir_idx); 650 651 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 652 ("ptbl_free: invalid pdir_idx")); 653 654 ptbl = pmap->pm_pdir[pdir_idx]; 655 656 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 657 658 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl")); 659 660 /* 661 * Invalidate the pdir entry as soon as possible, so that other CPUs 662 * don't attempt to look up the page tables we are releasing. 663 */ 664 mtx_lock_spin(&tlbivax_mutex); 665 tlb_miss_lock(); 666 667 pmap->pm_pdir[pdir_idx] = NULL; 668 669 tlb_miss_unlock(); 670 mtx_unlock_spin(&tlbivax_mutex); 671 672 for (i = 0; i < PTBL_PAGES; i++) { 673 va = ((vm_offset_t)ptbl + (i * PAGE_SIZE)); 674 pa = pte_vatopa(mmu, kernel_pmap, va); 675 m = PHYS_TO_VM_PAGE(pa); 676 vm_page_free_zero(m); 677 atomic_subtract_int(&vm_cnt.v_wire_count, 1); 678 mmu_booke_kremove(mmu, va); 679 } 680 681 ptbl_free_pmap_ptbl(pmap, ptbl); 682 } 683 684 /* 685 * Decrement ptbl pages hold count and attempt to free ptbl pages. 686 * Called when removing pte entry from ptbl. 687 * 688 * Return 1 if ptbl pages were freed. 689 */ 690 static int 691 ptbl_unhold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 692 { 693 pte_t *ptbl; 694 vm_paddr_t pa; 695 vm_page_t m; 696 int i; 697 698 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 699 (pmap == kernel_pmap), pdir_idx); 700 701 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 702 ("ptbl_unhold: invalid pdir_idx")); 703 KASSERT((pmap != kernel_pmap), 704 ("ptbl_unhold: unholding kernel ptbl!")); 705 706 ptbl = pmap->pm_pdir[pdir_idx]; 707 708 //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl); 709 KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS), 710 ("ptbl_unhold: non kva ptbl")); 711 712 /* decrement hold count */ 713 for (i = 0; i < PTBL_PAGES; i++) { 714 pa = pte_vatopa(mmu, kernel_pmap, 715 (vm_offset_t)ptbl + (i * PAGE_SIZE)); 716 m = PHYS_TO_VM_PAGE(pa); 717 m->wire_count--; 718 } 719 720 /* 721 * Free ptbl pages if there are no pte etries in this ptbl. 722 * wire_count has the same value for all ptbl pages, so check the last 723 * page. 724 */ 725 if (m->wire_count == 0) { 726 ptbl_free(mmu, pmap, pdir_idx); 727 728 //debugf("ptbl_unhold: e (freed ptbl)\n"); 729 return (1); 730 } 731 732 return (0); 733 } 734 735 /* 736 * Increment hold count for ptbl pages. This routine is used when a new pte 737 * entry is being inserted into the ptbl. 738 */ 739 static void 740 ptbl_hold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 741 { 742 vm_paddr_t pa; 743 pte_t *ptbl; 744 vm_page_t m; 745 int i; 746 747 CTR3(KTR_PMAP, "%s: pmap = %p pdir_idx = %d", __func__, pmap, 748 pdir_idx); 749 750 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 751 ("ptbl_hold: invalid pdir_idx")); 752 KASSERT((pmap != kernel_pmap), 753 ("ptbl_hold: holding kernel ptbl!")); 754 755 ptbl = pmap->pm_pdir[pdir_idx]; 756 757 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl")); 758 759 for (i = 0; i < PTBL_PAGES; i++) { 760 pa = pte_vatopa(mmu, kernel_pmap, 761 (vm_offset_t)ptbl + (i * PAGE_SIZE)); 762 m = PHYS_TO_VM_PAGE(pa); 763 m->wire_count++; 764 } 765 } 766 767 /* Allocate pv_entry structure. */ 768 pv_entry_t 769 pv_alloc(void) 770 { 771 pv_entry_t pv; 772 773 pv_entry_count++; 774 if (pv_entry_count > pv_entry_high_water) 775 pagedaemon_wakeup(); 776 pv = uma_zalloc(pvzone, M_NOWAIT); 777 778 return (pv); 779 } 780 781 /* Free pv_entry structure. */ 782 static __inline void 783 pv_free(pv_entry_t pve) 784 { 785 786 pv_entry_count--; 787 uma_zfree(pvzone, pve); 788 } 789 790 791 /* Allocate and initialize pv_entry structure. */ 792 static void 793 pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m) 794 { 795 pv_entry_t pve; 796 797 //int su = (pmap == kernel_pmap); 798 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su, 799 // (u_int32_t)pmap, va, (u_int32_t)m); 800 801 pve = pv_alloc(); 802 if (pve == NULL) 803 panic("pv_insert: no pv entries!"); 804 805 pve->pv_pmap = pmap; 806 pve->pv_va = va; 807 808 /* add to pv_list */ 809 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 810 rw_assert(&pvh_global_lock, RA_WLOCKED); 811 812 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link); 813 814 //debugf("pv_insert: e\n"); 815 } 816 817 /* Destroy pv entry. */ 818 static void 819 pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m) 820 { 821 pv_entry_t pve; 822 823 //int su = (pmap == kernel_pmap); 824 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va); 825 826 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 827 rw_assert(&pvh_global_lock, RA_WLOCKED); 828 829 /* find pv entry */ 830 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) { 831 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) { 832 /* remove from pv_list */ 833 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link); 834 if (TAILQ_EMPTY(&m->md.pv_list)) 835 vm_page_aflag_clear(m, PGA_WRITEABLE); 836 837 /* free pv entry struct */ 838 pv_free(pve); 839 break; 840 } 841 } 842 843 //debugf("pv_remove: e\n"); 844 } 845 846 /* 847 * Clean pte entry, try to free page table page if requested. 848 * 849 * Return 1 if ptbl pages were freed, otherwise return 0. 850 */ 851 static int 852 pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, uint8_t flags) 853 { 854 unsigned int pdir_idx = PDIR_IDX(va); 855 unsigned int ptbl_idx = PTBL_IDX(va); 856 vm_page_t m; 857 pte_t *ptbl; 858 pte_t *pte; 859 860 //int su = (pmap == kernel_pmap); 861 //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n", 862 // su, (u_int32_t)pmap, va, flags); 863 864 ptbl = pmap->pm_pdir[pdir_idx]; 865 KASSERT(ptbl, ("pte_remove: null ptbl")); 866 867 pte = &ptbl[ptbl_idx]; 868 869 if (pte == NULL || !PTE_ISVALID(pte)) 870 return (0); 871 872 if (PTE_ISWIRED(pte)) 873 pmap->pm_stats.wired_count--; 874 875 /* Handle managed entry. */ 876 if (PTE_ISMANAGED(pte)) { 877 /* Get vm_page_t for mapped pte. */ 878 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 879 880 if (PTE_ISMODIFIED(pte)) 881 vm_page_dirty(m); 882 883 if (PTE_ISREFERENCED(pte)) 884 vm_page_aflag_set(m, PGA_REFERENCED); 885 886 pv_remove(pmap, va, m); 887 } 888 889 mtx_lock_spin(&tlbivax_mutex); 890 tlb_miss_lock(); 891 892 tlb0_flush_entry(va); 893 *pte = 0; 894 895 tlb_miss_unlock(); 896 mtx_unlock_spin(&tlbivax_mutex); 897 898 pmap->pm_stats.resident_count--; 899 900 if (flags & PTBL_UNHOLD) { 901 //debugf("pte_remove: e (unhold)\n"); 902 return (ptbl_unhold(mmu, pmap, pdir_idx)); 903 } 904 905 //debugf("pte_remove: e\n"); 906 return (0); 907 } 908 909 /* 910 * Insert PTE for a given page and virtual address. 911 */ 912 static int 913 pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags, 914 boolean_t nosleep) 915 { 916 unsigned int pdir_idx = PDIR_IDX(va); 917 unsigned int ptbl_idx = PTBL_IDX(va); 918 pte_t *ptbl, *pte; 919 920 CTR4(KTR_PMAP, "%s: su = %d pmap = %p va = %p", __func__, 921 pmap == kernel_pmap, pmap, va); 922 923 /* Get the page table pointer. */ 924 ptbl = pmap->pm_pdir[pdir_idx]; 925 926 if (ptbl == NULL) { 927 /* Allocate page table pages. */ 928 ptbl = ptbl_alloc(mmu, pmap, pdir_idx, nosleep); 929 if (ptbl == NULL) { 930 KASSERT(nosleep, ("nosleep and NULL ptbl")); 931 return (ENOMEM); 932 } 933 } else { 934 /* 935 * Check if there is valid mapping for requested 936 * va, if there is, remove it. 937 */ 938 pte = &pmap->pm_pdir[pdir_idx][ptbl_idx]; 939 if (PTE_ISVALID(pte)) { 940 pte_remove(mmu, pmap, va, PTBL_HOLD); 941 } else { 942 /* 943 * pte is not used, increment hold count 944 * for ptbl pages. 945 */ 946 if (pmap != kernel_pmap) 947 ptbl_hold(mmu, pmap, pdir_idx); 948 } 949 } 950 951 /* 952 * Insert pv_entry into pv_list for mapped page if part of managed 953 * memory. 954 */ 955 if ((m->oflags & VPO_UNMANAGED) == 0) { 956 flags |= PTE_MANAGED; 957 958 /* Create and insert pv entry. */ 959 pv_insert(pmap, va, m); 960 } 961 962 pmap->pm_stats.resident_count++; 963 964 mtx_lock_spin(&tlbivax_mutex); 965 tlb_miss_lock(); 966 967 tlb0_flush_entry(va); 968 if (pmap->pm_pdir[pdir_idx] == NULL) { 969 /* 970 * If we just allocated a new page table, hook it in 971 * the pdir. 972 */ 973 pmap->pm_pdir[pdir_idx] = ptbl; 974 } 975 pte = &(pmap->pm_pdir[pdir_idx][ptbl_idx]); 976 *pte = PTE_RPN_FROM_PA(VM_PAGE_TO_PHYS(m)); 977 *pte |= (PTE_VALID | flags | PTE_PS_4KB); /* 4KB pages only */ 978 979 tlb_miss_unlock(); 980 mtx_unlock_spin(&tlbivax_mutex); 981 return (0); 982 } 983 984 /* Return the pa for the given pmap/va. */ 985 static vm_paddr_t 986 pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va) 987 { 988 vm_paddr_t pa = 0; 989 pte_t *pte; 990 991 pte = pte_find(mmu, pmap, va); 992 if ((pte != NULL) && PTE_ISVALID(pte)) 993 pa = (PTE_PA(pte) | (va & PTE_PA_MASK)); 994 return (pa); 995 } 996 997 /* Get a pointer to a PTE in a page table. */ 998 static pte_t * 999 pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1000 { 1001 unsigned int pdir_idx = PDIR_IDX(va); 1002 unsigned int ptbl_idx = PTBL_IDX(va); 1003 1004 KASSERT((pmap != NULL), ("pte_find: invalid pmap")); 1005 1006 if (pmap->pm_pdir[pdir_idx]) 1007 return (&(pmap->pm_pdir[pdir_idx][ptbl_idx])); 1008 1009 return (NULL); 1010 } 1011 1012 /* Set up kernel page tables. */ 1013 static void 1014 kernel_pte_alloc(vm_offset_t data_end, vm_offset_t addr, vm_offset_t pdir) 1015 { 1016 int i; 1017 vm_offset_t va; 1018 pte_t *pte; 1019 1020 /* Initialize kernel pdir */ 1021 for (i = 0; i < kernel_ptbls; i++) 1022 kernel_pmap->pm_pdir[kptbl_min + i] = 1023 (pte_t *)(pdir + (i * PAGE_SIZE * PTBL_PAGES)); 1024 1025 /* 1026 * Fill in PTEs covering kernel code and data. They are not required 1027 * for address translation, as this area is covered by static TLB1 1028 * entries, but for pte_vatopa() to work correctly with kernel area 1029 * addresses. 1030 */ 1031 for (va = addr; va < data_end; va += PAGE_SIZE) { 1032 pte = &(kernel_pmap->pm_pdir[PDIR_IDX(va)][PTBL_IDX(va)]); 1033 *pte = PTE_RPN_FROM_PA(kernload + (va - kernstart)); 1034 *pte |= PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | 1035 PTE_VALID | PTE_PS_4KB; 1036 } 1037 } 1038 1039 /**************************************************************************/ 1040 /* PMAP related */ 1041 /**************************************************************************/ 1042 1043 /* 1044 * This is called during booke_init, before the system is really initialized. 1045 */ 1046 static void 1047 mmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend) 1048 { 1049 vm_paddr_t phys_kernelend; 1050 struct mem_region *mp, *mp1; 1051 int cnt, i, j; 1052 vm_paddr_t s, e, sz; 1053 vm_paddr_t physsz, hwphyssz; 1054 u_int phys_avail_count; 1055 vm_size_t kstack0_sz; 1056 vm_offset_t kernel_pdir, kstack0; 1057 vm_paddr_t kstack0_phys; 1058 void *dpcpu; 1059 1060 debugf("mmu_booke_bootstrap: entered\n"); 1061 1062 /* Set interesting system properties */ 1063 hw_direct_map = 0; 1064 elf32_nxstack = 1; 1065 1066 /* Initialize invalidation mutex */ 1067 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN); 1068 1069 /* Read TLB0 size and associativity. */ 1070 tlb0_get_tlbconf(); 1071 1072 /* 1073 * Align kernel start and end address (kernel image). 1074 * Note that kernel end does not necessarily relate to kernsize. 1075 * kernsize is the size of the kernel that is actually mapped. 1076 */ 1077 kernstart = trunc_page(start); 1078 data_start = round_page(kernelend); 1079 data_end = data_start; 1080 1081 /* 1082 * Addresses of preloaded modules (like file systems) use 1083 * physical addresses. Make sure we relocate those into 1084 * virtual addresses. 1085 */ 1086 preload_addr_relocate = kernstart - kernload; 1087 1088 /* Allocate the dynamic per-cpu area. */ 1089 dpcpu = (void *)data_end; 1090 data_end += DPCPU_SIZE; 1091 1092 /* Allocate space for the message buffer. */ 1093 msgbufp = (struct msgbuf *)data_end; 1094 data_end += msgbufsize; 1095 debugf(" msgbufp at 0x%08x end = 0x%08x\n", (uint32_t)msgbufp, 1096 data_end); 1097 1098 data_end = round_page(data_end); 1099 1100 /* Allocate space for ptbl_bufs. */ 1101 ptbl_bufs = (struct ptbl_buf *)data_end; 1102 data_end += sizeof(struct ptbl_buf) * PTBL_BUFS; 1103 debugf(" ptbl_bufs at 0x%08x end = 0x%08x\n", (uint32_t)ptbl_bufs, 1104 data_end); 1105 1106 data_end = round_page(data_end); 1107 1108 /* Allocate PTE tables for kernel KVA. */ 1109 kernel_pdir = data_end; 1110 kernel_ptbls = howmany(VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS, 1111 PDIR_SIZE); 1112 data_end += kernel_ptbls * PTBL_PAGES * PAGE_SIZE; 1113 debugf(" kernel ptbls: %d\n", kernel_ptbls); 1114 debugf(" kernel pdir at 0x%08x end = 0x%08x\n", kernel_pdir, data_end); 1115 1116 debugf(" data_end: 0x%08x\n", data_end); 1117 if (data_end - kernstart > kernsize) { 1118 kernsize += tlb1_mapin_region(kernstart + kernsize, 1119 kernload + kernsize, (data_end - kernstart) - kernsize); 1120 } 1121 data_end = kernstart + kernsize; 1122 debugf(" updated data_end: 0x%08x\n", data_end); 1123 1124 /* 1125 * Clear the structures - note we can only do it safely after the 1126 * possible additional TLB1 translations are in place (above) so that 1127 * all range up to the currently calculated 'data_end' is covered. 1128 */ 1129 dpcpu_init(dpcpu, 0); 1130 memset((void *)ptbl_bufs, 0, sizeof(struct ptbl_buf) * PTBL_SIZE); 1131 memset((void *)kernel_pdir, 0, kernel_ptbls * PTBL_PAGES * PAGE_SIZE); 1132 1133 /*******************************************************/ 1134 /* Set the start and end of kva. */ 1135 /*******************************************************/ 1136 virtual_avail = round_page(data_end); 1137 virtual_end = VM_MAX_KERNEL_ADDRESS; 1138 1139 /* Allocate KVA space for page zero/copy operations. */ 1140 zero_page_va = virtual_avail; 1141 virtual_avail += PAGE_SIZE; 1142 copy_page_src_va = virtual_avail; 1143 virtual_avail += PAGE_SIZE; 1144 copy_page_dst_va = virtual_avail; 1145 virtual_avail += PAGE_SIZE; 1146 debugf("zero_page_va = 0x%08x\n", zero_page_va); 1147 debugf("copy_page_src_va = 0x%08x\n", copy_page_src_va); 1148 debugf("copy_page_dst_va = 0x%08x\n", copy_page_dst_va); 1149 1150 /* Initialize page zero/copy mutexes. */ 1151 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF); 1152 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF); 1153 1154 /* Allocate KVA space for ptbl bufs. */ 1155 ptbl_buf_pool_vabase = virtual_avail; 1156 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE; 1157 debugf("ptbl_buf_pool_vabase = 0x%08x end = 0x%08x\n", 1158 ptbl_buf_pool_vabase, virtual_avail); 1159 1160 /* Calculate corresponding physical addresses for the kernel region. */ 1161 phys_kernelend = kernload + kernsize; 1162 debugf("kernel image and allocated data:\n"); 1163 debugf(" kernload = 0x%09llx\n", (uint64_t)kernload); 1164 debugf(" kernstart = 0x%08x\n", kernstart); 1165 debugf(" kernsize = 0x%08x\n", kernsize); 1166 1167 if (sizeof(phys_avail) / sizeof(phys_avail[0]) < availmem_regions_sz) 1168 panic("mmu_booke_bootstrap: phys_avail too small"); 1169 1170 /* 1171 * Remove kernel physical address range from avail regions list. Page 1172 * align all regions. Non-page aligned memory isn't very interesting 1173 * to us. Also, sort the entries for ascending addresses. 1174 */ 1175 1176 /* Retrieve phys/avail mem regions */ 1177 mem_regions(&physmem_regions, &physmem_regions_sz, 1178 &availmem_regions, &availmem_regions_sz); 1179 sz = 0; 1180 cnt = availmem_regions_sz; 1181 debugf("processing avail regions:\n"); 1182 for (mp = availmem_regions; mp->mr_size; mp++) { 1183 s = mp->mr_start; 1184 e = mp->mr_start + mp->mr_size; 1185 debugf(" %09jx-%09jx -> ", (uintmax_t)s, (uintmax_t)e); 1186 /* Check whether this region holds all of the kernel. */ 1187 if (s < kernload && e > phys_kernelend) { 1188 availmem_regions[cnt].mr_start = phys_kernelend; 1189 availmem_regions[cnt++].mr_size = e - phys_kernelend; 1190 e = kernload; 1191 } 1192 /* Look whether this regions starts within the kernel. */ 1193 if (s >= kernload && s < phys_kernelend) { 1194 if (e <= phys_kernelend) 1195 goto empty; 1196 s = phys_kernelend; 1197 } 1198 /* Now look whether this region ends within the kernel. */ 1199 if (e > kernload && e <= phys_kernelend) { 1200 if (s >= kernload) 1201 goto empty; 1202 e = kernload; 1203 } 1204 /* Now page align the start and size of the region. */ 1205 s = round_page(s); 1206 e = trunc_page(e); 1207 if (e < s) 1208 e = s; 1209 sz = e - s; 1210 debugf("%09jx-%09jx = %jx\n", 1211 (uintmax_t)s, (uintmax_t)e, (uintmax_t)sz); 1212 1213 /* Check whether some memory is left here. */ 1214 if (sz == 0) { 1215 empty: 1216 memmove(mp, mp + 1, 1217 (cnt - (mp - availmem_regions)) * sizeof(*mp)); 1218 cnt--; 1219 mp--; 1220 continue; 1221 } 1222 1223 /* Do an insertion sort. */ 1224 for (mp1 = availmem_regions; mp1 < mp; mp1++) 1225 if (s < mp1->mr_start) 1226 break; 1227 if (mp1 < mp) { 1228 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1); 1229 mp1->mr_start = s; 1230 mp1->mr_size = sz; 1231 } else { 1232 mp->mr_start = s; 1233 mp->mr_size = sz; 1234 } 1235 } 1236 availmem_regions_sz = cnt; 1237 1238 /*******************************************************/ 1239 /* Steal physical memory for kernel stack from the end */ 1240 /* of the first avail region */ 1241 /*******************************************************/ 1242 kstack0_sz = kstack_pages * PAGE_SIZE; 1243 kstack0_phys = availmem_regions[0].mr_start + 1244 availmem_regions[0].mr_size; 1245 kstack0_phys -= kstack0_sz; 1246 availmem_regions[0].mr_size -= kstack0_sz; 1247 1248 /*******************************************************/ 1249 /* Fill in phys_avail table, based on availmem_regions */ 1250 /*******************************************************/ 1251 phys_avail_count = 0; 1252 physsz = 0; 1253 hwphyssz = 0; 1254 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 1255 1256 debugf("fill in phys_avail:\n"); 1257 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) { 1258 1259 debugf(" region: 0x%jx - 0x%jx (0x%jx)\n", 1260 (uintmax_t)availmem_regions[i].mr_start, 1261 (uintmax_t)availmem_regions[i].mr_start + 1262 availmem_regions[i].mr_size, 1263 (uintmax_t)availmem_regions[i].mr_size); 1264 1265 if (hwphyssz != 0 && 1266 (physsz + availmem_regions[i].mr_size) >= hwphyssz) { 1267 debugf(" hw.physmem adjust\n"); 1268 if (physsz < hwphyssz) { 1269 phys_avail[j] = availmem_regions[i].mr_start; 1270 phys_avail[j + 1] = 1271 availmem_regions[i].mr_start + 1272 hwphyssz - physsz; 1273 physsz = hwphyssz; 1274 phys_avail_count++; 1275 } 1276 break; 1277 } 1278 1279 phys_avail[j] = availmem_regions[i].mr_start; 1280 phys_avail[j + 1] = availmem_regions[i].mr_start + 1281 availmem_regions[i].mr_size; 1282 phys_avail_count++; 1283 physsz += availmem_regions[i].mr_size; 1284 } 1285 physmem = btoc(physsz); 1286 1287 /* Calculate the last available physical address. */ 1288 for (i = 0; phys_avail[i + 2] != 0; i += 2) 1289 ; 1290 Maxmem = powerpc_btop(phys_avail[i + 1]); 1291 1292 debugf("Maxmem = 0x%08lx\n", Maxmem); 1293 debugf("phys_avail_count = %d\n", phys_avail_count); 1294 debugf("physsz = 0x%09jx physmem = %jd (0x%09jx)\n", 1295 (uintmax_t)physsz, (uintmax_t)physmem, (uintmax_t)physmem); 1296 1297 /*******************************************************/ 1298 /* Initialize (statically allocated) kernel pmap. */ 1299 /*******************************************************/ 1300 PMAP_LOCK_INIT(kernel_pmap); 1301 kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE; 1302 1303 debugf("kernel_pmap = 0x%08x\n", (uint32_t)kernel_pmap); 1304 debugf("kptbl_min = %d, kernel_ptbls = %d\n", kptbl_min, kernel_ptbls); 1305 debugf("kernel pdir range: 0x%08x - 0x%08x\n", 1306 kptbl_min * PDIR_SIZE, (kptbl_min + kernel_ptbls) * PDIR_SIZE - 1); 1307 1308 kernel_pte_alloc(data_end, kernstart, kernel_pdir); 1309 for (i = 0; i < MAXCPU; i++) { 1310 kernel_pmap->pm_tid[i] = TID_KERNEL; 1311 1312 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */ 1313 tidbusy[i][TID_KERNEL] = kernel_pmap; 1314 } 1315 1316 /* Mark kernel_pmap active on all CPUs */ 1317 CPU_FILL(&kernel_pmap->pm_active); 1318 1319 /* 1320 * Initialize the global pv list lock. 1321 */ 1322 rw_init(&pvh_global_lock, "pmap pv global"); 1323 1324 /*******************************************************/ 1325 /* Final setup */ 1326 /*******************************************************/ 1327 1328 /* Enter kstack0 into kernel map, provide guard page */ 1329 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1330 thread0.td_kstack = kstack0; 1331 thread0.td_kstack_pages = kstack_pages; 1332 1333 debugf("kstack_sz = 0x%08x\n", kstack0_sz); 1334 debugf("kstack0_phys at 0x%09llx - 0x%09llx\n", 1335 kstack0_phys, kstack0_phys + kstack0_sz); 1336 debugf("kstack0 at 0x%08x - 0x%08x\n", kstack0, kstack0 + kstack0_sz); 1337 1338 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz; 1339 for (i = 0; i < kstack_pages; i++) { 1340 mmu_booke_kenter(mmu, kstack0, kstack0_phys); 1341 kstack0 += PAGE_SIZE; 1342 kstack0_phys += PAGE_SIZE; 1343 } 1344 1345 pmap_bootstrapped = 1; 1346 1347 debugf("virtual_avail = %08x\n", virtual_avail); 1348 debugf("virtual_end = %08x\n", virtual_end); 1349 1350 debugf("mmu_booke_bootstrap: exit\n"); 1351 } 1352 1353 #ifdef SMP 1354 void 1355 tlb1_ap_prep(void) 1356 { 1357 tlb_entry_t *e, tmp; 1358 unsigned int i; 1359 1360 /* Prepare TLB1 image for AP processors */ 1361 e = __boot_tlb1; 1362 for (i = 0; i < TLB1_ENTRIES; i++) { 1363 tlb1_read_entry(&tmp, i); 1364 1365 if ((tmp.mas1 & MAS1_VALID) && (tmp.mas2 & _TLB_ENTRY_SHARED)) 1366 memcpy(e++, &tmp, sizeof(tmp)); 1367 } 1368 } 1369 1370 void 1371 pmap_bootstrap_ap(volatile uint32_t *trcp __unused) 1372 { 1373 int i; 1374 1375 /* 1376 * Finish TLB1 configuration: the BSP already set up its TLB1 and we 1377 * have the snapshot of its contents in the s/w __boot_tlb1[] table 1378 * created by tlb1_ap_prep(), so use these values directly to 1379 * (re)program AP's TLB1 hardware. 1380 * 1381 * Start at index 1 because index 0 has the kernel map. 1382 */ 1383 for (i = 1; i < TLB1_ENTRIES; i++) { 1384 if (__boot_tlb1[i].mas1 & MAS1_VALID) 1385 tlb1_write_entry(&__boot_tlb1[i], i); 1386 } 1387 1388 set_mas4_defaults(); 1389 } 1390 #endif 1391 1392 static void 1393 booke_pmap_init_qpages(void) 1394 { 1395 struct pcpu *pc; 1396 int i; 1397 1398 CPU_FOREACH(i) { 1399 pc = pcpu_find(i); 1400 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE); 1401 if (pc->pc_qmap_addr == 0) 1402 panic("pmap_init_qpages: unable to allocate KVA"); 1403 } 1404 } 1405 1406 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, booke_pmap_init_qpages, NULL); 1407 1408 /* 1409 * Get the physical page address for the given pmap/virtual address. 1410 */ 1411 static vm_paddr_t 1412 mmu_booke_extract(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1413 { 1414 vm_paddr_t pa; 1415 1416 PMAP_LOCK(pmap); 1417 pa = pte_vatopa(mmu, pmap, va); 1418 PMAP_UNLOCK(pmap); 1419 1420 return (pa); 1421 } 1422 1423 /* 1424 * Extract the physical page address associated with the given 1425 * kernel virtual address. 1426 */ 1427 static vm_paddr_t 1428 mmu_booke_kextract(mmu_t mmu, vm_offset_t va) 1429 { 1430 tlb_entry_t e; 1431 int i; 1432 1433 /* Check TLB1 mappings */ 1434 for (i = 0; i < TLB1_ENTRIES; i++) { 1435 tlb1_read_entry(&e, i); 1436 if (!(e.mas1 & MAS1_VALID)) 1437 continue; 1438 if (va >= e.virt && va < e.virt + e.size) 1439 return (e.phys + (va - e.virt)); 1440 } 1441 1442 return (pte_vatopa(mmu, kernel_pmap, va)); 1443 } 1444 1445 /* 1446 * Initialize the pmap module. 1447 * Called by vm_init, to initialize any structures that the pmap 1448 * system needs to map virtual memory. 1449 */ 1450 static void 1451 mmu_booke_init(mmu_t mmu) 1452 { 1453 int shpgperproc = PMAP_SHPGPERPROC; 1454 1455 /* 1456 * Initialize the address space (zone) for the pv entries. Set a 1457 * high water mark so that the system can recover from excessive 1458 * numbers of pv entries. 1459 */ 1460 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL, 1461 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1462 1463 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 1464 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count; 1465 1466 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 1467 pv_entry_high_water = 9 * (pv_entry_max / 10); 1468 1469 uma_zone_reserve_kva(pvzone, pv_entry_max); 1470 1471 /* Pre-fill pvzone with initial number of pv entries. */ 1472 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN); 1473 1474 /* Initialize ptbl allocation. */ 1475 ptbl_init(); 1476 } 1477 1478 /* 1479 * Map a list of wired pages into kernel virtual address space. This is 1480 * intended for temporary mappings which do not need page modification or 1481 * references recorded. Existing mappings in the region are overwritten. 1482 */ 1483 static void 1484 mmu_booke_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1485 { 1486 vm_offset_t va; 1487 1488 va = sva; 1489 while (count-- > 0) { 1490 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1491 va += PAGE_SIZE; 1492 m++; 1493 } 1494 } 1495 1496 /* 1497 * Remove page mappings from kernel virtual address space. Intended for 1498 * temporary mappings entered by mmu_booke_qenter. 1499 */ 1500 static void 1501 mmu_booke_qremove(mmu_t mmu, vm_offset_t sva, int count) 1502 { 1503 vm_offset_t va; 1504 1505 va = sva; 1506 while (count-- > 0) { 1507 mmu_booke_kremove(mmu, va); 1508 va += PAGE_SIZE; 1509 } 1510 } 1511 1512 /* 1513 * Map a wired page into kernel virtual address space. 1514 */ 1515 static void 1516 mmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1517 { 1518 1519 mmu_booke_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1520 } 1521 1522 static void 1523 mmu_booke_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 1524 { 1525 uint32_t flags; 1526 pte_t *pte; 1527 1528 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1529 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va")); 1530 1531 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID; 1532 flags |= tlb_calc_wimg(pa, ma) << PTE_MAS2_SHIFT; 1533 flags |= PTE_PS_4KB; 1534 1535 pte = pte_find(mmu, kernel_pmap, va); 1536 1537 mtx_lock_spin(&tlbivax_mutex); 1538 tlb_miss_lock(); 1539 1540 if (PTE_ISVALID(pte)) { 1541 1542 CTR1(KTR_PMAP, "%s: replacing entry!", __func__); 1543 1544 /* Flush entry from TLB0 */ 1545 tlb0_flush_entry(va); 1546 } 1547 1548 *pte = PTE_RPN_FROM_PA(pa) | flags; 1549 1550 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x " 1551 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n", 1552 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags); 1553 1554 /* Flush the real memory from the instruction cache. */ 1555 if ((flags & (PTE_I | PTE_G)) == 0) 1556 __syncicache((void *)va, PAGE_SIZE); 1557 1558 tlb_miss_unlock(); 1559 mtx_unlock_spin(&tlbivax_mutex); 1560 } 1561 1562 /* 1563 * Remove a page from kernel page table. 1564 */ 1565 static void 1566 mmu_booke_kremove(mmu_t mmu, vm_offset_t va) 1567 { 1568 pte_t *pte; 1569 1570 CTR2(KTR_PMAP,"%s: s (va = 0x%08x)\n", __func__, va); 1571 1572 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1573 (va <= VM_MAX_KERNEL_ADDRESS)), 1574 ("mmu_booke_kremove: invalid va")); 1575 1576 pte = pte_find(mmu, kernel_pmap, va); 1577 1578 if (!PTE_ISVALID(pte)) { 1579 1580 CTR1(KTR_PMAP, "%s: invalid pte", __func__); 1581 1582 return; 1583 } 1584 1585 mtx_lock_spin(&tlbivax_mutex); 1586 tlb_miss_lock(); 1587 1588 /* Invalidate entry in TLB0, update PTE. */ 1589 tlb0_flush_entry(va); 1590 *pte = 0; 1591 1592 tlb_miss_unlock(); 1593 mtx_unlock_spin(&tlbivax_mutex); 1594 } 1595 1596 /* 1597 * Initialize pmap associated with process 0. 1598 */ 1599 static void 1600 mmu_booke_pinit0(mmu_t mmu, pmap_t pmap) 1601 { 1602 1603 PMAP_LOCK_INIT(pmap); 1604 mmu_booke_pinit(mmu, pmap); 1605 PCPU_SET(curpmap, pmap); 1606 } 1607 1608 /* 1609 * Initialize a preallocated and zeroed pmap structure, 1610 * such as one in a vmspace structure. 1611 */ 1612 static void 1613 mmu_booke_pinit(mmu_t mmu, pmap_t pmap) 1614 { 1615 int i; 1616 1617 CTR4(KTR_PMAP, "%s: pmap = %p, proc %d '%s'", __func__, pmap, 1618 curthread->td_proc->p_pid, curthread->td_proc->p_comm); 1619 1620 KASSERT((pmap != kernel_pmap), ("pmap_pinit: initializing kernel_pmap")); 1621 1622 for (i = 0; i < MAXCPU; i++) 1623 pmap->pm_tid[i] = TID_NONE; 1624 CPU_ZERO(&kernel_pmap->pm_active); 1625 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats)); 1626 bzero(&pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES); 1627 TAILQ_INIT(&pmap->pm_ptbl_list); 1628 } 1629 1630 /* 1631 * Release any resources held by the given physical map. 1632 * Called when a pmap initialized by mmu_booke_pinit is being released. 1633 * Should only be called if the map contains no valid mappings. 1634 */ 1635 static void 1636 mmu_booke_release(mmu_t mmu, pmap_t pmap) 1637 { 1638 1639 KASSERT(pmap->pm_stats.resident_count == 0, 1640 ("pmap_release: pmap resident count %ld != 0", 1641 pmap->pm_stats.resident_count)); 1642 } 1643 1644 /* 1645 * Insert the given physical page at the specified virtual address in the 1646 * target physical map with the protection requested. If specified the page 1647 * will be wired down. 1648 */ 1649 static int 1650 mmu_booke_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1651 vm_prot_t prot, u_int flags, int8_t psind) 1652 { 1653 int error; 1654 1655 rw_wlock(&pvh_global_lock); 1656 PMAP_LOCK(pmap); 1657 error = mmu_booke_enter_locked(mmu, pmap, va, m, prot, flags, psind); 1658 rw_wunlock(&pvh_global_lock); 1659 PMAP_UNLOCK(pmap); 1660 return (error); 1661 } 1662 1663 static int 1664 mmu_booke_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1665 vm_prot_t prot, u_int pmap_flags, int8_t psind __unused) 1666 { 1667 pte_t *pte; 1668 vm_paddr_t pa; 1669 uint32_t flags; 1670 int error, su, sync; 1671 1672 pa = VM_PAGE_TO_PHYS(m); 1673 su = (pmap == kernel_pmap); 1674 sync = 0; 1675 1676 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x " 1677 // "pa=0x%08x prot=0x%08x flags=%#x)\n", 1678 // (u_int32_t)pmap, su, pmap->pm_tid, 1679 // (u_int32_t)m, va, pa, prot, flags); 1680 1681 if (su) { 1682 KASSERT(((va >= virtual_avail) && 1683 (va <= VM_MAX_KERNEL_ADDRESS)), 1684 ("mmu_booke_enter_locked: kernel pmap, non kernel va")); 1685 } else { 1686 KASSERT((va <= VM_MAXUSER_ADDRESS), 1687 ("mmu_booke_enter_locked: user pmap, non user va")); 1688 } 1689 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1690 VM_OBJECT_ASSERT_LOCKED(m->object); 1691 1692 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1693 1694 /* 1695 * If there is an existing mapping, and the physical address has not 1696 * changed, must be protection or wiring change. 1697 */ 1698 if (((pte = pte_find(mmu, pmap, va)) != NULL) && 1699 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) { 1700 1701 /* 1702 * Before actually updating pte->flags we calculate and 1703 * prepare its new value in a helper var. 1704 */ 1705 flags = *pte; 1706 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED); 1707 1708 /* Wiring change, just update stats. */ 1709 if ((pmap_flags & PMAP_ENTER_WIRED) != 0) { 1710 if (!PTE_ISWIRED(pte)) { 1711 flags |= PTE_WIRED; 1712 pmap->pm_stats.wired_count++; 1713 } 1714 } else { 1715 if (PTE_ISWIRED(pte)) { 1716 flags &= ~PTE_WIRED; 1717 pmap->pm_stats.wired_count--; 1718 } 1719 } 1720 1721 if (prot & VM_PROT_WRITE) { 1722 /* Add write permissions. */ 1723 flags |= PTE_SW; 1724 if (!su) 1725 flags |= PTE_UW; 1726 1727 if ((flags & PTE_MANAGED) != 0) 1728 vm_page_aflag_set(m, PGA_WRITEABLE); 1729 } else { 1730 /* Handle modified pages, sense modify status. */ 1731 1732 /* 1733 * The PTE_MODIFIED flag could be set by underlying 1734 * TLB misses since we last read it (above), possibly 1735 * other CPUs could update it so we check in the PTE 1736 * directly rather than rely on that saved local flags 1737 * copy. 1738 */ 1739 if (PTE_ISMODIFIED(pte)) 1740 vm_page_dirty(m); 1741 } 1742 1743 if (prot & VM_PROT_EXECUTE) { 1744 flags |= PTE_SX; 1745 if (!su) 1746 flags |= PTE_UX; 1747 1748 /* 1749 * Check existing flags for execute permissions: if we 1750 * are turning execute permissions on, icache should 1751 * be flushed. 1752 */ 1753 if ((*pte & (PTE_UX | PTE_SX)) == 0) 1754 sync++; 1755 } 1756 1757 flags &= ~PTE_REFERENCED; 1758 1759 /* 1760 * The new flags value is all calculated -- only now actually 1761 * update the PTE. 1762 */ 1763 mtx_lock_spin(&tlbivax_mutex); 1764 tlb_miss_lock(); 1765 1766 tlb0_flush_entry(va); 1767 *pte &= ~PTE_FLAGS_MASK; 1768 *pte |= flags; 1769 1770 tlb_miss_unlock(); 1771 mtx_unlock_spin(&tlbivax_mutex); 1772 1773 } else { 1774 /* 1775 * If there is an existing mapping, but it's for a different 1776 * physical address, pte_enter() will delete the old mapping. 1777 */ 1778 //if ((pte != NULL) && PTE_ISVALID(pte)) 1779 // debugf("mmu_booke_enter_locked: replace\n"); 1780 //else 1781 // debugf("mmu_booke_enter_locked: new\n"); 1782 1783 /* Now set up the flags and install the new mapping. */ 1784 flags = (PTE_SR | PTE_VALID); 1785 flags |= PTE_M; 1786 1787 if (!su) 1788 flags |= PTE_UR; 1789 1790 if (prot & VM_PROT_WRITE) { 1791 flags |= PTE_SW; 1792 if (!su) 1793 flags |= PTE_UW; 1794 1795 if ((m->oflags & VPO_UNMANAGED) == 0) 1796 vm_page_aflag_set(m, PGA_WRITEABLE); 1797 } 1798 1799 if (prot & VM_PROT_EXECUTE) { 1800 flags |= PTE_SX; 1801 if (!su) 1802 flags |= PTE_UX; 1803 } 1804 1805 /* If its wired update stats. */ 1806 if ((pmap_flags & PMAP_ENTER_WIRED) != 0) 1807 flags |= PTE_WIRED; 1808 1809 error = pte_enter(mmu, pmap, m, va, flags, 1810 (pmap_flags & PMAP_ENTER_NOSLEEP) != 0); 1811 if (error != 0) 1812 return (KERN_RESOURCE_SHORTAGE); 1813 1814 if ((flags & PMAP_ENTER_WIRED) != 0) 1815 pmap->pm_stats.wired_count++; 1816 1817 /* Flush the real memory from the instruction cache. */ 1818 if (prot & VM_PROT_EXECUTE) 1819 sync++; 1820 } 1821 1822 if (sync && (su || pmap == PCPU_GET(curpmap))) { 1823 __syncicache((void *)va, PAGE_SIZE); 1824 sync = 0; 1825 } 1826 1827 return (KERN_SUCCESS); 1828 } 1829 1830 /* 1831 * Maps a sequence of resident pages belonging to the same object. 1832 * The sequence begins with the given page m_start. This page is 1833 * mapped at the given virtual address start. Each subsequent page is 1834 * mapped at a virtual address that is offset from start by the same 1835 * amount as the page is offset from m_start within the object. The 1836 * last page in the sequence is the page with the largest offset from 1837 * m_start that can be mapped at a virtual address less than the given 1838 * virtual address end. Not every virtual page between start and end 1839 * is mapped; only those for which a resident page exists with the 1840 * corresponding offset from m_start are mapped. 1841 */ 1842 static void 1843 mmu_booke_enter_object(mmu_t mmu, pmap_t pmap, vm_offset_t start, 1844 vm_offset_t end, vm_page_t m_start, vm_prot_t prot) 1845 { 1846 vm_page_t m; 1847 vm_pindex_t diff, psize; 1848 1849 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1850 1851 psize = atop(end - start); 1852 m = m_start; 1853 rw_wlock(&pvh_global_lock); 1854 PMAP_LOCK(pmap); 1855 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1856 mmu_booke_enter_locked(mmu, pmap, start + ptoa(diff), m, 1857 prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1858 PMAP_ENTER_NOSLEEP, 0); 1859 m = TAILQ_NEXT(m, listq); 1860 } 1861 rw_wunlock(&pvh_global_lock); 1862 PMAP_UNLOCK(pmap); 1863 } 1864 1865 static void 1866 mmu_booke_enter_quick(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1867 vm_prot_t prot) 1868 { 1869 1870 rw_wlock(&pvh_global_lock); 1871 PMAP_LOCK(pmap); 1872 mmu_booke_enter_locked(mmu, pmap, va, m, 1873 prot & (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP, 1874 0); 1875 rw_wunlock(&pvh_global_lock); 1876 PMAP_UNLOCK(pmap); 1877 } 1878 1879 /* 1880 * Remove the given range of addresses from the specified map. 1881 * 1882 * It is assumed that the start and end are properly rounded to the page size. 1883 */ 1884 static void 1885 mmu_booke_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t endva) 1886 { 1887 pte_t *pte; 1888 uint8_t hold_flag; 1889 1890 int su = (pmap == kernel_pmap); 1891 1892 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n", 1893 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva); 1894 1895 if (su) { 1896 KASSERT(((va >= virtual_avail) && 1897 (va <= VM_MAX_KERNEL_ADDRESS)), 1898 ("mmu_booke_remove: kernel pmap, non kernel va")); 1899 } else { 1900 KASSERT((va <= VM_MAXUSER_ADDRESS), 1901 ("mmu_booke_remove: user pmap, non user va")); 1902 } 1903 1904 if (PMAP_REMOVE_DONE(pmap)) { 1905 //debugf("mmu_booke_remove: e (empty)\n"); 1906 return; 1907 } 1908 1909 hold_flag = PTBL_HOLD_FLAG(pmap); 1910 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag); 1911 1912 rw_wlock(&pvh_global_lock); 1913 PMAP_LOCK(pmap); 1914 for (; va < endva; va += PAGE_SIZE) { 1915 pte = pte_find(mmu, pmap, va); 1916 if ((pte != NULL) && PTE_ISVALID(pte)) 1917 pte_remove(mmu, pmap, va, hold_flag); 1918 } 1919 PMAP_UNLOCK(pmap); 1920 rw_wunlock(&pvh_global_lock); 1921 1922 //debugf("mmu_booke_remove: e\n"); 1923 } 1924 1925 /* 1926 * Remove physical page from all pmaps in which it resides. 1927 */ 1928 static void 1929 mmu_booke_remove_all(mmu_t mmu, vm_page_t m) 1930 { 1931 pv_entry_t pv, pvn; 1932 uint8_t hold_flag; 1933 1934 rw_wlock(&pvh_global_lock); 1935 for (pv = TAILQ_FIRST(&m->md.pv_list); pv != NULL; pv = pvn) { 1936 pvn = TAILQ_NEXT(pv, pv_link); 1937 1938 PMAP_LOCK(pv->pv_pmap); 1939 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap); 1940 pte_remove(mmu, pv->pv_pmap, pv->pv_va, hold_flag); 1941 PMAP_UNLOCK(pv->pv_pmap); 1942 } 1943 vm_page_aflag_clear(m, PGA_WRITEABLE); 1944 rw_wunlock(&pvh_global_lock); 1945 } 1946 1947 /* 1948 * Map a range of physical addresses into kernel virtual address space. 1949 */ 1950 static vm_offset_t 1951 mmu_booke_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1952 vm_paddr_t pa_end, int prot) 1953 { 1954 vm_offset_t sva = *virt; 1955 vm_offset_t va = sva; 1956 1957 //debugf("mmu_booke_map: s (sva = 0x%08x pa_start = 0x%08x pa_end = 0x%08x)\n", 1958 // sva, pa_start, pa_end); 1959 1960 while (pa_start < pa_end) { 1961 mmu_booke_kenter(mmu, va, pa_start); 1962 va += PAGE_SIZE; 1963 pa_start += PAGE_SIZE; 1964 } 1965 *virt = va; 1966 1967 //debugf("mmu_booke_map: e (va = 0x%08x)\n", va); 1968 return (sva); 1969 } 1970 1971 /* 1972 * The pmap must be activated before it's address space can be accessed in any 1973 * way. 1974 */ 1975 static void 1976 mmu_booke_activate(mmu_t mmu, struct thread *td) 1977 { 1978 pmap_t pmap; 1979 u_int cpuid; 1980 1981 pmap = &td->td_proc->p_vmspace->vm_pmap; 1982 1983 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%08x)", 1984 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1985 1986 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!")); 1987 1988 sched_pin(); 1989 1990 cpuid = PCPU_GET(cpuid); 1991 CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 1992 PCPU_SET(curpmap, pmap); 1993 1994 if (pmap->pm_tid[cpuid] == TID_NONE) 1995 tid_alloc(pmap); 1996 1997 /* Load PID0 register with pmap tid value. */ 1998 mtspr(SPR_PID0, pmap->pm_tid[cpuid]); 1999 __asm __volatile("isync"); 2000 2001 mtspr(SPR_DBCR0, td->td_pcb->pcb_cpu.booke.dbcr0); 2002 2003 sched_unpin(); 2004 2005 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__, 2006 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm); 2007 } 2008 2009 /* 2010 * Deactivate the specified process's address space. 2011 */ 2012 static void 2013 mmu_booke_deactivate(mmu_t mmu, struct thread *td) 2014 { 2015 pmap_t pmap; 2016 2017 pmap = &td->td_proc->p_vmspace->vm_pmap; 2018 2019 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%08x", 2020 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 2021 2022 td->td_pcb->pcb_cpu.booke.dbcr0 = mfspr(SPR_DBCR0); 2023 2024 CPU_CLR_ATOMIC(PCPU_GET(cpuid), &pmap->pm_active); 2025 PCPU_SET(curpmap, NULL); 2026 } 2027 2028 /* 2029 * Copy the range specified by src_addr/len 2030 * from the source map to the range dst_addr/len 2031 * in the destination map. 2032 * 2033 * This routine is only advisory and need not do anything. 2034 */ 2035 static void 2036 mmu_booke_copy(mmu_t mmu, pmap_t dst_pmap, pmap_t src_pmap, 2037 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr) 2038 { 2039 2040 } 2041 2042 /* 2043 * Set the physical protection on the specified range of this map as requested. 2044 */ 2045 static void 2046 mmu_booke_protect(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 2047 vm_prot_t prot) 2048 { 2049 vm_offset_t va; 2050 vm_page_t m; 2051 pte_t *pte; 2052 2053 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2054 mmu_booke_remove(mmu, pmap, sva, eva); 2055 return; 2056 } 2057 2058 if (prot & VM_PROT_WRITE) 2059 return; 2060 2061 PMAP_LOCK(pmap); 2062 for (va = sva; va < eva; va += PAGE_SIZE) { 2063 if ((pte = pte_find(mmu, pmap, va)) != NULL) { 2064 if (PTE_ISVALID(pte)) { 2065 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2066 2067 mtx_lock_spin(&tlbivax_mutex); 2068 tlb_miss_lock(); 2069 2070 /* Handle modified pages. */ 2071 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte)) 2072 vm_page_dirty(m); 2073 2074 tlb0_flush_entry(va); 2075 *pte &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 2076 2077 tlb_miss_unlock(); 2078 mtx_unlock_spin(&tlbivax_mutex); 2079 } 2080 } 2081 } 2082 PMAP_UNLOCK(pmap); 2083 } 2084 2085 /* 2086 * Clear the write and modified bits in each of the given page's mappings. 2087 */ 2088 static void 2089 mmu_booke_remove_write(mmu_t mmu, vm_page_t m) 2090 { 2091 pv_entry_t pv; 2092 pte_t *pte; 2093 2094 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2095 ("mmu_booke_remove_write: page %p is not managed", m)); 2096 2097 /* 2098 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 2099 * set by another thread while the object is locked. Thus, 2100 * if PGA_WRITEABLE is clear, no page table entries need updating. 2101 */ 2102 VM_OBJECT_ASSERT_WLOCKED(m->object); 2103 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 2104 return; 2105 rw_wlock(&pvh_global_lock); 2106 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2107 PMAP_LOCK(pv->pv_pmap); 2108 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 2109 if (PTE_ISVALID(pte)) { 2110 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2111 2112 mtx_lock_spin(&tlbivax_mutex); 2113 tlb_miss_lock(); 2114 2115 /* Handle modified pages. */ 2116 if (PTE_ISMODIFIED(pte)) 2117 vm_page_dirty(m); 2118 2119 /* Flush mapping from TLB0. */ 2120 *pte &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 2121 2122 tlb_miss_unlock(); 2123 mtx_unlock_spin(&tlbivax_mutex); 2124 } 2125 } 2126 PMAP_UNLOCK(pv->pv_pmap); 2127 } 2128 vm_page_aflag_clear(m, PGA_WRITEABLE); 2129 rw_wunlock(&pvh_global_lock); 2130 } 2131 2132 static void 2133 mmu_booke_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2134 { 2135 pte_t *pte; 2136 pmap_t pmap; 2137 vm_page_t m; 2138 vm_offset_t addr; 2139 vm_paddr_t pa = 0; 2140 int active, valid; 2141 2142 va = trunc_page(va); 2143 sz = round_page(sz); 2144 2145 rw_wlock(&pvh_global_lock); 2146 pmap = PCPU_GET(curpmap); 2147 active = (pm == kernel_pmap || pm == pmap) ? 1 : 0; 2148 while (sz > 0) { 2149 PMAP_LOCK(pm); 2150 pte = pte_find(mmu, pm, va); 2151 valid = (pte != NULL && PTE_ISVALID(pte)) ? 1 : 0; 2152 if (valid) 2153 pa = PTE_PA(pte); 2154 PMAP_UNLOCK(pm); 2155 if (valid) { 2156 if (!active) { 2157 /* Create a mapping in the active pmap. */ 2158 addr = 0; 2159 m = PHYS_TO_VM_PAGE(pa); 2160 PMAP_LOCK(pmap); 2161 pte_enter(mmu, pmap, m, addr, 2162 PTE_SR | PTE_VALID | PTE_UR, FALSE); 2163 __syncicache((void *)addr, PAGE_SIZE); 2164 pte_remove(mmu, pmap, addr, PTBL_UNHOLD); 2165 PMAP_UNLOCK(pmap); 2166 } else 2167 __syncicache((void *)va, PAGE_SIZE); 2168 } 2169 va += PAGE_SIZE; 2170 sz -= PAGE_SIZE; 2171 } 2172 rw_wunlock(&pvh_global_lock); 2173 } 2174 2175 /* 2176 * Atomically extract and hold the physical page with the given 2177 * pmap and virtual address pair if that mapping permits the given 2178 * protection. 2179 */ 2180 static vm_page_t 2181 mmu_booke_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, 2182 vm_prot_t prot) 2183 { 2184 pte_t *pte; 2185 vm_page_t m; 2186 uint32_t pte_wbit; 2187 vm_paddr_t pa; 2188 2189 m = NULL; 2190 pa = 0; 2191 PMAP_LOCK(pmap); 2192 retry: 2193 pte = pte_find(mmu, pmap, va); 2194 if ((pte != NULL) && PTE_ISVALID(pte)) { 2195 if (pmap == kernel_pmap) 2196 pte_wbit = PTE_SW; 2197 else 2198 pte_wbit = PTE_UW; 2199 2200 if ((*pte & pte_wbit) || ((prot & VM_PROT_WRITE) == 0)) { 2201 if (vm_page_pa_tryrelock(pmap, PTE_PA(pte), &pa)) 2202 goto retry; 2203 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2204 vm_page_hold(m); 2205 } 2206 } 2207 2208 PA_UNLOCK_COND(pa); 2209 PMAP_UNLOCK(pmap); 2210 return (m); 2211 } 2212 2213 /* 2214 * Initialize a vm_page's machine-dependent fields. 2215 */ 2216 static void 2217 mmu_booke_page_init(mmu_t mmu, vm_page_t m) 2218 { 2219 2220 TAILQ_INIT(&m->md.pv_list); 2221 } 2222 2223 /* 2224 * mmu_booke_zero_page_area zeros the specified hardware page by 2225 * mapping it into virtual memory and using bzero to clear 2226 * its contents. 2227 * 2228 * off and size must reside within a single page. 2229 */ 2230 static void 2231 mmu_booke_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 2232 { 2233 vm_offset_t va; 2234 2235 /* XXX KASSERT off and size are within a single page? */ 2236 2237 mtx_lock(&zero_page_mutex); 2238 va = zero_page_va; 2239 2240 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2241 bzero((caddr_t)va + off, size); 2242 mmu_booke_kremove(mmu, va); 2243 2244 mtx_unlock(&zero_page_mutex); 2245 } 2246 2247 /* 2248 * mmu_booke_zero_page zeros the specified hardware page. 2249 */ 2250 static void 2251 mmu_booke_zero_page(mmu_t mmu, vm_page_t m) 2252 { 2253 vm_offset_t off, va; 2254 2255 mtx_lock(&zero_page_mutex); 2256 va = zero_page_va; 2257 2258 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2259 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 2260 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 2261 mmu_booke_kremove(mmu, va); 2262 2263 mtx_unlock(&zero_page_mutex); 2264 } 2265 2266 /* 2267 * mmu_booke_copy_page copies the specified (machine independent) page by 2268 * mapping the page into virtual memory and using memcopy to copy the page, 2269 * one machine dependent page at a time. 2270 */ 2271 static void 2272 mmu_booke_copy_page(mmu_t mmu, vm_page_t sm, vm_page_t dm) 2273 { 2274 vm_offset_t sva, dva; 2275 2276 sva = copy_page_src_va; 2277 dva = copy_page_dst_va; 2278 2279 mtx_lock(©_page_mutex); 2280 mmu_booke_kenter(mmu, sva, VM_PAGE_TO_PHYS(sm)); 2281 mmu_booke_kenter(mmu, dva, VM_PAGE_TO_PHYS(dm)); 2282 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE); 2283 mmu_booke_kremove(mmu, dva); 2284 mmu_booke_kremove(mmu, sva); 2285 mtx_unlock(©_page_mutex); 2286 } 2287 2288 static inline void 2289 mmu_booke_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 2290 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 2291 { 2292 void *a_cp, *b_cp; 2293 vm_offset_t a_pg_offset, b_pg_offset; 2294 int cnt; 2295 2296 mtx_lock(©_page_mutex); 2297 while (xfersize > 0) { 2298 a_pg_offset = a_offset & PAGE_MASK; 2299 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 2300 mmu_booke_kenter(mmu, copy_page_src_va, 2301 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 2302 a_cp = (char *)copy_page_src_va + a_pg_offset; 2303 b_pg_offset = b_offset & PAGE_MASK; 2304 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 2305 mmu_booke_kenter(mmu, copy_page_dst_va, 2306 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 2307 b_cp = (char *)copy_page_dst_va + b_pg_offset; 2308 bcopy(a_cp, b_cp, cnt); 2309 mmu_booke_kremove(mmu, copy_page_dst_va); 2310 mmu_booke_kremove(mmu, copy_page_src_va); 2311 a_offset += cnt; 2312 b_offset += cnt; 2313 xfersize -= cnt; 2314 } 2315 mtx_unlock(©_page_mutex); 2316 } 2317 2318 static vm_offset_t 2319 mmu_booke_quick_enter_page(mmu_t mmu, vm_page_t m) 2320 { 2321 vm_paddr_t paddr; 2322 vm_offset_t qaddr; 2323 uint32_t flags; 2324 pte_t *pte; 2325 2326 paddr = VM_PAGE_TO_PHYS(m); 2327 2328 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID; 2329 flags |= tlb_calc_wimg(paddr, pmap_page_get_memattr(m)) << PTE_MAS2_SHIFT; 2330 flags |= PTE_PS_4KB; 2331 2332 critical_enter(); 2333 qaddr = PCPU_GET(qmap_addr); 2334 2335 pte = pte_find(mmu, kernel_pmap, qaddr); 2336 2337 KASSERT(*pte == 0, ("mmu_booke_quick_enter_page: PTE busy")); 2338 2339 /* 2340 * XXX: tlbivax is broadcast to other cores, but qaddr should 2341 * not be present in other TLBs. Is there a better instruction 2342 * sequence to use? Or just forget it & use mmu_booke_kenter()... 2343 */ 2344 __asm __volatile("tlbivax 0, %0" :: "r"(qaddr & MAS2_EPN_MASK)); 2345 __asm __volatile("isync; msync"); 2346 2347 *pte = PTE_RPN_FROM_PA(paddr) | flags; 2348 2349 /* Flush the real memory from the instruction cache. */ 2350 if ((flags & (PTE_I | PTE_G)) == 0) 2351 __syncicache((void *)qaddr, PAGE_SIZE); 2352 2353 return (qaddr); 2354 } 2355 2356 static void 2357 mmu_booke_quick_remove_page(mmu_t mmu, vm_offset_t addr) 2358 { 2359 pte_t *pte; 2360 2361 pte = pte_find(mmu, kernel_pmap, addr); 2362 2363 KASSERT(PCPU_GET(qmap_addr) == addr, 2364 ("mmu_booke_quick_remove_page: invalid address")); 2365 KASSERT(*pte != 0, 2366 ("mmu_booke_quick_remove_page: PTE not in use")); 2367 2368 *pte = 0; 2369 critical_exit(); 2370 } 2371 2372 /* 2373 * Return whether or not the specified physical page was modified 2374 * in any of physical maps. 2375 */ 2376 static boolean_t 2377 mmu_booke_is_modified(mmu_t mmu, vm_page_t m) 2378 { 2379 pte_t *pte; 2380 pv_entry_t pv; 2381 boolean_t rv; 2382 2383 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2384 ("mmu_booke_is_modified: page %p is not managed", m)); 2385 rv = FALSE; 2386 2387 /* 2388 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 2389 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 2390 * is clear, no PTEs can be modified. 2391 */ 2392 VM_OBJECT_ASSERT_WLOCKED(m->object); 2393 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 2394 return (rv); 2395 rw_wlock(&pvh_global_lock); 2396 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2397 PMAP_LOCK(pv->pv_pmap); 2398 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2399 PTE_ISVALID(pte)) { 2400 if (PTE_ISMODIFIED(pte)) 2401 rv = TRUE; 2402 } 2403 PMAP_UNLOCK(pv->pv_pmap); 2404 if (rv) 2405 break; 2406 } 2407 rw_wunlock(&pvh_global_lock); 2408 return (rv); 2409 } 2410 2411 /* 2412 * Return whether or not the specified virtual address is eligible 2413 * for prefault. 2414 */ 2415 static boolean_t 2416 mmu_booke_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t addr) 2417 { 2418 2419 return (FALSE); 2420 } 2421 2422 /* 2423 * Return whether or not the specified physical page was referenced 2424 * in any physical maps. 2425 */ 2426 static boolean_t 2427 mmu_booke_is_referenced(mmu_t mmu, vm_page_t m) 2428 { 2429 pte_t *pte; 2430 pv_entry_t pv; 2431 boolean_t rv; 2432 2433 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2434 ("mmu_booke_is_referenced: page %p is not managed", m)); 2435 rv = FALSE; 2436 rw_wlock(&pvh_global_lock); 2437 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2438 PMAP_LOCK(pv->pv_pmap); 2439 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2440 PTE_ISVALID(pte)) { 2441 if (PTE_ISREFERENCED(pte)) 2442 rv = TRUE; 2443 } 2444 PMAP_UNLOCK(pv->pv_pmap); 2445 if (rv) 2446 break; 2447 } 2448 rw_wunlock(&pvh_global_lock); 2449 return (rv); 2450 } 2451 2452 /* 2453 * Clear the modify bits on the specified physical page. 2454 */ 2455 static void 2456 mmu_booke_clear_modify(mmu_t mmu, vm_page_t m) 2457 { 2458 pte_t *pte; 2459 pv_entry_t pv; 2460 2461 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2462 ("mmu_booke_clear_modify: page %p is not managed", m)); 2463 VM_OBJECT_ASSERT_WLOCKED(m->object); 2464 KASSERT(!vm_page_xbusied(m), 2465 ("mmu_booke_clear_modify: page %p is exclusive busied", m)); 2466 2467 /* 2468 * If the page is not PG_AWRITEABLE, then no PTEs can be modified. 2469 * If the object containing the page is locked and the page is not 2470 * exclusive busied, then PG_AWRITEABLE cannot be concurrently set. 2471 */ 2472 if ((m->aflags & PGA_WRITEABLE) == 0) 2473 return; 2474 rw_wlock(&pvh_global_lock); 2475 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2476 PMAP_LOCK(pv->pv_pmap); 2477 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2478 PTE_ISVALID(pte)) { 2479 mtx_lock_spin(&tlbivax_mutex); 2480 tlb_miss_lock(); 2481 2482 if (*pte & (PTE_SW | PTE_UW | PTE_MODIFIED)) { 2483 tlb0_flush_entry(pv->pv_va); 2484 *pte &= ~(PTE_SW | PTE_UW | PTE_MODIFIED | 2485 PTE_REFERENCED); 2486 } 2487 2488 tlb_miss_unlock(); 2489 mtx_unlock_spin(&tlbivax_mutex); 2490 } 2491 PMAP_UNLOCK(pv->pv_pmap); 2492 } 2493 rw_wunlock(&pvh_global_lock); 2494 } 2495 2496 /* 2497 * Return a count of reference bits for a page, clearing those bits. 2498 * It is not necessary for every reference bit to be cleared, but it 2499 * is necessary that 0 only be returned when there are truly no 2500 * reference bits set. 2501 * 2502 * As an optimization, update the page's dirty field if a modified bit is 2503 * found while counting reference bits. This opportunistic update can be 2504 * performed at low cost and can eliminate the need for some future calls 2505 * to pmap_is_modified(). However, since this function stops after 2506 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some 2507 * dirty pages. Those dirty pages will only be detected by a future call 2508 * to pmap_is_modified(). 2509 */ 2510 static int 2511 mmu_booke_ts_referenced(mmu_t mmu, vm_page_t m) 2512 { 2513 pte_t *pte; 2514 pv_entry_t pv; 2515 int count; 2516 2517 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2518 ("mmu_booke_ts_referenced: page %p is not managed", m)); 2519 count = 0; 2520 rw_wlock(&pvh_global_lock); 2521 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2522 PMAP_LOCK(pv->pv_pmap); 2523 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2524 PTE_ISVALID(pte)) { 2525 if (PTE_ISMODIFIED(pte)) 2526 vm_page_dirty(m); 2527 if (PTE_ISREFERENCED(pte)) { 2528 mtx_lock_spin(&tlbivax_mutex); 2529 tlb_miss_lock(); 2530 2531 tlb0_flush_entry(pv->pv_va); 2532 *pte &= ~PTE_REFERENCED; 2533 2534 tlb_miss_unlock(); 2535 mtx_unlock_spin(&tlbivax_mutex); 2536 2537 if (++count >= PMAP_TS_REFERENCED_MAX) { 2538 PMAP_UNLOCK(pv->pv_pmap); 2539 break; 2540 } 2541 } 2542 } 2543 PMAP_UNLOCK(pv->pv_pmap); 2544 } 2545 rw_wunlock(&pvh_global_lock); 2546 return (count); 2547 } 2548 2549 /* 2550 * Clear the wired attribute from the mappings for the specified range of 2551 * addresses in the given pmap. Every valid mapping within that range must 2552 * have the wired attribute set. In contrast, invalid mappings cannot have 2553 * the wired attribute set, so they are ignored. 2554 * 2555 * The wired attribute of the page table entry is not a hardware feature, so 2556 * there is no need to invalidate any TLB entries. 2557 */ 2558 static void 2559 mmu_booke_unwire(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 2560 { 2561 vm_offset_t va; 2562 pte_t *pte; 2563 2564 PMAP_LOCK(pmap); 2565 for (va = sva; va < eva; va += PAGE_SIZE) { 2566 if ((pte = pte_find(mmu, pmap, va)) != NULL && 2567 PTE_ISVALID(pte)) { 2568 if (!PTE_ISWIRED(pte)) 2569 panic("mmu_booke_unwire: pte %p isn't wired", 2570 pte); 2571 *pte &= ~PTE_WIRED; 2572 pmap->pm_stats.wired_count--; 2573 } 2574 } 2575 PMAP_UNLOCK(pmap); 2576 2577 } 2578 2579 /* 2580 * Return true if the pmap's pv is one of the first 16 pvs linked to from this 2581 * page. This count may be changed upwards or downwards in the future; it is 2582 * only necessary that true be returned for a small subset of pmaps for proper 2583 * page aging. 2584 */ 2585 static boolean_t 2586 mmu_booke_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 2587 { 2588 pv_entry_t pv; 2589 int loops; 2590 boolean_t rv; 2591 2592 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2593 ("mmu_booke_page_exists_quick: page %p is not managed", m)); 2594 loops = 0; 2595 rv = FALSE; 2596 rw_wlock(&pvh_global_lock); 2597 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2598 if (pv->pv_pmap == pmap) { 2599 rv = TRUE; 2600 break; 2601 } 2602 if (++loops >= 16) 2603 break; 2604 } 2605 rw_wunlock(&pvh_global_lock); 2606 return (rv); 2607 } 2608 2609 /* 2610 * Return the number of managed mappings to the given physical page that are 2611 * wired. 2612 */ 2613 static int 2614 mmu_booke_page_wired_mappings(mmu_t mmu, vm_page_t m) 2615 { 2616 pv_entry_t pv; 2617 pte_t *pte; 2618 int count = 0; 2619 2620 if ((m->oflags & VPO_UNMANAGED) != 0) 2621 return (count); 2622 rw_wlock(&pvh_global_lock); 2623 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2624 PMAP_LOCK(pv->pv_pmap); 2625 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) 2626 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte)) 2627 count++; 2628 PMAP_UNLOCK(pv->pv_pmap); 2629 } 2630 rw_wunlock(&pvh_global_lock); 2631 return (count); 2632 } 2633 2634 static int 2635 mmu_booke_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2636 { 2637 int i; 2638 vm_offset_t va; 2639 2640 /* 2641 * This currently does not work for entries that 2642 * overlap TLB1 entries. 2643 */ 2644 for (i = 0; i < TLB1_ENTRIES; i ++) { 2645 if (tlb1_iomapped(i, pa, size, &va) == 0) 2646 return (0); 2647 } 2648 2649 return (EFAULT); 2650 } 2651 2652 void 2653 mmu_booke_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va) 2654 { 2655 vm_paddr_t ppa; 2656 vm_offset_t ofs; 2657 vm_size_t gran; 2658 2659 /* Minidumps are based on virtual memory addresses. */ 2660 if (do_minidump) { 2661 *va = (void *)(vm_offset_t)pa; 2662 return; 2663 } 2664 2665 /* Raw physical memory dumps don't have a virtual address. */ 2666 /* We always map a 256MB page at 256M. */ 2667 gran = 256 * 1024 * 1024; 2668 ppa = rounddown2(pa, gran); 2669 ofs = pa - ppa; 2670 *va = (void *)gran; 2671 tlb1_set_entry((vm_offset_t)va, ppa, gran, _TLB_ENTRY_IO); 2672 2673 if (sz > (gran - ofs)) 2674 tlb1_set_entry((vm_offset_t)(va + gran), ppa + gran, gran, 2675 _TLB_ENTRY_IO); 2676 } 2677 2678 void 2679 mmu_booke_dumpsys_unmap(mmu_t mmu, vm_paddr_t pa, size_t sz, void *va) 2680 { 2681 vm_paddr_t ppa; 2682 vm_offset_t ofs; 2683 vm_size_t gran; 2684 tlb_entry_t e; 2685 int i; 2686 2687 /* Minidumps are based on virtual memory addresses. */ 2688 /* Nothing to do... */ 2689 if (do_minidump) 2690 return; 2691 2692 for (i = 0; i < TLB1_ENTRIES; i++) { 2693 tlb1_read_entry(&e, i); 2694 if (!(e.mas1 & MAS1_VALID)) 2695 break; 2696 } 2697 2698 /* Raw physical memory dumps don't have a virtual address. */ 2699 i--; 2700 e.mas1 = 0; 2701 e.mas2 = 0; 2702 e.mas3 = 0; 2703 tlb1_write_entry(&e, i); 2704 2705 gran = 256 * 1024 * 1024; 2706 ppa = rounddown2(pa, gran); 2707 ofs = pa - ppa; 2708 if (sz > (gran - ofs)) { 2709 i--; 2710 e.mas1 = 0; 2711 e.mas2 = 0; 2712 e.mas3 = 0; 2713 tlb1_write_entry(&e, i); 2714 } 2715 } 2716 2717 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2718 2719 void 2720 mmu_booke_scan_init(mmu_t mmu) 2721 { 2722 vm_offset_t va; 2723 pte_t *pte; 2724 int i; 2725 2726 if (!do_minidump) { 2727 /* Initialize phys. segments for dumpsys(). */ 2728 memset(&dump_map, 0, sizeof(dump_map)); 2729 mem_regions(&physmem_regions, &physmem_regions_sz, &availmem_regions, 2730 &availmem_regions_sz); 2731 for (i = 0; i < physmem_regions_sz; i++) { 2732 dump_map[i].pa_start = physmem_regions[i].mr_start; 2733 dump_map[i].pa_size = physmem_regions[i].mr_size; 2734 } 2735 return; 2736 } 2737 2738 /* Virtual segments for minidumps: */ 2739 memset(&dump_map, 0, sizeof(dump_map)); 2740 2741 /* 1st: kernel .data and .bss. */ 2742 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2743 dump_map[0].pa_size = 2744 round_page((uintptr_t)_end) - dump_map[0].pa_start; 2745 2746 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2747 dump_map[1].pa_start = data_start; 2748 dump_map[1].pa_size = data_end - data_start; 2749 2750 /* 3rd: kernel VM. */ 2751 va = dump_map[1].pa_start + dump_map[1].pa_size; 2752 /* Find start of next chunk (from va). */ 2753 while (va < virtual_end) { 2754 /* Don't dump the buffer cache. */ 2755 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2756 va = kmi.buffer_eva; 2757 continue; 2758 } 2759 pte = pte_find(mmu, kernel_pmap, va); 2760 if (pte != NULL && PTE_ISVALID(pte)) 2761 break; 2762 va += PAGE_SIZE; 2763 } 2764 if (va < virtual_end) { 2765 dump_map[2].pa_start = va; 2766 va += PAGE_SIZE; 2767 /* Find last page in chunk. */ 2768 while (va < virtual_end) { 2769 /* Don't run into the buffer cache. */ 2770 if (va == kmi.buffer_sva) 2771 break; 2772 pte = pte_find(mmu, kernel_pmap, va); 2773 if (pte == NULL || !PTE_ISVALID(pte)) 2774 break; 2775 va += PAGE_SIZE; 2776 } 2777 dump_map[2].pa_size = va - dump_map[2].pa_start; 2778 } 2779 } 2780 2781 /* 2782 * Map a set of physical memory pages into the kernel virtual address space. 2783 * Return a pointer to where it is mapped. This routine is intended to be used 2784 * for mapping device memory, NOT real memory. 2785 */ 2786 static void * 2787 mmu_booke_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2788 { 2789 2790 return (mmu_booke_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT)); 2791 } 2792 2793 static void * 2794 mmu_booke_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 2795 { 2796 tlb_entry_t e; 2797 void *res; 2798 uintptr_t va, tmpva; 2799 vm_size_t sz; 2800 int i; 2801 2802 /* 2803 * Check if this is premapped in TLB1. Note: this should probably also 2804 * check whether a sequence of TLB1 entries exist that match the 2805 * requirement, but now only checks the easy case. 2806 */ 2807 if (ma == VM_MEMATTR_DEFAULT) { 2808 for (i = 0; i < TLB1_ENTRIES; i++) { 2809 tlb1_read_entry(&e, i); 2810 if (!(e.mas1 & MAS1_VALID)) 2811 continue; 2812 if (pa >= e.phys && 2813 (pa + size) <= (e.phys + e.size)) 2814 return (void *)(e.virt + 2815 (vm_offset_t)(pa - e.phys)); 2816 } 2817 } 2818 2819 size = roundup(size, PAGE_SIZE); 2820 2821 /* 2822 * The device mapping area is between VM_MAXUSER_ADDRESS and 2823 * VM_MIN_KERNEL_ADDRESS. This gives 1GB of device addressing. 2824 */ 2825 #ifdef SPARSE_MAPDEV 2826 /* 2827 * With a sparse mapdev, align to the largest starting region. This 2828 * could feasibly be optimized for a 'best-fit' alignment, but that 2829 * calculation could be very costly. 2830 */ 2831 do { 2832 tmpva = tlb1_map_base; 2833 va = roundup(tlb1_map_base, 1 << flsl(size)); 2834 } while (!atomic_cmpset_int(&tlb1_map_base, tmpva, va + size)); 2835 #else 2836 va = atomic_fetchadd_int(&tlb1_map_base, size); 2837 #endif 2838 res = (void *)va; 2839 2840 do { 2841 sz = 1 << (ilog2(size) & ~1); 2842 if (va % sz != 0) { 2843 do { 2844 sz >>= 2; 2845 } while (va % sz != 0); 2846 } 2847 if (bootverbose) 2848 printf("Wiring VA=%x to PA=%jx (size=%x)\n", 2849 va, (uintmax_t)pa, sz); 2850 tlb1_set_entry(va, pa, sz, 2851 _TLB_ENTRY_SHARED | tlb_calc_wimg(pa, ma)); 2852 size -= sz; 2853 pa += sz; 2854 va += sz; 2855 } while (size > 0); 2856 2857 return (res); 2858 } 2859 2860 /* 2861 * 'Unmap' a range mapped by mmu_booke_mapdev(). 2862 */ 2863 static void 2864 mmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2865 { 2866 #ifdef SUPPORTS_SHRINKING_TLB1 2867 vm_offset_t base, offset; 2868 2869 /* 2870 * Unmap only if this is inside kernel virtual space. 2871 */ 2872 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) { 2873 base = trunc_page(va); 2874 offset = va & PAGE_MASK; 2875 size = roundup(offset + size, PAGE_SIZE); 2876 kva_free(base, size); 2877 } 2878 #endif 2879 } 2880 2881 /* 2882 * mmu_booke_object_init_pt preloads the ptes for a given object into the 2883 * specified pmap. This eliminates the blast of soft faults on process startup 2884 * and immediately after an mmap. 2885 */ 2886 static void 2887 mmu_booke_object_init_pt(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2888 vm_object_t object, vm_pindex_t pindex, vm_size_t size) 2889 { 2890 2891 VM_OBJECT_ASSERT_WLOCKED(object); 2892 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 2893 ("mmu_booke_object_init_pt: non-device object")); 2894 } 2895 2896 /* 2897 * Perform the pmap work for mincore. 2898 */ 2899 static int 2900 mmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2901 vm_paddr_t *locked_pa) 2902 { 2903 2904 /* XXX: this should be implemented at some point */ 2905 return (0); 2906 } 2907 2908 static int 2909 mmu_booke_change_attr(mmu_t mmu, vm_offset_t addr, vm_size_t sz, 2910 vm_memattr_t mode) 2911 { 2912 vm_offset_t va; 2913 pte_t *pte; 2914 int i, j; 2915 tlb_entry_t e; 2916 2917 /* Check TLB1 mappings */ 2918 for (i = 0; i < TLB1_ENTRIES; i++) { 2919 tlb1_read_entry(&e, i); 2920 if (!(e.mas1 & MAS1_VALID)) 2921 continue; 2922 if (addr >= e.virt && addr < e.virt + e.size) 2923 break; 2924 } 2925 if (i < TLB1_ENTRIES) { 2926 /* Only allow full mappings to be modified for now. */ 2927 /* Validate the range. */ 2928 for (j = i, va = addr; va < addr + sz; va += e.size, j++) { 2929 tlb1_read_entry(&e, j); 2930 if (va != e.virt || (sz - (va - addr) < e.size)) 2931 return (EINVAL); 2932 } 2933 for (va = addr; va < addr + sz; va += e.size, i++) { 2934 tlb1_read_entry(&e, i); 2935 e.mas2 &= ~MAS2_WIMGE_MASK; 2936 e.mas2 |= tlb_calc_wimg(e.phys, mode); 2937 2938 /* 2939 * Write it out to the TLB. Should really re-sync with other 2940 * cores. 2941 */ 2942 tlb1_write_entry(&e, i); 2943 } 2944 return (0); 2945 } 2946 2947 /* Not in TLB1, try through pmap */ 2948 /* First validate the range. */ 2949 for (va = addr; va < addr + sz; va += PAGE_SIZE) { 2950 pte = pte_find(mmu, kernel_pmap, va); 2951 if (pte == NULL || !PTE_ISVALID(pte)) 2952 return (EINVAL); 2953 } 2954 2955 mtx_lock_spin(&tlbivax_mutex); 2956 tlb_miss_lock(); 2957 for (va = addr; va < addr + sz; va += PAGE_SIZE) { 2958 pte = pte_find(mmu, kernel_pmap, va); 2959 *pte &= ~(PTE_MAS2_MASK << PTE_MAS2_SHIFT); 2960 *pte |= tlb_calc_wimg(PTE_PA(pte), mode << PTE_MAS2_SHIFT); 2961 tlb0_flush_entry(va); 2962 } 2963 tlb_miss_unlock(); 2964 mtx_unlock_spin(&tlbivax_mutex); 2965 2966 return (pte_vatopa(mmu, kernel_pmap, va)); 2967 } 2968 2969 /**************************************************************************/ 2970 /* TID handling */ 2971 /**************************************************************************/ 2972 2973 /* 2974 * Allocate a TID. If necessary, steal one from someone else. 2975 * The new TID is flushed from the TLB before returning. 2976 */ 2977 static tlbtid_t 2978 tid_alloc(pmap_t pmap) 2979 { 2980 tlbtid_t tid; 2981 int thiscpu; 2982 2983 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap")); 2984 2985 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap); 2986 2987 thiscpu = PCPU_GET(cpuid); 2988 2989 tid = PCPU_GET(tid_next); 2990 if (tid > TID_MAX) 2991 tid = TID_MIN; 2992 PCPU_SET(tid_next, tid + 1); 2993 2994 /* If we are stealing TID then clear the relevant pmap's field */ 2995 if (tidbusy[thiscpu][tid] != NULL) { 2996 2997 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid); 2998 2999 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE; 3000 3001 /* Flush all entries from TLB0 matching this TID. */ 3002 tid_flush(tid); 3003 } 3004 3005 tidbusy[thiscpu][tid] = pmap; 3006 pmap->pm_tid[thiscpu] = tid; 3007 __asm __volatile("msync; isync"); 3008 3009 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid, 3010 PCPU_GET(tid_next)); 3011 3012 return (tid); 3013 } 3014 3015 /**************************************************************************/ 3016 /* TLB0 handling */ 3017 /**************************************************************************/ 3018 3019 static void 3020 tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3, 3021 uint32_t mas7) 3022 { 3023 int as; 3024 char desc[3]; 3025 tlbtid_t tid; 3026 vm_size_t size; 3027 unsigned int tsize; 3028 3029 desc[2] = '\0'; 3030 if (mas1 & MAS1_VALID) 3031 desc[0] = 'V'; 3032 else 3033 desc[0] = ' '; 3034 3035 if (mas1 & MAS1_IPROT) 3036 desc[1] = 'P'; 3037 else 3038 desc[1] = ' '; 3039 3040 as = (mas1 & MAS1_TS_MASK) ? 1 : 0; 3041 tid = MAS1_GETTID(mas1); 3042 3043 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3044 size = 0; 3045 if (tsize) 3046 size = tsize2size(tsize); 3047 3048 debugf("%3d: (%s) [AS=%d] " 3049 "sz = 0x%08x tsz = %d tid = %d mas1 = 0x%08x " 3050 "mas2(va) = 0x%08x mas3(pa) = 0x%08x mas7 = 0x%08x\n", 3051 i, desc, as, size, tsize, tid, mas1, mas2, mas3, mas7); 3052 } 3053 3054 /* Convert TLB0 va and way number to tlb0[] table index. */ 3055 static inline unsigned int 3056 tlb0_tableidx(vm_offset_t va, unsigned int way) 3057 { 3058 unsigned int idx; 3059 3060 idx = (way * TLB0_ENTRIES_PER_WAY); 3061 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT; 3062 return (idx); 3063 } 3064 3065 /* 3066 * Invalidate TLB0 entry. 3067 */ 3068 static inline void 3069 tlb0_flush_entry(vm_offset_t va) 3070 { 3071 3072 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va); 3073 3074 mtx_assert(&tlbivax_mutex, MA_OWNED); 3075 3076 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK)); 3077 __asm __volatile("isync; msync"); 3078 __asm __volatile("tlbsync; msync"); 3079 3080 CTR1(KTR_PMAP, "%s: e", __func__); 3081 } 3082 3083 /* Print out contents of the MAS registers for each TLB0 entry */ 3084 void 3085 tlb0_print_tlbentries(void) 3086 { 3087 uint32_t mas0, mas1, mas2, mas3, mas7; 3088 int entryidx, way, idx; 3089 3090 debugf("TLB0 entries:\n"); 3091 for (way = 0; way < TLB0_WAYS; way ++) 3092 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) { 3093 3094 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 3095 mtspr(SPR_MAS0, mas0); 3096 __asm __volatile("isync"); 3097 3098 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT; 3099 mtspr(SPR_MAS2, mas2); 3100 3101 __asm __volatile("isync; tlbre"); 3102 3103 mas1 = mfspr(SPR_MAS1); 3104 mas2 = mfspr(SPR_MAS2); 3105 mas3 = mfspr(SPR_MAS3); 3106 mas7 = mfspr(SPR_MAS7); 3107 3108 idx = tlb0_tableidx(mas2, way); 3109 tlb_print_entry(idx, mas1, mas2, mas3, mas7); 3110 } 3111 } 3112 3113 /**************************************************************************/ 3114 /* TLB1 handling */ 3115 /**************************************************************************/ 3116 3117 /* 3118 * TLB1 mapping notes: 3119 * 3120 * TLB1[0] Kernel text and data. 3121 * TLB1[1-15] Additional kernel text and data mappings (if required), PCI 3122 * windows, other devices mappings. 3123 */ 3124 3125 /* 3126 * Read an entry from given TLB1 slot. 3127 */ 3128 void 3129 tlb1_read_entry(tlb_entry_t *entry, unsigned int slot) 3130 { 3131 uint32_t mas0; 3132 3133 KASSERT((entry != NULL), ("%s(): Entry is NULL!", __func__)); 3134 3135 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(slot); 3136 mtspr(SPR_MAS0, mas0); 3137 __asm __volatile("isync; tlbre"); 3138 3139 entry->mas1 = mfspr(SPR_MAS1); 3140 entry->mas2 = mfspr(SPR_MAS2); 3141 entry->mas3 = mfspr(SPR_MAS3); 3142 3143 switch ((mfpvr() >> 16) & 0xFFFF) { 3144 case FSL_E500v2: 3145 case FSL_E500mc: 3146 case FSL_E5500: 3147 case FSL_E6500: 3148 entry->mas7 = mfspr(SPR_MAS7); 3149 break; 3150 default: 3151 entry->mas7 = 0; 3152 break; 3153 } 3154 3155 entry->virt = entry->mas2 & MAS2_EPN_MASK; 3156 entry->phys = ((vm_paddr_t)(entry->mas7 & MAS7_RPN) << 32) | 3157 (entry->mas3 & MAS3_RPN); 3158 entry->size = 3159 tsize2size((entry->mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT); 3160 } 3161 3162 /* 3163 * Write given entry to TLB1 hardware. 3164 * Use 32 bit pa, clear 4 high-order bits of RPN (mas7). 3165 */ 3166 static void 3167 tlb1_write_entry(tlb_entry_t *e, unsigned int idx) 3168 { 3169 uint32_t mas0; 3170 3171 //debugf("tlb1_write_entry: s\n"); 3172 3173 /* Select entry */ 3174 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx); 3175 //debugf("tlb1_write_entry: mas0 = 0x%08x\n", mas0); 3176 3177 mtspr(SPR_MAS0, mas0); 3178 __asm __volatile("isync"); 3179 mtspr(SPR_MAS1, e->mas1); 3180 __asm __volatile("isync"); 3181 mtspr(SPR_MAS2, e->mas2); 3182 __asm __volatile("isync"); 3183 mtspr(SPR_MAS3, e->mas3); 3184 __asm __volatile("isync"); 3185 switch ((mfpvr() >> 16) & 0xFFFF) { 3186 case FSL_E500mc: 3187 case FSL_E5500: 3188 case FSL_E6500: 3189 mtspr(SPR_MAS8, 0); 3190 __asm __volatile("isync"); 3191 /* FALLTHROUGH */ 3192 case FSL_E500v2: 3193 mtspr(SPR_MAS7, e->mas7); 3194 __asm __volatile("isync"); 3195 break; 3196 default: 3197 break; 3198 } 3199 3200 __asm __volatile("tlbwe; isync; msync"); 3201 3202 //debugf("tlb1_write_entry: e\n"); 3203 } 3204 3205 /* 3206 * Return the largest uint value log such that 2^log <= num. 3207 */ 3208 static unsigned int 3209 ilog2(unsigned int num) 3210 { 3211 int lz; 3212 3213 __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num)); 3214 return (31 - lz); 3215 } 3216 3217 /* 3218 * Convert TLB TSIZE value to mapped region size. 3219 */ 3220 static vm_size_t 3221 tsize2size(unsigned int tsize) 3222 { 3223 3224 /* 3225 * size = 4^tsize KB 3226 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10) 3227 */ 3228 3229 return ((1 << (2 * tsize)) * 1024); 3230 } 3231 3232 /* 3233 * Convert region size (must be power of 4) to TLB TSIZE value. 3234 */ 3235 static unsigned int 3236 size2tsize(vm_size_t size) 3237 { 3238 3239 return (ilog2(size) / 2 - 5); 3240 } 3241 3242 /* 3243 * Register permanent kernel mapping in TLB1. 3244 * 3245 * Entries are created starting from index 0 (current free entry is 3246 * kept in tlb1_idx) and are not supposed to be invalidated. 3247 */ 3248 int 3249 tlb1_set_entry(vm_offset_t va, vm_paddr_t pa, vm_size_t size, 3250 uint32_t flags) 3251 { 3252 tlb_entry_t e; 3253 uint32_t ts, tid; 3254 int tsize, index; 3255 3256 for (index = 0; index < TLB1_ENTRIES; index++) { 3257 tlb1_read_entry(&e, index); 3258 if ((e.mas1 & MAS1_VALID) == 0) 3259 break; 3260 /* Check if we're just updating the flags, and update them. */ 3261 if (e.phys == pa && e.virt == va && e.size == size) { 3262 e.mas2 = (va & MAS2_EPN_MASK) | flags; 3263 tlb1_write_entry(&e, index); 3264 return (0); 3265 } 3266 } 3267 if (index >= TLB1_ENTRIES) { 3268 printf("tlb1_set_entry: TLB1 full!\n"); 3269 return (-1); 3270 } 3271 3272 /* Convert size to TSIZE */ 3273 tsize = size2tsize(size); 3274 3275 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK; 3276 /* XXX TS is hard coded to 0 for now as we only use single address space */ 3277 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK; 3278 3279 e.phys = pa; 3280 e.virt = va; 3281 e.size = size; 3282 e.mas1 = MAS1_VALID | MAS1_IPROT | ts | tid; 3283 e.mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK); 3284 e.mas2 = (va & MAS2_EPN_MASK) | flags; 3285 3286 /* Set supervisor RWX permission bits */ 3287 e.mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX; 3288 e.mas7 = (pa >> 32) & MAS7_RPN; 3289 3290 tlb1_write_entry(&e, index); 3291 3292 /* 3293 * XXX in general TLB1 updates should be propagated between CPUs, 3294 * since current design assumes to have the same TLB1 set-up on all 3295 * cores. 3296 */ 3297 return (0); 3298 } 3299 3300 /* 3301 * Map in contiguous RAM region into the TLB1 using maximum of 3302 * KERNEL_REGION_MAX_TLB_ENTRIES entries. 3303 * 3304 * If necessary round up last entry size and return total size 3305 * used by all allocated entries. 3306 */ 3307 vm_size_t 3308 tlb1_mapin_region(vm_offset_t va, vm_paddr_t pa, vm_size_t size) 3309 { 3310 vm_size_t pgs[KERNEL_REGION_MAX_TLB_ENTRIES]; 3311 vm_size_t mapped, pgsz, base, mask; 3312 int idx, nents; 3313 3314 /* Round up to the next 1M */ 3315 size = roundup2(size, 1 << 20); 3316 3317 mapped = 0; 3318 idx = 0; 3319 base = va; 3320 pgsz = 64*1024*1024; 3321 while (mapped < size) { 3322 while (mapped < size && idx < KERNEL_REGION_MAX_TLB_ENTRIES) { 3323 while (pgsz > (size - mapped)) 3324 pgsz >>= 2; 3325 pgs[idx++] = pgsz; 3326 mapped += pgsz; 3327 } 3328 3329 /* We under-map. Correct for this. */ 3330 if (mapped < size) { 3331 while (pgs[idx - 1] == pgsz) { 3332 idx--; 3333 mapped -= pgsz; 3334 } 3335 /* XXX We may increase beyond out starting point. */ 3336 pgsz <<= 2; 3337 pgs[idx++] = pgsz; 3338 mapped += pgsz; 3339 } 3340 } 3341 3342 nents = idx; 3343 mask = pgs[0] - 1; 3344 /* Align address to the boundary */ 3345 if (va & mask) { 3346 va = (va + mask) & ~mask; 3347 pa = (pa + mask) & ~mask; 3348 } 3349 3350 for (idx = 0; idx < nents; idx++) { 3351 pgsz = pgs[idx]; 3352 debugf("%u: %llx -> %x, size=%x\n", idx, pa, va, pgsz); 3353 tlb1_set_entry(va, pa, pgsz, 3354 _TLB_ENTRY_SHARED | _TLB_ENTRY_MEM); 3355 pa += pgsz; 3356 va += pgsz; 3357 } 3358 3359 mapped = (va - base); 3360 #ifdef __powerpc64__ 3361 printf("mapped size 0x%016lx (wasted space 0x%16lx)\n", 3362 #else 3363 printf("mapped size 0x%08x (wasted space 0x%08x)\n", 3364 #endif 3365 mapped, mapped - size); 3366 return (mapped); 3367 } 3368 3369 /* 3370 * TLB1 initialization routine, to be called after the very first 3371 * assembler level setup done in locore.S. 3372 */ 3373 void 3374 tlb1_init() 3375 { 3376 uint32_t mas0, mas1, mas2, mas3, mas7; 3377 uint32_t tsz; 3378 3379 tlb1_get_tlbconf(); 3380 3381 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(0); 3382 mtspr(SPR_MAS0, mas0); 3383 __asm __volatile("isync; tlbre"); 3384 3385 mas1 = mfspr(SPR_MAS1); 3386 mas2 = mfspr(SPR_MAS2); 3387 mas3 = mfspr(SPR_MAS3); 3388 mas7 = mfspr(SPR_MAS7); 3389 3390 kernload = ((vm_paddr_t)(mas7 & MAS7_RPN) << 32) | 3391 (mas3 & MAS3_RPN); 3392 3393 tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3394 kernsize += (tsz > 0) ? tsize2size(tsz) : 0; 3395 3396 /* Setup TLB miss defaults */ 3397 set_mas4_defaults(); 3398 } 3399 3400 /* 3401 * pmap_early_io_unmap() should be used in short conjunction with 3402 * pmap_early_io_map(), as in the following snippet: 3403 * 3404 * x = pmap_early_io_map(...); 3405 * <do something with x> 3406 * pmap_early_io_unmap(x, size); 3407 * 3408 * And avoiding more allocations between. 3409 */ 3410 void 3411 pmap_early_io_unmap(vm_offset_t va, vm_size_t size) 3412 { 3413 int i; 3414 tlb_entry_t e; 3415 vm_size_t isize; 3416 3417 size = roundup(size, PAGE_SIZE); 3418 isize = size; 3419 for (i = 0; i < TLB1_ENTRIES && size > 0; i++) { 3420 tlb1_read_entry(&e, i); 3421 if (!(e.mas1 & MAS1_VALID)) 3422 continue; 3423 if (va <= e.virt && (va + isize) >= (e.virt + e.size)) { 3424 size -= e.size; 3425 e.mas1 &= ~MAS1_VALID; 3426 tlb1_write_entry(&e, i); 3427 } 3428 } 3429 if (tlb1_map_base == va + isize) 3430 tlb1_map_base -= isize; 3431 } 3432 3433 vm_offset_t 3434 pmap_early_io_map(vm_paddr_t pa, vm_size_t size) 3435 { 3436 vm_paddr_t pa_base; 3437 vm_offset_t va, sz; 3438 int i; 3439 tlb_entry_t e; 3440 3441 KASSERT(!pmap_bootstrapped, ("Do not use after PMAP is up!")); 3442 3443 for (i = 0; i < TLB1_ENTRIES; i++) { 3444 tlb1_read_entry(&e, i); 3445 if (!(e.mas1 & MAS1_VALID)) 3446 continue; 3447 if (pa >= e.phys && (pa + size) <= 3448 (e.phys + e.size)) 3449 return (e.virt + (pa - e.phys)); 3450 } 3451 3452 pa_base = rounddown(pa, PAGE_SIZE); 3453 size = roundup(size + (pa - pa_base), PAGE_SIZE); 3454 tlb1_map_base = roundup2(tlb1_map_base, 1 << (ilog2(size) & ~1)); 3455 va = tlb1_map_base + (pa - pa_base); 3456 3457 do { 3458 sz = 1 << (ilog2(size) & ~1); 3459 tlb1_set_entry(tlb1_map_base, pa_base, sz, 3460 _TLB_ENTRY_SHARED | _TLB_ENTRY_IO); 3461 size -= sz; 3462 pa_base += sz; 3463 tlb1_map_base += sz; 3464 } while (size > 0); 3465 3466 return (va); 3467 } 3468 3469 /* 3470 * Setup MAS4 defaults. 3471 * These values are loaded to MAS0-2 on a TLB miss. 3472 */ 3473 static void 3474 set_mas4_defaults(void) 3475 { 3476 uint32_t mas4; 3477 3478 /* Defaults: TLB0, PID0, TSIZED=4K */ 3479 mas4 = MAS4_TLBSELD0; 3480 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK; 3481 #ifdef SMP 3482 mas4 |= MAS4_MD; 3483 #endif 3484 mtspr(SPR_MAS4, mas4); 3485 __asm __volatile("isync"); 3486 } 3487 3488 /* 3489 * Print out contents of the MAS registers for each TLB1 entry 3490 */ 3491 void 3492 tlb1_print_tlbentries(void) 3493 { 3494 uint32_t mas0, mas1, mas2, mas3, mas7; 3495 int i; 3496 3497 debugf("TLB1 entries:\n"); 3498 for (i = 0; i < TLB1_ENTRIES; i++) { 3499 3500 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i); 3501 mtspr(SPR_MAS0, mas0); 3502 3503 __asm __volatile("isync; tlbre"); 3504 3505 mas1 = mfspr(SPR_MAS1); 3506 mas2 = mfspr(SPR_MAS2); 3507 mas3 = mfspr(SPR_MAS3); 3508 mas7 = mfspr(SPR_MAS7); 3509 3510 tlb_print_entry(i, mas1, mas2, mas3, mas7); 3511 } 3512 } 3513 3514 /* 3515 * Return 0 if the physical IO range is encompassed by one of the 3516 * the TLB1 entries, otherwise return related error code. 3517 */ 3518 static int 3519 tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va) 3520 { 3521 uint32_t prot; 3522 vm_paddr_t pa_start; 3523 vm_paddr_t pa_end; 3524 unsigned int entry_tsize; 3525 vm_size_t entry_size; 3526 tlb_entry_t e; 3527 3528 *va = (vm_offset_t)NULL; 3529 3530 tlb1_read_entry(&e, i); 3531 /* Skip invalid entries */ 3532 if (!(e.mas1 & MAS1_VALID)) 3533 return (EINVAL); 3534 3535 /* 3536 * The entry must be cache-inhibited, guarded, and r/w 3537 * so it can function as an i/o page 3538 */ 3539 prot = e.mas2 & (MAS2_I | MAS2_G); 3540 if (prot != (MAS2_I | MAS2_G)) 3541 return (EPERM); 3542 3543 prot = e.mas3 & (MAS3_SR | MAS3_SW); 3544 if (prot != (MAS3_SR | MAS3_SW)) 3545 return (EPERM); 3546 3547 /* The address should be within the entry range. */ 3548 entry_tsize = (e.mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3549 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize")); 3550 3551 entry_size = tsize2size(entry_tsize); 3552 pa_start = (((vm_paddr_t)e.mas7 & MAS7_RPN) << 32) | 3553 (e.mas3 & MAS3_RPN); 3554 pa_end = pa_start + entry_size; 3555 3556 if ((pa < pa_start) || ((pa + size) > pa_end)) 3557 return (ERANGE); 3558 3559 /* Return virtual address of this mapping. */ 3560 *va = (e.mas2 & MAS2_EPN_MASK) + (pa - pa_start); 3561 return (0); 3562 } 3563 3564 /* 3565 * Invalidate all TLB0 entries which match the given TID. Note this is 3566 * dedicated for cases when invalidations should NOT be propagated to other 3567 * CPUs. 3568 */ 3569 static void 3570 tid_flush(tlbtid_t tid) 3571 { 3572 register_t msr; 3573 uint32_t mas0, mas1, mas2; 3574 int entry, way; 3575 3576 3577 /* Don't evict kernel translations */ 3578 if (tid == TID_KERNEL) 3579 return; 3580 3581 msr = mfmsr(); 3582 __asm __volatile("wrteei 0"); 3583 3584 for (way = 0; way < TLB0_WAYS; way++) 3585 for (entry = 0; entry < TLB0_ENTRIES_PER_WAY; entry++) { 3586 3587 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 3588 mtspr(SPR_MAS0, mas0); 3589 __asm __volatile("isync"); 3590 3591 mas2 = entry << MAS2_TLB0_ENTRY_IDX_SHIFT; 3592 mtspr(SPR_MAS2, mas2); 3593 3594 __asm __volatile("isync; tlbre"); 3595 3596 mas1 = mfspr(SPR_MAS1); 3597 3598 if (!(mas1 & MAS1_VALID)) 3599 continue; 3600 if (((mas1 & MAS1_TID_MASK) >> MAS1_TID_SHIFT) != tid) 3601 continue; 3602 mas1 &= ~MAS1_VALID; 3603 mtspr(SPR_MAS1, mas1); 3604 __asm __volatile("isync; tlbwe; isync; msync"); 3605 } 3606 mtmsr(msr); 3607 } 3608