1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD AND 4-Clause-BSD 3 * 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /*- 32 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 33 * Copyright (C) 1995, 1996 TooLs GmbH. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by TooLs GmbH. 47 * 4. The name of TooLs GmbH may not be used to endorse or promote products 48 * derived from this software without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 51 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 52 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 53 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 54 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 55 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 56 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 57 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 58 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 59 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60 * 61 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 62 */ 63 /*- 64 * Copyright (C) 2001 Benno Rice. 65 * All rights reserved. 66 * 67 * Redistribution and use in source and binary forms, with or without 68 * modification, are permitted provided that the following conditions 69 * are met: 70 * 1. Redistributions of source code must retain the above copyright 71 * notice, this list of conditions and the following disclaimer. 72 * 2. Redistributions in binary form must reproduce the above copyright 73 * notice, this list of conditions and the following disclaimer in the 74 * documentation and/or other materials provided with the distribution. 75 * 76 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 77 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 78 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 79 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 80 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 81 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 82 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 83 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 84 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 85 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 86 */ 87 88 #include <sys/cdefs.h> 89 __FBSDID("$FreeBSD$"); 90 91 /* 92 * Native 64-bit page table operations for running without a hypervisor. 93 */ 94 95 #include <sys/param.h> 96 #include <sys/kernel.h> 97 #include <sys/ktr.h> 98 #include <sys/lock.h> 99 #include <sys/mutex.h> 100 #include <sys/proc.h> 101 #include <sys/sched.h> 102 #include <sys/sysctl.h> 103 #include <sys/systm.h> 104 #include <sys/rwlock.h> 105 #include <sys/endian.h> 106 107 #include <sys/kdb.h> 108 109 #include <vm/vm.h> 110 #include <vm/vm_param.h> 111 #include <vm/vm_kern.h> 112 #include <vm/vm_page.h> 113 #include <vm/vm_map.h> 114 #include <vm/vm_object.h> 115 #include <vm/vm_extern.h> 116 #include <vm/vm_pageout.h> 117 118 #include <machine/cpu.h> 119 #include <machine/hid.h> 120 #include <machine/md_var.h> 121 #include <machine/mmuvar.h> 122 123 #include "mmu_oea64.h" 124 125 #define PTESYNC() __asm __volatile("ptesync"); 126 #define TLBSYNC() __asm __volatile("tlbsync; ptesync"); 127 #define SYNC() __asm __volatile("sync"); 128 #define EIEIO() __asm __volatile("eieio"); 129 130 #define VSID_HASH_MASK 0x0000007fffffffffULL 131 132 /* POWER9 only permits a 64k partition table size. */ 133 #define PART_SIZE 0x10000 134 135 /* Actual page sizes (to be used with tlbie, when L=0) */ 136 #define AP_4K 0x00 137 #define AP_16M 0x80 138 139 #define LPTE_KERNEL_VSID_BIT (KERNEL_VSID_BIT << \ 140 (16 - (ADDR_API_SHFT64 - ADDR_PIDX_SHFT))) 141 142 /* Abbreviated Virtual Address Page - high bits */ 143 #define LPTE_AVA_PGNHI_MASK 0x0000000000000F80ULL 144 #define LPTE_AVA_PGNHI_SHIFT 7 145 146 /* Effective Address Page - low bits */ 147 #define EA_PAGELO_MASK 0x7ffULL 148 #define EA_PAGELO_SHIFT 11 149 150 static bool moea64_crop_tlbie; 151 static bool moea64_need_lock; 152 153 /* 154 * The tlbie instruction has two forms: an old one used by PowerISA 155 * 2.03 and prior, and a newer one used by PowerISA 2.06 and later. 156 * We need to support both. 157 */ 158 static __inline void 159 TLBIE(uint64_t vpn, uint64_t oldptehi) 160 { 161 #ifndef __powerpc64__ 162 register_t vpn_hi, vpn_lo; 163 register_t msr; 164 register_t scratch, intr; 165 #endif 166 167 static volatile u_int tlbie_lock = 0; 168 bool need_lock = moea64_need_lock; 169 170 vpn <<= ADDR_PIDX_SHFT; 171 172 /* Hobo spinlock: we need stronger guarantees than mutexes provide */ 173 if (need_lock) { 174 while (!atomic_cmpset_int(&tlbie_lock, 0, 1)); 175 isync(); /* Flush instruction queue once lock acquired */ 176 177 if (moea64_crop_tlbie) { 178 vpn &= ~(0xffffULL << 48); 179 #ifdef __powerpc64__ 180 if ((oldptehi & LPTE_BIG) != 0) 181 __asm __volatile("tlbie %0, 1" :: "r"(vpn) : 182 "memory"); 183 else 184 __asm __volatile("tlbie %0, 0" :: "r"(vpn) : 185 "memory"); 186 __asm __volatile("eieio; tlbsync; ptesync" ::: 187 "memory"); 188 goto done; 189 #endif 190 } 191 } 192 193 #ifdef __powerpc64__ 194 /* 195 * If this page has LPTE_BIG set and is from userspace, then 196 * it must be a superpage with 4KB base/16MB actual page size. 197 */ 198 if ((oldptehi & LPTE_BIG) != 0 && 199 (oldptehi & LPTE_KERNEL_VSID_BIT) == 0) 200 vpn |= AP_16M; 201 202 /* 203 * Explicitly clobber r0. The tlbie instruction has two forms: an old 204 * one used by PowerISA 2.03 and prior, and a newer one used by PowerISA 205 * 2.06 (maybe 2.05?) and later. We need to support both, and it just 206 * so happens that since we use 4k pages we can simply zero out r0, and 207 * clobber it, and the assembler will interpret the single-operand form 208 * of tlbie as having RB set, and everything else as 0. The RS operand 209 * in the newer form is in the same position as the L(page size) bit of 210 * the old form, so a slong as RS is 0, we're good on both sides. 211 */ 212 __asm __volatile("li 0, 0 \n tlbie %0, 0" :: "r"(vpn) : "r0", "memory"); 213 __asm __volatile("eieio; tlbsync; ptesync" ::: "memory"); 214 done: 215 216 #else 217 vpn_hi = (uint32_t)(vpn >> 32); 218 vpn_lo = (uint32_t)vpn; 219 220 intr = intr_disable(); 221 __asm __volatile("\ 222 mfmsr %0; \ 223 mr %1, %0; \ 224 insrdi %1,%5,1,0; \ 225 mtmsrd %1; isync; \ 226 \ 227 sld %1,%2,%4; \ 228 or %1,%1,%3; \ 229 tlbie %1; \ 230 \ 231 mtmsrd %0; isync; \ 232 eieio; \ 233 tlbsync; \ 234 ptesync;" 235 : "=r"(msr), "=r"(scratch) : "r"(vpn_hi), "r"(vpn_lo), "r"(32), "r"(1) 236 : "memory"); 237 intr_restore(intr); 238 #endif 239 240 /* No barriers or special ops -- taken care of by ptesync above */ 241 if (need_lock) 242 tlbie_lock = 0; 243 } 244 245 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR) 246 #define ENABLE_TRANS(msr) mtmsr(msr) 247 248 /* 249 * PTEG data. 250 */ 251 static volatile struct lpte *moea64_pteg_table; 252 static struct rwlock moea64_eviction_lock; 253 254 static volatile struct pate *moea64_part_table; 255 256 /* 257 * Dump function. 258 */ 259 static void *moea64_dump_pmap_native(void *ctx, void *buf, 260 u_long *nbytes); 261 262 /* 263 * PTE calls. 264 */ 265 static int64_t moea64_pte_insert_native(struct pvo_entry *); 266 static int64_t moea64_pte_synch_native(struct pvo_entry *); 267 static int64_t moea64_pte_clear_native(struct pvo_entry *, uint64_t); 268 static int64_t moea64_pte_replace_native(struct pvo_entry *, int); 269 static int64_t moea64_pte_unset_native(struct pvo_entry *); 270 static int64_t moea64_pte_insert_sp_native(struct pvo_entry *); 271 static int64_t moea64_pte_unset_sp_native(struct pvo_entry *); 272 static int64_t moea64_pte_replace_sp_native(struct pvo_entry *); 273 274 /* 275 * Utility routines. 276 */ 277 static void moea64_bootstrap_native( 278 vm_offset_t kernelstart, vm_offset_t kernelend); 279 static void moea64_cpu_bootstrap_native(int ap); 280 static void tlbia(void); 281 static void moea64_install_native(void); 282 283 static struct pmap_funcs moea64_native_methods = { 284 .install = moea64_install_native, 285 286 /* Internal interfaces */ 287 .bootstrap = moea64_bootstrap_native, 288 .cpu_bootstrap = moea64_cpu_bootstrap_native, 289 .dumpsys_dump_pmap = moea64_dump_pmap_native, 290 }; 291 292 static struct moea64_funcs moea64_native_funcs = { 293 .pte_synch = moea64_pte_synch_native, 294 .pte_clear = moea64_pte_clear_native, 295 .pte_unset = moea64_pte_unset_native, 296 .pte_replace = moea64_pte_replace_native, 297 .pte_insert = moea64_pte_insert_native, 298 .pte_insert_sp = moea64_pte_insert_sp_native, 299 .pte_unset_sp = moea64_pte_unset_sp_native, 300 .pte_replace_sp = moea64_pte_replace_sp_native, 301 }; 302 303 MMU_DEF_INHERIT(oea64_mmu_native, MMU_TYPE_G5, moea64_native_methods, oea64_mmu); 304 305 static void 306 moea64_install_native() 307 { 308 309 /* Install the MOEA64 ops. */ 310 moea64_ops = &moea64_native_funcs; 311 } 312 313 static int64_t 314 moea64_pte_synch_native(struct pvo_entry *pvo) 315 { 316 volatile struct lpte *pt = moea64_pteg_table + pvo->pvo_pte.slot; 317 uint64_t ptelo, pvo_ptevpn; 318 319 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 320 321 pvo_ptevpn = moea64_pte_vpn_from_pvo_vpn(pvo); 322 323 rw_rlock(&moea64_eviction_lock); 324 if ((be64toh(pt->pte_hi) & LPTE_AVPN_MASK) != pvo_ptevpn) { 325 /* Evicted */ 326 rw_runlock(&moea64_eviction_lock); 327 return (-1); 328 } 329 330 PTESYNC(); 331 ptelo = be64toh(pt->pte_lo); 332 333 rw_runlock(&moea64_eviction_lock); 334 335 return (ptelo & (LPTE_REF | LPTE_CHG)); 336 } 337 338 static int64_t 339 moea64_pte_clear_native(struct pvo_entry *pvo, uint64_t ptebit) 340 { 341 volatile struct lpte *pt = moea64_pteg_table + pvo->pvo_pte.slot; 342 struct lpte properpt; 343 uint64_t ptelo; 344 345 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 346 347 moea64_pte_from_pvo(pvo, &properpt); 348 349 rw_rlock(&moea64_eviction_lock); 350 if ((be64toh(pt->pte_hi) & LPTE_AVPN_MASK) != 351 (properpt.pte_hi & LPTE_AVPN_MASK)) { 352 /* Evicted */ 353 rw_runlock(&moea64_eviction_lock); 354 return (-1); 355 } 356 357 if (ptebit == LPTE_REF) { 358 /* See "Resetting the Reference Bit" in arch manual */ 359 PTESYNC(); 360 /* 2-step here safe: precision is not guaranteed */ 361 ptelo = be64toh(pt->pte_lo); 362 363 /* One-byte store to avoid touching the C bit */ 364 ((volatile uint8_t *)(&pt->pte_lo))[6] = 365 #if BYTE_ORDER == BIG_ENDIAN 366 ((uint8_t *)(&properpt.pte_lo))[6]; 367 #else 368 ((uint8_t *)(&properpt.pte_lo))[1]; 369 #endif 370 rw_runlock(&moea64_eviction_lock); 371 372 critical_enter(); 373 TLBIE(pvo->pvo_vpn, properpt.pte_hi); 374 critical_exit(); 375 } else { 376 rw_runlock(&moea64_eviction_lock); 377 ptelo = moea64_pte_unset_native(pvo); 378 moea64_pte_insert_native(pvo); 379 } 380 381 return (ptelo & (LPTE_REF | LPTE_CHG)); 382 } 383 384 static __always_inline int64_t 385 moea64_pte_unset_locked(volatile struct lpte *pt, uint64_t vpn) 386 { 387 uint64_t ptelo; 388 389 /* 390 * Invalidate the pte, briefly locking it to collect RC bits. No 391 * atomics needed since this is protected against eviction by the lock. 392 */ 393 isync(); 394 critical_enter(); 395 pt->pte_hi = htobe64((be64toh(pt->pte_hi) & ~LPTE_VALID) | LPTE_LOCKED); 396 PTESYNC(); 397 TLBIE(vpn, pt->pte_hi); 398 ptelo = be64toh(pt->pte_lo); 399 *((volatile int32_t *)(&pt->pte_hi) + 1) = 0; /* Release lock */ 400 critical_exit(); 401 402 /* Keep statistics */ 403 STAT_MOEA64(moea64_pte_valid--); 404 405 return (ptelo & (LPTE_CHG | LPTE_REF)); 406 } 407 408 static int64_t 409 moea64_pte_unset_native(struct pvo_entry *pvo) 410 { 411 volatile struct lpte *pt = moea64_pteg_table + pvo->pvo_pte.slot; 412 int64_t ret; 413 uint64_t pvo_ptevpn; 414 415 pvo_ptevpn = moea64_pte_vpn_from_pvo_vpn(pvo); 416 417 rw_rlock(&moea64_eviction_lock); 418 419 if ((be64toh(pt->pte_hi & LPTE_AVPN_MASK)) != pvo_ptevpn) { 420 /* Evicted */ 421 STAT_MOEA64(moea64_pte_overflow--); 422 ret = -1; 423 } else 424 ret = moea64_pte_unset_locked(pt, pvo->pvo_vpn); 425 426 rw_runlock(&moea64_eviction_lock); 427 428 return (ret); 429 } 430 431 static int64_t 432 moea64_pte_replace_inval_native(struct pvo_entry *pvo, 433 volatile struct lpte *pt) 434 { 435 struct lpte properpt; 436 uint64_t ptelo; 437 438 moea64_pte_from_pvo(pvo, &properpt); 439 440 rw_rlock(&moea64_eviction_lock); 441 if ((be64toh(pt->pte_hi) & LPTE_AVPN_MASK) != 442 (properpt.pte_hi & LPTE_AVPN_MASK)) { 443 /* Evicted */ 444 STAT_MOEA64(moea64_pte_overflow--); 445 rw_runlock(&moea64_eviction_lock); 446 return (-1); 447 } 448 449 /* 450 * Replace the pte, briefly locking it to collect RC bits. No 451 * atomics needed since this is protected against eviction by the lock. 452 */ 453 isync(); 454 critical_enter(); 455 pt->pte_hi = htobe64((be64toh(pt->pte_hi) & ~LPTE_VALID) | LPTE_LOCKED); 456 PTESYNC(); 457 TLBIE(pvo->pvo_vpn, pt->pte_hi); 458 ptelo = be64toh(pt->pte_lo); 459 EIEIO(); 460 pt->pte_lo = htobe64(properpt.pte_lo); 461 EIEIO(); 462 pt->pte_hi = htobe64(properpt.pte_hi); /* Release lock */ 463 PTESYNC(); 464 critical_exit(); 465 rw_runlock(&moea64_eviction_lock); 466 467 return (ptelo & (LPTE_CHG | LPTE_REF)); 468 } 469 470 static int64_t 471 moea64_pte_replace_native(struct pvo_entry *pvo, int flags) 472 { 473 volatile struct lpte *pt = moea64_pteg_table + pvo->pvo_pte.slot; 474 struct lpte properpt; 475 int64_t ptelo; 476 477 if (flags == 0) { 478 /* Just some software bits changing. */ 479 moea64_pte_from_pvo(pvo, &properpt); 480 481 rw_rlock(&moea64_eviction_lock); 482 if ((be64toh(pt->pte_hi) & LPTE_AVPN_MASK) != 483 (properpt.pte_hi & LPTE_AVPN_MASK)) { 484 rw_runlock(&moea64_eviction_lock); 485 return (-1); 486 } 487 pt->pte_hi = htobe64(properpt.pte_hi); 488 ptelo = be64toh(pt->pte_lo); 489 rw_runlock(&moea64_eviction_lock); 490 } else { 491 /* Otherwise, need reinsertion and deletion */ 492 ptelo = moea64_pte_replace_inval_native(pvo, pt); 493 } 494 495 return (ptelo); 496 } 497 498 static void 499 moea64_cpu_bootstrap_native(int ap) 500 { 501 int i = 0; 502 #ifdef __powerpc64__ 503 struct slb *slb = PCPU_GET(aim.slb); 504 register_t seg0; 505 #endif 506 507 /* 508 * Initialize segment registers and MMU 509 */ 510 511 mtmsr(mfmsr() & ~PSL_DR & ~PSL_IR); 512 513 switch(mfpvr() >> 16) { 514 case IBMPOWER9: 515 mtspr(SPR_HID0, mfspr(SPR_HID0) & ~HID0_RADIX); 516 break; 517 } 518 519 /* 520 * Install kernel SLB entries 521 */ 522 523 #ifdef __powerpc64__ 524 __asm __volatile ("slbia"); 525 __asm __volatile ("slbmfee %0,%1; slbie %0;" : "=r"(seg0) : 526 "r"(0)); 527 528 for (i = 0; i < n_slbs; i++) { 529 if (!(slb[i].slbe & SLBE_VALID)) 530 continue; 531 532 __asm __volatile ("slbmte %0, %1" :: 533 "r"(slb[i].slbv), "r"(slb[i].slbe)); 534 } 535 #else 536 for (i = 0; i < 16; i++) 537 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]); 538 #endif 539 540 /* 541 * Install page table 542 */ 543 544 if (cpu_features2 & PPC_FEATURE2_ARCH_3_00) 545 mtspr(SPR_PTCR, 546 ((uintptr_t)moea64_part_table & ~DMAP_BASE_ADDRESS) | 547 flsl((PART_SIZE >> 12) - 1)); 548 else 549 __asm __volatile ("ptesync; mtsdr1 %0; isync" 550 :: "r"(((uintptr_t)moea64_pteg_table & ~DMAP_BASE_ADDRESS) 551 | (uintptr_t)(flsl(moea64_pteg_mask >> 11)))); 552 tlbia(); 553 } 554 555 static void 556 moea64_bootstrap_native(vm_offset_t kernelstart, vm_offset_t kernelend) 557 { 558 vm_size_t size; 559 vm_offset_t off; 560 vm_paddr_t pa; 561 register_t msr; 562 563 moea64_early_bootstrap(kernelstart, kernelend); 564 565 switch (mfpvr() >> 16) { 566 case IBMPOWER9: 567 moea64_need_lock = false; 568 break; 569 case IBMPOWER4: 570 case IBMPOWER4PLUS: 571 case IBM970: 572 case IBM970FX: 573 case IBM970GX: 574 case IBM970MP: 575 moea64_crop_tlbie = true; 576 default: 577 moea64_need_lock = true; 578 } 579 /* 580 * Allocate PTEG table. 581 */ 582 583 size = moea64_pteg_count * sizeof(struct lpteg); 584 CTR2(KTR_PMAP, "moea64_bootstrap: %lu PTEGs, %lu bytes", 585 moea64_pteg_count, size); 586 rw_init(&moea64_eviction_lock, "pte eviction"); 587 588 /* 589 * We now need to allocate memory. This memory, to be allocated, 590 * has to reside in a page table. The page table we are about to 591 * allocate. We don't have BAT. So drop to data real mode for a minute 592 * as a measure of last resort. We do this a couple times. 593 */ 594 /* 595 * PTEG table must be aligned on a 256k boundary, but can be placed 596 * anywhere with that alignment on POWER ISA 3+ systems. On earlier 597 * systems, offset addition is done by the CPU with bitwise OR rather 598 * than addition, so the table must also be aligned on a boundary of 599 * its own size. Pick the larger of the two, which works on all 600 * systems. 601 */ 602 moea64_pteg_table = (struct lpte *)moea64_bootstrap_alloc(size, 603 MAX(256*1024, size)); 604 if (hw_direct_map) 605 moea64_pteg_table = 606 (struct lpte *)PHYS_TO_DMAP((vm_offset_t)moea64_pteg_table); 607 /* Allocate partition table (ISA 3.0). */ 608 if (cpu_features2 & PPC_FEATURE2_ARCH_3_00) { 609 moea64_part_table = 610 (struct pate *)moea64_bootstrap_alloc(PART_SIZE, PART_SIZE); 611 moea64_part_table = 612 (struct pate *)PHYS_TO_DMAP((vm_offset_t)moea64_part_table); 613 } 614 DISABLE_TRANS(msr); 615 bzero(__DEVOLATILE(void *, moea64_pteg_table), moea64_pteg_count * 616 sizeof(struct lpteg)); 617 if (cpu_features2 & PPC_FEATURE2_ARCH_3_00) { 618 bzero(__DEVOLATILE(void *, moea64_part_table), PART_SIZE); 619 moea64_part_table[0].pagetab = htobe64( 620 (DMAP_TO_PHYS((vm_offset_t)moea64_pteg_table)) | 621 (uintptr_t)(flsl((moea64_pteg_count - 1) >> 11))); 622 } 623 ENABLE_TRANS(msr); 624 625 CTR1(KTR_PMAP, "moea64_bootstrap: PTEG table at %p", moea64_pteg_table); 626 627 moea64_mid_bootstrap(kernelstart, kernelend); 628 629 /* 630 * Add a mapping for the page table itself if there is no direct map. 631 */ 632 if (!hw_direct_map) { 633 size = moea64_pteg_count * sizeof(struct lpteg); 634 off = (vm_offset_t)(moea64_pteg_table); 635 DISABLE_TRANS(msr); 636 for (pa = off; pa < off + size; pa += PAGE_SIZE) 637 pmap_kenter(pa, pa); 638 ENABLE_TRANS(msr); 639 } 640 641 /* Bring up virtual memory */ 642 moea64_late_bootstrap(kernelstart, kernelend); 643 } 644 645 static void 646 tlbia(void) 647 { 648 vm_offset_t i; 649 #ifndef __powerpc64__ 650 register_t msr, scratch; 651 #endif 652 653 i = 0xc00; /* IS = 11 */ 654 switch (mfpvr() >> 16) { 655 case IBM970: 656 case IBM970FX: 657 case IBM970MP: 658 case IBM970GX: 659 case IBMPOWER4: 660 case IBMPOWER4PLUS: 661 case IBMPOWER5: 662 case IBMPOWER5PLUS: 663 i = 0; /* IS not supported */ 664 break; 665 } 666 667 TLBSYNC(); 668 669 for (; i < 0x400000; i += 0x00001000) { 670 #ifdef __powerpc64__ 671 __asm __volatile("tlbiel %0" :: "r"(i)); 672 #else 673 __asm __volatile("\ 674 mfmsr %0; \ 675 mr %1, %0; \ 676 insrdi %1,%3,1,0; \ 677 mtmsrd %1; \ 678 isync; \ 679 \ 680 tlbiel %2; \ 681 \ 682 mtmsrd %0; \ 683 isync;" 684 : "=r"(msr), "=r"(scratch) : "r"(i), "r"(1)); 685 #endif 686 } 687 688 EIEIO(); 689 TLBSYNC(); 690 } 691 692 static int 693 atomic_pte_lock(volatile struct lpte *pte, uint64_t bitmask, uint64_t *oldhi) 694 { 695 int ret; 696 #ifdef __powerpc64__ 697 uint64_t temp; 698 #else 699 uint32_t oldhihalf; 700 #endif 701 702 /* 703 * Note: in principle, if just the locked bit were set here, we 704 * could avoid needing the eviction lock. However, eviction occurs 705 * so rarely that it isn't worth bothering about in practice. 706 */ 707 #ifdef __powerpc64__ 708 /* 709 * Note: Success of this sequence has the side effect of invalidating 710 * the PTE, as we are setting it to LPTE_LOCKED and discarding the 711 * other bits, including LPTE_V. 712 */ 713 __asm __volatile ( 714 "1:\tldarx %1, 0, %3\n\t" /* load old value */ 715 "and. %0,%1,%4\n\t" /* check if any bits set */ 716 "bne 2f\n\t" /* exit if any set */ 717 "stdcx. %5, 0, %3\n\t" /* attempt to store */ 718 "bne- 1b\n\t" /* spin if failed */ 719 "li %0, 1\n\t" /* success - retval = 1 */ 720 "b 3f\n\t" /* we've succeeded */ 721 "2:\n\t" 722 "stdcx. %1, 0, %3\n\t" /* clear reservation (74xx) */ 723 "li %0, 0\n\t" /* failure - retval = 0 */ 724 "3:\n\t" 725 : "=&r" (ret), "=&r"(temp), "=m" (pte->pte_hi) 726 : "r" ((volatile char *)&pte->pte_hi), 727 "r" (htobe64(bitmask)), "r" (htobe64(LPTE_LOCKED)), 728 "m" (pte->pte_hi) 729 : "cr0", "cr1", "cr2", "memory"); 730 *oldhi = be64toh(temp); 731 #else 732 /* 733 * This code is used on bridge mode only. 734 */ 735 __asm __volatile ( 736 "1:\tlwarx %1, 0, %3\n\t" /* load old value */ 737 "and. %0,%1,%4\n\t" /* check if any bits set */ 738 "bne 2f\n\t" /* exit if any set */ 739 "stwcx. %5, 0, %3\n\t" /* attempt to store */ 740 "bne- 1b\n\t" /* spin if failed */ 741 "li %0, 1\n\t" /* success - retval = 1 */ 742 "b 3f\n\t" /* we've succeeded */ 743 "2:\n\t" 744 "stwcx. %1, 0, %3\n\t" /* clear reservation (74xx) */ 745 "li %0, 0\n\t" /* failure - retval = 0 */ 746 "3:\n\t" 747 : "=&r" (ret), "=&r"(oldhihalf), "=m" (pte->pte_hi) 748 : "r" ((volatile char *)&pte->pte_hi + 4), 749 "r" ((uint32_t)bitmask), "r" ((uint32_t)LPTE_LOCKED), 750 "m" (pte->pte_hi) 751 : "cr0", "cr1", "cr2", "memory"); 752 753 *oldhi = (pte->pte_hi & 0xffffffff00000000ULL) | oldhihalf; 754 #endif 755 756 return (ret); 757 } 758 759 static uintptr_t 760 moea64_insert_to_pteg_native(struct lpte *pvo_pt, uintptr_t slotbase, 761 uint64_t mask) 762 { 763 volatile struct lpte *pt; 764 uint64_t oldptehi, va; 765 uintptr_t k; 766 int i, j; 767 768 /* Start at a random slot */ 769 i = mftb() % 8; 770 for (j = 0; j < 8; j++) { 771 k = slotbase + (i + j) % 8; 772 pt = &moea64_pteg_table[k]; 773 /* Invalidate and seize lock only if no bits in mask set */ 774 if (atomic_pte_lock(pt, mask, &oldptehi)) /* Lock obtained */ 775 break; 776 } 777 778 if (j == 8) 779 return (-1); 780 781 if (oldptehi & LPTE_VALID) { 782 KASSERT(!(oldptehi & LPTE_WIRED), ("Unmapped wired entry")); 783 /* 784 * Need to invalidate old entry completely: see 785 * "Modifying a Page Table Entry". Need to reconstruct 786 * the virtual address for the outgoing entry to do that. 787 */ 788 va = oldptehi >> (ADDR_SR_SHFT - ADDR_API_SHFT64); 789 if (oldptehi & LPTE_HID) 790 va = (((k >> 3) ^ moea64_pteg_mask) ^ va) & 791 (ADDR_PIDX >> ADDR_PIDX_SHFT); 792 else 793 va = ((k >> 3) ^ va) & (ADDR_PIDX >> ADDR_PIDX_SHFT); 794 va |= (oldptehi & LPTE_AVPN_MASK) << 795 (ADDR_API_SHFT64 - ADDR_PIDX_SHFT); 796 PTESYNC(); 797 TLBIE(va, oldptehi); 798 STAT_MOEA64(moea64_pte_valid--); 799 STAT_MOEA64(moea64_pte_overflow++); 800 } 801 802 /* 803 * Update the PTE as per "Adding a Page Table Entry". Lock is released 804 * by setting the high doubleworld. 805 */ 806 pt->pte_lo = htobe64(pvo_pt->pte_lo); 807 EIEIO(); 808 pt->pte_hi = htobe64(pvo_pt->pte_hi); 809 PTESYNC(); 810 811 /* Keep statistics */ 812 STAT_MOEA64(moea64_pte_valid++); 813 814 return (k); 815 } 816 817 static __always_inline int64_t 818 moea64_pte_insert_locked(struct pvo_entry *pvo, struct lpte *insertpt, 819 uint64_t mask) 820 { 821 uintptr_t slot; 822 823 /* 824 * First try primary hash. 825 */ 826 slot = moea64_insert_to_pteg_native(insertpt, pvo->pvo_pte.slot, 827 mask | LPTE_WIRED | LPTE_LOCKED); 828 if (slot != -1) { 829 pvo->pvo_pte.slot = slot; 830 return (0); 831 } 832 833 /* 834 * Now try secondary hash. 835 */ 836 pvo->pvo_vaddr ^= PVO_HID; 837 insertpt->pte_hi ^= LPTE_HID; 838 pvo->pvo_pte.slot ^= (moea64_pteg_mask << 3); 839 slot = moea64_insert_to_pteg_native(insertpt, pvo->pvo_pte.slot, 840 mask | LPTE_WIRED | LPTE_LOCKED); 841 if (slot != -1) { 842 pvo->pvo_pte.slot = slot; 843 return (0); 844 } 845 846 return (-1); 847 } 848 849 static int64_t 850 moea64_pte_insert_native(struct pvo_entry *pvo) 851 { 852 struct lpte insertpt; 853 int64_t ret; 854 855 /* Initialize PTE */ 856 moea64_pte_from_pvo(pvo, &insertpt); 857 858 /* Make sure further insertion is locked out during evictions */ 859 rw_rlock(&moea64_eviction_lock); 860 861 pvo->pvo_pte.slot &= ~7ULL; /* Base slot address */ 862 ret = moea64_pte_insert_locked(pvo, &insertpt, LPTE_VALID); 863 if (ret == -1) { 864 /* 865 * Out of luck. Find a PTE to sacrifice. 866 */ 867 868 /* Lock out all insertions for a bit */ 869 if (!rw_try_upgrade(&moea64_eviction_lock)) { 870 rw_runlock(&moea64_eviction_lock); 871 rw_wlock(&moea64_eviction_lock); 872 } 873 /* Don't evict large pages */ 874 ret = moea64_pte_insert_locked(pvo, &insertpt, LPTE_BIG); 875 rw_wunlock(&moea64_eviction_lock); 876 /* No freeable slots in either PTEG? We're hosed. */ 877 if (ret == -1) 878 panic("moea64_pte_insert: overflow"); 879 } else 880 rw_runlock(&moea64_eviction_lock); 881 882 return (0); 883 } 884 885 static void * 886 moea64_dump_pmap_native(void *ctx, void *buf, u_long *nbytes) 887 { 888 struct dump_context *dctx; 889 u_long ptex, ptex_end; 890 891 dctx = (struct dump_context *)ctx; 892 ptex = dctx->ptex; 893 ptex_end = ptex + dctx->blksz / sizeof(struct lpte); 894 ptex_end = MIN(ptex_end, dctx->ptex_end); 895 *nbytes = (ptex_end - ptex) * sizeof(struct lpte); 896 897 if (*nbytes == 0) 898 return (NULL); 899 900 dctx->ptex = ptex_end; 901 return (__DEVOLATILE(struct lpte *, moea64_pteg_table) + ptex); 902 } 903 904 static __always_inline uint64_t 905 moea64_vpn_from_pte(uint64_t ptehi, uintptr_t slot) 906 { 907 uint64_t pgn, pgnlo, vsid; 908 909 vsid = (ptehi & LPTE_AVA_MASK) >> LPTE_VSID_SHIFT; 910 if ((ptehi & LPTE_HID) != 0) 911 slot ^= (moea64_pteg_mask << 3); 912 pgnlo = ((vsid & VSID_HASH_MASK) ^ (slot >> 3)) & EA_PAGELO_MASK; 913 pgn = ((ptehi & LPTE_AVA_PGNHI_MASK) << (EA_PAGELO_SHIFT - 914 LPTE_AVA_PGNHI_SHIFT)) | pgnlo; 915 return ((vsid << 16) | pgn); 916 } 917 918 static __always_inline int64_t 919 moea64_pte_unset_sp_locked(struct pvo_entry *pvo) 920 { 921 volatile struct lpte *pt; 922 uint64_t ptehi, refchg, vpn; 923 vm_offset_t eva; 924 pmap_t pm; 925 926 pm = pvo->pvo_pmap; 927 refchg = 0; 928 eva = PVO_VADDR(pvo) + HPT_SP_SIZE; 929 930 for (; pvo != NULL && PVO_VADDR(pvo) < eva; 931 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 932 pt = moea64_pteg_table + pvo->pvo_pte.slot; 933 ptehi = be64toh(pt->pte_hi); 934 if ((ptehi & LPTE_AVPN_MASK) != 935 moea64_pte_vpn_from_pvo_vpn(pvo)) { 936 /* Evicted: invalidate new entry */ 937 STAT_MOEA64(moea64_pte_overflow--); 938 vpn = moea64_vpn_from_pte(ptehi, pvo->pvo_pte.slot); 939 CTR1(KTR_PMAP, "Evicted page in pte_unset_sp: vpn=%jx", 940 (uintmax_t)vpn); 941 /* Assume evicted page was modified */ 942 refchg |= LPTE_CHG; 943 } else 944 vpn = pvo->pvo_vpn; 945 946 refchg |= moea64_pte_unset_locked(pt, vpn); 947 } 948 949 return (refchg); 950 } 951 952 static int64_t 953 moea64_pte_unset_sp_native(struct pvo_entry *pvo) 954 { 955 uint64_t refchg; 956 957 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 958 KASSERT((PVO_VADDR(pvo) & HPT_SP_MASK) == 0, 959 ("%s: va %#jx unaligned", __func__, (uintmax_t)PVO_VADDR(pvo))); 960 961 rw_rlock(&moea64_eviction_lock); 962 refchg = moea64_pte_unset_sp_locked(pvo); 963 rw_runlock(&moea64_eviction_lock); 964 965 return (refchg); 966 } 967 968 static __always_inline int64_t 969 moea64_pte_insert_sp_locked(struct pvo_entry *pvo) 970 { 971 struct lpte insertpt; 972 int64_t ret; 973 vm_offset_t eva; 974 pmap_t pm; 975 976 pm = pvo->pvo_pmap; 977 eva = PVO_VADDR(pvo) + HPT_SP_SIZE; 978 979 for (; pvo != NULL && PVO_VADDR(pvo) < eva; 980 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 981 moea64_pte_from_pvo(pvo, &insertpt); 982 pvo->pvo_pte.slot &= ~7ULL; /* Base slot address */ 983 984 ret = moea64_pte_insert_locked(pvo, &insertpt, LPTE_VALID); 985 if (ret == -1) { 986 /* Lock out all insertions for a bit */ 987 if (!rw_try_upgrade(&moea64_eviction_lock)) { 988 rw_runlock(&moea64_eviction_lock); 989 rw_wlock(&moea64_eviction_lock); 990 } 991 /* Don't evict large pages */ 992 ret = moea64_pte_insert_locked(pvo, &insertpt, 993 LPTE_BIG); 994 rw_downgrade(&moea64_eviction_lock); 995 /* No freeable slots in either PTEG? We're hosed. */ 996 if (ret == -1) 997 panic("moea64_pte_insert_sp: overflow"); 998 } 999 } 1000 1001 return (0); 1002 } 1003 1004 static int64_t 1005 moea64_pte_insert_sp_native(struct pvo_entry *pvo) 1006 { 1007 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 1008 KASSERT((PVO_VADDR(pvo) & HPT_SP_MASK) == 0, 1009 ("%s: va %#jx unaligned", __func__, (uintmax_t)PVO_VADDR(pvo))); 1010 1011 rw_rlock(&moea64_eviction_lock); 1012 moea64_pte_insert_sp_locked(pvo); 1013 rw_runlock(&moea64_eviction_lock); 1014 1015 return (0); 1016 } 1017 1018 static int64_t 1019 moea64_pte_replace_sp_native(struct pvo_entry *pvo) 1020 { 1021 uint64_t refchg; 1022 1023 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 1024 KASSERT((PVO_VADDR(pvo) & HPT_SP_MASK) == 0, 1025 ("%s: va %#jx unaligned", __func__, (uintmax_t)PVO_VADDR(pvo))); 1026 1027 rw_rlock(&moea64_eviction_lock); 1028 refchg = moea64_pte_unset_sp_locked(pvo); 1029 moea64_pte_insert_sp_locked(pvo); 1030 rw_runlock(&moea64_eviction_lock); 1031 1032 return (refchg); 1033 } 1034