1 /*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 /*- 37 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 38 * Copyright (C) 1995, 1996 TooLs GmbH. 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by TooLs GmbH. 52 * 4. The name of TooLs GmbH may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 67 */ 68 /*- 69 * Copyright (C) 2001 Benno Rice. 70 * All rights reserved. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 91 */ 92 93 #include <sys/cdefs.h> 94 __FBSDID("$FreeBSD$"); 95 96 /* 97 * Native 64-bit page table operations for running without a hypervisor. 98 */ 99 100 #include <sys/param.h> 101 #include <sys/kernel.h> 102 #include <sys/ktr.h> 103 #include <sys/lock.h> 104 #include <sys/mutex.h> 105 #include <sys/proc.h> 106 #include <sys/sched.h> 107 #include <sys/sysctl.h> 108 #include <sys/systm.h> 109 110 #include <sys/kdb.h> 111 112 #include <vm/vm.h> 113 #include <vm/vm_param.h> 114 #include <vm/vm_kern.h> 115 #include <vm/vm_page.h> 116 #include <vm/vm_map.h> 117 #include <vm/vm_object.h> 118 #include <vm/vm_extern.h> 119 #include <vm/vm_pageout.h> 120 #include <vm/vm_pager.h> 121 122 #include <machine/md_var.h> 123 #include <machine/mmuvar.h> 124 125 #include "mmu_oea64.h" 126 #include "mmu_if.h" 127 #include "moea64_if.h" 128 129 #define PTESYNC() __asm __volatile("ptesync"); 130 #define TLBSYNC() __asm __volatile("tlbsync; ptesync"); 131 #define SYNC() __asm __volatile("sync"); 132 #define EIEIO() __asm __volatile("eieio"); 133 134 #define VSID_HASH_MASK 0x0000007fffffffffULL 135 136 static __inline void 137 TLBIE(uint64_t vpn) { 138 #ifndef __powerpc64__ 139 register_t vpn_hi, vpn_lo; 140 register_t msr; 141 register_t scratch, intr; 142 #endif 143 144 static volatile u_int tlbie_lock = 0; 145 146 vpn <<= ADDR_PIDX_SHFT; 147 vpn &= ~(0xffffULL << 48); 148 149 /* Hobo spinlock: we need stronger guarantees than mutexes provide */ 150 while (!atomic_cmpset_int(&tlbie_lock, 0, 1)); 151 isync(); /* Flush instruction queue once lock acquired */ 152 153 #ifdef __powerpc64__ 154 __asm __volatile("tlbie %0" :: "r"(vpn) : "memory"); 155 __asm __volatile("eieio; tlbsync; ptesync" ::: "memory"); 156 #else 157 vpn_hi = (uint32_t)(vpn >> 32); 158 vpn_lo = (uint32_t)vpn; 159 160 intr = intr_disable(); 161 __asm __volatile("\ 162 mfmsr %0; \ 163 mr %1, %0; \ 164 insrdi %1,%5,1,0; \ 165 mtmsrd %1; isync; \ 166 \ 167 sld %1,%2,%4; \ 168 or %1,%1,%3; \ 169 tlbie %1; \ 170 \ 171 mtmsrd %0; isync; \ 172 eieio; \ 173 tlbsync; \ 174 ptesync;" 175 : "=r"(msr), "=r"(scratch) : "r"(vpn_hi), "r"(vpn_lo), "r"(32), "r"(1) 176 : "memory"); 177 intr_restore(intr); 178 #endif 179 180 /* No barriers or special ops -- taken care of by ptesync above */ 181 tlbie_lock = 0; 182 } 183 184 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR) 185 #define ENABLE_TRANS(msr) mtmsr(msr) 186 187 /* 188 * PTEG data. 189 */ 190 static struct lpteg *moea64_pteg_table; 191 192 /* 193 * PTE calls. 194 */ 195 static int moea64_pte_insert_native(mmu_t, u_int, struct lpte *); 196 static uintptr_t moea64_pvo_to_pte_native(mmu_t, const struct pvo_entry *); 197 static void moea64_pte_synch_native(mmu_t, uintptr_t pt, 198 struct lpte *pvo_pt); 199 static void moea64_pte_clear_native(mmu_t, uintptr_t pt, 200 struct lpte *pvo_pt, uint64_t vpn, uint64_t ptebit); 201 static void moea64_pte_change_native(mmu_t, uintptr_t pt, 202 struct lpte *pvo_pt, uint64_t vpn); 203 static void moea64_pte_unset_native(mmu_t mmu, uintptr_t pt, 204 struct lpte *pvo_pt, uint64_t vpn); 205 206 /* 207 * Utility routines. 208 */ 209 static void moea64_bootstrap_native(mmu_t mmup, 210 vm_offset_t kernelstart, vm_offset_t kernelend); 211 static void moea64_cpu_bootstrap_native(mmu_t, int ap); 212 static void tlbia(void); 213 214 static mmu_method_t moea64_native_methods[] = { 215 /* Internal interfaces */ 216 MMUMETHOD(mmu_bootstrap, moea64_bootstrap_native), 217 MMUMETHOD(mmu_cpu_bootstrap, moea64_cpu_bootstrap_native), 218 219 MMUMETHOD(moea64_pte_synch, moea64_pte_synch_native), 220 MMUMETHOD(moea64_pte_clear, moea64_pte_clear_native), 221 MMUMETHOD(moea64_pte_unset, moea64_pte_unset_native), 222 MMUMETHOD(moea64_pte_change, moea64_pte_change_native), 223 MMUMETHOD(moea64_pte_insert, moea64_pte_insert_native), 224 MMUMETHOD(moea64_pvo_to_pte, moea64_pvo_to_pte_native), 225 226 { 0, 0 } 227 }; 228 229 MMU_DEF_INHERIT(oea64_mmu_native, MMU_TYPE_G5, moea64_native_methods, 230 0, oea64_mmu); 231 232 static __inline u_int 233 va_to_pteg(uint64_t vsid, vm_offset_t addr, int large) 234 { 235 uint64_t hash; 236 int shift; 237 238 shift = large ? moea64_large_page_shift : ADDR_PIDX_SHFT; 239 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)addr & ADDR_PIDX) >> 240 shift); 241 return (hash & moea64_pteg_mask); 242 } 243 244 static void 245 moea64_pte_synch_native(mmu_t mmu, uintptr_t pt_cookie, struct lpte *pvo_pt) 246 { 247 struct lpte *pt = (struct lpte *)pt_cookie; 248 249 pvo_pt->pte_lo |= pt->pte_lo & (LPTE_REF | LPTE_CHG); 250 } 251 252 static void 253 moea64_pte_clear_native(mmu_t mmu, uintptr_t pt_cookie, struct lpte *pvo_pt, 254 uint64_t vpn, uint64_t ptebit) 255 { 256 struct lpte *pt = (struct lpte *)pt_cookie; 257 258 /* 259 * As shown in Section 7.6.3.2.3 260 */ 261 pt->pte_lo &= ~ptebit; 262 critical_enter(); 263 TLBIE(vpn); 264 critical_exit(); 265 } 266 267 static void 268 moea64_pte_set_native(struct lpte *pt, struct lpte *pvo_pt) 269 { 270 271 pvo_pt->pte_hi |= LPTE_VALID; 272 273 /* 274 * Update the PTE as defined in section 7.6.3.1. 275 * Note that the REF/CHG bits are from pvo_pt and thus should have 276 * been saved so this routine can restore them (if desired). 277 */ 278 pt->pte_lo = pvo_pt->pte_lo; 279 EIEIO(); 280 pt->pte_hi = pvo_pt->pte_hi; 281 PTESYNC(); 282 283 /* Keep statistics for unlocked pages */ 284 if (!(pvo_pt->pte_hi & LPTE_LOCKED)) 285 moea64_pte_valid++; 286 } 287 288 static void 289 moea64_pte_unset_native(mmu_t mmu, uintptr_t pt_cookie, struct lpte *pvo_pt, 290 uint64_t vpn) 291 { 292 struct lpte *pt = (struct lpte *)pt_cookie; 293 294 /* 295 * Invalidate the pte. 296 */ 297 isync(); 298 critical_enter(); 299 pvo_pt->pte_hi &= ~LPTE_VALID; 300 pt->pte_hi &= ~LPTE_VALID; 301 PTESYNC(); 302 TLBIE(vpn); 303 critical_exit(); 304 305 /* 306 * Save the reg & chg bits. 307 */ 308 moea64_pte_synch_native(mmu, pt_cookie, pvo_pt); 309 310 /* Keep statistics for unlocked pages */ 311 if (!(pvo_pt->pte_hi & LPTE_LOCKED)) 312 moea64_pte_valid--; 313 } 314 315 static void 316 moea64_pte_change_native(mmu_t mmu, uintptr_t pt, struct lpte *pvo_pt, 317 uint64_t vpn) 318 { 319 320 /* 321 * Invalidate the PTE 322 */ 323 moea64_pte_unset_native(mmu, pt, pvo_pt, vpn); 324 moea64_pte_set_native((struct lpte *)pt, pvo_pt); 325 } 326 327 static void 328 moea64_cpu_bootstrap_native(mmu_t mmup, int ap) 329 { 330 int i = 0; 331 #ifdef __powerpc64__ 332 struct slb *slb = PCPU_GET(slb); 333 register_t seg0; 334 #endif 335 336 /* 337 * Initialize segment registers and MMU 338 */ 339 340 mtmsr(mfmsr() & ~PSL_DR & ~PSL_IR); 341 342 /* 343 * Install kernel SLB entries 344 */ 345 346 #ifdef __powerpc64__ 347 __asm __volatile ("slbia"); 348 __asm __volatile ("slbmfee %0,%1; slbie %0;" : "=r"(seg0) : 349 "r"(0)); 350 351 for (i = 0; i < 64; i++) { 352 if (!(slb[i].slbe & SLBE_VALID)) 353 continue; 354 355 __asm __volatile ("slbmte %0, %1" :: 356 "r"(slb[i].slbv), "r"(slb[i].slbe)); 357 } 358 #else 359 for (i = 0; i < 16; i++) 360 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]); 361 #endif 362 363 /* 364 * Install page table 365 */ 366 367 __asm __volatile ("ptesync; mtsdr1 %0; isync" 368 :: "r"((uintptr_t)moea64_pteg_table 369 | (uintptr_t)(flsl(moea64_pteg_mask >> 11)))); 370 tlbia(); 371 } 372 373 static void 374 moea64_bootstrap_native(mmu_t mmup, vm_offset_t kernelstart, 375 vm_offset_t kernelend) 376 { 377 vm_size_t size; 378 vm_offset_t off; 379 vm_paddr_t pa; 380 register_t msr; 381 382 moea64_early_bootstrap(mmup, kernelstart, kernelend); 383 384 /* 385 * Allocate PTEG table. 386 */ 387 388 size = moea64_pteg_count * sizeof(struct lpteg); 389 CTR2(KTR_PMAP, "moea64_bootstrap: %d PTEGs, %d bytes", 390 moea64_pteg_count, size); 391 392 /* 393 * We now need to allocate memory. This memory, to be allocated, 394 * has to reside in a page table. The page table we are about to 395 * allocate. We don't have BAT. So drop to data real mode for a minute 396 * as a measure of last resort. We do this a couple times. 397 */ 398 399 moea64_pteg_table = (struct lpteg *)moea64_bootstrap_alloc(size, size); 400 DISABLE_TRANS(msr); 401 bzero((void *)moea64_pteg_table, moea64_pteg_count * sizeof(struct lpteg)); 402 ENABLE_TRANS(msr); 403 404 CTR1(KTR_PMAP, "moea64_bootstrap: PTEG table at %p", moea64_pteg_table); 405 406 moea64_mid_bootstrap(mmup, kernelstart, kernelend); 407 408 /* 409 * Add a mapping for the page table itself if there is no direct map. 410 */ 411 if (!hw_direct_map) { 412 size = moea64_pteg_count * sizeof(struct lpteg); 413 off = (vm_offset_t)(moea64_pteg_table); 414 DISABLE_TRANS(msr); 415 for (pa = off; pa < off + size; pa += PAGE_SIZE) 416 pmap_kenter(pa, pa); 417 ENABLE_TRANS(msr); 418 } 419 420 /* Bring up virtual memory */ 421 moea64_late_bootstrap(mmup, kernelstart, kernelend); 422 } 423 424 static void 425 tlbia(void) 426 { 427 vm_offset_t i; 428 #ifndef __powerpc64__ 429 register_t msr, scratch; 430 #endif 431 432 TLBSYNC(); 433 434 for (i = 0; i < 0xFF000; i += 0x00001000) { 435 #ifdef __powerpc64__ 436 __asm __volatile("tlbiel %0" :: "r"(i)); 437 #else 438 __asm __volatile("\ 439 mfmsr %0; \ 440 mr %1, %0; \ 441 insrdi %1,%3,1,0; \ 442 mtmsrd %1; \ 443 isync; \ 444 \ 445 tlbiel %2; \ 446 \ 447 mtmsrd %0; \ 448 isync;" 449 : "=r"(msr), "=r"(scratch) : "r"(i), "r"(1)); 450 #endif 451 } 452 453 EIEIO(); 454 TLBSYNC(); 455 } 456 457 static uintptr_t 458 moea64_pvo_to_pte_native(mmu_t mmu, const struct pvo_entry *pvo) 459 { 460 struct lpte *pt; 461 int pteidx, ptegidx; 462 uint64_t vsid; 463 464 /* If the PTEG index is not set, then there is no page table entry */ 465 if (!PVO_PTEGIDX_ISSET(pvo)) 466 return (-1); 467 468 /* 469 * Calculate the ptegidx 470 */ 471 vsid = PVO_VSID(pvo); 472 ptegidx = va_to_pteg(vsid, PVO_VADDR(pvo), 473 pvo->pvo_vaddr & PVO_LARGE); 474 475 /* 476 * We can find the actual pte entry without searching by grabbing 477 * the PTEG index from 3 unused bits in pvo_vaddr and by 478 * noticing the HID bit. 479 */ 480 if (pvo->pvo_pte.lpte.pte_hi & LPTE_HID) 481 ptegidx ^= moea64_pteg_mask; 482 483 pteidx = (ptegidx << 3) | PVO_PTEGIDX_GET(pvo); 484 485 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) && 486 !PVO_PTEGIDX_ISSET(pvo)) { 487 panic("moea64_pvo_to_pte: pvo %p has valid pte in pvo but no " 488 "valid pte index", pvo); 489 } 490 491 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0 && 492 PVO_PTEGIDX_ISSET(pvo)) { 493 panic("moea64_pvo_to_pte: pvo %p has valid pte index in pvo " 494 "pvo but no valid pte", pvo); 495 } 496 497 pt = &moea64_pteg_table[pteidx >> 3].pt[pteidx & 7]; 498 if ((pt->pte_hi ^ (pvo->pvo_pte.lpte.pte_hi & ~LPTE_VALID)) == 499 LPTE_VALID) { 500 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0) { 501 panic("moea64_pvo_to_pte: pvo %p has valid pte in " 502 "moea64_pteg_table %p but invalid in pvo", pvo, pt); 503 } 504 505 if (((pt->pte_lo ^ pvo->pvo_pte.lpte.pte_lo) & 506 ~(LPTE_M|LPTE_CHG|LPTE_REF)) != 0) { 507 panic("moea64_pvo_to_pte: pvo %p pte does not match " 508 "pte %p in moea64_pteg_table difference is %#x", 509 pvo, pt, 510 (uint32_t)(pt->pte_lo ^ pvo->pvo_pte.lpte.pte_lo)); 511 } 512 513 return ((uintptr_t)pt); 514 } 515 516 if (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) { 517 panic("moea64_pvo_to_pte: pvo %p has invalid pte %p in " 518 "moea64_pteg_table but valid in pvo", pvo, pt); 519 } 520 521 return (-1); 522 } 523 524 static __inline int 525 moea64_pte_spillable_ident(u_int ptegidx) 526 { 527 struct lpte *pt; 528 int i, j, k; 529 530 /* Start at a random slot */ 531 i = mftb() % 8; 532 k = -1; 533 for (j = 0; j < 8; j++) { 534 pt = &moea64_pteg_table[ptegidx].pt[(i + j) % 8]; 535 if (pt->pte_hi & (LPTE_LOCKED | LPTE_WIRED)) 536 continue; 537 538 /* This is a candidate, so remember it */ 539 k = (i + j) % 8; 540 541 /* Try to get a page that has not been used lately */ 542 if (!(pt->pte_lo & LPTE_REF)) 543 return (k); 544 } 545 546 return (k); 547 } 548 549 static int 550 moea64_pte_insert_native(mmu_t mmu, u_int ptegidx, struct lpte *pvo_pt) 551 { 552 struct lpte *pt; 553 struct pvo_entry *pvo; 554 u_int pteg_bktidx; 555 int i; 556 557 /* 558 * First try primary hash. 559 */ 560 pteg_bktidx = ptegidx; 561 for (pt = moea64_pteg_table[pteg_bktidx].pt, i = 0; i < 8; i++, pt++) { 562 if ((pt->pte_hi & (LPTE_VALID | LPTE_LOCKED)) == 0) { 563 pvo_pt->pte_hi &= ~LPTE_HID; 564 moea64_pte_set_native(pt, pvo_pt); 565 return (i); 566 } 567 } 568 569 /* 570 * Now try secondary hash. 571 */ 572 pteg_bktidx ^= moea64_pteg_mask; 573 for (pt = moea64_pteg_table[pteg_bktidx].pt, i = 0; i < 8; i++, pt++) { 574 if ((pt->pte_hi & (LPTE_VALID | LPTE_LOCKED)) == 0) { 575 pvo_pt->pte_hi |= LPTE_HID; 576 moea64_pte_set_native(pt, pvo_pt); 577 return (i); 578 } 579 } 580 581 /* 582 * Out of luck. Find a PTE to sacrifice. 583 */ 584 pteg_bktidx = ptegidx; 585 i = moea64_pte_spillable_ident(pteg_bktidx); 586 if (i < 0) { 587 pteg_bktidx ^= moea64_pteg_mask; 588 i = moea64_pte_spillable_ident(pteg_bktidx); 589 } 590 591 if (i < 0) { 592 /* No freeable slots in either PTEG? We're hosed. */ 593 panic("moea64_pte_insert: overflow"); 594 return (-1); 595 } 596 597 if (pteg_bktidx == ptegidx) 598 pvo_pt->pte_hi &= ~LPTE_HID; 599 else 600 pvo_pt->pte_hi |= LPTE_HID; 601 602 /* 603 * Synchronize the sacrifice PTE with its PVO, then mark both 604 * invalid. The PVO will be reused when/if the VM system comes 605 * here after a fault. 606 */ 607 pt = &moea64_pteg_table[pteg_bktidx].pt[i]; 608 609 if (pt->pte_hi & LPTE_HID) 610 pteg_bktidx ^= moea64_pteg_mask; /* PTEs indexed by primary */ 611 612 LIST_FOREACH(pvo, &moea64_pvo_table[pteg_bktidx], pvo_olink) { 613 if (pvo->pvo_pte.lpte.pte_hi == pt->pte_hi) { 614 KASSERT(pvo->pvo_pte.lpte.pte_hi & LPTE_VALID, 615 ("Invalid PVO for valid PTE!")); 616 moea64_pte_unset_native(mmu, (uintptr_t)pt, 617 &pvo->pvo_pte.lpte, pvo->pvo_vpn); 618 PVO_PTEGIDX_CLR(pvo); 619 moea64_pte_overflow++; 620 break; 621 } 622 } 623 624 KASSERT(pvo->pvo_pte.lpte.pte_hi == pt->pte_hi, 625 ("Unable to find PVO for spilled PTE")); 626 627 /* 628 * Set the new PTE. 629 */ 630 moea64_pte_set_native(pt, pvo_pt); 631 632 return (i); 633 } 634 635