1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD AND 4-Clause-BSD 3 * 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /*- 32 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 33 * Copyright (C) 1995, 1996 TooLs GmbH. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by TooLs GmbH. 47 * 4. The name of TooLs GmbH may not be used to endorse or promote products 48 * derived from this software without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 51 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 52 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 53 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 54 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 55 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 56 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 57 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 58 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 59 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60 * 61 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 62 */ 63 /*- 64 * Copyright (C) 2001 Benno Rice. 65 * All rights reserved. 66 * 67 * Redistribution and use in source and binary forms, with or without 68 * modification, are permitted provided that the following conditions 69 * are met: 70 * 1. Redistributions of source code must retain the above copyright 71 * notice, this list of conditions and the following disclaimer. 72 * 2. Redistributions in binary form must reproduce the above copyright 73 * notice, this list of conditions and the following disclaimer in the 74 * documentation and/or other materials provided with the distribution. 75 * 76 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 77 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 78 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 79 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 80 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 81 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 82 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 83 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 84 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 85 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 86 */ 87 88 #include <sys/cdefs.h> 89 __FBSDID("$FreeBSD$"); 90 91 /* 92 * Native 64-bit page table operations for running without a hypervisor. 93 */ 94 95 #include <sys/param.h> 96 #include <sys/kernel.h> 97 #include <sys/ktr.h> 98 #include <sys/lock.h> 99 #include <sys/mutex.h> 100 #include <sys/proc.h> 101 #include <sys/sched.h> 102 #include <sys/sysctl.h> 103 #include <sys/systm.h> 104 #include <sys/rwlock.h> 105 #include <sys/endian.h> 106 107 #include <sys/kdb.h> 108 109 #include <vm/vm.h> 110 #include <vm/vm_param.h> 111 #include <vm/vm_kern.h> 112 #include <vm/vm_page.h> 113 #include <vm/vm_map.h> 114 #include <vm/vm_object.h> 115 #include <vm/vm_extern.h> 116 #include <vm/vm_pageout.h> 117 118 #include <machine/cpu.h> 119 #include <machine/hid.h> 120 #include <machine/md_var.h> 121 #include <machine/mmuvar.h> 122 123 #include "mmu_oea64.h" 124 #include "mmu_if.h" 125 #include "moea64_if.h" 126 127 #define PTESYNC() __asm __volatile("ptesync"); 128 #define TLBSYNC() __asm __volatile("tlbsync; ptesync"); 129 #define SYNC() __asm __volatile("sync"); 130 #define EIEIO() __asm __volatile("eieio"); 131 132 #define VSID_HASH_MASK 0x0000007fffffffffULL 133 134 /* POWER9 only permits a 64k partition table size. */ 135 #define PART_SIZE 0x10000 136 137 static bool moea64_crop_tlbie; 138 static bool moea64_need_lock; 139 140 static __inline void 141 TLBIE(uint64_t vpn) { 142 #ifndef __powerpc64__ 143 register_t vpn_hi, vpn_lo; 144 register_t msr; 145 register_t scratch, intr; 146 #endif 147 148 static volatile u_int tlbie_lock = 0; 149 bool need_lock = moea64_need_lock; 150 151 vpn <<= ADDR_PIDX_SHFT; 152 153 /* Hobo spinlock: we need stronger guarantees than mutexes provide */ 154 if (need_lock) { 155 while (!atomic_cmpset_int(&tlbie_lock, 0, 1)); 156 isync(); /* Flush instruction queue once lock acquired */ 157 158 if (moea64_crop_tlbie) 159 vpn &= ~(0xffffULL << 48); 160 } 161 162 #ifdef __powerpc64__ 163 /* 164 * Explicitly clobber r0. The tlbie instruction has two forms: an old 165 * one used by PowerISA 2.03 and prior, and a newer one used by PowerISA 166 * 2.06 (maybe 2.05?) and later. We need to support both, and it just 167 * so happens that since we use 4k pages we can simply zero out r0, and 168 * clobber it, and the assembler will interpret the single-operand form 169 * of tlbie as having RB set, and everything else as 0. The RS operand 170 * in the newer form is in the same position as the L(page size) bit of 171 * the old form, so a slong as RS is 0, we're good on both sides. 172 */ 173 __asm __volatile("li 0, 0 \n tlbie %0" :: "r"(vpn) : "r0", "memory"); 174 __asm __volatile("eieio; tlbsync; ptesync" ::: "memory"); 175 #else 176 vpn_hi = (uint32_t)(vpn >> 32); 177 vpn_lo = (uint32_t)vpn; 178 179 intr = intr_disable(); 180 __asm __volatile("\ 181 mfmsr %0; \ 182 mr %1, %0; \ 183 insrdi %1,%5,1,0; \ 184 mtmsrd %1; isync; \ 185 \ 186 sld %1,%2,%4; \ 187 or %1,%1,%3; \ 188 tlbie %1; \ 189 \ 190 mtmsrd %0; isync; \ 191 eieio; \ 192 tlbsync; \ 193 ptesync;" 194 : "=r"(msr), "=r"(scratch) : "r"(vpn_hi), "r"(vpn_lo), "r"(32), "r"(1) 195 : "memory"); 196 intr_restore(intr); 197 #endif 198 199 /* No barriers or special ops -- taken care of by ptesync above */ 200 if (need_lock) 201 tlbie_lock = 0; 202 } 203 204 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR) 205 #define ENABLE_TRANS(msr) mtmsr(msr) 206 207 /* 208 * PTEG data. 209 */ 210 static volatile struct lpte *moea64_pteg_table; 211 static struct rwlock moea64_eviction_lock; 212 213 static volatile struct pate *moea64_part_table; 214 215 /* 216 * PTE calls. 217 */ 218 static int moea64_pte_insert_native(mmu_t, struct pvo_entry *); 219 static int64_t moea64_pte_synch_native(mmu_t, struct pvo_entry *); 220 static int64_t moea64_pte_clear_native(mmu_t, struct pvo_entry *, uint64_t); 221 static int64_t moea64_pte_replace_native(mmu_t, struct pvo_entry *, int); 222 static int64_t moea64_pte_unset_native(mmu_t mmu, struct pvo_entry *); 223 224 /* 225 * Utility routines. 226 */ 227 static void moea64_bootstrap_native(mmu_t mmup, 228 vm_offset_t kernelstart, vm_offset_t kernelend); 229 static void moea64_cpu_bootstrap_native(mmu_t, int ap); 230 static void tlbia(void); 231 232 static mmu_method_t moea64_native_methods[] = { 233 /* Internal interfaces */ 234 MMUMETHOD(mmu_bootstrap, moea64_bootstrap_native), 235 MMUMETHOD(mmu_cpu_bootstrap, moea64_cpu_bootstrap_native), 236 237 MMUMETHOD(moea64_pte_synch, moea64_pte_synch_native), 238 MMUMETHOD(moea64_pte_clear, moea64_pte_clear_native), 239 MMUMETHOD(moea64_pte_unset, moea64_pte_unset_native), 240 MMUMETHOD(moea64_pte_replace, moea64_pte_replace_native), 241 MMUMETHOD(moea64_pte_insert, moea64_pte_insert_native), 242 243 { 0, 0 } 244 }; 245 246 MMU_DEF_INHERIT(oea64_mmu_native, MMU_TYPE_G5, moea64_native_methods, 247 0, oea64_mmu); 248 249 static int64_t 250 moea64_pte_synch_native(mmu_t mmu, struct pvo_entry *pvo) 251 { 252 volatile struct lpte *pt = moea64_pteg_table + pvo->pvo_pte.slot; 253 struct lpte properpt; 254 uint64_t ptelo; 255 256 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 257 258 moea64_pte_from_pvo(pvo, &properpt); 259 260 rw_rlock(&moea64_eviction_lock); 261 if ((be64toh(pt->pte_hi) & LPTE_AVPN_MASK) != 262 (properpt.pte_hi & LPTE_AVPN_MASK)) { 263 /* Evicted */ 264 rw_runlock(&moea64_eviction_lock); 265 return (-1); 266 } 267 268 PTESYNC(); 269 ptelo = be64toh(pt->pte_lo); 270 271 rw_runlock(&moea64_eviction_lock); 272 273 return (ptelo & (LPTE_REF | LPTE_CHG)); 274 } 275 276 static int64_t 277 moea64_pte_clear_native(mmu_t mmu, struct pvo_entry *pvo, uint64_t ptebit) 278 { 279 volatile struct lpte *pt = moea64_pteg_table + pvo->pvo_pte.slot; 280 struct lpte properpt; 281 uint64_t ptelo; 282 283 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 284 285 moea64_pte_from_pvo(pvo, &properpt); 286 287 rw_rlock(&moea64_eviction_lock); 288 if ((be64toh(pt->pte_hi) & LPTE_AVPN_MASK) != 289 (properpt.pte_hi & LPTE_AVPN_MASK)) { 290 /* Evicted */ 291 rw_runlock(&moea64_eviction_lock); 292 return (-1); 293 } 294 295 if (ptebit == LPTE_REF) { 296 /* See "Resetting the Reference Bit" in arch manual */ 297 PTESYNC(); 298 /* 2-step here safe: precision is not guaranteed */ 299 ptelo = be64toh(pt->pte_lo); 300 301 /* One-byte store to avoid touching the C bit */ 302 ((volatile uint8_t *)(&pt->pte_lo))[6] = 303 #if BYTE_ORDER == BIG_ENDIAN 304 ((uint8_t *)(&properpt.pte_lo))[6]; 305 #else 306 ((uint8_t *)(&properpt.pte_lo))[1]; 307 #endif 308 rw_runlock(&moea64_eviction_lock); 309 310 critical_enter(); 311 TLBIE(pvo->pvo_vpn); 312 critical_exit(); 313 } else { 314 rw_runlock(&moea64_eviction_lock); 315 ptelo = moea64_pte_unset_native(mmu, pvo); 316 moea64_pte_insert_native(mmu, pvo); 317 } 318 319 return (ptelo & (LPTE_REF | LPTE_CHG)); 320 } 321 322 static int64_t 323 moea64_pte_unset_native(mmu_t mmu, struct pvo_entry *pvo) 324 { 325 volatile struct lpte *pt = moea64_pteg_table + pvo->pvo_pte.slot; 326 struct lpte properpt; 327 uint64_t ptelo; 328 329 moea64_pte_from_pvo(pvo, &properpt); 330 331 rw_rlock(&moea64_eviction_lock); 332 if ((be64toh(pt->pte_hi & LPTE_AVPN_MASK)) != 333 (properpt.pte_hi & LPTE_AVPN_MASK)) { 334 /* Evicted */ 335 moea64_pte_overflow--; 336 rw_runlock(&moea64_eviction_lock); 337 return (-1); 338 } 339 340 /* 341 * Invalidate the pte, briefly locking it to collect RC bits. No 342 * atomics needed since this is protected against eviction by the lock. 343 */ 344 isync(); 345 critical_enter(); 346 pt->pte_hi = be64toh((pt->pte_hi & ~LPTE_VALID) | LPTE_LOCKED); 347 PTESYNC(); 348 TLBIE(pvo->pvo_vpn); 349 ptelo = be64toh(pt->pte_lo); 350 *((volatile int32_t *)(&pt->pte_hi) + 1) = 0; /* Release lock */ 351 critical_exit(); 352 rw_runlock(&moea64_eviction_lock); 353 354 /* Keep statistics */ 355 moea64_pte_valid--; 356 357 return (ptelo & (LPTE_CHG | LPTE_REF)); 358 } 359 360 static int64_t 361 moea64_pte_replace_native(mmu_t mmu, struct pvo_entry *pvo, int flags) 362 { 363 volatile struct lpte *pt = moea64_pteg_table + pvo->pvo_pte.slot; 364 struct lpte properpt; 365 int64_t ptelo; 366 367 if (flags == 0) { 368 /* Just some software bits changing. */ 369 moea64_pte_from_pvo(pvo, &properpt); 370 371 rw_rlock(&moea64_eviction_lock); 372 if ((be64toh(pt->pte_hi) & LPTE_AVPN_MASK) != 373 (properpt.pte_hi & LPTE_AVPN_MASK)) { 374 rw_runlock(&moea64_eviction_lock); 375 return (-1); 376 } 377 pt->pte_hi = htobe64(properpt.pte_hi); 378 ptelo = be64toh(pt->pte_lo); 379 rw_runlock(&moea64_eviction_lock); 380 } else { 381 /* Otherwise, need reinsertion and deletion */ 382 ptelo = moea64_pte_unset_native(mmu, pvo); 383 moea64_pte_insert_native(mmu, pvo); 384 } 385 386 return (ptelo); 387 } 388 389 static void 390 moea64_cpu_bootstrap_native(mmu_t mmup, int ap) 391 { 392 int i = 0; 393 #ifdef __powerpc64__ 394 struct slb *slb = PCPU_GET(aim.slb); 395 register_t seg0; 396 #endif 397 398 /* 399 * Initialize segment registers and MMU 400 */ 401 402 mtmsr(mfmsr() & ~PSL_DR & ~PSL_IR); 403 404 switch(mfpvr() >> 16) { 405 case IBMPOWER9: 406 mtspr(SPR_HID0, mfspr(SPR_HID0) & ~HID0_RADIX); 407 break; 408 } 409 410 /* 411 * Install kernel SLB entries 412 */ 413 414 #ifdef __powerpc64__ 415 __asm __volatile ("slbia"); 416 __asm __volatile ("slbmfee %0,%1; slbie %0;" : "=r"(seg0) : 417 "r"(0)); 418 419 for (i = 0; i < n_slbs; i++) { 420 if (!(slb[i].slbe & SLBE_VALID)) 421 continue; 422 423 __asm __volatile ("slbmte %0, %1" :: 424 "r"(slb[i].slbv), "r"(slb[i].slbe)); 425 } 426 #else 427 for (i = 0; i < 16; i++) 428 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]); 429 #endif 430 431 /* 432 * Install page table 433 */ 434 435 if (cpu_features2 & PPC_FEATURE2_ARCH_3_00) 436 mtspr(SPR_PTCR, 437 ((uintptr_t)moea64_part_table & ~DMAP_BASE_ADDRESS) | 438 flsl((PART_SIZE >> 12) - 1)); 439 else 440 __asm __volatile ("ptesync; mtsdr1 %0; isync" 441 :: "r"(((uintptr_t)moea64_pteg_table & ~DMAP_BASE_ADDRESS) 442 | (uintptr_t)(flsl(moea64_pteg_mask >> 11)))); 443 tlbia(); 444 } 445 446 static void 447 moea64_bootstrap_native(mmu_t mmup, vm_offset_t kernelstart, 448 vm_offset_t kernelend) 449 { 450 vm_size_t size; 451 vm_offset_t off; 452 vm_paddr_t pa; 453 register_t msr; 454 455 moea64_early_bootstrap(mmup, kernelstart, kernelend); 456 457 switch (mfpvr() >> 16) { 458 case IBMPOWER9: 459 moea64_need_lock = false; 460 break; 461 case IBMPOWER4: 462 case IBMPOWER4PLUS: 463 case IBM970: 464 case IBM970FX: 465 case IBM970GX: 466 case IBM970MP: 467 moea64_crop_tlbie = true; 468 default: 469 moea64_need_lock = true; 470 } 471 /* 472 * Allocate PTEG table. 473 */ 474 475 size = moea64_pteg_count * sizeof(struct lpteg); 476 CTR2(KTR_PMAP, "moea64_bootstrap: %lu PTEGs, %lu bytes", 477 moea64_pteg_count, size); 478 rw_init(&moea64_eviction_lock, "pte eviction"); 479 480 /* 481 * We now need to allocate memory. This memory, to be allocated, 482 * has to reside in a page table. The page table we are about to 483 * allocate. We don't have BAT. So drop to data real mode for a minute 484 * as a measure of last resort. We do this a couple times. 485 */ 486 /* 487 * PTEG table must be aligned on a 256k boundary, but can be placed 488 * anywhere with that alignment on POWER ISA 3+ systems. On earlier 489 * systems, offset addition is done by the CPU with bitwise OR rather 490 * than addition, so the table must also be aligned on a boundary of 491 * its own size. Pick the larger of the two, which works on all 492 * systems. 493 */ 494 moea64_pteg_table = (struct lpte *)moea64_bootstrap_alloc(size, 495 MAX(256*1024, size)); 496 if (hw_direct_map) 497 moea64_pteg_table = 498 (struct lpte *)PHYS_TO_DMAP((vm_offset_t)moea64_pteg_table); 499 /* Allocate partition table (ISA 3.0). */ 500 if (cpu_features2 & PPC_FEATURE2_ARCH_3_00) { 501 moea64_part_table = 502 (struct pate *)moea64_bootstrap_alloc(PART_SIZE, PART_SIZE); 503 if (hw_direct_map) 504 moea64_part_table = 505 (struct pate *)PHYS_TO_DMAP((vm_offset_t)moea64_part_table); 506 } 507 DISABLE_TRANS(msr); 508 bzero(__DEVOLATILE(void *, moea64_pteg_table), moea64_pteg_count * 509 sizeof(struct lpteg)); 510 if (cpu_features2 & PPC_FEATURE2_ARCH_3_00) { 511 bzero(__DEVOLATILE(void *, moea64_part_table), PART_SIZE); 512 moea64_part_table[0].pagetab = 513 (DMAP_TO_PHYS((vm_offset_t)moea64_pteg_table)) | 514 (uintptr_t)(flsl((moea64_pteg_count - 1) >> 11)); 515 } 516 ENABLE_TRANS(msr); 517 518 CTR1(KTR_PMAP, "moea64_bootstrap: PTEG table at %p", moea64_pteg_table); 519 520 moea64_mid_bootstrap(mmup, kernelstart, kernelend); 521 522 /* 523 * Add a mapping for the page table itself if there is no direct map. 524 */ 525 if (!hw_direct_map) { 526 size = moea64_pteg_count * sizeof(struct lpteg); 527 off = (vm_offset_t)(moea64_pteg_table); 528 DISABLE_TRANS(msr); 529 for (pa = off; pa < off + size; pa += PAGE_SIZE) 530 pmap_kenter(pa, pa); 531 ENABLE_TRANS(msr); 532 } 533 534 /* Bring up virtual memory */ 535 moea64_late_bootstrap(mmup, kernelstart, kernelend); 536 } 537 538 static void 539 tlbia(void) 540 { 541 vm_offset_t i; 542 #ifndef __powerpc64__ 543 register_t msr, scratch; 544 #endif 545 546 i = 0xc00; /* IS = 11 */ 547 switch (mfpvr() >> 16) { 548 case IBM970: 549 case IBM970FX: 550 case IBM970MP: 551 case IBM970GX: 552 case IBMPOWER4: 553 case IBMPOWER4PLUS: 554 case IBMPOWER5: 555 case IBMPOWER5PLUS: 556 i = 0; /* IS not supported */ 557 break; 558 } 559 560 TLBSYNC(); 561 562 for (; i < 0x400000; i += 0x00001000) { 563 #ifdef __powerpc64__ 564 __asm __volatile("tlbiel %0" :: "r"(i)); 565 #else 566 __asm __volatile("\ 567 mfmsr %0; \ 568 mr %1, %0; \ 569 insrdi %1,%3,1,0; \ 570 mtmsrd %1; \ 571 isync; \ 572 \ 573 tlbiel %2; \ 574 \ 575 mtmsrd %0; \ 576 isync;" 577 : "=r"(msr), "=r"(scratch) : "r"(i), "r"(1)); 578 #endif 579 } 580 581 EIEIO(); 582 TLBSYNC(); 583 } 584 585 static int 586 atomic_pte_lock(volatile struct lpte *pte, uint64_t bitmask, uint64_t *oldhi) 587 { 588 int ret; 589 uint32_t oldhihalf; 590 591 /* 592 * Note: in principle, if just the locked bit were set here, we 593 * could avoid needing the eviction lock. However, eviction occurs 594 * so rarely that it isn't worth bothering about in practice. 595 */ 596 597 __asm __volatile ( 598 "1:\tlwarx %1, 0, %3\n\t" /* load old value */ 599 "and. %0,%1,%4\n\t" /* check if any bits set */ 600 "bne 2f\n\t" /* exit if any set */ 601 "stwcx. %5, 0, %3\n\t" /* attempt to store */ 602 "bne- 1b\n\t" /* spin if failed */ 603 "li %0, 1\n\t" /* success - retval = 1 */ 604 "b 3f\n\t" /* we've succeeded */ 605 "2:\n\t" 606 "stwcx. %1, 0, %3\n\t" /* clear reservation (74xx) */ 607 "li %0, 0\n\t" /* failure - retval = 0 */ 608 "3:\n\t" 609 : "=&r" (ret), "=&r"(oldhihalf), "=m" (pte->pte_hi) 610 : "r" ((volatile char *)&pte->pte_hi + 4), 611 "r" ((uint32_t)bitmask), "r" ((uint32_t)LPTE_LOCKED), 612 "m" (pte->pte_hi) 613 : "cr0", "cr1", "cr2", "memory"); 614 615 *oldhi = (pte->pte_hi & 0xffffffff00000000ULL) | oldhihalf; 616 617 return (ret); 618 } 619 620 static uintptr_t 621 moea64_insert_to_pteg_native(struct lpte *pvo_pt, uintptr_t slotbase, 622 uint64_t mask) 623 { 624 volatile struct lpte *pt; 625 uint64_t oldptehi, va; 626 uintptr_t k; 627 int i, j; 628 629 /* Start at a random slot */ 630 i = mftb() % 8; 631 for (j = 0; j < 8; j++) { 632 k = slotbase + (i + j) % 8; 633 pt = &moea64_pteg_table[k]; 634 /* Invalidate and seize lock only if no bits in mask set */ 635 if (atomic_pte_lock(pt, mask, &oldptehi)) /* Lock obtained */ 636 break; 637 } 638 639 if (j == 8) 640 return (-1); 641 642 if (oldptehi & LPTE_VALID) { 643 KASSERT(!(oldptehi & LPTE_WIRED), ("Unmapped wired entry")); 644 /* 645 * Need to invalidate old entry completely: see 646 * "Modifying a Page Table Entry". Need to reconstruct 647 * the virtual address for the outgoing entry to do that. 648 */ 649 va = oldptehi >> (ADDR_SR_SHFT - ADDR_API_SHFT64); 650 if (oldptehi & LPTE_HID) 651 va = (((k >> 3) ^ moea64_pteg_mask) ^ va) & 652 (ADDR_PIDX >> ADDR_PIDX_SHFT); 653 else 654 va = ((k >> 3) ^ va) & (ADDR_PIDX >> ADDR_PIDX_SHFT); 655 va |= (oldptehi & LPTE_AVPN_MASK) << 656 (ADDR_API_SHFT64 - ADDR_PIDX_SHFT); 657 PTESYNC(); 658 TLBIE(va); 659 moea64_pte_valid--; 660 moea64_pte_overflow++; 661 } 662 663 /* 664 * Update the PTE as per "Adding a Page Table Entry". Lock is released 665 * by setting the high doubleworld. 666 */ 667 pt->pte_lo = htobe64(pvo_pt->pte_lo); 668 EIEIO(); 669 pt->pte_hi = htobe64(pvo_pt->pte_hi); 670 PTESYNC(); 671 672 /* Keep statistics */ 673 moea64_pte_valid++; 674 675 return (k); 676 } 677 678 static int 679 moea64_pte_insert_native(mmu_t mmu, struct pvo_entry *pvo) 680 { 681 struct lpte insertpt; 682 uintptr_t slot; 683 684 /* Initialize PTE */ 685 moea64_pte_from_pvo(pvo, &insertpt); 686 687 /* Make sure further insertion is locked out during evictions */ 688 rw_rlock(&moea64_eviction_lock); 689 690 /* 691 * First try primary hash. 692 */ 693 pvo->pvo_pte.slot &= ~7ULL; /* Base slot address */ 694 slot = moea64_insert_to_pteg_native(&insertpt, pvo->pvo_pte.slot, 695 LPTE_VALID | LPTE_WIRED | LPTE_LOCKED); 696 if (slot != -1) { 697 rw_runlock(&moea64_eviction_lock); 698 pvo->pvo_pte.slot = slot; 699 return (0); 700 } 701 702 /* 703 * Now try secondary hash. 704 */ 705 pvo->pvo_vaddr ^= PVO_HID; 706 insertpt.pte_hi ^= LPTE_HID; 707 pvo->pvo_pte.slot ^= (moea64_pteg_mask << 3); 708 slot = moea64_insert_to_pteg_native(&insertpt, pvo->pvo_pte.slot, 709 LPTE_VALID | LPTE_WIRED | LPTE_LOCKED); 710 if (slot != -1) { 711 rw_runlock(&moea64_eviction_lock); 712 pvo->pvo_pte.slot = slot; 713 return (0); 714 } 715 716 /* 717 * Out of luck. Find a PTE to sacrifice. 718 */ 719 720 /* Lock out all insertions for a bit */ 721 if (!rw_try_upgrade(&moea64_eviction_lock)) { 722 rw_runlock(&moea64_eviction_lock); 723 rw_wlock(&moea64_eviction_lock); 724 } 725 726 slot = moea64_insert_to_pteg_native(&insertpt, pvo->pvo_pte.slot, 727 LPTE_WIRED | LPTE_LOCKED); 728 if (slot != -1) { 729 rw_wunlock(&moea64_eviction_lock); 730 pvo->pvo_pte.slot = slot; 731 return (0); 732 } 733 734 /* Try other hash table. Now we're getting desperate... */ 735 pvo->pvo_vaddr ^= PVO_HID; 736 insertpt.pte_hi ^= LPTE_HID; 737 pvo->pvo_pte.slot ^= (moea64_pteg_mask << 3); 738 slot = moea64_insert_to_pteg_native(&insertpt, pvo->pvo_pte.slot, 739 LPTE_WIRED | LPTE_LOCKED); 740 if (slot != -1) { 741 rw_wunlock(&moea64_eviction_lock); 742 pvo->pvo_pte.slot = slot; 743 return (0); 744 } 745 746 /* No freeable slots in either PTEG? We're hosed. */ 747 rw_wunlock(&moea64_eviction_lock); 748 panic("moea64_pte_insert: overflow"); 749 return (-1); 750 } 751 752