1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD AND 4-Clause-BSD 3 * 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /*- 32 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 33 * Copyright (C) 1995, 1996 TooLs GmbH. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by TooLs GmbH. 47 * 4. The name of TooLs GmbH may not be used to endorse or promote products 48 * derived from this software without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 51 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 52 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 53 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 54 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 55 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 56 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 57 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 58 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 59 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60 * 61 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 62 */ 63 /*- 64 * Copyright (C) 2001 Benno Rice. 65 * All rights reserved. 66 * 67 * Redistribution and use in source and binary forms, with or without 68 * modification, are permitted provided that the following conditions 69 * are met: 70 * 1. Redistributions of source code must retain the above copyright 71 * notice, this list of conditions and the following disclaimer. 72 * 2. Redistributions in binary form must reproduce the above copyright 73 * notice, this list of conditions and the following disclaimer in the 74 * documentation and/or other materials provided with the distribution. 75 * 76 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 77 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 78 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 79 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 80 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 81 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 82 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 83 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 84 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 85 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 86 */ 87 88 #include <sys/cdefs.h> 89 __FBSDID("$FreeBSD$"); 90 91 /* 92 * Native 64-bit page table operations for running without a hypervisor. 93 */ 94 95 #include <sys/param.h> 96 #include <sys/kernel.h> 97 #include <sys/ktr.h> 98 #include <sys/lock.h> 99 #include <sys/mutex.h> 100 #include <sys/proc.h> 101 #include <sys/sched.h> 102 #include <sys/sysctl.h> 103 #include <sys/systm.h> 104 #include <sys/rwlock.h> 105 #include <sys/endian.h> 106 107 #include <sys/kdb.h> 108 109 #include <vm/vm.h> 110 #include <vm/vm_param.h> 111 #include <vm/vm_kern.h> 112 #include <vm/vm_page.h> 113 #include <vm/vm_map.h> 114 #include <vm/vm_object.h> 115 #include <vm/vm_extern.h> 116 #include <vm/vm_pageout.h> 117 118 #include <machine/cpu.h> 119 #include <machine/hid.h> 120 #include <machine/md_var.h> 121 #include <machine/mmuvar.h> 122 123 #include "mmu_oea64.h" 124 #include "mmu_if.h" 125 #include "moea64_if.h" 126 127 #define PTESYNC() __asm __volatile("ptesync"); 128 #define TLBSYNC() __asm __volatile("tlbsync; ptesync"); 129 #define SYNC() __asm __volatile("sync"); 130 #define EIEIO() __asm __volatile("eieio"); 131 132 #define VSID_HASH_MASK 0x0000007fffffffffULL 133 134 /* POWER9 only permits a 64k partition table size. */ 135 #define PART_SIZE 0x10000 136 137 static bool moea64_crop_tlbie; 138 static bool moea64_need_lock; 139 140 static __inline void 141 TLBIE(uint64_t vpn) { 142 #ifndef __powerpc64__ 143 register_t vpn_hi, vpn_lo; 144 register_t msr; 145 register_t scratch, intr; 146 #endif 147 148 static volatile u_int tlbie_lock = 0; 149 bool need_lock = moea64_need_lock; 150 151 vpn <<= ADDR_PIDX_SHFT; 152 153 /* Hobo spinlock: we need stronger guarantees than mutexes provide */ 154 if (need_lock) { 155 while (!atomic_cmpset_int(&tlbie_lock, 0, 1)); 156 isync(); /* Flush instruction queue once lock acquired */ 157 158 if (moea64_crop_tlbie) 159 vpn &= ~(0xffffULL << 48); 160 } 161 162 #ifdef __powerpc64__ 163 /* 164 * Explicitly clobber r0. The tlbie instruction has two forms: an old 165 * one used by PowerISA 2.03 and prior, and a newer one used by PowerISA 166 * 2.06 (maybe 2.05?) and later. We need to support both, and it just 167 * so happens that since we use 4k pages we can simply zero out r0, and 168 * clobber it, and the assembler will interpret the single-operand form 169 * of tlbie as having RB set, and everything else as 0. The RS operand 170 * in the newer form is in the same position as the L(page size) bit of 171 * the old form, so a slong as RS is 0, we're good on both sides. 172 */ 173 __asm __volatile("li 0, 0 \n tlbie %0" :: "r"(vpn) : "r0", "memory"); 174 __asm __volatile("eieio; tlbsync; ptesync" ::: "memory"); 175 #else 176 vpn_hi = (uint32_t)(vpn >> 32); 177 vpn_lo = (uint32_t)vpn; 178 179 intr = intr_disable(); 180 __asm __volatile("\ 181 mfmsr %0; \ 182 mr %1, %0; \ 183 insrdi %1,%5,1,0; \ 184 mtmsrd %1; isync; \ 185 \ 186 sld %1,%2,%4; \ 187 or %1,%1,%3; \ 188 tlbie %1; \ 189 \ 190 mtmsrd %0; isync; \ 191 eieio; \ 192 tlbsync; \ 193 ptesync;" 194 : "=r"(msr), "=r"(scratch) : "r"(vpn_hi), "r"(vpn_lo), "r"(32), "r"(1) 195 : "memory"); 196 intr_restore(intr); 197 #endif 198 199 /* No barriers or special ops -- taken care of by ptesync above */ 200 if (need_lock) 201 tlbie_lock = 0; 202 } 203 204 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR) 205 #define ENABLE_TRANS(msr) mtmsr(msr) 206 207 /* 208 * PTEG data. 209 */ 210 static volatile struct lpte *moea64_pteg_table; 211 static struct rwlock moea64_eviction_lock; 212 213 static volatile struct pate *moea64_part_table; 214 215 /* 216 * Dump function. 217 */ 218 static void *moea64_dump_pmap_native(mmu_t mmu, void *ctx, void *buf, 219 u_long *nbytes); 220 221 /* 222 * PTE calls. 223 */ 224 static int moea64_pte_insert_native(mmu_t, struct pvo_entry *); 225 static int64_t moea64_pte_synch_native(mmu_t, struct pvo_entry *); 226 static int64_t moea64_pte_clear_native(mmu_t, struct pvo_entry *, uint64_t); 227 static int64_t moea64_pte_replace_native(mmu_t, struct pvo_entry *, int); 228 static int64_t moea64_pte_unset_native(mmu_t mmu, struct pvo_entry *); 229 230 /* 231 * Utility routines. 232 */ 233 static void moea64_bootstrap_native(mmu_t mmup, 234 vm_offset_t kernelstart, vm_offset_t kernelend); 235 static void moea64_cpu_bootstrap_native(mmu_t, int ap); 236 static void tlbia(void); 237 238 static mmu_method_t moea64_native_methods[] = { 239 /* Internal interfaces */ 240 MMUMETHOD(mmu_bootstrap, moea64_bootstrap_native), 241 MMUMETHOD(mmu_cpu_bootstrap, moea64_cpu_bootstrap_native), 242 MMUMETHOD(mmu_dump_pmap, moea64_dump_pmap_native), 243 244 MMUMETHOD(moea64_pte_synch, moea64_pte_synch_native), 245 MMUMETHOD(moea64_pte_clear, moea64_pte_clear_native), 246 MMUMETHOD(moea64_pte_unset, moea64_pte_unset_native), 247 MMUMETHOD(moea64_pte_replace, moea64_pte_replace_native), 248 MMUMETHOD(moea64_pte_insert, moea64_pte_insert_native), 249 250 { 0, 0 } 251 }; 252 253 MMU_DEF_INHERIT(oea64_mmu_native, MMU_TYPE_G5, moea64_native_methods, 254 0, oea64_mmu); 255 256 static int64_t 257 moea64_pte_synch_native(mmu_t mmu, struct pvo_entry *pvo) 258 { 259 volatile struct lpte *pt = moea64_pteg_table + pvo->pvo_pte.slot; 260 uint64_t ptelo, pvo_ptevpn; 261 262 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 263 264 pvo_ptevpn = moea64_pte_vpn_from_pvo_vpn(pvo); 265 266 rw_rlock(&moea64_eviction_lock); 267 if ((be64toh(pt->pte_hi) & LPTE_AVPN_MASK) != pvo_ptevpn) { 268 /* Evicted */ 269 rw_runlock(&moea64_eviction_lock); 270 return (-1); 271 } 272 273 PTESYNC(); 274 ptelo = be64toh(pt->pte_lo); 275 276 rw_runlock(&moea64_eviction_lock); 277 278 return (ptelo & (LPTE_REF | LPTE_CHG)); 279 } 280 281 static int64_t 282 moea64_pte_clear_native(mmu_t mmu, struct pvo_entry *pvo, uint64_t ptebit) 283 { 284 volatile struct lpte *pt = moea64_pteg_table + pvo->pvo_pte.slot; 285 struct lpte properpt; 286 uint64_t ptelo; 287 288 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 289 290 moea64_pte_from_pvo(pvo, &properpt); 291 292 rw_rlock(&moea64_eviction_lock); 293 if ((be64toh(pt->pte_hi) & LPTE_AVPN_MASK) != 294 (properpt.pte_hi & LPTE_AVPN_MASK)) { 295 /* Evicted */ 296 rw_runlock(&moea64_eviction_lock); 297 return (-1); 298 } 299 300 if (ptebit == LPTE_REF) { 301 /* See "Resetting the Reference Bit" in arch manual */ 302 PTESYNC(); 303 /* 2-step here safe: precision is not guaranteed */ 304 ptelo = be64toh(pt->pte_lo); 305 306 /* One-byte store to avoid touching the C bit */ 307 ((volatile uint8_t *)(&pt->pte_lo))[6] = 308 #if BYTE_ORDER == BIG_ENDIAN 309 ((uint8_t *)(&properpt.pte_lo))[6]; 310 #else 311 ((uint8_t *)(&properpt.pte_lo))[1]; 312 #endif 313 rw_runlock(&moea64_eviction_lock); 314 315 critical_enter(); 316 TLBIE(pvo->pvo_vpn); 317 critical_exit(); 318 } else { 319 rw_runlock(&moea64_eviction_lock); 320 ptelo = moea64_pte_unset_native(mmu, pvo); 321 moea64_pte_insert_native(mmu, pvo); 322 } 323 324 return (ptelo & (LPTE_REF | LPTE_CHG)); 325 } 326 327 static int64_t 328 moea64_pte_unset_native(mmu_t mmu, struct pvo_entry *pvo) 329 { 330 volatile struct lpte *pt = moea64_pteg_table + pvo->pvo_pte.slot; 331 uint64_t ptelo, pvo_ptevpn; 332 333 pvo_ptevpn = moea64_pte_vpn_from_pvo_vpn(pvo); 334 335 rw_rlock(&moea64_eviction_lock); 336 if ((be64toh(pt->pte_hi & LPTE_AVPN_MASK)) != pvo_ptevpn) { 337 /* Evicted */ 338 STAT_MOEA64(moea64_pte_overflow--); 339 rw_runlock(&moea64_eviction_lock); 340 return (-1); 341 } 342 343 /* 344 * Invalidate the pte, briefly locking it to collect RC bits. No 345 * atomics needed since this is protected against eviction by the lock. 346 */ 347 isync(); 348 critical_enter(); 349 pt->pte_hi = be64toh((pt->pte_hi & ~LPTE_VALID) | LPTE_LOCKED); 350 PTESYNC(); 351 TLBIE(pvo->pvo_vpn); 352 ptelo = be64toh(pt->pte_lo); 353 *((volatile int32_t *)(&pt->pte_hi) + 1) = 0; /* Release lock */ 354 critical_exit(); 355 rw_runlock(&moea64_eviction_lock); 356 357 /* Keep statistics */ 358 STAT_MOEA64(moea64_pte_valid--); 359 360 return (ptelo & (LPTE_CHG | LPTE_REF)); 361 } 362 363 static int64_t 364 moea64_pte_replace_inval_native(mmu_t mmu, struct pvo_entry *pvo, 365 volatile struct lpte *pt) 366 { 367 struct lpte properpt; 368 uint64_t ptelo; 369 370 moea64_pte_from_pvo(pvo, &properpt); 371 372 rw_rlock(&moea64_eviction_lock); 373 if ((be64toh(pt->pte_hi & LPTE_AVPN_MASK)) != 374 (properpt.pte_hi & LPTE_AVPN_MASK)) { 375 /* Evicted */ 376 STAT_MOEA64(moea64_pte_overflow--); 377 rw_runlock(&moea64_eviction_lock); 378 return (-1); 379 } 380 381 /* 382 * Replace the pte, briefly locking it to collect RC bits. No 383 * atomics needed since this is protected against eviction by the lock. 384 */ 385 isync(); 386 critical_enter(); 387 pt->pte_hi = be64toh((pt->pte_hi & ~LPTE_VALID) | LPTE_LOCKED); 388 PTESYNC(); 389 TLBIE(pvo->pvo_vpn); 390 ptelo = be64toh(pt->pte_lo); 391 EIEIO(); 392 pt->pte_lo = htobe64(properpt.pte_lo); 393 EIEIO(); 394 pt->pte_hi = htobe64(properpt.pte_hi); /* Release lock */ 395 PTESYNC(); 396 critical_exit(); 397 rw_runlock(&moea64_eviction_lock); 398 399 return (ptelo & (LPTE_CHG | LPTE_REF)); 400 } 401 402 static int64_t 403 moea64_pte_replace_native(mmu_t mmu, struct pvo_entry *pvo, int flags) 404 { 405 volatile struct lpte *pt = moea64_pteg_table + pvo->pvo_pte.slot; 406 struct lpte properpt; 407 int64_t ptelo; 408 409 if (flags == 0) { 410 /* Just some software bits changing. */ 411 moea64_pte_from_pvo(pvo, &properpt); 412 413 rw_rlock(&moea64_eviction_lock); 414 if ((be64toh(pt->pte_hi) & LPTE_AVPN_MASK) != 415 (properpt.pte_hi & LPTE_AVPN_MASK)) { 416 rw_runlock(&moea64_eviction_lock); 417 return (-1); 418 } 419 pt->pte_hi = htobe64(properpt.pte_hi); 420 ptelo = be64toh(pt->pte_lo); 421 rw_runlock(&moea64_eviction_lock); 422 } else { 423 /* Otherwise, need reinsertion and deletion */ 424 ptelo = moea64_pte_replace_inval_native(mmu, pvo, pt); 425 } 426 427 return (ptelo); 428 } 429 430 static void 431 moea64_cpu_bootstrap_native(mmu_t mmup, int ap) 432 { 433 int i = 0; 434 #ifdef __powerpc64__ 435 struct slb *slb = PCPU_GET(aim.slb); 436 register_t seg0; 437 #endif 438 439 /* 440 * Initialize segment registers and MMU 441 */ 442 443 mtmsr(mfmsr() & ~PSL_DR & ~PSL_IR); 444 445 switch(mfpvr() >> 16) { 446 case IBMPOWER9: 447 mtspr(SPR_HID0, mfspr(SPR_HID0) & ~HID0_RADIX); 448 break; 449 } 450 451 /* 452 * Install kernel SLB entries 453 */ 454 455 #ifdef __powerpc64__ 456 __asm __volatile ("slbia"); 457 __asm __volatile ("slbmfee %0,%1; slbie %0;" : "=r"(seg0) : 458 "r"(0)); 459 460 for (i = 0; i < n_slbs; i++) { 461 if (!(slb[i].slbe & SLBE_VALID)) 462 continue; 463 464 __asm __volatile ("slbmte %0, %1" :: 465 "r"(slb[i].slbv), "r"(slb[i].slbe)); 466 } 467 #else 468 for (i = 0; i < 16; i++) 469 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]); 470 #endif 471 472 /* 473 * Install page table 474 */ 475 476 if (cpu_features2 & PPC_FEATURE2_ARCH_3_00) 477 mtspr(SPR_PTCR, 478 ((uintptr_t)moea64_part_table & ~DMAP_BASE_ADDRESS) | 479 flsl((PART_SIZE >> 12) - 1)); 480 else 481 __asm __volatile ("ptesync; mtsdr1 %0; isync" 482 :: "r"(((uintptr_t)moea64_pteg_table & ~DMAP_BASE_ADDRESS) 483 | (uintptr_t)(flsl(moea64_pteg_mask >> 11)))); 484 tlbia(); 485 } 486 487 static void 488 moea64_bootstrap_native(mmu_t mmup, vm_offset_t kernelstart, 489 vm_offset_t kernelend) 490 { 491 vm_size_t size; 492 vm_offset_t off; 493 vm_paddr_t pa; 494 register_t msr; 495 496 moea64_early_bootstrap(mmup, kernelstart, kernelend); 497 498 switch (mfpvr() >> 16) { 499 case IBMPOWER9: 500 moea64_need_lock = false; 501 break; 502 case IBMPOWER4: 503 case IBMPOWER4PLUS: 504 case IBM970: 505 case IBM970FX: 506 case IBM970GX: 507 case IBM970MP: 508 moea64_crop_tlbie = true; 509 default: 510 moea64_need_lock = true; 511 } 512 /* 513 * Allocate PTEG table. 514 */ 515 516 size = moea64_pteg_count * sizeof(struct lpteg); 517 CTR2(KTR_PMAP, "moea64_bootstrap: %lu PTEGs, %lu bytes", 518 moea64_pteg_count, size); 519 rw_init(&moea64_eviction_lock, "pte eviction"); 520 521 /* 522 * We now need to allocate memory. This memory, to be allocated, 523 * has to reside in a page table. The page table we are about to 524 * allocate. We don't have BAT. So drop to data real mode for a minute 525 * as a measure of last resort. We do this a couple times. 526 */ 527 /* 528 * PTEG table must be aligned on a 256k boundary, but can be placed 529 * anywhere with that alignment on POWER ISA 3+ systems. On earlier 530 * systems, offset addition is done by the CPU with bitwise OR rather 531 * than addition, so the table must also be aligned on a boundary of 532 * its own size. Pick the larger of the two, which works on all 533 * systems. 534 */ 535 moea64_pteg_table = (struct lpte *)moea64_bootstrap_alloc(size, 536 MAX(256*1024, size)); 537 if (hw_direct_map) 538 moea64_pteg_table = 539 (struct lpte *)PHYS_TO_DMAP((vm_offset_t)moea64_pteg_table); 540 /* Allocate partition table (ISA 3.0). */ 541 if (cpu_features2 & PPC_FEATURE2_ARCH_3_00) { 542 moea64_part_table = 543 (struct pate *)moea64_bootstrap_alloc(PART_SIZE, PART_SIZE); 544 moea64_part_table = 545 (struct pate *)PHYS_TO_DMAP((vm_offset_t)moea64_part_table); 546 } 547 DISABLE_TRANS(msr); 548 bzero(__DEVOLATILE(void *, moea64_pteg_table), moea64_pteg_count * 549 sizeof(struct lpteg)); 550 if (cpu_features2 & PPC_FEATURE2_ARCH_3_00) { 551 bzero(__DEVOLATILE(void *, moea64_part_table), PART_SIZE); 552 moea64_part_table[0].pagetab = 553 (DMAP_TO_PHYS((vm_offset_t)moea64_pteg_table)) | 554 (uintptr_t)(flsl((moea64_pteg_count - 1) >> 11)); 555 } 556 ENABLE_TRANS(msr); 557 558 CTR1(KTR_PMAP, "moea64_bootstrap: PTEG table at %p", moea64_pteg_table); 559 560 moea64_mid_bootstrap(mmup, kernelstart, kernelend); 561 562 /* 563 * Add a mapping for the page table itself if there is no direct map. 564 */ 565 if (!hw_direct_map) { 566 size = moea64_pteg_count * sizeof(struct lpteg); 567 off = (vm_offset_t)(moea64_pteg_table); 568 DISABLE_TRANS(msr); 569 for (pa = off; pa < off + size; pa += PAGE_SIZE) 570 pmap_kenter(pa, pa); 571 ENABLE_TRANS(msr); 572 } 573 574 /* Bring up virtual memory */ 575 moea64_late_bootstrap(mmup, kernelstart, kernelend); 576 } 577 578 static void 579 tlbia(void) 580 { 581 vm_offset_t i; 582 #ifndef __powerpc64__ 583 register_t msr, scratch; 584 #endif 585 586 i = 0xc00; /* IS = 11 */ 587 switch (mfpvr() >> 16) { 588 case IBM970: 589 case IBM970FX: 590 case IBM970MP: 591 case IBM970GX: 592 case IBMPOWER4: 593 case IBMPOWER4PLUS: 594 case IBMPOWER5: 595 case IBMPOWER5PLUS: 596 i = 0; /* IS not supported */ 597 break; 598 } 599 600 TLBSYNC(); 601 602 for (; i < 0x400000; i += 0x00001000) { 603 #ifdef __powerpc64__ 604 __asm __volatile("tlbiel %0" :: "r"(i)); 605 #else 606 __asm __volatile("\ 607 mfmsr %0; \ 608 mr %1, %0; \ 609 insrdi %1,%3,1,0; \ 610 mtmsrd %1; \ 611 isync; \ 612 \ 613 tlbiel %2; \ 614 \ 615 mtmsrd %0; \ 616 isync;" 617 : "=r"(msr), "=r"(scratch) : "r"(i), "r"(1)); 618 #endif 619 } 620 621 EIEIO(); 622 TLBSYNC(); 623 } 624 625 static int 626 atomic_pte_lock(volatile struct lpte *pte, uint64_t bitmask, uint64_t *oldhi) 627 { 628 int ret; 629 uint32_t oldhihalf; 630 631 /* 632 * Note: in principle, if just the locked bit were set here, we 633 * could avoid needing the eviction lock. However, eviction occurs 634 * so rarely that it isn't worth bothering about in practice. 635 */ 636 637 __asm __volatile ( 638 "1:\tlwarx %1, 0, %3\n\t" /* load old value */ 639 "and. %0,%1,%4\n\t" /* check if any bits set */ 640 "bne 2f\n\t" /* exit if any set */ 641 "stwcx. %5, 0, %3\n\t" /* attempt to store */ 642 "bne- 1b\n\t" /* spin if failed */ 643 "li %0, 1\n\t" /* success - retval = 1 */ 644 "b 3f\n\t" /* we've succeeded */ 645 "2:\n\t" 646 "stwcx. %1, 0, %3\n\t" /* clear reservation (74xx) */ 647 "li %0, 0\n\t" /* failure - retval = 0 */ 648 "3:\n\t" 649 : "=&r" (ret), "=&r"(oldhihalf), "=m" (pte->pte_hi) 650 : "r" ((volatile char *)&pte->pte_hi + 4), 651 "r" ((uint32_t)bitmask), "r" ((uint32_t)LPTE_LOCKED), 652 "m" (pte->pte_hi) 653 : "cr0", "cr1", "cr2", "memory"); 654 655 *oldhi = (pte->pte_hi & 0xffffffff00000000ULL) | oldhihalf; 656 657 return (ret); 658 } 659 660 static uintptr_t 661 moea64_insert_to_pteg_native(struct lpte *pvo_pt, uintptr_t slotbase, 662 uint64_t mask) 663 { 664 volatile struct lpte *pt; 665 uint64_t oldptehi, va; 666 uintptr_t k; 667 int i, j; 668 669 /* Start at a random slot */ 670 i = mftb() % 8; 671 for (j = 0; j < 8; j++) { 672 k = slotbase + (i + j) % 8; 673 pt = &moea64_pteg_table[k]; 674 /* Invalidate and seize lock only if no bits in mask set */ 675 if (atomic_pte_lock(pt, mask, &oldptehi)) /* Lock obtained */ 676 break; 677 } 678 679 if (j == 8) 680 return (-1); 681 682 if (oldptehi & LPTE_VALID) { 683 KASSERT(!(oldptehi & LPTE_WIRED), ("Unmapped wired entry")); 684 /* 685 * Need to invalidate old entry completely: see 686 * "Modifying a Page Table Entry". Need to reconstruct 687 * the virtual address for the outgoing entry to do that. 688 */ 689 va = oldptehi >> (ADDR_SR_SHFT - ADDR_API_SHFT64); 690 if (oldptehi & LPTE_HID) 691 va = (((k >> 3) ^ moea64_pteg_mask) ^ va) & 692 (ADDR_PIDX >> ADDR_PIDX_SHFT); 693 else 694 va = ((k >> 3) ^ va) & (ADDR_PIDX >> ADDR_PIDX_SHFT); 695 va |= (oldptehi & LPTE_AVPN_MASK) << 696 (ADDR_API_SHFT64 - ADDR_PIDX_SHFT); 697 PTESYNC(); 698 TLBIE(va); 699 STAT_MOEA64(moea64_pte_valid--); 700 STAT_MOEA64(moea64_pte_overflow++); 701 } 702 703 /* 704 * Update the PTE as per "Adding a Page Table Entry". Lock is released 705 * by setting the high doubleworld. 706 */ 707 pt->pte_lo = htobe64(pvo_pt->pte_lo); 708 EIEIO(); 709 pt->pte_hi = htobe64(pvo_pt->pte_hi); 710 PTESYNC(); 711 712 /* Keep statistics */ 713 STAT_MOEA64(moea64_pte_valid++); 714 715 return (k); 716 } 717 718 static int 719 moea64_pte_insert_native(mmu_t mmu, struct pvo_entry *pvo) 720 { 721 struct lpte insertpt; 722 uintptr_t slot; 723 724 /* Initialize PTE */ 725 moea64_pte_from_pvo(pvo, &insertpt); 726 727 /* Make sure further insertion is locked out during evictions */ 728 rw_rlock(&moea64_eviction_lock); 729 730 /* 731 * First try primary hash. 732 */ 733 pvo->pvo_pte.slot &= ~7ULL; /* Base slot address */ 734 slot = moea64_insert_to_pteg_native(&insertpt, pvo->pvo_pte.slot, 735 LPTE_VALID | LPTE_WIRED | LPTE_LOCKED); 736 if (slot != -1) { 737 rw_runlock(&moea64_eviction_lock); 738 pvo->pvo_pte.slot = slot; 739 return (0); 740 } 741 742 /* 743 * Now try secondary hash. 744 */ 745 pvo->pvo_vaddr ^= PVO_HID; 746 insertpt.pte_hi ^= LPTE_HID; 747 pvo->pvo_pte.slot ^= (moea64_pteg_mask << 3); 748 slot = moea64_insert_to_pteg_native(&insertpt, pvo->pvo_pte.slot, 749 LPTE_VALID | LPTE_WIRED | LPTE_LOCKED); 750 if (slot != -1) { 751 rw_runlock(&moea64_eviction_lock); 752 pvo->pvo_pte.slot = slot; 753 return (0); 754 } 755 756 /* 757 * Out of luck. Find a PTE to sacrifice. 758 */ 759 760 /* Lock out all insertions for a bit */ 761 if (!rw_try_upgrade(&moea64_eviction_lock)) { 762 rw_runlock(&moea64_eviction_lock); 763 rw_wlock(&moea64_eviction_lock); 764 } 765 766 slot = moea64_insert_to_pteg_native(&insertpt, pvo->pvo_pte.slot, 767 LPTE_WIRED | LPTE_LOCKED); 768 if (slot != -1) { 769 rw_wunlock(&moea64_eviction_lock); 770 pvo->pvo_pte.slot = slot; 771 return (0); 772 } 773 774 /* Try other hash table. Now we're getting desperate... */ 775 pvo->pvo_vaddr ^= PVO_HID; 776 insertpt.pte_hi ^= LPTE_HID; 777 pvo->pvo_pte.slot ^= (moea64_pteg_mask << 3); 778 slot = moea64_insert_to_pteg_native(&insertpt, pvo->pvo_pte.slot, 779 LPTE_WIRED | LPTE_LOCKED); 780 if (slot != -1) { 781 rw_wunlock(&moea64_eviction_lock); 782 pvo->pvo_pte.slot = slot; 783 return (0); 784 } 785 786 /* No freeable slots in either PTEG? We're hosed. */ 787 rw_wunlock(&moea64_eviction_lock); 788 panic("moea64_pte_insert: overflow"); 789 return (-1); 790 } 791 792 static void * 793 moea64_dump_pmap_native(mmu_t mmu, void *ctx, void *buf, u_long *nbytes) 794 { 795 struct dump_context *dctx; 796 u_long ptex, ptex_end; 797 798 dctx = (struct dump_context *)ctx; 799 ptex = dctx->ptex; 800 ptex_end = ptex + dctx->blksz / sizeof(struct lpte); 801 ptex_end = MIN(ptex_end, dctx->ptex_end); 802 *nbytes = (ptex_end - ptex) * sizeof(struct lpte); 803 804 if (*nbytes == 0) 805 return (NULL); 806 807 dctx->ptex = ptex_end; 808 return (__DEVOLATILE(struct lpte *, moea64_pteg_table) + ptex); 809 } 810