1 /*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 /*- 37 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 38 * Copyright (C) 1995, 1996 TooLs GmbH. 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by TooLs GmbH. 52 * 4. The name of TooLs GmbH may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 67 */ 68 /*- 69 * Copyright (C) 2001 Benno Rice. 70 * All rights reserved. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 91 */ 92 93 #include <sys/cdefs.h> 94 __FBSDID("$FreeBSD$"); 95 96 /* 97 * Native 64-bit page table operations for running without a hypervisor. 98 */ 99 100 #include <sys/param.h> 101 #include <sys/kernel.h> 102 #include <sys/ktr.h> 103 #include <sys/lock.h> 104 #include <sys/mutex.h> 105 #include <sys/proc.h> 106 #include <sys/sysctl.h> 107 #include <sys/systm.h> 108 109 #include <sys/kdb.h> 110 111 #include <vm/vm.h> 112 #include <vm/vm_param.h> 113 #include <vm/vm_kern.h> 114 #include <vm/vm_page.h> 115 #include <vm/vm_map.h> 116 #include <vm/vm_object.h> 117 #include <vm/vm_extern.h> 118 #include <vm/vm_pageout.h> 119 #include <vm/vm_pager.h> 120 121 #include <machine/md_var.h> 122 #include <machine/mmuvar.h> 123 124 #include "mmu_oea64.h" 125 #include "mmu_if.h" 126 #include "moea64_if.h" 127 128 #define PTESYNC() __asm __volatile("ptesync"); 129 #define TLBSYNC() __asm __volatile("tlbsync; ptesync"); 130 #define SYNC() __asm __volatile("sync"); 131 #define EIEIO() __asm __volatile("eieio"); 132 133 #define VSID_HASH_MASK 0x0000007fffffffffULL 134 135 /* 136 * The tlbie instruction must be executed in 64-bit mode 137 * so we have to twiddle MSR[SF] around every invocation. 138 * Just to add to the fun, exceptions must be off as well 139 * so that we can't trap in 64-bit mode. What a pain. 140 */ 141 struct mtx tlbie_mutex; 142 143 static __inline void 144 TLBIE(uint64_t vpn) { 145 #ifndef __powerpc64__ 146 register_t vpn_hi, vpn_lo; 147 register_t msr; 148 register_t scratch; 149 #endif 150 151 vpn <<= ADDR_PIDX_SHFT; 152 vpn &= ~(0xffffULL << 48); 153 154 mtx_lock_spin(&tlbie_mutex); 155 #ifdef __powerpc64__ 156 __asm __volatile("\ 157 ptesync; \ 158 tlbie %0; \ 159 eieio; \ 160 tlbsync; \ 161 ptesync;" 162 :: "r"(vpn) : "memory"); 163 #else 164 vpn_hi = (uint32_t)(vpn >> 32); 165 vpn_lo = (uint32_t)vpn; 166 167 __asm __volatile("\ 168 mfmsr %0; \ 169 mr %1, %0; \ 170 insrdi %1,%5,1,0; \ 171 mtmsrd %1; isync; \ 172 ptesync; \ 173 \ 174 sld %1,%2,%4; \ 175 or %1,%1,%3; \ 176 tlbie %1; \ 177 \ 178 mtmsrd %0; isync; \ 179 eieio; \ 180 tlbsync; \ 181 ptesync;" 182 : "=r"(msr), "=r"(scratch) : "r"(vpn_hi), "r"(vpn_lo), "r"(32), "r"(1) 183 : "memory"); 184 #endif 185 mtx_unlock_spin(&tlbie_mutex); 186 } 187 188 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR) 189 #define ENABLE_TRANS(msr) mtmsr(msr) 190 191 /* 192 * PTEG data. 193 */ 194 static struct lpteg *moea64_pteg_table; 195 196 /* 197 * PTE calls. 198 */ 199 static int moea64_pte_insert_native(mmu_t, u_int, struct lpte *); 200 static uintptr_t moea64_pvo_to_pte_native(mmu_t, const struct pvo_entry *); 201 static void moea64_pte_synch_native(mmu_t, uintptr_t pt, 202 struct lpte *pvo_pt); 203 static void moea64_pte_clear_native(mmu_t, uintptr_t pt, 204 struct lpte *pvo_pt, uint64_t vpn, uint64_t ptebit); 205 static void moea64_pte_change_native(mmu_t, uintptr_t pt, 206 struct lpte *pvo_pt, uint64_t vpn); 207 static void moea64_pte_unset_native(mmu_t mmu, uintptr_t pt, 208 struct lpte *pvo_pt, uint64_t vpn); 209 210 /* 211 * Utility routines. 212 */ 213 static void moea64_bootstrap_native(mmu_t mmup, 214 vm_offset_t kernelstart, vm_offset_t kernelend); 215 static void moea64_cpu_bootstrap_native(mmu_t, int ap); 216 static void tlbia(void); 217 218 static mmu_method_t moea64_native_methods[] = { 219 /* Internal interfaces */ 220 MMUMETHOD(mmu_bootstrap, moea64_bootstrap_native), 221 MMUMETHOD(mmu_cpu_bootstrap, moea64_cpu_bootstrap_native), 222 223 MMUMETHOD(moea64_pte_synch, moea64_pte_synch_native), 224 MMUMETHOD(moea64_pte_clear, moea64_pte_clear_native), 225 MMUMETHOD(moea64_pte_unset, moea64_pte_unset_native), 226 MMUMETHOD(moea64_pte_change, moea64_pte_change_native), 227 MMUMETHOD(moea64_pte_insert, moea64_pte_insert_native), 228 MMUMETHOD(moea64_pvo_to_pte, moea64_pvo_to_pte_native), 229 230 { 0, 0 } 231 }; 232 233 MMU_DEF_INHERIT(oea64_mmu_native, MMU_TYPE_G5, moea64_native_methods, 234 0, oea64_mmu); 235 236 static __inline u_int 237 va_to_pteg(uint64_t vsid, vm_offset_t addr, int large) 238 { 239 uint64_t hash; 240 int shift; 241 242 shift = large ? moea64_large_page_shift : ADDR_PIDX_SHFT; 243 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)addr & ADDR_PIDX) >> 244 shift); 245 return (hash & moea64_pteg_mask); 246 } 247 248 static void 249 moea64_pte_synch_native(mmu_t mmu, uintptr_t pt_cookie, struct lpte *pvo_pt) 250 { 251 struct lpte *pt = (struct lpte *)pt_cookie; 252 253 pvo_pt->pte_lo |= pt->pte_lo & (LPTE_REF | LPTE_CHG); 254 } 255 256 static void 257 moea64_pte_clear_native(mmu_t mmu, uintptr_t pt_cookie, struct lpte *pvo_pt, 258 uint64_t vpn, uint64_t ptebit) 259 { 260 struct lpte *pt = (struct lpte *)pt_cookie; 261 262 /* 263 * As shown in Section 7.6.3.2.3 264 */ 265 pt->pte_lo &= ~ptebit; 266 TLBIE(vpn); 267 } 268 269 static void 270 moea64_pte_set_native(struct lpte *pt, struct lpte *pvo_pt) 271 { 272 273 pvo_pt->pte_hi |= LPTE_VALID; 274 275 /* 276 * Update the PTE as defined in section 7.6.3.1. 277 * Note that the REF/CHG bits are from pvo_pt and thus should have 278 * been saved so this routine can restore them (if desired). 279 */ 280 pt->pte_lo = pvo_pt->pte_lo; 281 EIEIO(); 282 pt->pte_hi = pvo_pt->pte_hi; 283 PTESYNC(); 284 285 /* Keep statistics for unlocked pages */ 286 if (!(pvo_pt->pte_hi & LPTE_LOCKED)) 287 moea64_pte_valid++; 288 } 289 290 static void 291 moea64_pte_unset_native(mmu_t mmu, uintptr_t pt_cookie, struct lpte *pvo_pt, 292 uint64_t vpn) 293 { 294 struct lpte *pt = (struct lpte *)pt_cookie; 295 296 pvo_pt->pte_hi &= ~LPTE_VALID; 297 298 /* Finish all pending operations */ 299 isync(); 300 301 /* 302 * Force the reg & chg bits back into the PTEs. 303 */ 304 SYNC(); 305 306 /* 307 * Invalidate the pte. 308 */ 309 pt->pte_hi &= ~LPTE_VALID; 310 TLBIE(vpn); 311 312 /* 313 * Save the reg & chg bits. 314 */ 315 moea64_pte_synch_native(mmu, pt_cookie, pvo_pt); 316 317 /* Keep statistics for unlocked pages */ 318 if (!(pvo_pt->pte_hi & LPTE_LOCKED)) 319 moea64_pte_valid--; 320 } 321 322 static void 323 moea64_pte_change_native(mmu_t mmu, uintptr_t pt, struct lpte *pvo_pt, 324 uint64_t vpn) 325 { 326 327 /* 328 * Invalidate the PTE 329 */ 330 moea64_pte_unset_native(mmu, pt, pvo_pt, vpn); 331 moea64_pte_set_native((struct lpte *)pt, pvo_pt); 332 } 333 334 static void 335 moea64_cpu_bootstrap_native(mmu_t mmup, int ap) 336 { 337 int i = 0; 338 #ifdef __powerpc64__ 339 struct slb *slb = PCPU_GET(slb); 340 register_t seg0; 341 #endif 342 343 /* 344 * Initialize segment registers and MMU 345 */ 346 347 mtmsr(mfmsr() & ~PSL_DR & ~PSL_IR); 348 349 /* 350 * Install kernel SLB entries 351 */ 352 353 #ifdef __powerpc64__ 354 __asm __volatile ("slbia"); 355 __asm __volatile ("slbmfee %0,%1; slbie %0;" : "=r"(seg0) : 356 "r"(0)); 357 358 for (i = 0; i < 64; i++) { 359 if (!(slb[i].slbe & SLBE_VALID)) 360 continue; 361 362 __asm __volatile ("slbmte %0, %1" :: 363 "r"(slb[i].slbv), "r"(slb[i].slbe)); 364 } 365 #else 366 for (i = 0; i < 16; i++) 367 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]); 368 #endif 369 370 /* 371 * Install page table 372 */ 373 374 __asm __volatile ("ptesync; mtsdr1 %0; isync" 375 :: "r"((uintptr_t)moea64_pteg_table 376 | (uintptr_t)(flsl(moea64_pteg_mask >> 11)))); 377 tlbia(); 378 } 379 380 static void 381 moea64_bootstrap_native(mmu_t mmup, vm_offset_t kernelstart, 382 vm_offset_t kernelend) 383 { 384 vm_size_t size; 385 vm_offset_t off; 386 vm_paddr_t pa; 387 register_t msr; 388 389 moea64_early_bootstrap(mmup, kernelstart, kernelend); 390 391 /* 392 * Allocate PTEG table. 393 */ 394 395 size = moea64_pteg_count * sizeof(struct lpteg); 396 CTR2(KTR_PMAP, "moea64_bootstrap: %d PTEGs, %d bytes", 397 moea64_pteg_count, size); 398 399 /* 400 * We now need to allocate memory. This memory, to be allocated, 401 * has to reside in a page table. The page table we are about to 402 * allocate. We don't have BAT. So drop to data real mode for a minute 403 * as a measure of last resort. We do this a couple times. 404 */ 405 406 moea64_pteg_table = (struct lpteg *)moea64_bootstrap_alloc(size, size); 407 DISABLE_TRANS(msr); 408 bzero((void *)moea64_pteg_table, moea64_pteg_count * sizeof(struct lpteg)); 409 ENABLE_TRANS(msr); 410 411 CTR1(KTR_PMAP, "moea64_bootstrap: PTEG table at %p", moea64_pteg_table); 412 413 /* 414 * Initialize the TLBIE lock. TLBIE can only be executed by one CPU. 415 */ 416 mtx_init(&tlbie_mutex, "tlbie mutex", NULL, MTX_SPIN); 417 418 moea64_mid_bootstrap(mmup, kernelstart, kernelend); 419 420 /* 421 * Add a mapping for the page table itself if there is no direct map. 422 */ 423 if (!hw_direct_map) { 424 size = moea64_pteg_count * sizeof(struct lpteg); 425 off = (vm_offset_t)(moea64_pteg_table); 426 DISABLE_TRANS(msr); 427 for (pa = off; pa < off + size; pa += PAGE_SIZE) 428 pmap_kenter(pa, pa); 429 ENABLE_TRANS(msr); 430 } 431 432 /* Bring up virtual memory */ 433 moea64_late_bootstrap(mmup, kernelstart, kernelend); 434 } 435 436 static void 437 tlbia(void) 438 { 439 vm_offset_t i; 440 #ifndef __powerpc64__ 441 register_t msr, scratch; 442 #endif 443 444 TLBSYNC(); 445 446 for (i = 0; i < 0xFF000; i += 0x00001000) { 447 #ifdef __powerpc64__ 448 __asm __volatile("tlbiel %0" :: "r"(i)); 449 #else 450 __asm __volatile("\ 451 mfmsr %0; \ 452 mr %1, %0; \ 453 insrdi %1,%3,1,0; \ 454 mtmsrd %1; \ 455 isync; \ 456 \ 457 tlbiel %2; \ 458 \ 459 mtmsrd %0; \ 460 isync;" 461 : "=r"(msr), "=r"(scratch) : "r"(i), "r"(1)); 462 #endif 463 } 464 465 EIEIO(); 466 TLBSYNC(); 467 } 468 469 static uintptr_t 470 moea64_pvo_to_pte_native(mmu_t mmu, const struct pvo_entry *pvo) 471 { 472 struct lpte *pt; 473 int pteidx, ptegidx; 474 uint64_t vsid; 475 476 /* If the PTEG index is not set, then there is no page table entry */ 477 if (!PVO_PTEGIDX_ISSET(pvo)) 478 return (-1); 479 480 /* 481 * Calculate the ptegidx 482 */ 483 vsid = PVO_VSID(pvo); 484 ptegidx = va_to_pteg(vsid, PVO_VADDR(pvo), 485 pvo->pvo_vaddr & PVO_LARGE); 486 487 /* 488 * We can find the actual pte entry without searching by grabbing 489 * the PTEG index from 3 unused bits in pvo_vaddr and by 490 * noticing the HID bit. 491 */ 492 if (pvo->pvo_pte.lpte.pte_hi & LPTE_HID) 493 ptegidx ^= moea64_pteg_mask; 494 495 pteidx = (ptegidx << 3) | PVO_PTEGIDX_GET(pvo); 496 497 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) && 498 !PVO_PTEGIDX_ISSET(pvo)) { 499 panic("moea64_pvo_to_pte: pvo %p has valid pte in pvo but no " 500 "valid pte index", pvo); 501 } 502 503 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0 && 504 PVO_PTEGIDX_ISSET(pvo)) { 505 panic("moea64_pvo_to_pte: pvo %p has valid pte index in pvo " 506 "pvo but no valid pte", pvo); 507 } 508 509 pt = &moea64_pteg_table[pteidx >> 3].pt[pteidx & 7]; 510 if ((pt->pte_hi ^ (pvo->pvo_pte.lpte.pte_hi & ~LPTE_VALID)) == 511 LPTE_VALID) { 512 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0) { 513 panic("moea64_pvo_to_pte: pvo %p has valid pte in " 514 "moea64_pteg_table %p but invalid in pvo", pvo, pt); 515 } 516 517 if (((pt->pte_lo ^ pvo->pvo_pte.lpte.pte_lo) & 518 ~(LPTE_M|LPTE_CHG|LPTE_REF)) != 0) { 519 panic("moea64_pvo_to_pte: pvo %p pte does not match " 520 "pte %p in moea64_pteg_table difference is %#x", 521 pvo, pt, 522 (uint32_t)(pt->pte_lo ^ pvo->pvo_pte.lpte.pte_lo)); 523 } 524 525 return ((uintptr_t)pt); 526 } 527 528 if (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) { 529 panic("moea64_pvo_to_pte: pvo %p has invalid pte %p in " 530 "moea64_pteg_table but valid in pvo", pvo, pt); 531 } 532 533 return (-1); 534 } 535 536 static __inline int 537 moea64_pte_spillable_ident(u_int ptegidx) 538 { 539 struct lpte *pt; 540 int i, j, k; 541 542 /* Start at a random slot */ 543 i = mftb() % 8; 544 k = -1; 545 for (j = 0; j < 8; j++) { 546 pt = &moea64_pteg_table[ptegidx].pt[(i + j) % 8]; 547 if (pt->pte_hi & (LPTE_LOCKED | LPTE_WIRED)) 548 continue; 549 550 /* This is a candidate, so remember it */ 551 k = (i + j) % 8; 552 553 /* Try to get a page that has not been used lately */ 554 if (!(pt->pte_lo & LPTE_REF)) 555 return (k); 556 } 557 558 return (k); 559 } 560 561 static int 562 moea64_pte_insert_native(mmu_t mmu, u_int ptegidx, struct lpte *pvo_pt) 563 { 564 struct lpte *pt; 565 struct pvo_entry *pvo; 566 u_int pteg_bktidx; 567 int i; 568 569 /* 570 * First try primary hash. 571 */ 572 pteg_bktidx = ptegidx; 573 for (pt = moea64_pteg_table[pteg_bktidx].pt, i = 0; i < 8; i++, pt++) { 574 if ((pt->pte_hi & (LPTE_VALID | LPTE_LOCKED)) == 0) { 575 pvo_pt->pte_hi &= ~LPTE_HID; 576 moea64_pte_set_native(pt, pvo_pt); 577 return (i); 578 } 579 } 580 581 /* 582 * Now try secondary hash. 583 */ 584 pteg_bktidx ^= moea64_pteg_mask; 585 for (pt = moea64_pteg_table[pteg_bktidx].pt, i = 0; i < 8; i++, pt++) { 586 if ((pt->pte_hi & (LPTE_VALID | LPTE_LOCKED)) == 0) { 587 pvo_pt->pte_hi |= LPTE_HID; 588 moea64_pte_set_native(pt, pvo_pt); 589 return (i); 590 } 591 } 592 593 /* 594 * Out of luck. Find a PTE to sacrifice. 595 */ 596 pteg_bktidx = ptegidx; 597 i = moea64_pte_spillable_ident(pteg_bktidx); 598 if (i < 0) { 599 pteg_bktidx ^= moea64_pteg_mask; 600 i = moea64_pte_spillable_ident(pteg_bktidx); 601 } 602 603 if (i < 0) { 604 /* No freeable slots in either PTEG? We're hosed. */ 605 panic("moea64_pte_insert: overflow"); 606 return (-1); 607 } 608 609 if (pteg_bktidx == ptegidx) 610 pvo_pt->pte_hi &= ~LPTE_HID; 611 else 612 pvo_pt->pte_hi |= LPTE_HID; 613 614 /* 615 * Synchronize the sacrifice PTE with its PVO, then mark both 616 * invalid. The PVO will be reused when/if the VM system comes 617 * here after a fault. 618 */ 619 pt = &moea64_pteg_table[pteg_bktidx].pt[i]; 620 621 if (pt->pte_hi & LPTE_HID) 622 pteg_bktidx ^= moea64_pteg_mask; /* PTEs indexed by primary */ 623 624 LIST_FOREACH(pvo, &moea64_pvo_table[pteg_bktidx], pvo_olink) { 625 if (pvo->pvo_pte.lpte.pte_hi == pt->pte_hi) { 626 KASSERT(pvo->pvo_pte.lpte.pte_hi & LPTE_VALID, 627 ("Invalid PVO for valid PTE!")); 628 moea64_pte_unset_native(mmu, (uintptr_t)pt, 629 &pvo->pvo_pte.lpte, pvo->pvo_vpn); 630 PVO_PTEGIDX_CLR(pvo); 631 moea64_pte_overflow++; 632 break; 633 } 634 } 635 636 KASSERT(pvo->pvo_pte.lpte.pte_hi == pt->pte_hi, 637 ("Unable to find PVO for spilled PTE")); 638 639 /* 640 * Set the new PTE. 641 */ 642 moea64_pte_set_native(pt, pvo_pt); 643 644 return (i); 645 } 646 647