1 /*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 /*- 37 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 38 * Copyright (C) 1995, 1996 TooLs GmbH. 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by TooLs GmbH. 52 * 4. The name of TooLs GmbH may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 67 */ 68 /*- 69 * Copyright (C) 2001 Benno Rice. 70 * All rights reserved. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 91 */ 92 93 #include <sys/cdefs.h> 94 __FBSDID("$FreeBSD$"); 95 96 /* 97 * Native 64-bit page table operations for running without a hypervisor. 98 */ 99 100 #include <sys/param.h> 101 #include <sys/kernel.h> 102 #include <sys/ktr.h> 103 #include <sys/lock.h> 104 #include <sys/mutex.h> 105 #include <sys/proc.h> 106 #include <sys/sysctl.h> 107 #include <sys/systm.h> 108 109 #include <sys/kdb.h> 110 111 #include <vm/vm.h> 112 #include <vm/vm_param.h> 113 #include <vm/vm_kern.h> 114 #include <vm/vm_page.h> 115 #include <vm/vm_map.h> 116 #include <vm/vm_object.h> 117 #include <vm/vm_extern.h> 118 #include <vm/vm_pageout.h> 119 #include <vm/vm_pager.h> 120 121 #include <machine/md_var.h> 122 #include <machine/mmuvar.h> 123 124 #include "mmu_oea64.h" 125 #include "mmu_if.h" 126 #include "moea64_if.h" 127 128 #define PTESYNC() __asm __volatile("ptesync"); 129 #define TLBSYNC() __asm __volatile("tlbsync; ptesync"); 130 #define SYNC() __asm __volatile("sync"); 131 #define EIEIO() __asm __volatile("eieio"); 132 133 #define VSID_HASH_MASK 0x0000007fffffffffULL 134 135 /* 136 * The tlbie instruction must be executed in 64-bit mode 137 * so we have to twiddle MSR[SF] around every invocation. 138 * Just to add to the fun, exceptions must be off as well 139 * so that we can't trap in 64-bit mode. What a pain. 140 */ 141 struct mtx tlbie_mutex; 142 143 static __inline void 144 TLBIE(uint64_t vpn) { 145 #ifndef __powerpc64__ 146 register_t vpn_hi, vpn_lo; 147 register_t msr; 148 register_t scratch; 149 #endif 150 151 vpn <<= ADDR_PIDX_SHFT; 152 vpn &= ~(0xffffULL << 48); 153 154 mtx_lock_spin(&tlbie_mutex); 155 #ifdef __powerpc64__ 156 __asm __volatile("\ 157 ptesync; \ 158 tlbie %0; \ 159 eieio; \ 160 tlbsync; \ 161 ptesync;" 162 :: "r"(vpn) : "memory"); 163 #else 164 vpn_hi = (uint32_t)(vpn >> 32); 165 vpn_lo = (uint32_t)vpn; 166 167 __asm __volatile("\ 168 mfmsr %0; \ 169 mr %1, %0; \ 170 insrdi %1,%5,1,0; \ 171 mtmsrd %1; isync; \ 172 ptesync; \ 173 \ 174 sld %1,%2,%4; \ 175 or %1,%1,%3; \ 176 tlbie %1; \ 177 \ 178 mtmsrd %0; isync; \ 179 eieio; \ 180 tlbsync; \ 181 ptesync;" 182 : "=r"(msr), "=r"(scratch) : "r"(vpn_hi), "r"(vpn_lo), "r"(32), "r"(1) 183 : "memory"); 184 #endif 185 mtx_unlock_spin(&tlbie_mutex); 186 } 187 188 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR); isync() 189 #define ENABLE_TRANS(msr) mtmsr(msr); isync() 190 191 /* 192 * PTEG data. 193 */ 194 static struct lpteg *moea64_pteg_table; 195 196 /* 197 * PTE calls. 198 */ 199 static int moea64_pte_insert_native(mmu_t, u_int, struct lpte *); 200 static uintptr_t moea64_pvo_to_pte_native(mmu_t, const struct pvo_entry *); 201 static void moea64_pte_synch_native(mmu_t, uintptr_t pt, 202 struct lpte *pvo_pt); 203 static void moea64_pte_clear_native(mmu_t, uintptr_t pt, 204 struct lpte *pvo_pt, uint64_t vpn, uint64_t ptebit); 205 static void moea64_pte_change_native(mmu_t, uintptr_t pt, 206 struct lpte *pvo_pt, uint64_t vpn); 207 static void moea64_pte_unset_native(mmu_t mmu, uintptr_t pt, 208 struct lpte *pvo_pt, uint64_t vpn); 209 210 /* 211 * Utility routines. 212 */ 213 static void moea64_bootstrap_native(mmu_t mmup, 214 vm_offset_t kernelstart, vm_offset_t kernelend); 215 static void moea64_cpu_bootstrap_native(mmu_t, int ap); 216 static void tlbia(void); 217 218 static mmu_method_t moea64_native_methods[] = { 219 /* Internal interfaces */ 220 MMUMETHOD(mmu_bootstrap, moea64_bootstrap_native), 221 MMUMETHOD(mmu_cpu_bootstrap, moea64_cpu_bootstrap_native), 222 223 MMUMETHOD(moea64_pte_synch, moea64_pte_synch_native), 224 MMUMETHOD(moea64_pte_clear, moea64_pte_clear_native), 225 MMUMETHOD(moea64_pte_unset, moea64_pte_unset_native), 226 MMUMETHOD(moea64_pte_change, moea64_pte_change_native), 227 MMUMETHOD(moea64_pte_insert, moea64_pte_insert_native), 228 MMUMETHOD(moea64_pvo_to_pte, moea64_pvo_to_pte_native), 229 230 { 0, 0 } 231 }; 232 233 MMU_DEF_INHERIT(oea64_mmu_native, MMU_TYPE_G5, moea64_native_methods, 234 0, oea64_mmu); 235 236 static __inline u_int 237 va_to_pteg(uint64_t vsid, vm_offset_t addr, int large) 238 { 239 uint64_t hash; 240 int shift; 241 242 shift = large ? moea64_large_page_shift : ADDR_PIDX_SHFT; 243 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)addr & ADDR_PIDX) >> 244 shift); 245 return (hash & moea64_pteg_mask); 246 } 247 248 static void 249 moea64_pte_synch_native(mmu_t mmu, uintptr_t pt_cookie, struct lpte *pvo_pt) 250 { 251 struct lpte *pt = (struct lpte *)pt_cookie; 252 253 pvo_pt->pte_lo |= pt->pte_lo & (LPTE_REF | LPTE_CHG); 254 } 255 256 static void 257 moea64_pte_clear_native(mmu_t mmu, uintptr_t pt_cookie, struct lpte *pvo_pt, 258 uint64_t vpn, uint64_t ptebit) 259 { 260 struct lpte *pt = (struct lpte *)pt_cookie; 261 262 /* 263 * As shown in Section 7.6.3.2.3 264 */ 265 pt->pte_lo &= ~ptebit; 266 TLBIE(vpn); 267 } 268 269 static void 270 moea64_pte_set_native(struct lpte *pt, struct lpte *pvo_pt) 271 { 272 273 pvo_pt->pte_hi |= LPTE_VALID; 274 275 /* 276 * Update the PTE as defined in section 7.6.3.1. 277 * Note that the REF/CHG bits are from pvo_pt and thus should have 278 * been saved so this routine can restore them (if desired). 279 */ 280 pt->pte_lo = pvo_pt->pte_lo; 281 EIEIO(); 282 pt->pte_hi = pvo_pt->pte_hi; 283 PTESYNC(); 284 moea64_pte_valid++; 285 } 286 287 static void 288 moea64_pte_unset_native(mmu_t mmu, uintptr_t pt_cookie, struct lpte *pvo_pt, 289 uint64_t vpn) 290 { 291 struct lpte *pt = (struct lpte *)pt_cookie; 292 293 pvo_pt->pte_hi &= ~LPTE_VALID; 294 295 /* Finish all pending operations */ 296 isync(); 297 298 /* 299 * Force the reg & chg bits back into the PTEs. 300 */ 301 SYNC(); 302 303 /* 304 * Invalidate the pte. 305 */ 306 pt->pte_hi &= ~LPTE_VALID; 307 TLBIE(vpn); 308 309 /* 310 * Save the reg & chg bits. 311 */ 312 moea64_pte_synch_native(mmu, pt_cookie, pvo_pt); 313 moea64_pte_valid--; 314 } 315 316 static void 317 moea64_pte_change_native(mmu_t mmu, uintptr_t pt, struct lpte *pvo_pt, 318 uint64_t vpn) 319 { 320 321 /* 322 * Invalidate the PTE 323 */ 324 moea64_pte_unset_native(mmu, pt, pvo_pt, vpn); 325 moea64_pte_set_native((struct lpte *)pt, pvo_pt); 326 } 327 328 static void 329 moea64_cpu_bootstrap_native(mmu_t mmup, int ap) 330 { 331 int i = 0; 332 #ifdef __powerpc64__ 333 struct slb *slb = PCPU_GET(slb); 334 register_t seg0; 335 #endif 336 337 /* 338 * Initialize segment registers and MMU 339 */ 340 341 mtmsr(mfmsr() & ~PSL_DR & ~PSL_IR); isync(); 342 343 /* 344 * Install kernel SLB entries 345 */ 346 347 #ifdef __powerpc64__ 348 __asm __volatile ("slbia"); 349 __asm __volatile ("slbmfee %0,%1; slbie %0;" : "=r"(seg0) : 350 "r"(0)); 351 352 for (i = 0; i < 64; i++) { 353 if (!(slb[i].slbe & SLBE_VALID)) 354 continue; 355 356 __asm __volatile ("slbmte %0, %1" :: 357 "r"(slb[i].slbv), "r"(slb[i].slbe)); 358 } 359 #else 360 for (i = 0; i < 16; i++) 361 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]); 362 #endif 363 364 /* 365 * Install page table 366 */ 367 368 __asm __volatile ("ptesync; mtsdr1 %0; isync" 369 :: "r"((uintptr_t)moea64_pteg_table 370 | (uintptr_t)(flsl(moea64_pteg_mask >> 11)))); 371 tlbia(); 372 } 373 374 static void 375 moea64_bootstrap_native(mmu_t mmup, vm_offset_t kernelstart, 376 vm_offset_t kernelend) 377 { 378 vm_size_t size; 379 vm_offset_t off; 380 vm_paddr_t pa; 381 register_t msr; 382 383 moea64_early_bootstrap(mmup, kernelstart, kernelend); 384 385 /* 386 * Allocate PTEG table. 387 */ 388 389 size = moea64_pteg_count * sizeof(struct lpteg); 390 CTR2(KTR_PMAP, "moea64_bootstrap: %d PTEGs, %d bytes", 391 moea64_pteg_count, size); 392 393 /* 394 * We now need to allocate memory. This memory, to be allocated, 395 * has to reside in a page table. The page table we are about to 396 * allocate. We don't have BAT. So drop to data real mode for a minute 397 * as a measure of last resort. We do this a couple times. 398 */ 399 400 moea64_pteg_table = (struct lpteg *)moea64_bootstrap_alloc(size, size); 401 DISABLE_TRANS(msr); 402 bzero((void *)moea64_pteg_table, moea64_pteg_count * sizeof(struct lpteg)); 403 ENABLE_TRANS(msr); 404 405 CTR1(KTR_PMAP, "moea64_bootstrap: PTEG table at %p", moea64_pteg_table); 406 407 /* 408 * Initialize the TLBIE lock. TLBIE can only be executed by one CPU. 409 */ 410 mtx_init(&tlbie_mutex, "tlbie mutex", NULL, MTX_SPIN); 411 412 moea64_mid_bootstrap(mmup, kernelstart, kernelend); 413 414 /* 415 * Add a mapping for the page table itself if there is no direct map. 416 */ 417 if (!hw_direct_map) { 418 size = moea64_pteg_count * sizeof(struct lpteg); 419 off = (vm_offset_t)(moea64_pteg_table); 420 DISABLE_TRANS(msr); 421 for (pa = off; pa < off + size; pa += PAGE_SIZE) 422 pmap_kenter(pa, pa); 423 ENABLE_TRANS(msr); 424 } 425 426 /* Bring up virtual memory */ 427 moea64_late_bootstrap(mmup, kernelstart, kernelend); 428 } 429 430 static void 431 tlbia(void) 432 { 433 vm_offset_t i; 434 #ifndef __powerpc64__ 435 register_t msr, scratch; 436 #endif 437 438 TLBSYNC(); 439 440 for (i = 0; i < 0xFF000; i += 0x00001000) { 441 #ifdef __powerpc64__ 442 __asm __volatile("tlbiel %0" :: "r"(i)); 443 #else 444 __asm __volatile("\ 445 mfmsr %0; \ 446 mr %1, %0; \ 447 insrdi %1,%3,1,0; \ 448 mtmsrd %1; \ 449 isync; \ 450 \ 451 tlbiel %2; \ 452 \ 453 mtmsrd %0; \ 454 isync;" 455 : "=r"(msr), "=r"(scratch) : "r"(i), "r"(1)); 456 #endif 457 } 458 459 EIEIO(); 460 TLBSYNC(); 461 } 462 463 static uintptr_t 464 moea64_pvo_to_pte_native(mmu_t mmu, const struct pvo_entry *pvo) 465 { 466 struct lpte *pt; 467 int pteidx, ptegidx; 468 uint64_t vsid; 469 470 /* If the PTEG index is not set, then there is no page table entry */ 471 if (!PVO_PTEGIDX_ISSET(pvo)) 472 return (-1); 473 474 /* 475 * Calculate the ptegidx 476 */ 477 vsid = PVO_VSID(pvo); 478 ptegidx = va_to_pteg(vsid, PVO_VADDR(pvo), 479 pvo->pvo_vaddr & PVO_LARGE); 480 481 /* 482 * We can find the actual pte entry without searching by grabbing 483 * the PTEG index from 3 unused bits in pvo_vaddr and by 484 * noticing the HID bit. 485 */ 486 if (pvo->pvo_pte.lpte.pte_hi & LPTE_HID) 487 ptegidx ^= moea64_pteg_mask; 488 489 pteidx = (ptegidx << 3) | PVO_PTEGIDX_GET(pvo); 490 491 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) && 492 !PVO_PTEGIDX_ISSET(pvo)) { 493 panic("moea64_pvo_to_pte: pvo %p has valid pte in pvo but no " 494 "valid pte index", pvo); 495 } 496 497 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0 && 498 PVO_PTEGIDX_ISSET(pvo)) { 499 panic("moea64_pvo_to_pte: pvo %p has valid pte index in pvo " 500 "pvo but no valid pte", pvo); 501 } 502 503 pt = &moea64_pteg_table[pteidx >> 3].pt[pteidx & 7]; 504 if ((pt->pte_hi ^ (pvo->pvo_pte.lpte.pte_hi & ~LPTE_VALID)) == 505 LPTE_VALID) { 506 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0) { 507 panic("moea64_pvo_to_pte: pvo %p has valid pte in " 508 "moea64_pteg_table %p but invalid in pvo", pvo, pt); 509 } 510 511 if (((pt->pte_lo ^ pvo->pvo_pte.lpte.pte_lo) & 512 ~(LPTE_M|LPTE_CHG|LPTE_REF)) != 0) { 513 panic("moea64_pvo_to_pte: pvo %p pte does not match " 514 "pte %p in moea64_pteg_table difference is %#x", 515 pvo, pt, 516 (uint32_t)(pt->pte_lo ^ pvo->pvo_pte.lpte.pte_lo)); 517 } 518 519 return ((uintptr_t)pt); 520 } 521 522 if (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) { 523 panic("moea64_pvo_to_pte: pvo %p has invalid pte %p in " 524 "moea64_pteg_table but valid in pvo", pvo, pt); 525 } 526 527 return (-1); 528 } 529 530 static __inline int 531 moea64_pte_spillable_ident(u_int ptegidx) 532 { 533 struct lpte *pt; 534 int i, j, k; 535 536 /* Start at a random slot */ 537 i = mftb() % 8; 538 k = -1; 539 for (j = 0; j < 8; j++) { 540 pt = &moea64_pteg_table[ptegidx].pt[(i + j) % 8]; 541 if (pt->pte_hi & (LPTE_LOCKED | LPTE_WIRED)) 542 continue; 543 544 /* This is a candidate, so remember it */ 545 k = (i + j) % 8; 546 547 /* Try to get a page that has not been used lately */ 548 if (!(pt->pte_lo & LPTE_REF)) 549 return (k); 550 } 551 552 return (k); 553 } 554 555 static int 556 moea64_pte_insert_native(mmu_t mmu, u_int ptegidx, struct lpte *pvo_pt) 557 { 558 struct lpte *pt; 559 struct pvo_entry *pvo; 560 u_int pteg_bktidx; 561 int i; 562 563 /* 564 * First try primary hash. 565 */ 566 pteg_bktidx = ptegidx; 567 for (pt = moea64_pteg_table[pteg_bktidx].pt, i = 0; i < 8; i++, pt++) { 568 if ((pt->pte_hi & (LPTE_VALID | LPTE_LOCKED)) == 0) { 569 pvo_pt->pte_hi &= ~LPTE_HID; 570 moea64_pte_set_native(pt, pvo_pt); 571 return (i); 572 } 573 } 574 575 /* 576 * Now try secondary hash. 577 */ 578 pteg_bktidx ^= moea64_pteg_mask; 579 for (pt = moea64_pteg_table[pteg_bktidx].pt, i = 0; i < 8; i++, pt++) { 580 if ((pt->pte_hi & (LPTE_VALID | LPTE_LOCKED)) == 0) { 581 pvo_pt->pte_hi |= LPTE_HID; 582 moea64_pte_set_native(pt, pvo_pt); 583 return (i); 584 } 585 } 586 587 /* 588 * Out of luck. Find a PTE to sacrifice. 589 */ 590 pteg_bktidx = ptegidx; 591 i = moea64_pte_spillable_ident(pteg_bktidx); 592 if (i < 0) { 593 pteg_bktidx ^= moea64_pteg_mask; 594 i = moea64_pte_spillable_ident(pteg_bktidx); 595 } 596 597 if (i < 0) { 598 /* No freeable slots in either PTEG? We're hosed. */ 599 panic("moea64_pte_insert: overflow"); 600 return (-1); 601 } 602 603 if (pteg_bktidx == ptegidx) 604 pvo_pt->pte_hi &= ~LPTE_HID; 605 else 606 pvo_pt->pte_hi |= LPTE_HID; 607 608 /* 609 * Synchronize the sacrifice PTE with its PVO, then mark both 610 * invalid. The PVO will be reused when/if the VM system comes 611 * here after a fault. 612 */ 613 pt = &moea64_pteg_table[pteg_bktidx].pt[i]; 614 615 if (pt->pte_hi & LPTE_HID) 616 pteg_bktidx ^= moea64_pteg_mask; /* PTEs indexed by primary */ 617 618 LIST_FOREACH(pvo, &moea64_pvo_table[pteg_bktidx], pvo_olink) { 619 if (pvo->pvo_pte.lpte.pte_hi == pt->pte_hi) { 620 KASSERT(pvo->pvo_pte.lpte.pte_hi & LPTE_VALID, 621 ("Invalid PVO for valid PTE!")); 622 moea64_pte_unset_native(mmu, (uintptr_t)pt, 623 &pvo->pvo_pte.lpte, pvo->pvo_vpn); 624 PVO_PTEGIDX_CLR(pvo); 625 moea64_pte_overflow++; 626 break; 627 } 628 } 629 630 KASSERT(pvo->pvo_pte.lpte.pte_hi == pt->pte_hi, 631 ("Unable to find PVO for spilled PTE")); 632 633 /* 634 * Set the new PTE. 635 */ 636 moea64_pte_set_native(pt, pvo_pt); 637 638 return (i); 639 } 640 641