1# 2# NOTES -- Lines that can be cut/pasted into kernel and hints configs. 3# 4# This file contains machine dependent kernel configuration notes. For 5# machine independent notes, look in /sys/conf/NOTES. For notes shared 6# with amd64, look in /sys/x86/conf/NOTES. 7# 8# 9 10 11##################################################################### 12# SMP OPTIONS: 13# 14# The apic device enables the use of the I/O APIC for interrupt delivery. 15# The apic device can be used in both UP and SMP kernels, but is required 16# for SMP kernels. Thus, the apic device is not strictly an SMP option, 17# but it is a prerequisite for SMP. 18# 19# Notes: 20# 21# HTT CPUs should only be used if they are enabled in the BIOS. For 22# the ACPI case, ACPI only correctly tells us about any HTT CPUs if 23# they are enabled. However, most HTT systems do not list HTT CPUs 24# in the MP Table if they are enabled, thus we guess at the HTT CPUs 25# for the MP Table case. However, we shouldn't try to guess and use 26# these CPUs if HTT is disabled. Thus, HTT guessing is only enabled 27# for the MP Table if the user explicitly asks for it via the 28# MPTABLE_FORCE_HTT option. Do NOT use this option if you have HTT 29# disabled in your BIOS. 30# 31# IPI_PREEMPTION instructs the kernel to preempt threads running on other 32# CPUS if needed. Relies on the PREEMPTION option 33 34# Mandatory: 35device apic # I/O apic 36 37# Optional: 38options MPTABLE_FORCE_HTT # Enable HTT CPUs with the MP Table 39 40 41##################################################################### 42# CPU OPTIONS 43 44# 45# You must specify at least one CPU (the one you intend to run on); 46# deleting the specification for CPUs you don't need to use may make 47# parts of the system run faster. 48# 49cpu I486_CPU 50cpu I586_CPU # aka Pentium(tm) 51cpu I686_CPU # aka Pentium Pro(tm) 52 53# 54# Options for CPU features. 55# 56# CPU_ATHLON_SSE_HACK tries to enable SSE instructions when the BIOS has 57# forgotten to enable them. 58# 59# CPU_BLUELIGHTNING_3X enables triple-clock mode on IBM Blue Lightning 60# CPU if CPU supports it. The default is double-clock mode on 61# BlueLightning CPU box. 62# 63# CPU_BLUELIGHTNING_FPU_OP_CACHE enables FPU operand cache on IBM 64# BlueLightning CPU. It works only with Cyrix FPU, and this option 65# should not be used with Intel FPU. 66# 67# CPU_BTB_EN enables branch target buffer on Cyrix 5x86 (NOTE 1). 68# 69# CPU_CYRIX_NO_LOCK enables weak locking for the entire address space 70# of Cyrix 6x86 and 6x86MX CPUs by setting the NO_LOCK bit of CCR1. 71# Otherwise, the NO_LOCK bit of CCR1 is cleared. (NOTE 3) 72# 73# CPU_DIRECT_MAPPED_CACHE sets L1 cache of Cyrix 486DLC CPU in direct 74# mapped mode. Default is 2-way set associative mode. 75# 76# CPU_DISABLE_5X86_LSSER disables load store serialize (i.e., enables 77# reorder). This option should not be used if you use memory mapped 78# I/O device(s). 79# 80# CPU_ELAN enables support for AMDs ElanSC520 CPU. 81# CPU_ELAN_PPS enables precision timestamp code. 82# CPU_ELAN_XTAL sets the clock crystal frequency in Hz. 83# 84# CPU_ENABLE_LONGRUN enables support for Transmeta Crusoe LongRun 85# technology which allows to restrict power consumption of the CPU by 86# using group of hw.crusoe.* sysctls. 87# 88# CPU_FASTER_5X86_FPU enables faster FPU exception handler. 89# 90# CPU_GEODE is for the SC1100 Geode embedded processor. This option 91# is necessary because the i8254 timecounter is toast. 92# 93# CPU_I486_ON_386 enables CPU cache on i486 based CPU upgrade products 94# for i386 machines. 95# 96# CPU_IORT defines I/O clock delay time (NOTE 1). Default values of 97# I/O clock delay time on Cyrix 5x86 and 6x86 are 0 and 7,respectively 98# (no clock delay). 99# 100# CPU_L2_LATENCY specifies the L2 cache latency value. This option is used 101# only when CPU_PPRO2CELERON is defined and Mendocino Celeron is detected. 102# The default value is 5. 103# 104# CPU_LOOP_EN prevents flushing the prefetch buffer if the destination 105# of a jump is already present in the prefetch buffer on Cyrix 5x86(NOTE 106# 1). 107# 108# CPU_PPRO2CELERON enables L2 cache of Mendocino Celeron CPUs. This option 109# is useful when you use Socket 8 to Socket 370 converter, because most Pentium 110# Pro BIOSs do not enable L2 cache of Mendocino Celeron CPUs. 111# 112# CPU_RSTK_EN enables return stack on Cyrix 5x86 (NOTE 1). 113# 114# CPU_SOEKRIS enables support www.soekris.com hardware. 115# 116# CPU_SUSP_HLT enables suspend on HALT. If this option is set, CPU 117# enters suspend mode following execution of HALT instruction. 118# 119# CPU_UPGRADE_HW_CACHE eliminates unneeded cache flush instruction(s). 120# 121# CPU_WT_ALLOC enables write allocation on Cyrix 6x86/6x86MX and AMD 122# K5/K6/K6-2 CPUs. 123# 124# CYRIX_CACHE_WORKS enables CPU cache on Cyrix 486 CPUs with cache 125# flush at hold state. 126# 127# CYRIX_CACHE_REALLY_WORKS enables (1) CPU cache on Cyrix 486 CPUs 128# without cache flush at hold state, and (2) write-back CPU cache on 129# Cyrix 6x86 whose revision < 2.7 (NOTE 2). 130# 131# NO_F00F_HACK disables the hack that prevents Pentiums (and ONLY 132# Pentiums) from locking up when a LOCK CMPXCHG8B instruction is 133# executed. This option is only needed if I586_CPU is also defined, 134# and should be included for any non-Pentium CPU that defines it. 135# 136# NO_MEMORY_HOLE is an optimisation for systems with AMD K6 processors 137# which indicates that the 15-16MB range is *definitely* not being 138# occupied by an ISA memory hole. 139# 140# NOTE 1: The options, CPU_BTB_EN, CPU_LOOP_EN, CPU_IORT, 141# CPU_LOOP_EN and CPU_RSTK_EN should not be used because of CPU bugs. 142# These options may crash your system. 143# 144# NOTE 2: If CYRIX_CACHE_REALLY_WORKS is not set, CPU cache is enabled 145# in write-through mode when revision < 2.7. If revision of Cyrix 146# 6x86 >= 2.7, CPU cache is always enabled in write-back mode. 147# 148# NOTE 3: This option may cause failures for software that requires 149# locked cycles in order to operate correctly. 150# 151options CPU_ATHLON_SSE_HACK 152options CPU_BLUELIGHTNING_3X 153options CPU_BLUELIGHTNING_FPU_OP_CACHE 154options CPU_BTB_EN 155options CPU_DIRECT_MAPPED_CACHE 156options CPU_DISABLE_5X86_LSSER 157options CPU_ELAN 158options CPU_ELAN_PPS 159options CPU_ELAN_XTAL=32768000 160options CPU_ENABLE_LONGRUN 161options CPU_FASTER_5X86_FPU 162options CPU_GEODE 163options CPU_I486_ON_386 164options CPU_IORT 165options CPU_L2_LATENCY=5 166options CPU_LOOP_EN 167options CPU_PPRO2CELERON 168options CPU_RSTK_EN 169options CPU_SOEKRIS 170options CPU_SUSP_HLT 171options CPU_UPGRADE_HW_CACHE 172options CPU_WT_ALLOC 173options CYRIX_CACHE_WORKS 174options CYRIX_CACHE_REALLY_WORKS 175#options NO_F00F_HACK 176 177# Debug options 178options NPX_DEBUG # enable npx debugging 179 180# 181# PERFMON causes the driver for Pentium/Pentium Pro performance counters 182# to be compiled. See perfmon(4) for more information. 183# 184options PERFMON 185 186# 187# Hints for the non-optional Numeric Processing eXtension driver. 188envvar hint.npx.0.flags="0x0" 189envvar hint.npx.0.irq="13" 190 191# 192# `flags' for npx0: 193# 0x01 don't use the npx registers to optimize bcopy. 194# 0x02 don't use the npx registers to optimize bzero. 195# 0x04 don't use the npx registers to optimize copyin or copyout. 196# The npx registers are normally used to optimize copying and zeroing when 197# all of the following conditions are satisfied: 198# I586_CPU is an option 199# the cpu is an i586 (perhaps not a Pentium) 200# the probe for npx0 succeeds 201# INT 16 exception handling works. 202# Then copying and zeroing using the npx registers is normally 30-100% faster. 203# The flags can be used to control cases where it doesn't work or is slower. 204# Setting them at boot time using hints works right (the optimizations 205# are not used until later in the bootstrap when npx0 is attached). 206# Flag 0x08 automatically disables the i586 optimized routines. 207# 208 209 210##################################################################### 211# HARDWARE DEVICE CONFIGURATION 212 213# 214# Optional devices: 215# 216 217# 3Dfx Voodoo Graphics, Voodoo II /dev/3dfx CDEV support. This will create 218# the /dev/3dfx0 device to work with glide implementations. This should get 219# linked to /dev/3dfx and /dev/voodoo. Note that this is not the same as 220# the tdfx DRI module from XFree86 and is completely unrelated. 221# 222# To enable Linuxulator support, one must also load linux.ko and tdfx_linux.ko. 223 224device tdfx # Enable 3Dfx Voodoo support 225 226# 227# RAID adapters 228# 229device pst 230 231# 232# Adaptec by PMC RAID controllers, Series 6/7/8 and upcoming families 233device aacraid # Container interface, CAM required 234 235# 236# Network interfaces: 237# 238 239# sbni: Granch SBNI12-xx ISA and PCI adapters 240# vmx: VMware VMXNET3 Ethernet (BSD open source) 241# wpi: Intel 3945ABG Wireless LAN controller 242# Requires the wpi firmware module 243 244# Order for ISA/EISA devices is important here 245 246envvar hint.cs.0.at="isa" 247envvar hint.cs.0.port="0x300" 248envvar hint.ed.0.at="isa" 249envvar hint.ed.0.port="0x280" 250envvar hint.ed.0.irq="5" 251envvar hint.ed.0.maddr="0xd8000" 252# Hint for the i386-only ISA front-end of le(4). 253envvar hint.le.0.at="isa" 254envvar hint.le.0.port="0x280" 255envvar hint.le.0.irq="10" 256envvar hint.le.0.drq="0" 257device sbni 258envvar hint.sbni.0.at="isa" 259envvar hint.sbni.0.port="0x210" 260envvar hint.sbni.0.irq="0xefdead" 261envvar hint.sbni.0.flags="0" 262 263##################################################################### 264 265# 266# Miscellaneous hardware: 267# 268# smapi: System Management Application Program Interface driver 269 270device smapi 271 272# 273# Laptop/Notebook options: 274# 275# See also: 276# apm under `Miscellaneous hardware' 277# above. 278 279# For older notebooks that signal a powerfail condition (external 280# power supply dropped, or battery state low) by issuing an NMI: 281 282options POWERFAIL_NMI # make it beep instead of panicing 283 284# 285# I2C Bus 286# 287# Requires 'device iicbus'. 288# 289# Supported interfaces: 290# glxiic: AMD Geode LX CS5536 System Management Bus 291# pcf: Philips PCF8584 ISA-bus controller 292# 293device glxiic # AMD Geode LX CS5536 System Management Bus 294device pcf 295envvar hint.pcf.0.at="isa" 296envvar hint.pcf.0.port="0x320" 297envvar hint.pcf.0.irq="5" 298 299# 300# glxsb is a driver for the Security Block in AMD Geode LX processors. 301# Requires 'device crypto'. 302# 303device glxsb # AMD Geode LX Security Block 304 305##################################################################### 306# ABI Emulation 307 308# Enable (32-bit) a.out binary support 309options COMPAT_AOUT 310 311##################################################################### 312# VM OPTIONS 313 314# 315# Set the number of PV entries per process. Increasing this can 316# stop panics related to heavy use of shared memory. However, that can 317# (combined with large amounts of physical memory) cause panics at 318# boot time due the kernel running out of VM space. 319# 320# If you're tweaking this, you might also want to increase the sysctls 321# "vm.v_free_min", "vm.v_free_reserved", and "vm.v_free_target". 322# 323# The value below is the one more than the default. 324# 325options PMAP_SHPGPERPROC=201 326 327# 328# Number of initial kernel page table pages used for early bootstrap. 329# This number should include enough pages to map the kernel, any 330# modules or other data loaded with the kernel by the loader, and data 331# structures allocated before the VM system is initialized such as the 332# vm_page_t array. Each page table page maps 4MB (2MB with PAE). 333# 334options NKPT=31 335 336# KSTACK_PAGES is the number of memory pages to assign to the kernel 337# stack of each thread. 338 339options KSTACK_PAGES=5 340 341# Enable detailed accounting by the PV entry allocator. 342 343options PV_STATS 344 345##################################################################### 346# Items broken on i386 that are generally available elsewhere 347 348# Device uses bus_read_8 and friends, so can't work. Remove it from lint. 349nodevice bnxt 350