1/* 2 * P2020 DS Device Tree Source 3 * 4 * Copyright 2009 Freescale Semiconductor Inc. 5 * 6 * Neither the name of Freescale Semiconductor, Inc nor the names of 7 * its contributors may be used to endorse or promote products derived 8 * from this software without specific prior written permission. 9 * 10 * Freescale hereby publishes it under the following licenses: 11 * 12 * BSD License 13 * 14 * Redistribution and use in source and binary forms, with or 15 * without modification, are permitted provided that the following 16 * conditions are met: 17 * 18 * Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 21 * Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in 23 * the documentation and/or other materials provided with the 24 * distribution. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND 27 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 29 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 30 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 33 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 35 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 * 40 * GNU General Public License, version 2 41 * 42 * This program is free software; you can redistribute it and/or 43 * modify it under the terms of the GNU General Public License 44 * as published by the Free Software Foundation; either version 2 45 * of the License, or (at your option) any later version. 46 * 47 * This program is distributed in the hope that it will be useful, 48 * but WITHOUT ANY WARRANTY; without even the implied warranty of 49 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 50 * GNU General Public License for more details. 51 * 52 * You should have received a copy of the GNU General Public License 53 * along with this program; if not, write to the Free Software 54 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 55 * MA 02110-1301, USA. 56 * 57 * You may select the license of your choice. 58 *------------------------------------------------------------------ 59 */ 60/* $FreeBSD$ */ 61 62/dts-v1/; 63/ { 64 model = "fsl,P2020"; 65 compatible = "fsl,P2020DS"; 66 #address-cells = <2>; 67 #size-cells = <2>; 68 69 aliases { 70 ethernet0 = &enet0; 71 ethernet1 = &enet1; 72 ethernet2 = &enet2; 73 serial0 = &serial0; 74 serial1 = &serial1; 75 pci0 = &pci0; 76 pci1 = &pci1; 77 pci2 = &pci2; 78 }; 79 80 cpus { 81 #address-cells = <1>; 82 #size-cells = <0>; 83 84 PowerPC,P2020@0 { 85 device_type = "cpu"; 86 reg = <0x0>; 87 next-level-cache = <&L2>; 88 }; 89 90 PowerPC,P2020@1 { 91 device_type = "cpu"; 92 reg = <0x1>; 93 next-level-cache = <&L2>; 94 }; 95 }; 96 97 memory { 98 device_type = "memory"; 99 }; 100 101 localbus@ffe05000 { 102 #address-cells = <2>; 103 #size-cells = <1>; 104 compatible = "fsl,elbc", "simple-bus"; 105 reg = <0 0xffe05000 0 0x1000>; 106 interrupts = <19 2>; 107 interrupt-parent = <&mpic>; 108 109 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000 110 0x1 0x0 0x0 0xe0000000 0x08000000 111 0x2 0x0 0x0 0xffa00000 0x00040000 112 0x3 0x0 0x0 0xffdf0000 0x00008000 113 0x4 0x0 0x0 0xffa40000 0x00040000 114 0x5 0x0 0x0 0xffa80000 0x00040000 115 0x6 0x0 0x0 0xffac0000 0x00040000>; 116 117 nor@0,0 { 118 #address-cells = <1>; 119 #size-cells = <1>; 120 compatible = "cfi-flash"; 121 reg = <0x0 0x0 0x8000000>; 122 bank-width = <2>; 123 device-width = <1>; 124 125 ramdisk@0 { 126 reg = <0x0 0x03000000>; 127 read-only; 128 }; 129 130 diagnostic@3000000 { 131 reg = <0x03000000 0x00e00000>; 132 read-only; 133 }; 134 135 dink@3e00000 { 136 reg = <0x03e00000 0x00200000>; 137 read-only; 138 }; 139 140 kernel@4000000 { 141 reg = <0x04000000 0x00400000>; 142 read-only; 143 }; 144 145 jffs2@4400000 { 146 reg = <0x04400000 0x03b00000>; 147 }; 148 149 dtb@7f00000 { 150 reg = <0x07f00000 0x00080000>; 151 read-only; 152 }; 153 154 u-boot@7f80000 { 155 reg = <0x07f80000 0x00080000>; 156 read-only; 157 }; 158 }; 159 160 nand@2,0 { 161 #address-cells = <1>; 162 #size-cells = <1>; 163 compatible = "fsl,elbc-fcm-nand"; 164 reg = <0x2 0x0 0x40000>; 165 166 u-boot@0 { 167 reg = <0x0 0x02000000>; 168 read-only; 169 }; 170 171 jffs2@2000000 { 172 reg = <0x02000000 0x10000000>; 173 }; 174 175 ramdisk@12000000 { 176 reg = <0x12000000 0x08000000>; 177 read-only; 178 }; 179 180 kernel@1a000000 { 181 reg = <0x1a000000 0x04000000>; 182 }; 183 184 dtb@1e000000 { 185 reg = <0x1e000000 0x01000000>; 186 read-only; 187 }; 188 189 empty@1f000000 { 190 reg = <0x1f000000 0x21000000>; 191 }; 192 }; 193 194 nand@4,0 { 195 compatible = "fsl,elbc-fcm-nand"; 196 reg = <0x4 0x0 0x40000>; 197 }; 198 199 nand@5,0 { 200 compatible = "fsl,elbc-fcm-nand"; 201 reg = <0x5 0x0 0x40000>; 202 }; 203 204 nand@6,0 { 205 compatible = "fsl,elbc-fcm-nand"; 206 reg = <0x6 0x0 0x40000>; 207 }; 208 }; 209 210 soc@ffe00000 { 211 #address-cells = <1>; 212 #size-cells = <1>; 213 device_type = "soc"; 214 compatible = "fsl,p2020-immr", "simple-bus"; 215 ranges = <0x0 0 0xffe00000 0x100000>; 216 bus-frequency = <0>; // Filled out by uboot. 217 218 ecm-law@0 { 219 compatible = "fsl,ecm-law"; 220 reg = <0x0 0x1000>; 221 fsl,num-laws = <12>; 222 }; 223 224 ecm@1000 { 225 compatible = "fsl,p2020-ecm", "fsl,ecm"; 226 reg = <0x1000 0x1000>; 227 interrupts = <17 2>; 228 interrupt-parent = <&mpic>; 229 }; 230 231 memory-controller@2000 { 232 compatible = "fsl,p2020-memory-controller"; 233 reg = <0x2000 0x1000>; 234 interrupt-parent = <&mpic>; 235 interrupts = <18 2>; 236 }; 237 238 i2c@3000 { 239 #address-cells = <1>; 240 #size-cells = <0>; 241 cell-index = <0>; 242 compatible = "fsl-i2c"; 243 reg = <0x3000 0x100>; 244 interrupts = <43 2>; 245 interrupt-parent = <&mpic>; 246 dfsrr; 247 }; 248 249 i2c@3100 { 250 #address-cells = <1>; 251 #size-cells = <0>; 252 cell-index = <1>; 253 compatible = "fsl-i2c"; 254 reg = <0x3100 0x100>; 255 interrupts = <43 2>; 256 interrupt-parent = <&mpic>; 257 dfsrr; 258 }; 259 260 serial0: serial@4500 { 261 cell-index = <0>; 262 device_type = "serial"; 263 compatible = "ns16550"; 264 reg = <0x4500 0x100>; 265 clock-frequency = <0>; 266 interrupts = <42 2>; 267 interrupt-parent = <&mpic>; 268 }; 269 270 serial1: serial@4600 { 271 cell-index = <1>; 272 device_type = "serial"; 273 compatible = "ns16550"; 274 reg = <0x4600 0x100>; 275 clock-frequency = <0>; 276 interrupts = <42 2>; 277 interrupt-parent = <&mpic>; 278 }; 279 280 spi@7000 { 281 compatible = "fsl,espi"; 282 reg = <0x7000 0x1000>; 283 interrupts = <59 0x2>; 284 interrupt-parent = <&mpic>; 285 }; 286 287 dma@c300 { 288 #address-cells = <1>; 289 #size-cells = <1>; 290 compatible = "fsl,eloplus-dma"; 291 reg = <0xc300 0x4>; 292 ranges = <0x0 0xc100 0x200>; 293 cell-index = <1>; 294 dma-channel@0 { 295 compatible = "fsl,eloplus-dma-channel"; 296 reg = <0x0 0x80>; 297 cell-index = <0>; 298 interrupt-parent = <&mpic>; 299 interrupts = <76 2>; 300 }; 301 dma-channel@80 { 302 compatible = "fsl,eloplus-dma-channel"; 303 reg = <0x80 0x80>; 304 cell-index = <1>; 305 interrupt-parent = <&mpic>; 306 interrupts = <77 2>; 307 }; 308 dma-channel@100 { 309 compatible = "fsl,eloplus-dma-channel"; 310 reg = <0x100 0x80>; 311 cell-index = <2>; 312 interrupt-parent = <&mpic>; 313 interrupts = <78 2>; 314 }; 315 dma-channel@180 { 316 compatible = "fsl,eloplus-dma-channel"; 317 reg = <0x180 0x80>; 318 cell-index = <3>; 319 interrupt-parent = <&mpic>; 320 interrupts = <79 2>; 321 }; 322 }; 323 324 gpio: gpio-controller@f000 { 325 #gpio-cells = <2>; 326 compatible = "fsl,mpc8572-gpio"; 327 reg = <0xf000 0x100>; 328 interrupts = <47 0x2>; 329 interrupt-parent = <&mpic>; 330 gpio-controller; 331 }; 332 333 L2: l2-cache-controller@20000 { 334 compatible = "fsl,p2020-l2-cache-controller"; 335 reg = <0x20000 0x1000>; 336 cache-line-size = <32>; // 32 bytes 337 cache-size = <0x80000>; // L2, 512k 338 interrupt-parent = <&mpic>; 339 interrupts = <16 2>; 340 }; 341 342 dma@21300 { 343 #address-cells = <1>; 344 #size-cells = <1>; 345 compatible = "fsl,eloplus-dma"; 346 reg = <0x21300 0x4>; 347 ranges = <0x0 0x21100 0x200>; 348 cell-index = <0>; 349 dma-channel@0 { 350 compatible = "fsl,eloplus-dma-channel"; 351 reg = <0x0 0x80>; 352 cell-index = <0>; 353 interrupt-parent = <&mpic>; 354 interrupts = <20 2>; 355 }; 356 dma-channel@80 { 357 compatible = "fsl,eloplus-dma-channel"; 358 reg = <0x80 0x80>; 359 cell-index = <1>; 360 interrupt-parent = <&mpic>; 361 interrupts = <21 2>; 362 }; 363 dma-channel@100 { 364 compatible = "fsl,eloplus-dma-channel"; 365 reg = <0x100 0x80>; 366 cell-index = <2>; 367 interrupt-parent = <&mpic>; 368 interrupts = <22 2>; 369 }; 370 dma-channel@180 { 371 compatible = "fsl,eloplus-dma-channel"; 372 reg = <0x180 0x80>; 373 cell-index = <3>; 374 interrupt-parent = <&mpic>; 375 interrupts = <23 2>; 376 }; 377 }; 378 379 usb@22000 { 380 #address-cells = <1>; 381 #size-cells = <0>; 382 compatible = "fsl-usb2-dr"; 383 reg = <0x22000 0x1000>; 384 interrupt-parent = <&mpic>; 385 interrupts = <28 0x2>; 386 phy_type = "ulpi"; 387 }; 388 389 enet0: ethernet@24000 { 390 #address-cells = <1>; 391 #size-cells = <1>; 392 cell-index = <0>; 393 device_type = "network"; 394 model = "eTSEC"; 395 compatible = "gianfar"; 396 reg = <0x24000 0x1000>; 397 ranges = <0x0 0x24000 0x1000>; 398 local-mac-address = [ 00 00 00 00 00 00 ]; 399 interrupts = <29 2 30 2 34 2>; 400 interrupt-parent = <&mpic>; 401 tbi-handle = <&tbi0>; 402 phy-handle = <&phy0>; 403 phy-connection-type = "rgmii-id"; 404 405 mdio@520 { 406 #address-cells = <1>; 407 #size-cells = <0>; 408 compatible = "fsl,gianfar-mdio"; 409 reg = <0x520 0x20>; 410 411 phy0: ethernet-phy@0 { 412 interrupt-parent = <&mpic>; 413 interrupts = <3 1>; 414 reg = <0x0>; 415 }; 416 phy1: ethernet-phy@1 { 417 interrupt-parent = <&mpic>; 418 interrupts = <3 1>; 419 reg = <0x1>; 420 }; 421 phy2: ethernet-phy@2 { 422 interrupt-parent = <&mpic>; 423 interrupts = <3 1>; 424 reg = <0x2>; 425 }; 426 tbi0: tbi-phy@11 { 427 reg = <0x11>; 428 device_type = "tbi-phy"; 429 }; 430 }; 431 }; 432 433 enet1: ethernet@25000 { 434 #address-cells = <1>; 435 #size-cells = <1>; 436 cell-index = <1>; 437 device_type = "network"; 438 model = "eTSEC"; 439 compatible = "gianfar"; 440 reg = <0x25000 0x1000>; 441 ranges = <0x0 0x25000 0x1000>; 442 local-mac-address = [ 00 00 00 00 00 00 ]; 443 interrupts = <35 2 36 2 40 2>; 444 interrupt-parent = <&mpic>; 445 tbi-handle = <&tbi1>; 446 phy-handle = <&phy1>; 447 phy-connection-type = "rgmii-id"; 448 449 mdio@520 { 450 #address-cells = <1>; 451 #size-cells = <0>; 452 compatible = "fsl,gianfar-tbi"; 453 reg = <0x520 0x20>; 454 455 tbi1: tbi-phy@11 { 456 reg = <0x11>; 457 device_type = "tbi-phy"; 458 }; 459 }; 460 }; 461 462 enet2: ethernet@26000 { 463 #address-cells = <1>; 464 #size-cells = <1>; 465 cell-index = <2>; 466 device_type = "network"; 467 model = "eTSEC"; 468 compatible = "gianfar"; 469 reg = <0x26000 0x1000>; 470 ranges = <0x0 0x26000 0x1000>; 471 local-mac-address = [ 00 00 00 00 00 00 ]; 472 interrupts = <31 2 32 2 33 2>; 473 interrupt-parent = <&mpic>; 474 tbi-handle = <&tbi2>; 475 phy-handle = <&phy2>; 476 phy-connection-type = "rgmii-id"; 477 478 mdio@520 { 479 #address-cells = <1>; 480 #size-cells = <0>; 481 compatible = "fsl,gianfar-tbi"; 482 reg = <0x520 0x20>; 483 484 tbi2: tbi-phy@11 { 485 reg = <0x11>; 486 device_type = "tbi-phy"; 487 }; 488 }; 489 }; 490 491 sdhci@2e000 { 492 compatible = "fsl,p2020-esdhc", "fsl,esdhc"; 493 reg = <0x2e000 0x1000>; 494 interrupts = <72 0x2>; 495 interrupt-parent = <&mpic>; 496 /* Filled in by U-Boot */ 497 clock-frequency = <0>; 498 }; 499 500 crypto@30000 { 501 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4", 502 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0"; 503 reg = <0x30000 0x10000>; 504 interrupts = <45 2 58 2>; 505 interrupt-parent = <&mpic>; 506 fsl,num-channels = <4>; 507 fsl,channel-fifo-len = <24>; 508 fsl,exec-units-mask = <0xbfe>; 509 fsl,descriptor-types-mask = <0x3ab0ebf>; 510 }; 511 512 mpic: pic@40000 { 513 interrupt-controller; 514 #address-cells = <0>; 515 #interrupt-cells = <2>; 516 reg = <0x40000 0x40000>; 517 compatible = "chrp,open-pic"; 518 device_type = "open-pic"; 519 }; 520 521 msi@41600 { 522 compatible = "fsl,mpic-msi"; 523 reg = <0x41600 0x80>; 524 msi-available-ranges = <0 0x100>; 525 interrupts = < 526 0xe0 0 527 0xe1 0 528 0xe2 0 529 0xe3 0 530 0xe4 0 531 0xe5 0 532 0xe6 0 533 0xe7 0>; 534 interrupt-parent = <&mpic>; 535 }; 536 537 global-utilities@e0000 { //global utilities block 538 compatible = "fsl,p2020-guts"; 539 reg = <0xe0000 0x1000>; 540 fsl,has-rstcr; 541 }; 542 }; 543 544 pci0: pcie@ffe08000 { 545 compatible = "fsl,mpc8548-pcie"; 546 device_type = "pci"; 547 #interrupt-cells = <1>; 548 #size-cells = <2>; 549 #address-cells = <3>; 550 reg = <0 0xffe08000 0 0x1000>; 551 bus-range = <0 255>; 552 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 553 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; 554 clock-frequency = <33333333>; 555 interrupt-parent = <&mpic>; 556 interrupts = <24 2>; 557 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 558 interrupt-map = < 559 /* IDSEL 0x0 */ 560 0000 0x0 0x0 0x1 &mpic 0x8 0x1 561 0000 0x0 0x0 0x2 &mpic 0x9 0x1 562 0000 0x0 0x0 0x3 &mpic 0xa 0x1 563 0000 0x0 0x0 0x4 &mpic 0xb 0x1 564 >; 565 pcie@0 { 566 reg = <0x0 0x0 0x0 0x0 0x0>; 567 #size-cells = <2>; 568 #address-cells = <3>; 569 device_type = "pci"; 570 ranges = <0x2000000 0x0 0x80000000 571 0x2000000 0x0 0x80000000 572 0x0 0x20000000 573 574 0x1000000 0x0 0x0 575 0x1000000 0x0 0x0 576 0x0 0x10000>; 577 }; 578 }; 579 580 pci1: pcie@ffe09000 { 581 compatible = "fsl,mpc8548-pcie"; 582 device_type = "pci"; 583 #interrupt-cells = <1>; 584 #size-cells = <2>; 585 #address-cells = <3>; 586 reg = <0 0xffe09000 0 0x1000>; 587 bus-range = <0 255>; 588 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 589 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; 590 clock-frequency = <33333333>; 591 interrupt-parent = <&mpic>; 592 interrupts = <25 2>; 593 interrupt-map-mask = <0xff00 0x0 0x0 0x7>; 594 interrupt-map = < 595 596 // IDSEL 0x11 func 0 - PCI slot 1 597 0x8800 0x0 0x0 0x1 &i8259 0x9 0x2 598 0x8800 0x0 0x0 0x2 &i8259 0xa 0x2 599 600 // IDSEL 0x11 func 1 - PCI slot 1 601 0x8900 0x0 0x0 0x1 &i8259 0x9 0x2 602 0x8900 0x0 0x0 0x2 &i8259 0xa 0x2 603 604 // IDSEL 0x11 func 2 - PCI slot 1 605 0x8a00 0x0 0x0 0x1 &i8259 0x9 0x2 606 0x8a00 0x0 0x0 0x2 &i8259 0xa 0x2 607 608 // IDSEL 0x11 func 3 - PCI slot 1 609 0x8b00 0x0 0x0 0x1 &i8259 0x9 0x2 610 0x8b00 0x0 0x0 0x2 &i8259 0xa 0x2 611 612 // IDSEL 0x11 func 4 - PCI slot 1 613 0x8c00 0x0 0x0 0x1 &i8259 0x9 0x2 614 0x8c00 0x0 0x0 0x2 &i8259 0xa 0x2 615 616 // IDSEL 0x11 func 5 - PCI slot 1 617 0x8d00 0x0 0x0 0x1 &i8259 0x9 0x2 618 0x8d00 0x0 0x0 0x2 &i8259 0xa 0x2 619 620 // IDSEL 0x11 func 6 - PCI slot 1 621 0x8e00 0x0 0x0 0x1 &i8259 0x9 0x2 622 0x8e00 0x0 0x0 0x2 &i8259 0xa 0x2 623 624 // IDSEL 0x11 func 7 - PCI slot 1 625 0x8f00 0x0 0x0 0x1 &i8259 0x9 0x2 626 0x8f00 0x0 0x0 0x2 &i8259 0xa 0x2 627 628 // IDSEL 0x1d Audio 629 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2 630 631 // IDSEL 0x1e Legacy 632 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2 633 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2 634 635 // IDSEL 0x1f IDE/SATA 636 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2 637 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2 638 >; 639 640 pcie@0 { 641 reg = <0x0 0x0 0x0 0x0 0x0>; 642 #size-cells = <2>; 643 #address-cells = <3>; 644 device_type = "pci"; 645 ranges = <0x2000000 0x0 0xa0000000 646 0x2000000 0x0 0xa0000000 647 0x0 0x20000000 648 649 0x1000000 0x0 0x0 650 0x1000000 0x0 0x0 651 0x0 0x10000>; 652 uli1575@0 { 653 reg = <0x0 0x0 0x0 0x0 0x0>; 654 #size-cells = <2>; 655 #address-cells = <3>; 656 ranges = <0x2000000 0x0 0xa0000000 657 0x2000000 0x0 0xa0000000 658 0x0 0x20000000 659 660 0x1000000 0x0 0x0 661 0x1000000 0x0 0x0 662 0x0 0x10000>; 663 isa@1e { 664 device_type = "isa"; 665 #interrupt-cells = <2>; 666 #size-cells = <1>; 667 #address-cells = <2>; 668 reg = <0xf000 0x0 0x0 0x0 0x0>; 669 ranges = <0x1 0x0 0x1000000 0x0 0x0 670 0x1000>; 671 interrupt-parent = <&i8259>; 672 673 i8259: interrupt-controller@20 { 674 reg = <0x1 0x20 0x2 675 0x1 0xa0 0x2 676 0x1 0x4d0 0x2>; 677 interrupt-controller; 678 device_type = "interrupt-controller"; 679 #address-cells = <0>; 680 #interrupt-cells = <2>; 681 compatible = "chrp,iic"; 682 interrupts = <4 1>; 683 interrupt-parent = <&mpic>; 684 }; 685 686 i8042@60 { 687 #size-cells = <0>; 688 #address-cells = <1>; 689 reg = <0x1 0x60 0x1 0x1 0x64 0x1>; 690 interrupts = <1 3 12 3>; 691 interrupt-parent = 692 <&i8259>; 693 694 keyboard@0 { 695 reg = <0x0>; 696 compatible = "pnpPNP,303"; 697 }; 698 699 mouse@1 { 700 reg = <0x1>; 701 compatible = "pnpPNP,f03"; 702 }; 703 }; 704 705 rtc@70 { 706 compatible = "pnpPNP,b00"; 707 reg = <0x1 0x70 0x2>; 708 }; 709 710 gpio@400 { 711 reg = <0x1 0x400 0x80>; 712 }; 713 }; 714 }; 715 }; 716 717 }; 718 719 pci2: pcie@ffe0a000 { 720 compatible = "fsl,mpc8548-pcie"; 721 device_type = "pci"; 722 #interrupt-cells = <1>; 723 #size-cells = <2>; 724 #address-cells = <3>; 725 reg = <0 0xffe0a000 0 0x1000>; 726 bus-range = <0 255>; 727 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 728 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; 729 clock-frequency = <33333333>; 730 interrupt-parent = <&mpic>; 731 interrupts = <26 2>; 732 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 733 interrupt-map = < 734 /* IDSEL 0x0 */ 735 0000 0x0 0x0 0x1 &mpic 0x0 0x1 736 0000 0x0 0x0 0x2 &mpic 0x1 0x1 737 0000 0x0 0x0 0x3 &mpic 0x2 0x1 738 0000 0x0 0x0 0x4 &mpic 0x3 0x1 739 >; 740 pcie@0 { 741 reg = <0x0 0x0 0x0 0x0 0x0>; 742 #size-cells = <2>; 743 #address-cells = <3>; 744 device_type = "pci"; 745 ranges = <0x2000000 0x0 0xc0000000 746 0x2000000 0x0 0xc0000000 747 0x0 0x20000000 748 749 0x1000000 0x0 0x0 750 0x1000000 0x0 0x0 751 0x0 0x10000>; 752 }; 753 }; 754}; 755