1/*- 2 * Copyright (c) 2011 The FreeBSD Foundation 3 * Copyright (c) 2012 Andrew Turner 4 * All rights reserved. 5 * 6 * Developed by Damjan Marion <damjan.marion@gmail.com> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 */ 30 31/ { 32 compatible = "compal,paz00", "nvidia,tegra20"; 33 #address-cells = <1>; 34 #size-cells = <1>; 35 interrupt-parent = <&GIC>; 36 37 SOC: tegra20@0 { 38 #address-cells = <1>; 39 #size-cells = <1>; 40 compatible = "simple-bus"; 41 ranges; 42 bus-frequency = <0>; 43 44 GIC: interrupt-controller@50041000 { 45 compatible = "arm,gic"; 46 reg = < 0x50041000 0x1000 >, /* Distributor Registers */ 47 < 0x50040100 0x0100 >; /* CPU Interface Registers */ 48 interrupt-controller; 49 #interrupt-cells = <1>; 50 }; 51 52 mp_tmr@50040200 { 53 compatible = "arm,mpcore-timers"; 54 clock-frequency = < 50040200 >; 55 #address-cells = <1>; 56 #size-cells = <0>; 57 reg = < 0x50040200 0x100 >, /* Global Timer Registers */ 58 < 0x50040600 0x100 >; /* Private Timer Registers */ 59 interrupts = < 27 29 >; 60 interrupt-parent = <&GIC>; 61 }; 62 63 serial@70006000 { 64 compatible = "ns16550"; 65 reg = <0x70006000 0x40>; 66 reg-shift = <2>; 67 interrupts = < 68 >; 68 interrupt-parent = <&GIC>; 69 clock-frequency = < 215654400 >; 70 }; 71 }; 72}; 73 74