1 /*- 2 * SPDX-License-Identifier: (BSD-2-Clause AND BSD-1-Clause) 3 * 4 * Copyright (c) 2006 Sam Leffler, Errno Consulting 5 * Copyright (c) 2008-2009 Weongyo Jeong <weongyo@freebsd.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 16 * redistribution must be conditioned upon including a substantially 17 * similar Disclaimer requirement for further binary redistribution. 18 * 19 * NO WARRANTY 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 23 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 24 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 25 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 28 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGES. 31 */ 32 33 /* 34 * This driver is distantly derived from a driver of the same name 35 * by Damien Bergamini. The original copyright is included below: 36 * 37 * Copyright (c) 2006 38 * Damien Bergamini <damien.bergamini@free.fr> 39 * 40 * Permission to use, copy, modify, and distribute this software for any 41 * purpose with or without fee is hereby granted, provided that the above 42 * copyright notice and this permission notice appear in all copies. 43 * 44 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 45 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 46 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 47 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 48 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 49 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 50 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 51 */ 52 53 /*- 54 * Driver for Atheros AR5523 USB parts. 55 * 56 * The driver requires firmware to be loaded into the device. This 57 * is done on device discovery from a user application (uathload) 58 * that is launched by devd when a device with suitable product ID 59 * is recognized. Once firmware has been loaded the device will 60 * reset the USB port and re-attach with the original product ID+1 61 * and this driver will be attached. The firmware is licensed for 62 * general use (royalty free) and may be incorporated in products. 63 * Note that the firmware normally packaged with the NDIS drivers 64 * for these devices does not work in this way and so does not work 65 * with this driver. 66 */ 67 68 #include "opt_wlan.h" 69 70 #include <sys/param.h> 71 #include <sys/sockio.h> 72 #include <sys/sysctl.h> 73 #include <sys/lock.h> 74 #include <sys/mutex.h> 75 #include <sys/mbuf.h> 76 #include <sys/kernel.h> 77 #include <sys/socket.h> 78 #include <sys/systm.h> 79 #include <sys/malloc.h> 80 #include <sys/module.h> 81 #include <sys/bus.h> 82 #include <sys/endian.h> 83 #include <sys/kdb.h> 84 85 #include <net/bpf.h> 86 #include <net/if.h> 87 #include <net/if_var.h> 88 #include <net/if_arp.h> 89 #include <net/ethernet.h> 90 #include <net/if_dl.h> 91 #include <net/if_media.h> 92 #include <net/if_types.h> 93 94 #ifdef INET 95 #include <netinet/in.h> 96 #include <netinet/in_systm.h> 97 #include <netinet/in_var.h> 98 #include <netinet/if_ether.h> 99 #include <netinet/ip.h> 100 #endif 101 102 #include <net80211/ieee80211_var.h> 103 #include <net80211/ieee80211_input.h> 104 #include <net80211/ieee80211_regdomain.h> 105 #include <net80211/ieee80211_radiotap.h> 106 107 #include <dev/usb/usb.h> 108 #include <dev/usb/usbdi.h> 109 #include "usbdevs.h" 110 111 #include <dev/usb/wlan/if_uathreg.h> 112 #include <dev/usb/wlan/if_uathvar.h> 113 114 static SYSCTL_NODE(_hw_usb, OID_AUTO, uath, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 115 "USB Atheros"); 116 117 static int uath_countrycode = CTRY_DEFAULT; /* country code */ 118 SYSCTL_INT(_hw_usb_uath, OID_AUTO, countrycode, CTLFLAG_RWTUN, &uath_countrycode, 119 0, "country code"); 120 static int uath_regdomain = 0; /* regulatory domain */ 121 SYSCTL_INT(_hw_usb_uath, OID_AUTO, regdomain, CTLFLAG_RD, &uath_regdomain, 122 0, "regulatory domain"); 123 124 #ifdef UATH_DEBUG 125 int uath_debug = 0; 126 SYSCTL_INT(_hw_usb_uath, OID_AUTO, debug, CTLFLAG_RWTUN, &uath_debug, 0, 127 "uath debug level"); 128 enum { 129 UATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 130 UATH_DEBUG_XMIT_DUMP = 0x00000002, /* xmit dump */ 131 UATH_DEBUG_RECV = 0x00000004, /* basic recv operation */ 132 UATH_DEBUG_TX_PROC = 0x00000008, /* tx ISR proc */ 133 UATH_DEBUG_RX_PROC = 0x00000010, /* rx ISR proc */ 134 UATH_DEBUG_RECV_ALL = 0x00000020, /* trace all frames (beacons) */ 135 UATH_DEBUG_INIT = 0x00000040, /* initialization of dev */ 136 UATH_DEBUG_DEVCAP = 0x00000080, /* dev caps */ 137 UATH_DEBUG_CMDS = 0x00000100, /* commands */ 138 UATH_DEBUG_CMDS_DUMP = 0x00000200, /* command buffer dump */ 139 UATH_DEBUG_RESET = 0x00000400, /* reset processing */ 140 UATH_DEBUG_STATE = 0x00000800, /* 802.11 state transitions */ 141 UATH_DEBUG_MULTICAST = 0x00001000, /* multicast */ 142 UATH_DEBUG_WME = 0x00002000, /* WME */ 143 UATH_DEBUG_CHANNEL = 0x00004000, /* channel */ 144 UATH_DEBUG_RATES = 0x00008000, /* rates */ 145 UATH_DEBUG_CRYPTO = 0x00010000, /* crypto */ 146 UATH_DEBUG_LED = 0x00020000, /* LED */ 147 UATH_DEBUG_ANY = 0xffffffff 148 }; 149 #define DPRINTF(sc, m, fmt, ...) do { \ 150 if (sc->sc_debug & (m)) \ 151 printf(fmt, __VA_ARGS__); \ 152 } while (0) 153 #else 154 #define DPRINTF(sc, m, fmt, ...) do { \ 155 (void) sc; \ 156 } while (0) 157 #endif 158 159 /* recognized device vendors/products */ 160 static const STRUCT_USB_HOST_ID uath_devs[] = { 161 #define UATH_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 162 UATH_DEV(ACCTON, SMCWUSBTG2), 163 UATH_DEV(ATHEROS, AR5523), 164 UATH_DEV(ATHEROS2, AR5523_1), 165 UATH_DEV(ATHEROS2, AR5523_2), 166 UATH_DEV(ATHEROS2, AR5523_3), 167 UATH_DEV(CONCEPTRONIC, AR5523_1), 168 UATH_DEV(CONCEPTRONIC, AR5523_2), 169 UATH_DEV(DLINK, DWLAG122), 170 UATH_DEV(DLINK, DWLAG132), 171 UATH_DEV(DLINK, DWLG132), 172 UATH_DEV(DLINK2, DWA120), 173 UATH_DEV(GIGASET, AR5523), 174 UATH_DEV(GIGASET, SMCWUSBTG), 175 UATH_DEV(GLOBALSUN, AR5523_1), 176 UATH_DEV(GLOBALSUN, AR5523_2), 177 UATH_DEV(NETGEAR, WG111U), 178 UATH_DEV(NETGEAR3, WG111T), 179 UATH_DEV(NETGEAR3, WPN111), 180 UATH_DEV(NETGEAR3, WPN111_2), 181 UATH_DEV(UMEDIA, TEW444UBEU), 182 UATH_DEV(UMEDIA, AR5523_2), 183 UATH_DEV(WISTRONNEWEB, AR5523_1), 184 UATH_DEV(WISTRONNEWEB, AR5523_2), 185 UATH_DEV(WISTRONNEWEB, AR5523_2_ALT), 186 UATH_DEV(ZCOM, AR5523) 187 #undef UATH_DEV 188 }; 189 190 static usb_callback_t uath_intr_rx_callback; 191 static usb_callback_t uath_intr_tx_callback; 192 static usb_callback_t uath_bulk_rx_callback; 193 static usb_callback_t uath_bulk_tx_callback; 194 195 static const struct usb_config uath_usbconfig[UATH_N_XFERS] = { 196 [UATH_INTR_RX] = { 197 .type = UE_BULK, 198 .endpoint = 0x1, 199 .direction = UE_DIR_IN, 200 .bufsize = UATH_MAX_CMDSZ, 201 .flags = { 202 .pipe_bof = 1, 203 .short_xfer_ok = 1 204 }, 205 .callback = uath_intr_rx_callback 206 }, 207 [UATH_INTR_TX] = { 208 .type = UE_BULK, 209 .endpoint = 0x1, 210 .direction = UE_DIR_OUT, 211 .bufsize = UATH_MAX_CMDSZ * UATH_CMD_LIST_COUNT, 212 .flags = { 213 .force_short_xfer = 1, 214 .pipe_bof = 1, 215 }, 216 .callback = uath_intr_tx_callback, 217 .timeout = UATH_CMD_TIMEOUT 218 }, 219 [UATH_BULK_RX] = { 220 .type = UE_BULK, 221 .endpoint = 0x2, 222 .direction = UE_DIR_IN, 223 .bufsize = MCLBYTES, 224 .flags = { 225 .ext_buffer = 1, 226 .pipe_bof = 1, 227 .short_xfer_ok = 1 228 }, 229 .callback = uath_bulk_rx_callback 230 }, 231 [UATH_BULK_TX] = { 232 .type = UE_BULK, 233 .endpoint = 0x2, 234 .direction = UE_DIR_OUT, 235 .bufsize = UATH_MAX_TXBUFSZ * UATH_TX_DATA_LIST_COUNT, 236 .flags = { 237 .force_short_xfer = 1, 238 .pipe_bof = 1 239 }, 240 .callback = uath_bulk_tx_callback, 241 .timeout = UATH_DATA_TIMEOUT 242 } 243 }; 244 245 static struct ieee80211vap *uath_vap_create(struct ieee80211com *, 246 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 247 const uint8_t [IEEE80211_ADDR_LEN], 248 const uint8_t [IEEE80211_ADDR_LEN]); 249 static void uath_vap_delete(struct ieee80211vap *); 250 static int uath_alloc_cmd_list(struct uath_softc *, struct uath_cmd []); 251 static void uath_free_cmd_list(struct uath_softc *, struct uath_cmd []); 252 static int uath_host_available(struct uath_softc *); 253 static int uath_get_capability(struct uath_softc *, uint32_t, uint32_t *); 254 static int uath_get_devcap(struct uath_softc *); 255 static struct uath_cmd * 256 uath_get_cmdbuf(struct uath_softc *); 257 static int uath_cmd_read(struct uath_softc *, uint32_t, const void *, 258 int, void *, int, int); 259 static int uath_cmd_write(struct uath_softc *, uint32_t, const void *, 260 int, int); 261 static void uath_stat(void *); 262 #ifdef UATH_DEBUG 263 static void uath_dump_cmd(const uint8_t *, int, char); 264 static const char * 265 uath_codename(int); 266 #endif 267 static int uath_get_devstatus(struct uath_softc *, 268 uint8_t macaddr[IEEE80211_ADDR_LEN]); 269 static int uath_get_status(struct uath_softc *, uint32_t, void *, int); 270 static int uath_alloc_rx_data_list(struct uath_softc *); 271 static int uath_alloc_tx_data_list(struct uath_softc *); 272 static void uath_free_rx_data_list(struct uath_softc *); 273 static void uath_free_tx_data_list(struct uath_softc *); 274 static int uath_init(struct uath_softc *); 275 static void uath_stop(struct uath_softc *); 276 static void uath_parent(struct ieee80211com *); 277 static int uath_transmit(struct ieee80211com *, struct mbuf *); 278 static void uath_start(struct uath_softc *); 279 static int uath_raw_xmit(struct ieee80211_node *, struct mbuf *, 280 const struct ieee80211_bpf_params *); 281 static void uath_scan_start(struct ieee80211com *); 282 static void uath_scan_end(struct ieee80211com *); 283 static void uath_set_channel(struct ieee80211com *); 284 static void uath_update_mcast(struct ieee80211com *); 285 static void uath_update_promisc(struct ieee80211com *); 286 static int uath_config(struct uath_softc *, uint32_t, uint32_t); 287 static int uath_config_multi(struct uath_softc *, uint32_t, const void *, 288 int); 289 static int uath_switch_channel(struct uath_softc *, 290 struct ieee80211_channel *); 291 static int uath_set_rxfilter(struct uath_softc *, uint32_t, uint32_t); 292 static void uath_watchdog(void *); 293 static void uath_abort_xfers(struct uath_softc *); 294 static int uath_dataflush(struct uath_softc *); 295 static int uath_cmdflush(struct uath_softc *); 296 static int uath_flush(struct uath_softc *); 297 static int uath_set_ledstate(struct uath_softc *, int); 298 static int uath_set_chan(struct uath_softc *, struct ieee80211_channel *); 299 static int uath_reset_tx_queues(struct uath_softc *); 300 static int uath_wme_init(struct uath_softc *); 301 static struct uath_data * 302 uath_getbuf(struct uath_softc *); 303 static int uath_newstate(struct ieee80211vap *, enum ieee80211_state, 304 int); 305 static int uath_set_key(struct uath_softc *, 306 const struct ieee80211_key *, int); 307 static int uath_set_keys(struct uath_softc *, struct ieee80211vap *); 308 static void uath_sysctl_node(struct uath_softc *); 309 310 static int 311 uath_match(device_t dev) 312 { 313 struct usb_attach_arg *uaa = device_get_ivars(dev); 314 315 if (uaa->usb_mode != USB_MODE_HOST) 316 return (ENXIO); 317 if (uaa->info.bConfigIndex != UATH_CONFIG_INDEX) 318 return (ENXIO); 319 if (uaa->info.bIfaceIndex != UATH_IFACE_INDEX) 320 return (ENXIO); 321 322 return (usbd_lookup_id_by_uaa(uath_devs, sizeof(uath_devs), uaa)); 323 } 324 325 static int 326 uath_attach(device_t dev) 327 { 328 struct uath_softc *sc = device_get_softc(dev); 329 struct usb_attach_arg *uaa = device_get_ivars(dev); 330 struct ieee80211com *ic = &sc->sc_ic; 331 uint8_t bands[IEEE80211_MODE_BYTES]; 332 uint8_t iface_index = UATH_IFACE_INDEX; /* XXX */ 333 usb_error_t error; 334 335 sc->sc_dev = dev; 336 sc->sc_udev = uaa->device; 337 #ifdef UATH_DEBUG 338 sc->sc_debug = uath_debug; 339 #endif 340 device_set_usb_desc(dev); 341 342 /* 343 * Only post-firmware devices here. 344 */ 345 mtx_init(&sc->sc_mtx, device_get_nameunit(sc->sc_dev), MTX_NETWORK_LOCK, 346 MTX_DEF); 347 callout_init(&sc->stat_ch, 0); 348 callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0); 349 mbufq_init(&sc->sc_snd, ifqmaxlen); 350 351 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 352 uath_usbconfig, UATH_N_XFERS, sc, &sc->sc_mtx); 353 if (error) { 354 device_printf(dev, "could not allocate USB transfers, " 355 "err=%s\n", usbd_errstr(error)); 356 goto fail; 357 } 358 359 sc->sc_cmd_dma_buf = 360 usbd_xfer_get_frame_buffer(sc->sc_xfer[UATH_INTR_TX], 0); 361 sc->sc_tx_dma_buf = 362 usbd_xfer_get_frame_buffer(sc->sc_xfer[UATH_BULK_TX], 0); 363 364 /* 365 * Setup buffers for firmware commands. 366 */ 367 error = uath_alloc_cmd_list(sc, sc->sc_cmd); 368 if (error != 0) { 369 device_printf(sc->sc_dev, 370 "could not allocate Tx command list\n"); 371 goto fail1; 372 } 373 374 /* 375 * We're now ready to send+receive firmware commands. 376 */ 377 UATH_LOCK(sc); 378 error = uath_host_available(sc); 379 if (error != 0) { 380 device_printf(sc->sc_dev, "could not initialize adapter\n"); 381 goto fail2; 382 } 383 error = uath_get_devcap(sc); 384 if (error != 0) { 385 device_printf(sc->sc_dev, 386 "could not get device capabilities\n"); 387 goto fail2; 388 } 389 UATH_UNLOCK(sc); 390 391 /* Create device sysctl node. */ 392 uath_sysctl_node(sc); 393 394 UATH_LOCK(sc); 395 error = uath_get_devstatus(sc, ic->ic_macaddr); 396 if (error != 0) { 397 device_printf(sc->sc_dev, "could not get device status\n"); 398 goto fail2; 399 } 400 401 /* 402 * Allocate xfers for Rx/Tx data pipes. 403 */ 404 error = uath_alloc_rx_data_list(sc); 405 if (error != 0) { 406 device_printf(sc->sc_dev, "could not allocate Rx data list\n"); 407 goto fail2; 408 } 409 error = uath_alloc_tx_data_list(sc); 410 if (error != 0) { 411 device_printf(sc->sc_dev, "could not allocate Tx data list\n"); 412 goto fail2; 413 } 414 UATH_UNLOCK(sc); 415 416 ic->ic_softc = sc; 417 ic->ic_name = device_get_nameunit(dev); 418 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 419 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 420 421 /* set device capabilities */ 422 ic->ic_caps = 423 IEEE80211_C_STA | /* station mode */ 424 IEEE80211_C_MONITOR | /* monitor mode supported */ 425 IEEE80211_C_TXPMGT | /* tx power management */ 426 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 427 IEEE80211_C_SHSLOT | /* short slot time supported */ 428 IEEE80211_C_WPA | /* 802.11i */ 429 IEEE80211_C_BGSCAN | /* capable of bg scanning */ 430 IEEE80211_C_TXFRAG; /* handle tx frags */ 431 432 /* put a regulatory domain to reveal informations. */ 433 uath_regdomain = sc->sc_devcap.regDomain; 434 435 memset(bands, 0, sizeof(bands)); 436 setbit(bands, IEEE80211_MODE_11B); 437 setbit(bands, IEEE80211_MODE_11G); 438 if ((sc->sc_devcap.analog5GhzRevision & 0xf0) == 0x30) 439 setbit(bands, IEEE80211_MODE_11A); 440 /* XXX turbo */ 441 ieee80211_init_channels(ic, NULL, bands); 442 443 ieee80211_ifattach(ic); 444 445 /* Note: this has to happen AFTER ieee80211_ifattach() */ 446 ieee80211_set_software_ciphers(ic, 447 IEEE80211_CRYPTO_WEP | IEEE80211_CRYPTO_TKIP | 448 IEEE80211_CRYPTO_AES_CCM | IEEE80211_CRYPTO_AES_GCM_128); 449 450 ic->ic_raw_xmit = uath_raw_xmit; 451 ic->ic_scan_start = uath_scan_start; 452 ic->ic_scan_end = uath_scan_end; 453 ic->ic_set_channel = uath_set_channel; 454 ic->ic_vap_create = uath_vap_create; 455 ic->ic_vap_delete = uath_vap_delete; 456 ic->ic_update_mcast = uath_update_mcast; 457 ic->ic_update_promisc = uath_update_promisc; 458 ic->ic_transmit = uath_transmit; 459 ic->ic_parent = uath_parent; 460 461 ieee80211_radiotap_attach(ic, 462 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 463 UATH_TX_RADIOTAP_PRESENT, 464 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 465 UATH_RX_RADIOTAP_PRESENT); 466 467 if (bootverbose) 468 ieee80211_announce(ic); 469 470 return (0); 471 472 fail2: UATH_UNLOCK(sc); 473 uath_free_cmd_list(sc, sc->sc_cmd); 474 fail1: usbd_transfer_unsetup(sc->sc_xfer, UATH_N_XFERS); 475 fail: 476 return (error); 477 } 478 479 static int 480 uath_detach(device_t dev) 481 { 482 struct uath_softc *sc = device_get_softc(dev); 483 struct ieee80211com *ic = &sc->sc_ic; 484 unsigned x; 485 486 /* 487 * Prevent further allocations from RX/TX/CMD 488 * data lists and ioctls 489 */ 490 UATH_LOCK(sc); 491 sc->sc_flags |= UATH_FLAG_INVALID; 492 493 STAILQ_INIT(&sc->sc_rx_active); 494 STAILQ_INIT(&sc->sc_rx_inactive); 495 496 STAILQ_INIT(&sc->sc_tx_active); 497 STAILQ_INIT(&sc->sc_tx_inactive); 498 STAILQ_INIT(&sc->sc_tx_pending); 499 500 STAILQ_INIT(&sc->sc_cmd_active); 501 STAILQ_INIT(&sc->sc_cmd_pending); 502 STAILQ_INIT(&sc->sc_cmd_waiting); 503 STAILQ_INIT(&sc->sc_cmd_inactive); 504 505 uath_stop(sc); 506 UATH_UNLOCK(sc); 507 508 callout_drain(&sc->stat_ch); 509 callout_drain(&sc->watchdog_ch); 510 511 /* drain USB transfers */ 512 for (x = 0; x != UATH_N_XFERS; x++) 513 usbd_transfer_drain(sc->sc_xfer[x]); 514 515 /* free data buffers */ 516 UATH_LOCK(sc); 517 uath_free_rx_data_list(sc); 518 uath_free_tx_data_list(sc); 519 uath_free_cmd_list(sc, sc->sc_cmd); 520 UATH_UNLOCK(sc); 521 522 /* free USB transfers and some data buffers */ 523 usbd_transfer_unsetup(sc->sc_xfer, UATH_N_XFERS); 524 525 ieee80211_ifdetach(ic); 526 mbufq_drain(&sc->sc_snd); 527 mtx_destroy(&sc->sc_mtx); 528 return (0); 529 } 530 531 static void 532 uath_free_cmd_list(struct uath_softc *sc, struct uath_cmd cmds[]) 533 { 534 int i; 535 536 for (i = 0; i != UATH_CMD_LIST_COUNT; i++) 537 cmds[i].buf = NULL; 538 } 539 540 static int 541 uath_alloc_cmd_list(struct uath_softc *sc, struct uath_cmd cmds[]) 542 { 543 int i; 544 545 STAILQ_INIT(&sc->sc_cmd_active); 546 STAILQ_INIT(&sc->sc_cmd_pending); 547 STAILQ_INIT(&sc->sc_cmd_waiting); 548 STAILQ_INIT(&sc->sc_cmd_inactive); 549 550 for (i = 0; i != UATH_CMD_LIST_COUNT; i++) { 551 struct uath_cmd *cmd = &cmds[i]; 552 553 cmd->sc = sc; /* backpointer for callbacks */ 554 cmd->msgid = i; 555 cmd->buf = ((uint8_t *)sc->sc_cmd_dma_buf) + 556 (i * UATH_MAX_CMDSZ); 557 STAILQ_INSERT_TAIL(&sc->sc_cmd_inactive, cmd, next); 558 UATH_STAT_INC(sc, st_cmd_inactive); 559 } 560 return (0); 561 } 562 563 static int 564 uath_host_available(struct uath_softc *sc) 565 { 566 struct uath_cmd_host_available setup; 567 568 UATH_ASSERT_LOCKED(sc); 569 570 /* inform target the host is available */ 571 setup.sw_ver_major = htobe32(ATH_SW_VER_MAJOR); 572 setup.sw_ver_minor = htobe32(ATH_SW_VER_MINOR); 573 setup.sw_ver_patch = htobe32(ATH_SW_VER_PATCH); 574 setup.sw_ver_build = htobe32(ATH_SW_VER_BUILD); 575 return uath_cmd_read(sc, WDCMSG_HOST_AVAILABLE, 576 &setup, sizeof setup, NULL, 0, 0); 577 } 578 579 #ifdef UATH_DEBUG 580 static void 581 uath_dump_cmd(const uint8_t *buf, int len, char prefix) 582 { 583 const char *sep = ""; 584 int i; 585 586 for (i = 0; i < len; i++) { 587 if ((i % 16) == 0) { 588 printf("%s%c ", sep, prefix); 589 sep = "\n"; 590 } 591 else if ((i % 4) == 0) 592 printf(" "); 593 printf("%02x", buf[i]); 594 } 595 printf("\n"); 596 } 597 598 static const char * 599 uath_codename(int code) 600 { 601 static const char *names[] = { 602 "0x00", 603 "HOST_AVAILABLE", 604 "BIND", 605 "TARGET_RESET", 606 "TARGET_GET_CAPABILITY", 607 "TARGET_SET_CONFIG", 608 "TARGET_GET_STATUS", 609 "TARGET_GET_STATS", 610 "TARGET_START", 611 "TARGET_STOP", 612 "TARGET_ENABLE", 613 "TARGET_DISABLE", 614 "CREATE_CONNECTION", 615 "UPDATE_CONNECT_ATTR", 616 "DELETE_CONNECT", 617 "SEND", 618 "FLUSH", 619 "STATS_UPDATE", 620 "BMISS", 621 "DEVICE_AVAIL", 622 "SEND_COMPLETE", 623 "DATA_AVAIL", 624 "SET_PWR_MODE", 625 "BMISS_ACK", 626 "SET_LED_STEADY", 627 "SET_LED_BLINK", 628 "SETUP_BEACON_DESC", 629 "BEACON_INIT", 630 "RESET_KEY_CACHE", 631 "RESET_KEY_CACHE_ENTRY", 632 "SET_KEY_CACHE_ENTRY", 633 "SET_DECOMP_MASK", 634 "SET_REGULATORY_DOMAIN", 635 "SET_LED_STATE", 636 "WRITE_ASSOCID", 637 "SET_STA_BEACON_TIMERS", 638 "GET_TSF", 639 "RESET_TSF", 640 "SET_ADHOC_MODE", 641 "SET_BASIC_RATE", 642 "MIB_CONTROL", 643 "GET_CHANNEL_DATA", 644 "GET_CUR_RSSI", 645 "SET_ANTENNA_SWITCH", 646 "0x2c", "0x2d", "0x2e", 647 "USE_SHORT_SLOT_TIME", 648 "SET_POWER_MODE", 649 "SETUP_PSPOLL_DESC", 650 "SET_RX_MULTICAST_FILTER", 651 "RX_FILTER", 652 "PER_CALIBRATION", 653 "RESET", 654 "DISABLE", 655 "PHY_DISABLE", 656 "SET_TX_POWER_LIMIT", 657 "SET_TX_QUEUE_PARAMS", 658 "SETUP_TX_QUEUE", 659 "RELEASE_TX_QUEUE", 660 }; 661 static char buf[8]; 662 663 if (code < nitems(names)) 664 return names[code]; 665 if (code == WDCMSG_SET_DEFAULT_KEY) 666 return "SET_DEFAULT_KEY"; 667 snprintf(buf, sizeof(buf), "0x%02x", code); 668 return buf; 669 } 670 #endif 671 672 /* 673 * Low-level function to send read or write commands to the firmware. 674 */ 675 static int 676 uath_cmdsend(struct uath_softc *sc, uint32_t code, const void *idata, int ilen, 677 void *odata, int olen, int flags) 678 { 679 struct uath_cmd_hdr *hdr; 680 struct uath_cmd *cmd; 681 int error; 682 683 UATH_ASSERT_LOCKED(sc); 684 685 /* grab a xfer */ 686 cmd = uath_get_cmdbuf(sc); 687 if (cmd == NULL) { 688 device_printf(sc->sc_dev, "%s: empty inactive queue\n", 689 __func__); 690 return (ENOBUFS); 691 } 692 cmd->flags = flags; 693 /* always bulk-out a multiple of 4 bytes */ 694 cmd->buflen = roundup2(sizeof(struct uath_cmd_hdr) + ilen, 4); 695 696 hdr = (struct uath_cmd_hdr *)cmd->buf; 697 memset(hdr, 0, sizeof(struct uath_cmd_hdr)); 698 hdr->len = htobe32(cmd->buflen); 699 hdr->code = htobe32(code); 700 hdr->msgid = cmd->msgid; /* don't care about endianness */ 701 hdr->magic = htobe32((cmd->flags & UATH_CMD_FLAG_MAGIC) ? 1 << 24 : 0); 702 memcpy((uint8_t *)(hdr + 1), idata, ilen); 703 704 #ifdef UATH_DEBUG 705 if (sc->sc_debug & UATH_DEBUG_CMDS) { 706 printf("%s: send %s [flags 0x%x] olen %d\n", 707 __func__, uath_codename(code), cmd->flags, olen); 708 if (sc->sc_debug & UATH_DEBUG_CMDS_DUMP) 709 uath_dump_cmd(cmd->buf, cmd->buflen, '+'); 710 } 711 #endif 712 cmd->odata = odata; 713 KASSERT(odata == NULL || 714 olen < UATH_MAX_CMDSZ - sizeof(*hdr) + sizeof(uint32_t), 715 ("odata %p olen %u", odata, olen)); 716 cmd->olen = olen; 717 718 STAILQ_INSERT_TAIL(&sc->sc_cmd_pending, cmd, next); 719 UATH_STAT_INC(sc, st_cmd_pending); 720 usbd_transfer_start(sc->sc_xfer[UATH_INTR_TX]); 721 722 if (cmd->flags & UATH_CMD_FLAG_READ) { 723 usbd_transfer_start(sc->sc_xfer[UATH_INTR_RX]); 724 725 /* wait at most two seconds for command reply */ 726 error = mtx_sleep(cmd, &sc->sc_mtx, 0, "uathcmd", 2 * hz); 727 cmd->odata = NULL; /* in case reply comes too late */ 728 if (error != 0) { 729 device_printf(sc->sc_dev, "timeout waiting for reply " 730 "to cmd 0x%x (%u)\n", code, code); 731 } else if (cmd->olen != olen) { 732 device_printf(sc->sc_dev, "unexpected reply data count " 733 "to cmd 0x%x (%u), got %u, expected %u\n", 734 code, code, cmd->olen, olen); 735 error = EINVAL; 736 } 737 return (error); 738 } 739 return (0); 740 } 741 742 static int 743 uath_cmd_read(struct uath_softc *sc, uint32_t code, const void *idata, 744 int ilen, void *odata, int olen, int flags) 745 { 746 747 flags |= UATH_CMD_FLAG_READ; 748 return uath_cmdsend(sc, code, idata, ilen, odata, olen, flags); 749 } 750 751 static int 752 uath_cmd_write(struct uath_softc *sc, uint32_t code, const void *data, int len, 753 int flags) 754 { 755 756 flags &= ~UATH_CMD_FLAG_READ; 757 return uath_cmdsend(sc, code, data, len, NULL, 0, flags); 758 } 759 760 static struct uath_cmd * 761 uath_get_cmdbuf(struct uath_softc *sc) 762 { 763 struct uath_cmd *uc; 764 765 UATH_ASSERT_LOCKED(sc); 766 767 uc = STAILQ_FIRST(&sc->sc_cmd_inactive); 768 if (uc != NULL) { 769 STAILQ_REMOVE_HEAD(&sc->sc_cmd_inactive, next); 770 UATH_STAT_DEC(sc, st_cmd_inactive); 771 } else 772 uc = NULL; 773 if (uc == NULL) 774 DPRINTF(sc, UATH_DEBUG_XMIT, "%s: %s\n", __func__, 775 "out of command xmit buffers"); 776 return (uc); 777 } 778 779 /* 780 * This function is called periodically (every second) when associated to 781 * query device statistics. 782 */ 783 static void 784 uath_stat(void *arg) 785 { 786 struct uath_softc *sc = arg; 787 int error; 788 789 UATH_LOCK(sc); 790 /* 791 * Send request for statistics asynchronously. The timer will be 792 * restarted when we'll get the stats notification. 793 */ 794 error = uath_cmd_write(sc, WDCMSG_TARGET_GET_STATS, NULL, 0, 795 UATH_CMD_FLAG_ASYNC); 796 if (error != 0) { 797 device_printf(sc->sc_dev, 798 "could not query stats, error %d\n", error); 799 } 800 UATH_UNLOCK(sc); 801 } 802 803 static int 804 uath_get_capability(struct uath_softc *sc, uint32_t cap, uint32_t *val) 805 { 806 int error; 807 808 cap = htobe32(cap); 809 error = uath_cmd_read(sc, WDCMSG_TARGET_GET_CAPABILITY, 810 &cap, sizeof cap, val, sizeof(uint32_t), UATH_CMD_FLAG_MAGIC); 811 if (error != 0) { 812 device_printf(sc->sc_dev, "could not read capability %u\n", 813 be32toh(cap)); 814 return (error); 815 } 816 *val = be32toh(*val); 817 return (error); 818 } 819 820 static int 821 uath_get_devcap(struct uath_softc *sc) 822 { 823 #define GETCAP(x, v) do { \ 824 error = uath_get_capability(sc, x, &v); \ 825 if (error != 0) \ 826 return (error); \ 827 DPRINTF(sc, UATH_DEBUG_DEVCAP, \ 828 "%s: %s=0x%08x\n", __func__, #x, v); \ 829 } while (0) 830 struct uath_devcap *cap = &sc->sc_devcap; 831 int error; 832 833 /* collect device capabilities */ 834 GETCAP(CAP_TARGET_VERSION, cap->targetVersion); 835 GETCAP(CAP_TARGET_REVISION, cap->targetRevision); 836 GETCAP(CAP_MAC_VERSION, cap->macVersion); 837 GETCAP(CAP_MAC_REVISION, cap->macRevision); 838 GETCAP(CAP_PHY_REVISION, cap->phyRevision); 839 GETCAP(CAP_ANALOG_5GHz_REVISION, cap->analog5GhzRevision); 840 GETCAP(CAP_ANALOG_2GHz_REVISION, cap->analog2GhzRevision); 841 842 GETCAP(CAP_REG_DOMAIN, cap->regDomain); 843 GETCAP(CAP_REG_CAP_BITS, cap->regCapBits); 844 #if 0 845 /* NB: not supported in rev 1.5 */ 846 GETCAP(CAP_COUNTRY_CODE, cap->countryCode); 847 #endif 848 GETCAP(CAP_WIRELESS_MODES, cap->wirelessModes); 849 GETCAP(CAP_CHAN_SPREAD_SUPPORT, cap->chanSpreadSupport); 850 GETCAP(CAP_COMPRESS_SUPPORT, cap->compressSupport); 851 GETCAP(CAP_BURST_SUPPORT, cap->burstSupport); 852 GETCAP(CAP_FAST_FRAMES_SUPPORT, cap->fastFramesSupport); 853 GETCAP(CAP_CHAP_TUNING_SUPPORT, cap->chapTuningSupport); 854 GETCAP(CAP_TURBOG_SUPPORT, cap->turboGSupport); 855 GETCAP(CAP_TURBO_PRIME_SUPPORT, cap->turboPrimeSupport); 856 GETCAP(CAP_DEVICE_TYPE, cap->deviceType); 857 GETCAP(CAP_WME_SUPPORT, cap->wmeSupport); 858 GETCAP(CAP_TOTAL_QUEUES, cap->numTxQueues); 859 GETCAP(CAP_CONNECTION_ID_MAX, cap->connectionIdMax); 860 861 GETCAP(CAP_LOW_5GHZ_CHAN, cap->low5GhzChan); 862 GETCAP(CAP_HIGH_5GHZ_CHAN, cap->high5GhzChan); 863 GETCAP(CAP_LOW_2GHZ_CHAN, cap->low2GhzChan); 864 GETCAP(CAP_HIGH_2GHZ_CHAN, cap->high2GhzChan); 865 GETCAP(CAP_TWICE_ANTENNAGAIN_5G, cap->twiceAntennaGain5G); 866 GETCAP(CAP_TWICE_ANTENNAGAIN_2G, cap->twiceAntennaGain2G); 867 868 GETCAP(CAP_CIPHER_AES_CCM, cap->supportCipherAES_CCM); 869 GETCAP(CAP_CIPHER_TKIP, cap->supportCipherTKIP); 870 GETCAP(CAP_MIC_TKIP, cap->supportMicTKIP); 871 872 cap->supportCipherWEP = 1; /* NB: always available */ 873 874 return (0); 875 } 876 877 static int 878 uath_get_devstatus(struct uath_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 879 { 880 int error; 881 882 /* retrieve MAC address */ 883 error = uath_get_status(sc, ST_MAC_ADDR, macaddr, IEEE80211_ADDR_LEN); 884 if (error != 0) { 885 device_printf(sc->sc_dev, "could not read MAC address\n"); 886 return (error); 887 } 888 889 error = uath_get_status(sc, ST_SERIAL_NUMBER, 890 &sc->sc_serial[0], sizeof(sc->sc_serial)); 891 if (error != 0) { 892 device_printf(sc->sc_dev, 893 "could not read device serial number\n"); 894 return (error); 895 } 896 return (0); 897 } 898 899 static int 900 uath_get_status(struct uath_softc *sc, uint32_t which, void *odata, int olen) 901 { 902 int error; 903 904 which = htobe32(which); 905 error = uath_cmd_read(sc, WDCMSG_TARGET_GET_STATUS, 906 &which, sizeof(which), odata, olen, UATH_CMD_FLAG_MAGIC); 907 if (error != 0) 908 device_printf(sc->sc_dev, 909 "could not read EEPROM offset 0x%02x\n", be32toh(which)); 910 return (error); 911 } 912 913 static void 914 uath_free_data_list(struct uath_softc *sc, struct uath_data data[], int ndata, 915 int fillmbuf) 916 { 917 int i; 918 919 for (i = 0; i < ndata; i++) { 920 struct uath_data *dp = &data[i]; 921 922 if (fillmbuf == 1) { 923 if (dp->m != NULL) { 924 m_freem(dp->m); 925 dp->m = NULL; 926 dp->buf = NULL; 927 } 928 } else { 929 dp->buf = NULL; 930 } 931 if (dp->ni != NULL) { 932 ieee80211_free_node(dp->ni); 933 dp->ni = NULL; 934 } 935 } 936 } 937 938 static int 939 uath_alloc_data_list(struct uath_softc *sc, struct uath_data data[], 940 int ndata, int maxsz, void *dma_buf) 941 { 942 int i, error; 943 944 for (i = 0; i < ndata; i++) { 945 struct uath_data *dp = &data[i]; 946 947 dp->sc = sc; 948 if (dma_buf == NULL) { 949 /* XXX check maxsz */ 950 dp->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 951 if (dp->m == NULL) { 952 device_printf(sc->sc_dev, 953 "could not allocate rx mbuf\n"); 954 error = ENOMEM; 955 goto fail; 956 } 957 dp->buf = mtod(dp->m, uint8_t *); 958 } else { 959 dp->m = NULL; 960 dp->buf = ((uint8_t *)dma_buf) + (i * maxsz); 961 } 962 dp->ni = NULL; 963 } 964 965 return (0); 966 967 fail: uath_free_data_list(sc, data, ndata, 1 /* free mbufs */); 968 return (error); 969 } 970 971 static int 972 uath_alloc_rx_data_list(struct uath_softc *sc) 973 { 974 int error, i; 975 976 /* XXX is it enough to store the RX packet with MCLBYTES bytes? */ 977 error = uath_alloc_data_list(sc, 978 sc->sc_rx, UATH_RX_DATA_LIST_COUNT, MCLBYTES, 979 NULL /* setup mbufs */); 980 if (error != 0) 981 return (error); 982 983 STAILQ_INIT(&sc->sc_rx_active); 984 STAILQ_INIT(&sc->sc_rx_inactive); 985 986 for (i = 0; i < UATH_RX_DATA_LIST_COUNT; i++) { 987 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], 988 next); 989 UATH_STAT_INC(sc, st_rx_inactive); 990 } 991 992 return (0); 993 } 994 995 static int 996 uath_alloc_tx_data_list(struct uath_softc *sc) 997 { 998 int error, i; 999 1000 error = uath_alloc_data_list(sc, 1001 sc->sc_tx, UATH_TX_DATA_LIST_COUNT, UATH_MAX_TXBUFSZ, 1002 sc->sc_tx_dma_buf); 1003 if (error != 0) 1004 return (error); 1005 1006 STAILQ_INIT(&sc->sc_tx_active); 1007 STAILQ_INIT(&sc->sc_tx_inactive); 1008 STAILQ_INIT(&sc->sc_tx_pending); 1009 1010 for (i = 0; i < UATH_TX_DATA_LIST_COUNT; i++) { 1011 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], 1012 next); 1013 UATH_STAT_INC(sc, st_tx_inactive); 1014 } 1015 1016 return (0); 1017 } 1018 1019 static void 1020 uath_free_rx_data_list(struct uath_softc *sc) 1021 { 1022 uath_free_data_list(sc, sc->sc_rx, UATH_RX_DATA_LIST_COUNT, 1023 1 /* free mbufs */); 1024 } 1025 1026 static void 1027 uath_free_tx_data_list(struct uath_softc *sc) 1028 { 1029 uath_free_data_list(sc, sc->sc_tx, UATH_TX_DATA_LIST_COUNT, 1030 0 /* no mbufs */); 1031 } 1032 1033 static struct ieee80211vap * 1034 uath_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 1035 enum ieee80211_opmode opmode, int flags, 1036 const uint8_t bssid[IEEE80211_ADDR_LEN], 1037 const uint8_t mac[IEEE80211_ADDR_LEN]) 1038 { 1039 struct uath_vap *uvp; 1040 struct ieee80211vap *vap; 1041 1042 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 1043 return (NULL); 1044 uvp = malloc(sizeof(struct uath_vap), M_80211_VAP, M_WAITOK | M_ZERO); 1045 vap = &uvp->vap; 1046 /* enable s/w bmiss handling for sta mode */ 1047 1048 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 1049 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 1050 /* out of memory */ 1051 free(uvp, M_80211_VAP); 1052 return (NULL); 1053 } 1054 1055 /* override state transition machine */ 1056 uvp->newstate = vap->iv_newstate; 1057 vap->iv_newstate = uath_newstate; 1058 1059 /* complete setup */ 1060 ieee80211_vap_attach(vap, ieee80211_media_change, 1061 ieee80211_media_status, mac); 1062 ic->ic_opmode = opmode; 1063 return (vap); 1064 } 1065 1066 static void 1067 uath_vap_delete(struct ieee80211vap *vap) 1068 { 1069 struct uath_vap *uvp = UATH_VAP(vap); 1070 1071 ieee80211_vap_detach(vap); 1072 free(uvp, M_80211_VAP); 1073 } 1074 1075 static int 1076 uath_init(struct uath_softc *sc) 1077 { 1078 struct ieee80211com *ic = &sc->sc_ic; 1079 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1080 uint32_t val; 1081 int error; 1082 1083 UATH_ASSERT_LOCKED(sc); 1084 1085 if (sc->sc_flags & UATH_FLAG_INITDONE) 1086 uath_stop(sc); 1087 1088 /* reset variables */ 1089 sc->sc_intrx_nextnum = sc->sc_msgid = 0; 1090 1091 val = htobe32(0); 1092 uath_cmd_write(sc, WDCMSG_BIND, &val, sizeof val, 0); 1093 1094 /* set MAC address */ 1095 uath_config_multi(sc, CFG_MAC_ADDR, 1096 vap ? vap->iv_myaddr : ic->ic_macaddr, IEEE80211_ADDR_LEN); 1097 1098 /* XXX honor net80211 state */ 1099 uath_config(sc, CFG_RATE_CONTROL_ENABLE, 0x00000001); 1100 uath_config(sc, CFG_DIVERSITY_CTL, 0x00000001); 1101 uath_config(sc, CFG_ABOLT, 0x0000003f); 1102 uath_config(sc, CFG_WME_ENABLED, 0x00000001); 1103 1104 uath_config(sc, CFG_SERVICE_TYPE, 1); 1105 uath_config(sc, CFG_TP_SCALE, 0x00000000); 1106 uath_config(sc, CFG_TPC_HALF_DBM5, 0x0000003c); 1107 uath_config(sc, CFG_TPC_HALF_DBM2, 0x0000003c); 1108 uath_config(sc, CFG_OVERRD_TX_POWER, 0x00000000); 1109 uath_config(sc, CFG_GMODE_PROTECTION, 0x00000000); 1110 uath_config(sc, CFG_GMODE_PROTECT_RATE_INDEX, 0x00000003); 1111 uath_config(sc, CFG_PROTECTION_TYPE, 0x00000000); 1112 uath_config(sc, CFG_MODE_CTS, 0x00000002); 1113 1114 error = uath_cmd_read(sc, WDCMSG_TARGET_START, NULL, 0, 1115 &val, sizeof(val), UATH_CMD_FLAG_MAGIC); 1116 if (error) { 1117 device_printf(sc->sc_dev, 1118 "could not start target, error %d\n", error); 1119 goto fail; 1120 } 1121 DPRINTF(sc, UATH_DEBUG_INIT, "%s returns handle: 0x%x\n", 1122 uath_codename(WDCMSG_TARGET_START), be32toh(val)); 1123 1124 /* set default channel */ 1125 error = uath_switch_channel(sc, ic->ic_curchan); 1126 if (error) { 1127 device_printf(sc->sc_dev, 1128 "could not switch channel, error %d\n", error); 1129 goto fail; 1130 } 1131 1132 val = htobe32(TARGET_DEVICE_AWAKE); 1133 uath_cmd_write(sc, WDCMSG_SET_PWR_MODE, &val, sizeof val, 0); 1134 /* XXX? check */ 1135 uath_cmd_write(sc, WDCMSG_RESET_KEY_CACHE, NULL, 0, 0); 1136 1137 usbd_transfer_start(sc->sc_xfer[UATH_BULK_RX]); 1138 /* enable Rx */ 1139 uath_set_rxfilter(sc, 0x0, UATH_FILTER_OP_INIT); 1140 uath_set_rxfilter(sc, 1141 UATH_FILTER_RX_UCAST | UATH_FILTER_RX_MCAST | 1142 UATH_FILTER_RX_BCAST | UATH_FILTER_RX_BEACON, 1143 UATH_FILTER_OP_SET); 1144 1145 sc->sc_flags |= UATH_FLAG_INITDONE; 1146 1147 callout_reset(&sc->watchdog_ch, hz, uath_watchdog, sc); 1148 1149 return (0); 1150 1151 fail: 1152 uath_stop(sc); 1153 return (error); 1154 } 1155 1156 static void 1157 uath_stop(struct uath_softc *sc) 1158 { 1159 1160 UATH_ASSERT_LOCKED(sc); 1161 1162 sc->sc_flags &= ~UATH_FLAG_INITDONE; 1163 1164 callout_stop(&sc->stat_ch); 1165 callout_stop(&sc->watchdog_ch); 1166 sc->sc_tx_timer = 0; 1167 /* abort pending transmits */ 1168 uath_abort_xfers(sc); 1169 /* flush data & control requests into the target */ 1170 (void)uath_flush(sc); 1171 /* set a LED status to the disconnected. */ 1172 uath_set_ledstate(sc, 0); 1173 /* stop the target */ 1174 uath_cmd_write(sc, WDCMSG_TARGET_STOP, NULL, 0, 0); 1175 } 1176 1177 static int 1178 uath_config(struct uath_softc *sc, uint32_t reg, uint32_t val) 1179 { 1180 struct uath_write_mac write; 1181 int error; 1182 1183 write.reg = htobe32(reg); 1184 write.len = htobe32(0); /* 0 = single write */ 1185 *(uint32_t *)write.data = htobe32(val); 1186 1187 error = uath_cmd_write(sc, WDCMSG_TARGET_SET_CONFIG, &write, 1188 3 * sizeof (uint32_t), 0); 1189 if (error != 0) { 1190 device_printf(sc->sc_dev, "could not write register 0x%02x\n", 1191 reg); 1192 } 1193 return (error); 1194 } 1195 1196 static int 1197 uath_config_multi(struct uath_softc *sc, uint32_t reg, const void *data, 1198 int len) 1199 { 1200 struct uath_write_mac write; 1201 int error; 1202 1203 write.reg = htobe32(reg); 1204 write.len = htobe32(len); 1205 bcopy(data, write.data, len); 1206 1207 /* properly handle the case where len is zero (reset) */ 1208 error = uath_cmd_write(sc, WDCMSG_TARGET_SET_CONFIG, &write, 1209 (len == 0) ? sizeof (uint32_t) : 2 * sizeof (uint32_t) + len, 0); 1210 if (error != 0) { 1211 device_printf(sc->sc_dev, 1212 "could not write %d bytes to register 0x%02x\n", len, reg); 1213 } 1214 return (error); 1215 } 1216 1217 static int 1218 uath_switch_channel(struct uath_softc *sc, struct ieee80211_channel *c) 1219 { 1220 int error; 1221 1222 UATH_ASSERT_LOCKED(sc); 1223 1224 /* set radio frequency */ 1225 error = uath_set_chan(sc, c); 1226 if (error) { 1227 device_printf(sc->sc_dev, 1228 "could not set channel, error %d\n", error); 1229 goto failed; 1230 } 1231 /* reset Tx rings */ 1232 error = uath_reset_tx_queues(sc); 1233 if (error) { 1234 device_printf(sc->sc_dev, 1235 "could not reset Tx queues, error %d\n", error); 1236 goto failed; 1237 } 1238 /* set Tx rings WME properties */ 1239 error = uath_wme_init(sc); 1240 if (error) { 1241 device_printf(sc->sc_dev, 1242 "could not init Tx queues, error %d\n", error); 1243 goto failed; 1244 } 1245 error = uath_set_ledstate(sc, 0); 1246 if (error) { 1247 device_printf(sc->sc_dev, 1248 "could not set led state, error %d\n", error); 1249 goto failed; 1250 } 1251 error = uath_flush(sc); 1252 if (error) { 1253 device_printf(sc->sc_dev, 1254 "could not flush pipes, error %d\n", error); 1255 goto failed; 1256 } 1257 failed: 1258 return (error); 1259 } 1260 1261 static int 1262 uath_set_rxfilter(struct uath_softc *sc, uint32_t bits, uint32_t op) 1263 { 1264 struct uath_cmd_rx_filter rxfilter; 1265 1266 rxfilter.bits = htobe32(bits); 1267 rxfilter.op = htobe32(op); 1268 1269 DPRINTF(sc, UATH_DEBUG_RECV | UATH_DEBUG_RECV_ALL, 1270 "setting Rx filter=0x%x flags=0x%x\n", bits, op); 1271 return uath_cmd_write(sc, WDCMSG_RX_FILTER, &rxfilter, 1272 sizeof rxfilter, 0); 1273 } 1274 1275 static void 1276 uath_watchdog(void *arg) 1277 { 1278 struct uath_softc *sc = arg; 1279 struct ieee80211com *ic = &sc->sc_ic; 1280 1281 if (sc->sc_tx_timer > 0) { 1282 if (--sc->sc_tx_timer == 0) { 1283 device_printf(sc->sc_dev, "device timeout\n"); 1284 counter_u64_add(ic->ic_oerrors, 1); 1285 ieee80211_restart_all(ic); 1286 return; 1287 } 1288 callout_reset(&sc->watchdog_ch, hz, uath_watchdog, sc); 1289 } 1290 } 1291 1292 static void 1293 uath_abort_xfers(struct uath_softc *sc) 1294 { 1295 int i; 1296 1297 UATH_ASSERT_LOCKED(sc); 1298 /* abort any pending transfers */ 1299 for (i = 0; i < UATH_N_XFERS; i++) 1300 usbd_transfer_stop(sc->sc_xfer[i]); 1301 } 1302 1303 static int 1304 uath_flush(struct uath_softc *sc) 1305 { 1306 int error; 1307 1308 error = uath_dataflush(sc); 1309 if (error != 0) 1310 goto failed; 1311 1312 error = uath_cmdflush(sc); 1313 if (error != 0) 1314 goto failed; 1315 1316 failed: 1317 return (error); 1318 } 1319 1320 static int 1321 uath_cmdflush(struct uath_softc *sc) 1322 { 1323 1324 return uath_cmd_write(sc, WDCMSG_FLUSH, NULL, 0, 0); 1325 } 1326 1327 static int 1328 uath_dataflush(struct uath_softc *sc) 1329 { 1330 struct uath_data *data; 1331 struct uath_chunk *chunk; 1332 struct uath_tx_desc *desc; 1333 1334 UATH_ASSERT_LOCKED(sc); 1335 1336 data = uath_getbuf(sc); 1337 if (data == NULL) 1338 return (ENOBUFS); 1339 data->buflen = sizeof(struct uath_chunk) + sizeof(struct uath_tx_desc); 1340 data->m = NULL; 1341 data->ni = NULL; 1342 chunk = (struct uath_chunk *)data->buf; 1343 desc = (struct uath_tx_desc *)(chunk + 1); 1344 1345 /* one chunk only */ 1346 chunk->seqnum = 0; 1347 chunk->flags = UATH_CFLAGS_FINAL; 1348 chunk->length = htobe16(sizeof (struct uath_tx_desc)); 1349 1350 memset(desc, 0, sizeof(struct uath_tx_desc)); 1351 desc->msglen = htobe32(sizeof(struct uath_tx_desc)); 1352 desc->msgid = (sc->sc_msgid++) + 1; /* don't care about endianness */ 1353 desc->type = htobe32(WDCMSG_FLUSH); 1354 desc->txqid = htobe32(0); 1355 desc->connid = htobe32(0); 1356 desc->flags = htobe32(0); 1357 1358 #ifdef UATH_DEBUG 1359 if (sc->sc_debug & UATH_DEBUG_CMDS) { 1360 DPRINTF(sc, UATH_DEBUG_RESET, "send flush ix %d\n", 1361 desc->msgid); 1362 if (sc->sc_debug & UATH_DEBUG_CMDS_DUMP) 1363 uath_dump_cmd(data->buf, data->buflen, '+'); 1364 } 1365 #endif 1366 1367 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 1368 UATH_STAT_INC(sc, st_tx_pending); 1369 sc->sc_tx_timer = 5; 1370 usbd_transfer_start(sc->sc_xfer[UATH_BULK_TX]); 1371 1372 return (0); 1373 } 1374 1375 static struct uath_data * 1376 _uath_getbuf(struct uath_softc *sc) 1377 { 1378 struct uath_data *bf; 1379 1380 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 1381 if (bf != NULL) { 1382 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 1383 UATH_STAT_DEC(sc, st_tx_inactive); 1384 } else 1385 bf = NULL; 1386 if (bf == NULL) 1387 DPRINTF(sc, UATH_DEBUG_XMIT, "%s: %s\n", __func__, 1388 "out of xmit buffers"); 1389 return (bf); 1390 } 1391 1392 static struct uath_data * 1393 uath_getbuf(struct uath_softc *sc) 1394 { 1395 struct uath_data *bf; 1396 1397 UATH_ASSERT_LOCKED(sc); 1398 1399 bf = _uath_getbuf(sc); 1400 if (bf == NULL) 1401 DPRINTF(sc, UATH_DEBUG_XMIT, "%s: stop queue\n", __func__); 1402 return (bf); 1403 } 1404 1405 static int 1406 uath_set_ledstate(struct uath_softc *sc, int connected) 1407 { 1408 1409 DPRINTF(sc, UATH_DEBUG_LED, 1410 "set led state %sconnected\n", connected ? "" : "!"); 1411 connected = htobe32(connected); 1412 return uath_cmd_write(sc, WDCMSG_SET_LED_STATE, 1413 &connected, sizeof connected, 0); 1414 } 1415 1416 static int 1417 uath_set_chan(struct uath_softc *sc, struct ieee80211_channel *c) 1418 { 1419 #ifdef UATH_DEBUG 1420 struct ieee80211com *ic = &sc->sc_ic; 1421 #endif 1422 struct uath_cmd_reset reset; 1423 1424 memset(&reset, 0, sizeof(reset)); 1425 if (IEEE80211_IS_CHAN_2GHZ(c)) 1426 reset.flags |= htobe32(UATH_CHAN_2GHZ); 1427 if (IEEE80211_IS_CHAN_5GHZ(c)) 1428 reset.flags |= htobe32(UATH_CHAN_5GHZ); 1429 /* NB: 11g =>'s 11b so don't specify both OFDM and CCK */ 1430 if (IEEE80211_IS_CHAN_OFDM(c)) 1431 reset.flags |= htobe32(UATH_CHAN_OFDM); 1432 else if (IEEE80211_IS_CHAN_CCK(c)) 1433 reset.flags |= htobe32(UATH_CHAN_CCK); 1434 /* turbo can be used in either 2GHz or 5GHz */ 1435 if (c->ic_flags & IEEE80211_CHAN_TURBO) 1436 reset.flags |= htobe32(UATH_CHAN_TURBO); 1437 reset.freq = htobe32(c->ic_freq); 1438 reset.maxrdpower = htobe32(50); /* XXX */ 1439 reset.channelchange = htobe32(1); 1440 reset.keeprccontent = htobe32(0); 1441 1442 DPRINTF(sc, UATH_DEBUG_CHANNEL, "set channel %d, flags 0x%x freq %u\n", 1443 ieee80211_chan2ieee(ic, c), 1444 be32toh(reset.flags), be32toh(reset.freq)); 1445 return uath_cmd_write(sc, WDCMSG_RESET, &reset, sizeof reset, 0); 1446 } 1447 1448 static int 1449 uath_reset_tx_queues(struct uath_softc *sc) 1450 { 1451 int ac, error; 1452 1453 DPRINTF(sc, UATH_DEBUG_RESET, "%s: reset Tx queues\n", __func__); 1454 for (ac = 0; ac < 4; ac++) { 1455 const uint32_t qid = htobe32(ac); 1456 1457 error = uath_cmd_write(sc, WDCMSG_RELEASE_TX_QUEUE, &qid, 1458 sizeof qid, 0); 1459 if (error != 0) 1460 break; 1461 } 1462 return (error); 1463 } 1464 1465 static int 1466 uath_wme_init(struct uath_softc *sc) 1467 { 1468 /* XXX get from net80211 */ 1469 static const struct uath_wme_settings uath_wme_11g[4] = { 1470 { 7, 4, 10, 0, 0 }, /* Background */ 1471 { 3, 4, 10, 0, 0 }, /* Best-Effort */ 1472 { 3, 3, 4, 26, 0 }, /* Video */ 1473 { 2, 2, 3, 47, 0 } /* Voice */ 1474 }; 1475 struct uath_cmd_txq_setup qinfo; 1476 int ac, error; 1477 1478 DPRINTF(sc, UATH_DEBUG_WME, "%s: setup Tx queues\n", __func__); 1479 for (ac = 0; ac < 4; ac++) { 1480 qinfo.qid = htobe32(ac); 1481 qinfo.len = htobe32(sizeof(qinfo.attr)); 1482 qinfo.attr.priority = htobe32(ac); /* XXX */ 1483 qinfo.attr.aifs = htobe32(uath_wme_11g[ac].aifsn); 1484 qinfo.attr.logcwmin = htobe32(uath_wme_11g[ac].logcwmin); 1485 qinfo.attr.logcwmax = htobe32(uath_wme_11g[ac].logcwmax); 1486 qinfo.attr.bursttime = htobe32(IEEE80211_TXOP_TO_US( 1487 uath_wme_11g[ac].txop)); 1488 qinfo.attr.mode = htobe32(uath_wme_11g[ac].acm);/*XXX? */ 1489 qinfo.attr.qflags = htobe32(1); /* XXX? */ 1490 1491 error = uath_cmd_write(sc, WDCMSG_SETUP_TX_QUEUE, &qinfo, 1492 sizeof qinfo, 0); 1493 if (error != 0) 1494 break; 1495 } 1496 return (error); 1497 } 1498 1499 static void 1500 uath_parent(struct ieee80211com *ic) 1501 { 1502 struct uath_softc *sc = ic->ic_softc; 1503 int startall = 0; 1504 1505 UATH_LOCK(sc); 1506 if (sc->sc_flags & UATH_FLAG_INVALID) { 1507 UATH_UNLOCK(sc); 1508 return; 1509 } 1510 1511 if (ic->ic_nrunning > 0) { 1512 if (!(sc->sc_flags & UATH_FLAG_INITDONE)) { 1513 uath_init(sc); 1514 startall = 1; 1515 } 1516 } else if (sc->sc_flags & UATH_FLAG_INITDONE) 1517 uath_stop(sc); 1518 UATH_UNLOCK(sc); 1519 if (startall) 1520 ieee80211_start_all(ic); 1521 } 1522 1523 static int 1524 uath_tx_start(struct uath_softc *sc, struct mbuf *m0, struct ieee80211_node *ni, 1525 struct uath_data *data) 1526 { 1527 struct ieee80211vap *vap = ni->ni_vap; 1528 struct uath_chunk *chunk; 1529 struct uath_tx_desc *desc; 1530 const struct ieee80211_frame *wh; 1531 struct ieee80211_key *k; 1532 int framelen, msglen; 1533 1534 UATH_ASSERT_LOCKED(sc); 1535 1536 data->ni = ni; 1537 data->m = m0; 1538 chunk = (struct uath_chunk *)data->buf; 1539 desc = (struct uath_tx_desc *)(chunk + 1); 1540 1541 if (ieee80211_radiotap_active_vap(vap)) { 1542 struct uath_tx_radiotap_header *tap = &sc->sc_txtap; 1543 1544 tap->wt_flags = 0; 1545 if (m0->m_flags & M_FRAG) 1546 tap->wt_flags |= IEEE80211_RADIOTAP_F_FRAG; 1547 1548 ieee80211_radiotap_tx(vap, m0); 1549 } 1550 1551 wh = mtod(m0, struct ieee80211_frame *); 1552 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1553 k = ieee80211_crypto_encap(ni, m0); 1554 if (k == NULL) { 1555 m_freem(m0); 1556 return (ENOBUFS); 1557 } 1558 1559 /* packet header may have moved, reset our local pointer */ 1560 wh = mtod(m0, struct ieee80211_frame *); 1561 } 1562 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)(desc + 1)); 1563 1564 framelen = m0->m_pkthdr.len + IEEE80211_CRC_LEN; 1565 msglen = framelen + sizeof (struct uath_tx_desc); 1566 data->buflen = msglen + sizeof (struct uath_chunk); 1567 1568 /* one chunk only for now */ 1569 chunk->seqnum = sc->sc_seqnum++; 1570 chunk->flags = (m0->m_flags & M_FRAG) ? 0 : UATH_CFLAGS_FINAL; 1571 if (m0->m_flags & M_LASTFRAG) 1572 chunk->flags |= UATH_CFLAGS_FINAL; 1573 chunk->flags = UATH_CFLAGS_FINAL; 1574 chunk->length = htobe16(msglen); 1575 1576 /* fill Tx descriptor */ 1577 desc->msglen = htobe32(msglen); 1578 /* NB: to get UATH_TX_NOTIFY reply, `msgid' must be larger than 0 */ 1579 desc->msgid = (sc->sc_msgid++) + 1; /* don't care about endianness */ 1580 desc->type = htobe32(WDCMSG_SEND); 1581 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 1582 case IEEE80211_FC0_TYPE_CTL: 1583 case IEEE80211_FC0_TYPE_MGT: 1584 /* NB: force all management frames to highest queue */ 1585 if (ni->ni_flags & IEEE80211_NODE_QOS) { 1586 /* NB: force all management frames to highest queue */ 1587 desc->txqid = htobe32(WME_AC_VO | UATH_TXQID_MINRATE); 1588 } else 1589 desc->txqid = htobe32(WME_AC_BE | UATH_TXQID_MINRATE); 1590 break; 1591 case IEEE80211_FC0_TYPE_DATA: 1592 /* XXX multicast frames should honor mcastrate */ 1593 desc->txqid = htobe32(M_WME_GETAC(m0)); 1594 break; 1595 default: 1596 device_printf(sc->sc_dev, "bogus frame type 0x%x (%s)\n", 1597 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__); 1598 m_freem(m0); 1599 return (EIO); 1600 } 1601 if (vap->iv_state == IEEE80211_S_AUTH || 1602 vap->iv_state == IEEE80211_S_ASSOC || 1603 vap->iv_state == IEEE80211_S_RUN) 1604 desc->connid = htobe32(UATH_ID_BSS); 1605 else 1606 desc->connid = htobe32(UATH_ID_INVALID); 1607 desc->flags = htobe32(0 /* no UATH_TX_NOTIFY */); 1608 desc->buflen = htobe32(m0->m_pkthdr.len); 1609 1610 #ifdef UATH_DEBUG 1611 DPRINTF(sc, UATH_DEBUG_XMIT, 1612 "send frame ix %u framelen %d msglen %d connid 0x%x txqid 0x%x\n", 1613 desc->msgid, framelen, msglen, be32toh(desc->connid), 1614 be32toh(desc->txqid)); 1615 if (sc->sc_debug & UATH_DEBUG_XMIT_DUMP) 1616 uath_dump_cmd(data->buf, data->buflen, '+'); 1617 #endif 1618 1619 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 1620 UATH_STAT_INC(sc, st_tx_pending); 1621 usbd_transfer_start(sc->sc_xfer[UATH_BULK_TX]); 1622 1623 return (0); 1624 } 1625 1626 /* 1627 * Cleanup driver resources when we run out of buffers while processing 1628 * fragments; return the tx buffers allocated and drop node references. 1629 */ 1630 static void 1631 uath_txfrag_cleanup(struct uath_softc *sc, 1632 uath_datahead *frags, struct ieee80211_node *ni) 1633 { 1634 struct uath_data *bf, *next; 1635 1636 UATH_ASSERT_LOCKED(sc); 1637 1638 STAILQ_FOREACH_SAFE(bf, frags, next, next) { 1639 /* NB: bf assumed clean */ 1640 STAILQ_REMOVE_HEAD(frags, next); 1641 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 1642 UATH_STAT_INC(sc, st_tx_inactive); 1643 ieee80211_node_decref(ni); 1644 } 1645 } 1646 1647 /* 1648 * Setup xmit of a fragmented frame. Allocate a buffer for each frag and bump 1649 * the node reference count to reflect the held reference to be setup by 1650 * uath_tx_start. 1651 */ 1652 static int 1653 uath_txfrag_setup(struct uath_softc *sc, uath_datahead *frags, 1654 struct mbuf *m0, struct ieee80211_node *ni) 1655 { 1656 struct mbuf *m; 1657 struct uath_data *bf; 1658 1659 UATH_ASSERT_LOCKED(sc); 1660 for (m = m0->m_nextpkt; m != NULL; m = m->m_nextpkt) { 1661 bf = uath_getbuf(sc); 1662 if (bf == NULL) { /* out of buffers, cleanup */ 1663 uath_txfrag_cleanup(sc, frags, ni); 1664 break; 1665 } 1666 (void) ieee80211_ref_node(ni); 1667 STAILQ_INSERT_TAIL(frags, bf, next); 1668 } 1669 1670 return !STAILQ_EMPTY(frags); 1671 } 1672 1673 static int 1674 uath_transmit(struct ieee80211com *ic, struct mbuf *m) 1675 { 1676 struct uath_softc *sc = ic->ic_softc; 1677 int error; 1678 1679 UATH_LOCK(sc); 1680 if ((sc->sc_flags & UATH_FLAG_INITDONE) == 0) { 1681 UATH_UNLOCK(sc); 1682 return (ENXIO); 1683 } 1684 error = mbufq_enqueue(&sc->sc_snd, m); 1685 if (error) { 1686 UATH_UNLOCK(sc); 1687 return (error); 1688 } 1689 uath_start(sc); 1690 UATH_UNLOCK(sc); 1691 1692 return (0); 1693 } 1694 1695 static void 1696 uath_start(struct uath_softc *sc) 1697 { 1698 struct uath_data *bf; 1699 struct ieee80211_node *ni; 1700 struct mbuf *m, *next; 1701 uath_datahead frags; 1702 1703 UATH_ASSERT_LOCKED(sc); 1704 1705 if ((sc->sc_flags & UATH_FLAG_INITDONE) == 0 || 1706 (sc->sc_flags & UATH_FLAG_INVALID)) 1707 return; 1708 1709 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1710 bf = uath_getbuf(sc); 1711 if (bf == NULL) { 1712 mbufq_prepend(&sc->sc_snd, m); 1713 break; 1714 } 1715 1716 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1717 m->m_pkthdr.rcvif = NULL; 1718 1719 /* 1720 * Check for fragmentation. If this frame has been broken up 1721 * verify we have enough buffers to send all the fragments 1722 * so all go out or none... 1723 */ 1724 STAILQ_INIT(&frags); 1725 if ((m->m_flags & M_FRAG) && 1726 !uath_txfrag_setup(sc, &frags, m, ni)) { 1727 DPRINTF(sc, UATH_DEBUG_XMIT, 1728 "%s: out of txfrag buffers\n", __func__); 1729 ieee80211_free_mbuf(m); 1730 goto bad; 1731 } 1732 sc->sc_seqnum = 0; 1733 nextfrag: 1734 /* 1735 * Pass the frame to the h/w for transmission. 1736 * Fragmented frames have each frag chained together 1737 * with m_nextpkt. We know there are sufficient uath_data's 1738 * to send all the frags because of work done by 1739 * uath_txfrag_setup. 1740 */ 1741 next = m->m_nextpkt; 1742 if (uath_tx_start(sc, m, ni, bf) != 0) { 1743 bad: 1744 if_inc_counter(ni->ni_vap->iv_ifp, 1745 IFCOUNTER_OERRORS, 1); 1746 reclaim: 1747 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 1748 UATH_STAT_INC(sc, st_tx_inactive); 1749 uath_txfrag_cleanup(sc, &frags, ni); 1750 ieee80211_free_node(ni); 1751 continue; 1752 } 1753 1754 if (next != NULL) { 1755 /* 1756 * Beware of state changing between frags. 1757 XXX check sta power-save state? 1758 */ 1759 if (ni->ni_vap->iv_state != IEEE80211_S_RUN) { 1760 DPRINTF(sc, UATH_DEBUG_XMIT, 1761 "%s: flush fragmented packet, state %s\n", 1762 __func__, 1763 ieee80211_state_name[ni->ni_vap->iv_state]); 1764 ieee80211_free_mbuf(next); 1765 goto reclaim; 1766 } 1767 m = next; 1768 bf = STAILQ_FIRST(&frags); 1769 KASSERT(bf != NULL, ("no buf for txfrag")); 1770 STAILQ_REMOVE_HEAD(&frags, next); 1771 goto nextfrag; 1772 } 1773 1774 sc->sc_tx_timer = 5; 1775 } 1776 } 1777 1778 static int 1779 uath_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1780 const struct ieee80211_bpf_params *params) 1781 { 1782 struct ieee80211com *ic = ni->ni_ic; 1783 struct uath_data *bf; 1784 struct uath_softc *sc = ic->ic_softc; 1785 1786 UATH_LOCK(sc); 1787 /* prevent management frames from being sent if we're not ready */ 1788 if ((sc->sc_flags & UATH_FLAG_INVALID) || 1789 !(sc->sc_flags & UATH_FLAG_INITDONE)) { 1790 m_freem(m); 1791 UATH_UNLOCK(sc); 1792 return (ENETDOWN); 1793 } 1794 1795 /* grab a TX buffer */ 1796 bf = uath_getbuf(sc); 1797 if (bf == NULL) { 1798 m_freem(m); 1799 UATH_UNLOCK(sc); 1800 return (ENOBUFS); 1801 } 1802 1803 sc->sc_seqnum = 0; 1804 if (uath_tx_start(sc, m, ni, bf) != 0) { 1805 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 1806 UATH_STAT_INC(sc, st_tx_inactive); 1807 UATH_UNLOCK(sc); 1808 return (EIO); 1809 } 1810 UATH_UNLOCK(sc); 1811 1812 sc->sc_tx_timer = 5; 1813 return (0); 1814 } 1815 1816 static void 1817 uath_scan_start(struct ieee80211com *ic) 1818 { 1819 /* do nothing */ 1820 } 1821 1822 static void 1823 uath_scan_end(struct ieee80211com *ic) 1824 { 1825 /* do nothing */ 1826 } 1827 1828 static void 1829 uath_set_channel(struct ieee80211com *ic) 1830 { 1831 struct uath_softc *sc = ic->ic_softc; 1832 1833 UATH_LOCK(sc); 1834 if ((sc->sc_flags & UATH_FLAG_INVALID) || 1835 (sc->sc_flags & UATH_FLAG_INITDONE) == 0) { 1836 UATH_UNLOCK(sc); 1837 return; 1838 } 1839 /* flush data & control requests into the target */ 1840 (void)uath_flush(sc); 1841 (void)uath_switch_channel(sc, ic->ic_curchan); 1842 UATH_UNLOCK(sc); 1843 } 1844 1845 static int 1846 uath_set_rxmulti_filter(struct uath_softc *sc) 1847 { 1848 /* XXX broken */ 1849 return (0); 1850 } 1851 static void 1852 uath_update_mcast(struct ieee80211com *ic) 1853 { 1854 struct uath_softc *sc = ic->ic_softc; 1855 1856 UATH_LOCK(sc); 1857 if ((sc->sc_flags & UATH_FLAG_INVALID) || 1858 (sc->sc_flags & UATH_FLAG_INITDONE) == 0) { 1859 UATH_UNLOCK(sc); 1860 return; 1861 } 1862 /* 1863 * this is for avoiding the race condition when we're try to 1864 * connect to the AP with WPA. 1865 */ 1866 if (sc->sc_flags & UATH_FLAG_INITDONE) 1867 (void)uath_set_rxmulti_filter(sc); 1868 UATH_UNLOCK(sc); 1869 } 1870 1871 static void 1872 uath_update_promisc(struct ieee80211com *ic) 1873 { 1874 struct uath_softc *sc = ic->ic_softc; 1875 1876 UATH_LOCK(sc); 1877 if ((sc->sc_flags & UATH_FLAG_INVALID) || 1878 (sc->sc_flags & UATH_FLAG_INITDONE) == 0) { 1879 UATH_UNLOCK(sc); 1880 return; 1881 } 1882 if (sc->sc_flags & UATH_FLAG_INITDONE) { 1883 uath_set_rxfilter(sc, 1884 UATH_FILTER_RX_UCAST | UATH_FILTER_RX_MCAST | 1885 UATH_FILTER_RX_BCAST | UATH_FILTER_RX_BEACON | 1886 UATH_FILTER_RX_PROM, UATH_FILTER_OP_SET); 1887 } 1888 UATH_UNLOCK(sc); 1889 } 1890 1891 static int 1892 uath_create_connection(struct uath_softc *sc, uint32_t connid) 1893 { 1894 const struct ieee80211_rateset *rs; 1895 struct ieee80211com *ic = &sc->sc_ic; 1896 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1897 struct ieee80211_node *ni; 1898 struct uath_cmd_create_connection create; 1899 1900 ni = ieee80211_ref_node(vap->iv_bss); 1901 memset(&create, 0, sizeof(create)); 1902 create.connid = htobe32(connid); 1903 create.bssid = htobe32(0); 1904 /* XXX packed or not? */ 1905 create.size = htobe32(sizeof(struct uath_cmd_rateset)); 1906 1907 rs = &ni->ni_rates; 1908 create.connattr.rateset.length = rs->rs_nrates; 1909 bcopy(rs->rs_rates, &create.connattr.rateset.set[0], 1910 rs->rs_nrates); 1911 1912 /* XXX turbo */ 1913 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) 1914 create.connattr.wlanmode = htobe32(WLAN_MODE_11a); 1915 else if (IEEE80211_IS_CHAN_ANYG(ni->ni_chan)) 1916 create.connattr.wlanmode = htobe32(WLAN_MODE_11g); 1917 else 1918 create.connattr.wlanmode = htobe32(WLAN_MODE_11b); 1919 ieee80211_free_node(ni); 1920 1921 return uath_cmd_write(sc, WDCMSG_CREATE_CONNECTION, &create, 1922 sizeof create, 0); 1923 } 1924 1925 static int 1926 uath_set_rates(struct uath_softc *sc, const struct ieee80211_rateset *rs) 1927 { 1928 struct uath_cmd_rates rates; 1929 1930 memset(&rates, 0, sizeof(rates)); 1931 rates.connid = htobe32(UATH_ID_BSS); /* XXX */ 1932 rates.size = htobe32(sizeof(struct uath_cmd_rateset)); 1933 /* XXX bounds check rs->rs_nrates */ 1934 rates.rateset.length = rs->rs_nrates; 1935 bcopy(rs->rs_rates, &rates.rateset.set[0], rs->rs_nrates); 1936 1937 DPRINTF(sc, UATH_DEBUG_RATES, 1938 "setting supported rates nrates=%d\n", rs->rs_nrates); 1939 return uath_cmd_write(sc, WDCMSG_SET_BASIC_RATE, 1940 &rates, sizeof rates, 0); 1941 } 1942 1943 static int 1944 uath_write_associd(struct uath_softc *sc) 1945 { 1946 struct ieee80211com *ic = &sc->sc_ic; 1947 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1948 struct ieee80211_node *ni; 1949 struct uath_cmd_set_associd associd; 1950 1951 ni = ieee80211_ref_node(vap->iv_bss); 1952 memset(&associd, 0, sizeof(associd)); 1953 associd.defaultrateix = htobe32(1); /* XXX */ 1954 associd.associd = htobe32(ni->ni_associd); 1955 associd.timoffset = htobe32(0x3b); /* XXX */ 1956 IEEE80211_ADDR_COPY(associd.bssid, ni->ni_bssid); 1957 ieee80211_free_node(ni); 1958 return uath_cmd_write(sc, WDCMSG_WRITE_ASSOCID, &associd, 1959 sizeof associd, 0); 1960 } 1961 1962 static int 1963 uath_set_ledsteady(struct uath_softc *sc, int lednum, int ledmode) 1964 { 1965 struct uath_cmd_ledsteady led; 1966 1967 led.lednum = htobe32(lednum); 1968 led.ledmode = htobe32(ledmode); 1969 1970 DPRINTF(sc, UATH_DEBUG_LED, "set %s led %s (steady)\n", 1971 (lednum == UATH_LED_LINK) ? "link" : "activity", 1972 ledmode ? "on" : "off"); 1973 return uath_cmd_write(sc, WDCMSG_SET_LED_STEADY, &led, sizeof led, 0); 1974 } 1975 1976 static int 1977 uath_set_ledblink(struct uath_softc *sc, int lednum, int ledmode, 1978 int blinkrate, int slowmode) 1979 { 1980 struct uath_cmd_ledblink led; 1981 1982 led.lednum = htobe32(lednum); 1983 led.ledmode = htobe32(ledmode); 1984 led.blinkrate = htobe32(blinkrate); 1985 led.slowmode = htobe32(slowmode); 1986 1987 DPRINTF(sc, UATH_DEBUG_LED, "set %s led %s (blink)\n", 1988 (lednum == UATH_LED_LINK) ? "link" : "activity", 1989 ledmode ? "on" : "off"); 1990 return uath_cmd_write(sc, WDCMSG_SET_LED_BLINK, &led, sizeof led, 0); 1991 } 1992 1993 static int 1994 uath_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1995 { 1996 enum ieee80211_state ostate = vap->iv_state; 1997 int error; 1998 struct ieee80211_node *ni; 1999 struct ieee80211com *ic = vap->iv_ic; 2000 struct uath_softc *sc = ic->ic_softc; 2001 struct uath_vap *uvp = UATH_VAP(vap); 2002 2003 DPRINTF(sc, UATH_DEBUG_STATE, 2004 "%s: %s -> %s\n", __func__, ieee80211_state_name[vap->iv_state], 2005 ieee80211_state_name[nstate]); 2006 2007 IEEE80211_UNLOCK(ic); 2008 UATH_LOCK(sc); 2009 callout_stop(&sc->stat_ch); 2010 callout_stop(&sc->watchdog_ch); 2011 ni = ieee80211_ref_node(vap->iv_bss); 2012 2013 switch (nstate) { 2014 case IEEE80211_S_INIT: 2015 if (ostate == IEEE80211_S_RUN) { 2016 /* turn link and activity LEDs off */ 2017 uath_set_ledstate(sc, 0); 2018 } 2019 break; 2020 2021 case IEEE80211_S_SCAN: 2022 break; 2023 2024 case IEEE80211_S_AUTH: 2025 /* flush data & control requests into the target */ 2026 (void)uath_flush(sc); 2027 /* XXX good place? set RTS threshold */ 2028 uath_config(sc, CFG_USER_RTS_THRESHOLD, vap->iv_rtsthreshold); 2029 /* XXX bad place */ 2030 error = uath_set_keys(sc, vap); 2031 if (error != 0) { 2032 device_printf(sc->sc_dev, 2033 "could not set crypto keys, error %d\n", error); 2034 break; 2035 } 2036 if (uath_switch_channel(sc, ni->ni_chan) != 0) { 2037 device_printf(sc->sc_dev, "could not switch channel\n"); 2038 break; 2039 } 2040 if (uath_create_connection(sc, UATH_ID_BSS) != 0) { 2041 device_printf(sc->sc_dev, 2042 "could not create connection\n"); 2043 break; 2044 } 2045 break; 2046 2047 case IEEE80211_S_ASSOC: 2048 if (uath_set_rates(sc, &ni->ni_rates) != 0) { 2049 device_printf(sc->sc_dev, 2050 "could not set negotiated rate set\n"); 2051 break; 2052 } 2053 break; 2054 2055 case IEEE80211_S_RUN: 2056 /* XXX monitor mode doesn't be tested */ 2057 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2058 uath_set_ledstate(sc, 1); 2059 break; 2060 } 2061 2062 /* 2063 * Tx rate is controlled by firmware, report the maximum 2064 * negotiated rate in ifconfig output. 2065 */ 2066 ieee80211_node_set_txrate_dot11rate(ni, 2067 ni->ni_rates.rs_rates[ni->ni_rates.rs_nrates-1]); 2068 2069 if (uath_write_associd(sc) != 0) { 2070 device_printf(sc->sc_dev, 2071 "could not write association id\n"); 2072 break; 2073 } 2074 /* turn link LED on */ 2075 uath_set_ledsteady(sc, UATH_LED_LINK, UATH_LED_ON); 2076 /* make activity LED blink */ 2077 uath_set_ledblink(sc, UATH_LED_ACTIVITY, UATH_LED_ON, 1, 2); 2078 /* set state to associated */ 2079 uath_set_ledstate(sc, 1); 2080 2081 /* start statistics timer */ 2082 callout_reset(&sc->stat_ch, hz, uath_stat, sc); 2083 break; 2084 default: 2085 break; 2086 } 2087 ieee80211_free_node(ni); 2088 UATH_UNLOCK(sc); 2089 IEEE80211_LOCK(ic); 2090 return (uvp->newstate(vap, nstate, arg)); 2091 } 2092 2093 static int 2094 uath_set_key(struct uath_softc *sc, const struct ieee80211_key *wk, 2095 int index) 2096 { 2097 #if 0 2098 struct uath_cmd_crypto crypto; 2099 int i; 2100 2101 memset(&crypto, 0, sizeof(crypto)); 2102 crypto.keyidx = htobe32(index); 2103 crypto.magic1 = htobe32(1); 2104 crypto.size = htobe32(368); 2105 crypto.mask = htobe32(0xffff); 2106 crypto.flags = htobe32(0x80000068); 2107 if (index != UATH_DEFAULT_KEY) 2108 crypto.flags |= htobe32(index << 16); 2109 memset(crypto.magic2, 0xff, sizeof(crypto.magic2)); 2110 2111 /* 2112 * Each byte of the key must be XOR'ed with 10101010 before being 2113 * transmitted to the firmware. 2114 */ 2115 for (i = 0; i < wk->wk_keylen; i++) 2116 crypto.key[i] = wk->wk_key[i] ^ 0xaa; 2117 2118 DPRINTF(sc, UATH_DEBUG_CRYPTO, 2119 "setting crypto key index=%d len=%d\n", index, wk->wk_keylen); 2120 return uath_cmd_write(sc, WDCMSG_SET_KEY_CACHE_ENTRY, &crypto, 2121 sizeof crypto, 0); 2122 #else 2123 /* XXX support H/W cryto */ 2124 return (0); 2125 #endif 2126 } 2127 2128 static int 2129 uath_set_keys(struct uath_softc *sc, struct ieee80211vap *vap) 2130 { 2131 int i, error; 2132 2133 error = 0; 2134 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2135 const struct ieee80211_key *wk = &vap->iv_nw_keys[i]; 2136 2137 if (wk->wk_flags & (IEEE80211_KEY_XMIT|IEEE80211_KEY_RECV)) { 2138 error = uath_set_key(sc, wk, i); 2139 if (error) 2140 return (error); 2141 } 2142 } 2143 if (vap->iv_def_txkey != IEEE80211_KEYIX_NONE) { 2144 error = uath_set_key(sc, &vap->iv_nw_keys[vap->iv_def_txkey], 2145 UATH_DEFAULT_KEY); 2146 } 2147 return (error); 2148 } 2149 2150 #define UATH_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 2151 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 2152 2153 static void 2154 uath_sysctl_node(struct uath_softc *sc) 2155 { 2156 struct sysctl_ctx_list *ctx; 2157 struct sysctl_oid_list *child; 2158 struct sysctl_oid *tree; 2159 struct uath_stat *stats; 2160 2161 stats = &sc->sc_stat; 2162 ctx = device_get_sysctl_ctx(sc->sc_dev); 2163 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->sc_dev)); 2164 2165 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 2166 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "UATH statistics"); 2167 child = SYSCTL_CHILDREN(tree); 2168 UATH_SYSCTL_STAT_ADD32(ctx, child, "badchunkseqnum", 2169 &stats->st_badchunkseqnum, "Bad chunk sequence numbers"); 2170 UATH_SYSCTL_STAT_ADD32(ctx, child, "invalidlen", &stats->st_invalidlen, 2171 "Invalid length"); 2172 UATH_SYSCTL_STAT_ADD32(ctx, child, "multichunk", &stats->st_multichunk, 2173 "Multi chunks"); 2174 UATH_SYSCTL_STAT_ADD32(ctx, child, "toobigrxpkt", 2175 &stats->st_toobigrxpkt, "Too big rx packets"); 2176 UATH_SYSCTL_STAT_ADD32(ctx, child, "stopinprogress", 2177 &stats->st_stopinprogress, "Stop in progress"); 2178 UATH_SYSCTL_STAT_ADD32(ctx, child, "crcerrs", &stats->st_crcerr, 2179 "CRC errors"); 2180 UATH_SYSCTL_STAT_ADD32(ctx, child, "phyerr", &stats->st_phyerr, 2181 "PHY errors"); 2182 UATH_SYSCTL_STAT_ADD32(ctx, child, "decrypt_crcerr", 2183 &stats->st_decrypt_crcerr, "Decryption CRC errors"); 2184 UATH_SYSCTL_STAT_ADD32(ctx, child, "decrypt_micerr", 2185 &stats->st_decrypt_micerr, "Decryption Misc errors"); 2186 UATH_SYSCTL_STAT_ADD32(ctx, child, "decomperr", &stats->st_decomperr, 2187 "Decomp errors"); 2188 UATH_SYSCTL_STAT_ADD32(ctx, child, "keyerr", &stats->st_keyerr, 2189 "Key errors"); 2190 UATH_SYSCTL_STAT_ADD32(ctx, child, "err", &stats->st_err, 2191 "Unknown errors"); 2192 2193 UATH_SYSCTL_STAT_ADD32(ctx, child, "cmd_active", 2194 &stats->st_cmd_active, "Active numbers in Command queue"); 2195 UATH_SYSCTL_STAT_ADD32(ctx, child, "cmd_inactive", 2196 &stats->st_cmd_inactive, "Inactive numbers in Command queue"); 2197 UATH_SYSCTL_STAT_ADD32(ctx, child, "cmd_pending", 2198 &stats->st_cmd_pending, "Pending numbers in Command queue"); 2199 UATH_SYSCTL_STAT_ADD32(ctx, child, "cmd_waiting", 2200 &stats->st_cmd_waiting, "Waiting numbers in Command queue"); 2201 UATH_SYSCTL_STAT_ADD32(ctx, child, "rx_active", 2202 &stats->st_rx_active, "Active numbers in RX queue"); 2203 UATH_SYSCTL_STAT_ADD32(ctx, child, "rx_inactive", 2204 &stats->st_rx_inactive, "Inactive numbers in RX queue"); 2205 UATH_SYSCTL_STAT_ADD32(ctx, child, "tx_active", 2206 &stats->st_tx_active, "Active numbers in TX queue"); 2207 UATH_SYSCTL_STAT_ADD32(ctx, child, "tx_inactive", 2208 &stats->st_tx_inactive, "Inactive numbers in TX queue"); 2209 UATH_SYSCTL_STAT_ADD32(ctx, child, "tx_pending", 2210 &stats->st_tx_pending, "Pending numbers in TX queue"); 2211 } 2212 2213 #undef UATH_SYSCTL_STAT_ADD32 2214 2215 CTASSERT(sizeof(u_int) >= sizeof(uint32_t)); 2216 2217 static void 2218 uath_cmdeof(struct uath_softc *sc, struct uath_cmd *cmd) 2219 { 2220 struct uath_cmd_hdr *hdr; 2221 uint32_t dlen; 2222 2223 hdr = (struct uath_cmd_hdr *)cmd->buf; 2224 /* NB: msgid is passed thru w/o byte swapping */ 2225 #ifdef UATH_DEBUG 2226 if (sc->sc_debug & UATH_DEBUG_CMDS) { 2227 uint32_t len = be32toh(hdr->len); 2228 printf("%s: %s [ix %u] len %u status %u\n", 2229 __func__, uath_codename(be32toh(hdr->code)), 2230 hdr->msgid, len, be32toh(hdr->magic)); 2231 if (sc->sc_debug & UATH_DEBUG_CMDS_DUMP) 2232 uath_dump_cmd(cmd->buf, 2233 len > UATH_MAX_CMDSZ ? sizeof(*hdr) : len, '-'); 2234 } 2235 #endif 2236 hdr->code = be32toh(hdr->code); 2237 hdr->len = be32toh(hdr->len); 2238 hdr->magic = be32toh(hdr->magic); /* target status on return */ 2239 2240 switch (hdr->code & 0xff) { 2241 /* reply to a read command */ 2242 default: 2243 DPRINTF(sc, UATH_DEBUG_RX_PROC | UATH_DEBUG_RECV_ALL, 2244 "%s: code %d hdr len %u\n", 2245 __func__, hdr->code & 0xff, hdr->len); 2246 /* 2247 * The first response from the target after the 2248 * HOST_AVAILABLE has an invalid msgid so we must 2249 * treat it specially. 2250 */ 2251 if (hdr->msgid < UATH_CMD_LIST_COUNT) { 2252 uint32_t *rp = (uint32_t *)(hdr+1); 2253 u_int olen; 2254 2255 if (sizeof(*hdr) > hdr->len || 2256 hdr->len > UATH_MAX_CMDSZ) { 2257 device_printf(sc->sc_dev, 2258 "%s: invalid WDC msg length %u; " 2259 "msg ignored\n", __func__, hdr->len); 2260 return; 2261 } 2262 /* 2263 * Calculate return/receive payload size; the 2264 * first word, if present, always gives the 2265 * number of bytes--unless it's 0 in which 2266 * case a single 32-bit word should be present. 2267 */ 2268 dlen = hdr->len - sizeof(*hdr); 2269 if (dlen >= sizeof(uint32_t)) { 2270 olen = be32toh(rp[0]); 2271 dlen -= sizeof(uint32_t); 2272 if (olen == 0) { 2273 /* convention is 0 =>'s one word */ 2274 olen = sizeof(uint32_t); 2275 /* XXX KASSERT(olen == dlen ) */ 2276 } 2277 } else 2278 olen = 0; 2279 if (cmd->odata != NULL) { 2280 /* NB: cmd->olen validated in uath_cmd */ 2281 if (olen > (u_int)cmd->olen) { 2282 /* XXX complain? */ 2283 device_printf(sc->sc_dev, 2284 "%s: cmd 0x%x olen %u cmd olen %u\n", 2285 __func__, hdr->code, olen, 2286 cmd->olen); 2287 olen = cmd->olen; 2288 } 2289 if (olen > dlen) { 2290 /* XXX complain, shouldn't happen */ 2291 device_printf(sc->sc_dev, 2292 "%s: cmd 0x%x olen %u dlen %u\n", 2293 __func__, hdr->code, olen, dlen); 2294 olen = dlen; 2295 } 2296 /* XXX have submitter do this */ 2297 /* copy answer into caller's supplied buffer */ 2298 bcopy(&rp[1], cmd->odata, olen); 2299 cmd->olen = olen; 2300 } 2301 } 2302 wakeup_one(cmd); /* wake up caller */ 2303 break; 2304 2305 case WDCMSG_TARGET_START: 2306 if (hdr->msgid >= UATH_CMD_LIST_COUNT) { 2307 /* XXX */ 2308 return; 2309 } 2310 dlen = hdr->len - sizeof(*hdr); 2311 if (dlen != sizeof(uint32_t)) { 2312 device_printf(sc->sc_dev, 2313 "%s: dlen (%u) != %zu!\n", 2314 __func__, dlen, sizeof(uint32_t)); 2315 return; 2316 } 2317 if (cmd->odata != NULL) { 2318 /* XXX have submitter do this */ 2319 /* copy answer into caller's supplied buffer */ 2320 bcopy(hdr+1, cmd->odata, sizeof(uint32_t)); 2321 cmd->olen = sizeof(uint32_t); 2322 } 2323 wakeup_one(cmd); /* wake up caller */ 2324 break; 2325 2326 case WDCMSG_SEND_COMPLETE: 2327 /* this notification is sent when UATH_TX_NOTIFY is set */ 2328 DPRINTF(sc, UATH_DEBUG_RX_PROC | UATH_DEBUG_RECV_ALL, 2329 "%s: received Tx notification\n", __func__); 2330 break; 2331 2332 case WDCMSG_TARGET_GET_STATS: 2333 DPRINTF(sc, UATH_DEBUG_RX_PROC | UATH_DEBUG_RECV_ALL, 2334 "%s: received device statistics\n", __func__); 2335 callout_reset(&sc->stat_ch, hz, uath_stat, sc); 2336 break; 2337 } 2338 } 2339 2340 static void 2341 uath_intr_rx_callback(struct usb_xfer *xfer, usb_error_t error) 2342 { 2343 struct uath_softc *sc = usbd_xfer_softc(xfer); 2344 struct uath_cmd *cmd; 2345 struct uath_cmd_hdr *hdr; 2346 struct usb_page_cache *pc; 2347 int actlen; 2348 2349 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 2350 2351 UATH_ASSERT_LOCKED(sc); 2352 2353 switch (USB_GET_STATE(xfer)) { 2354 case USB_ST_TRANSFERRED: 2355 cmd = STAILQ_FIRST(&sc->sc_cmd_waiting); 2356 if (cmd == NULL) 2357 goto setup; 2358 STAILQ_REMOVE_HEAD(&sc->sc_cmd_waiting, next); 2359 UATH_STAT_DEC(sc, st_cmd_waiting); 2360 STAILQ_INSERT_TAIL(&sc->sc_cmd_inactive, cmd, next); 2361 UATH_STAT_INC(sc, st_cmd_inactive); 2362 2363 if (actlen < sizeof(struct uath_cmd_hdr)) { 2364 device_printf(sc->sc_dev, 2365 "%s: short xfer error (actlen %d)\n", 2366 __func__, actlen); 2367 goto setup; 2368 } 2369 2370 pc = usbd_xfer_get_frame(xfer, 0); 2371 usbd_copy_out(pc, 0, cmd->buf, actlen); 2372 2373 hdr = (struct uath_cmd_hdr *)cmd->buf; 2374 if (be32toh(hdr->len) > (uint32_t)actlen) { 2375 device_printf(sc->sc_dev, 2376 "%s: truncated xfer (len %u, actlen %d)\n", 2377 __func__, be32toh(hdr->len), actlen); 2378 goto setup; 2379 } 2380 2381 uath_cmdeof(sc, cmd); 2382 case USB_ST_SETUP: 2383 setup: 2384 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 2385 usbd_transfer_submit(xfer); 2386 break; 2387 default: 2388 if (error != USB_ERR_CANCELLED) { 2389 usbd_xfer_set_stall(xfer); 2390 goto setup; 2391 } 2392 break; 2393 } 2394 } 2395 2396 static void 2397 uath_intr_tx_callback(struct usb_xfer *xfer, usb_error_t error) 2398 { 2399 struct uath_softc *sc = usbd_xfer_softc(xfer); 2400 struct uath_cmd *cmd; 2401 2402 UATH_ASSERT_LOCKED(sc); 2403 2404 cmd = STAILQ_FIRST(&sc->sc_cmd_active); 2405 if (cmd != NULL && USB_GET_STATE(xfer) != USB_ST_SETUP) { 2406 STAILQ_REMOVE_HEAD(&sc->sc_cmd_active, next); 2407 UATH_STAT_DEC(sc, st_cmd_active); 2408 STAILQ_INSERT_TAIL((cmd->flags & UATH_CMD_FLAG_READ) ? 2409 &sc->sc_cmd_waiting : &sc->sc_cmd_inactive, cmd, next); 2410 if (cmd->flags & UATH_CMD_FLAG_READ) 2411 UATH_STAT_INC(sc, st_cmd_waiting); 2412 else 2413 UATH_STAT_INC(sc, st_cmd_inactive); 2414 } 2415 2416 switch (USB_GET_STATE(xfer)) { 2417 case USB_ST_TRANSFERRED: 2418 case USB_ST_SETUP: 2419 setup: 2420 cmd = STAILQ_FIRST(&sc->sc_cmd_pending); 2421 if (cmd == NULL) { 2422 DPRINTF(sc, UATH_DEBUG_XMIT, "%s: empty pending queue\n", 2423 __func__); 2424 return; 2425 } 2426 STAILQ_REMOVE_HEAD(&sc->sc_cmd_pending, next); 2427 UATH_STAT_DEC(sc, st_cmd_pending); 2428 STAILQ_INSERT_TAIL((cmd->flags & UATH_CMD_FLAG_ASYNC) ? 2429 &sc->sc_cmd_inactive : &sc->sc_cmd_active, cmd, next); 2430 if (cmd->flags & UATH_CMD_FLAG_ASYNC) 2431 UATH_STAT_INC(sc, st_cmd_inactive); 2432 else 2433 UATH_STAT_INC(sc, st_cmd_active); 2434 2435 usbd_xfer_set_frame_data(xfer, 0, cmd->buf, cmd->buflen); 2436 usbd_transfer_submit(xfer); 2437 break; 2438 default: 2439 if (error != USB_ERR_CANCELLED) { 2440 usbd_xfer_set_stall(xfer); 2441 goto setup; 2442 } 2443 break; 2444 } 2445 } 2446 2447 static void 2448 uath_update_rxstat(struct uath_softc *sc, uint32_t status) 2449 { 2450 2451 switch (status) { 2452 case UATH_STATUS_STOP_IN_PROGRESS: 2453 UATH_STAT_INC(sc, st_stopinprogress); 2454 break; 2455 case UATH_STATUS_CRC_ERR: 2456 UATH_STAT_INC(sc, st_crcerr); 2457 break; 2458 case UATH_STATUS_PHY_ERR: 2459 UATH_STAT_INC(sc, st_phyerr); 2460 break; 2461 case UATH_STATUS_DECRYPT_CRC_ERR: 2462 UATH_STAT_INC(sc, st_decrypt_crcerr); 2463 break; 2464 case UATH_STATUS_DECRYPT_MIC_ERR: 2465 UATH_STAT_INC(sc, st_decrypt_micerr); 2466 break; 2467 case UATH_STATUS_DECOMP_ERR: 2468 UATH_STAT_INC(sc, st_decomperr); 2469 break; 2470 case UATH_STATUS_KEY_ERR: 2471 UATH_STAT_INC(sc, st_keyerr); 2472 break; 2473 case UATH_STATUS_ERR: 2474 UATH_STAT_INC(sc, st_err); 2475 break; 2476 default: 2477 break; 2478 } 2479 } 2480 2481 CTASSERT(UATH_MIN_RXBUFSZ >= sizeof(struct uath_chunk)); 2482 2483 static struct mbuf * 2484 uath_data_rxeof(struct usb_xfer *xfer, struct uath_data *data, 2485 struct uath_rx_desc **pdesc) 2486 { 2487 struct uath_softc *sc = usbd_xfer_softc(xfer); 2488 struct ieee80211com *ic = &sc->sc_ic; 2489 struct uath_chunk *chunk; 2490 struct uath_rx_desc *desc; 2491 struct mbuf *m = data->m, *mnew, *mp; 2492 uint16_t chunklen; 2493 int actlen; 2494 2495 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 2496 2497 if (actlen < (int)UATH_MIN_RXBUFSZ) { 2498 DPRINTF(sc, UATH_DEBUG_RECV | UATH_DEBUG_RECV_ALL, 2499 "%s: wrong xfer size (len=%d)\n", __func__, actlen); 2500 counter_u64_add(ic->ic_ierrors, 1); 2501 return (NULL); 2502 } 2503 2504 chunk = (struct uath_chunk *)data->buf; 2505 chunklen = be16toh(chunk->length); 2506 if (chunk->seqnum == 0 && chunk->flags == 0 && chunklen == 0) { 2507 device_printf(sc->sc_dev, "%s: strange response\n", __func__); 2508 counter_u64_add(ic->ic_ierrors, 1); 2509 UATH_RESET_INTRX(sc); 2510 return (NULL); 2511 } 2512 2513 if (chunklen > actlen) { 2514 device_printf(sc->sc_dev, 2515 "%s: invalid chunk length (len %u > actlen %d)\n", 2516 __func__, chunklen, actlen); 2517 counter_u64_add(ic->ic_ierrors, 1); 2518 /* XXX cleanup? */ 2519 UATH_RESET_INTRX(sc); 2520 return (NULL); 2521 } 2522 2523 if (chunk->seqnum != sc->sc_intrx_nextnum) { 2524 DPRINTF(sc, UATH_DEBUG_XMIT, "invalid seqnum %d, expected %d\n", 2525 chunk->seqnum, sc->sc_intrx_nextnum); 2526 UATH_STAT_INC(sc, st_badchunkseqnum); 2527 if (sc->sc_intrx_head != NULL) 2528 m_freem(sc->sc_intrx_head); 2529 UATH_RESET_INTRX(sc); 2530 return (NULL); 2531 } 2532 2533 /* check multi-chunk frames */ 2534 if ((chunk->seqnum == 0 && !(chunk->flags & UATH_CFLAGS_FINAL)) || 2535 (chunk->seqnum != 0 && (chunk->flags & UATH_CFLAGS_FINAL)) || 2536 chunk->flags & UATH_CFLAGS_RXMSG) 2537 UATH_STAT_INC(sc, st_multichunk); 2538 2539 if (chunk->flags & UATH_CFLAGS_FINAL) { 2540 if (chunklen < sizeof(struct uath_rx_desc)) { 2541 device_printf(sc->sc_dev, 2542 "%s: invalid chunk length %d\n", 2543 __func__, chunklen); 2544 counter_u64_add(ic->ic_ierrors, 1); 2545 if (sc->sc_intrx_head != NULL) 2546 m_freem(sc->sc_intrx_head); 2547 UATH_RESET_INTRX(sc); 2548 return (NULL); 2549 } 2550 chunklen -= sizeof(struct uath_rx_desc); 2551 } 2552 2553 if (chunklen > 0 && 2554 (!(chunk->flags & UATH_CFLAGS_FINAL) || !(chunk->seqnum == 0))) { 2555 /* we should use intermediate RX buffer */ 2556 if (chunk->seqnum == 0) 2557 UATH_RESET_INTRX(sc); 2558 if ((sc->sc_intrx_len + sizeof(struct uath_rx_desc) + 2559 chunklen) > UATH_MAX_INTRX_SIZE) { 2560 UATH_STAT_INC(sc, st_invalidlen); 2561 counter_u64_add(ic->ic_ierrors, 1); 2562 if (sc->sc_intrx_head != NULL) 2563 m_freem(sc->sc_intrx_head); 2564 UATH_RESET_INTRX(sc); 2565 return (NULL); 2566 } 2567 2568 m->m_len = chunklen; 2569 m->m_data += sizeof(struct uath_chunk); 2570 2571 if (sc->sc_intrx_head == NULL) { 2572 sc->sc_intrx_head = m; 2573 sc->sc_intrx_tail = m; 2574 } else { 2575 m->m_flags &= ~M_PKTHDR; 2576 sc->sc_intrx_tail->m_next = m; 2577 sc->sc_intrx_tail = m; 2578 } 2579 } 2580 sc->sc_intrx_len += chunklen; 2581 2582 mnew = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 2583 if (mnew == NULL) { 2584 DPRINTF(sc, UATH_DEBUG_RECV | UATH_DEBUG_RECV_ALL, 2585 "%s: can't get new mbuf, drop frame\n", __func__); 2586 counter_u64_add(ic->ic_ierrors, 1); 2587 if (sc->sc_intrx_head != NULL) 2588 m_freem(sc->sc_intrx_head); 2589 UATH_RESET_INTRX(sc); 2590 return (NULL); 2591 } 2592 2593 data->m = mnew; 2594 data->buf = mtod(mnew, uint8_t *); 2595 2596 /* if the frame is not final continue the transfer */ 2597 if (!(chunk->flags & UATH_CFLAGS_FINAL)) { 2598 sc->sc_intrx_nextnum++; 2599 UATH_RESET_INTRX(sc); 2600 return (NULL); 2601 } 2602 2603 /* 2604 * if the frame is not set UATH_CFLAGS_RXMSG, then rx descriptor is 2605 * located at the end, 32-bit aligned 2606 */ 2607 desc = (chunk->flags & UATH_CFLAGS_RXMSG) ? 2608 (struct uath_rx_desc *)(chunk + 1) : 2609 (struct uath_rx_desc *)(((uint8_t *)chunk) + 2610 sizeof(struct uath_chunk) + be16toh(chunk->length) - 2611 sizeof(struct uath_rx_desc)); 2612 if ((uint8_t *)chunk + actlen - sizeof(struct uath_rx_desc) < 2613 (uint8_t *)desc) { 2614 device_printf(sc->sc_dev, 2615 "%s: wrong Rx descriptor pointer " 2616 "(desc %p chunk %p actlen %d)\n", 2617 __func__, desc, chunk, actlen); 2618 counter_u64_add(ic->ic_ierrors, 1); 2619 if (sc->sc_intrx_head != NULL) 2620 m_freem(sc->sc_intrx_head); 2621 UATH_RESET_INTRX(sc); 2622 return (NULL); 2623 } 2624 2625 *pdesc = desc; 2626 2627 DPRINTF(sc, UATH_DEBUG_RECV | UATH_DEBUG_RECV_ALL, 2628 "%s: frame len %u code %u status %u rate %u antenna %u " 2629 "rssi %d channel %u phyerror %u connix %u decrypterror %u " 2630 "keycachemiss %u\n", __func__, be32toh(desc->framelen) 2631 , be32toh(desc->code), be32toh(desc->status), be32toh(desc->rate) 2632 , be32toh(desc->antenna), be32toh(desc->rssi), be32toh(desc->channel) 2633 , be32toh(desc->phyerror), be32toh(desc->connix) 2634 , be32toh(desc->decrypterror), be32toh(desc->keycachemiss)); 2635 2636 if (be32toh(desc->len) > MCLBYTES) { 2637 DPRINTF(sc, UATH_DEBUG_RECV | UATH_DEBUG_RECV_ALL, 2638 "%s: bad descriptor (len=%d)\n", __func__, 2639 be32toh(desc->len)); 2640 counter_u64_add(ic->ic_ierrors, 1); 2641 UATH_STAT_INC(sc, st_toobigrxpkt); 2642 if (sc->sc_intrx_head != NULL) 2643 m_freem(sc->sc_intrx_head); 2644 UATH_RESET_INTRX(sc); 2645 return (NULL); 2646 } 2647 2648 uath_update_rxstat(sc, be32toh(desc->status)); 2649 2650 /* finalize mbuf */ 2651 if (sc->sc_intrx_head == NULL) { 2652 uint32_t framelen; 2653 2654 if (be32toh(desc->framelen) < UATH_RX_DUMMYSIZE) { 2655 device_printf(sc->sc_dev, 2656 "%s: framelen too small (%u)\n", 2657 __func__, be32toh(desc->framelen)); 2658 counter_u64_add(ic->ic_ierrors, 1); 2659 if (sc->sc_intrx_head != NULL) 2660 m_freem(sc->sc_intrx_head); 2661 UATH_RESET_INTRX(sc); 2662 return (NULL); 2663 } 2664 2665 framelen = be32toh(desc->framelen) - UATH_RX_DUMMYSIZE; 2666 if (framelen > actlen - sizeof(struct uath_chunk) || 2667 framelen < sizeof(struct ieee80211_frame_ack)) { 2668 device_printf(sc->sc_dev, 2669 "%s: wrong frame length (%u, actlen %d)!\n", 2670 __func__, framelen, actlen); 2671 counter_u64_add(ic->ic_ierrors, 1); 2672 if (sc->sc_intrx_head != NULL) 2673 m_freem(sc->sc_intrx_head); 2674 UATH_RESET_INTRX(sc); 2675 return (NULL); 2676 } 2677 2678 m->m_pkthdr.len = m->m_len = framelen; 2679 m->m_data += sizeof(struct uath_chunk); 2680 } else { 2681 mp = sc->sc_intrx_head; 2682 mp->m_flags |= M_PKTHDR; 2683 mp->m_pkthdr.len = sc->sc_intrx_len; 2684 m = mp; 2685 } 2686 2687 /* there are a lot more fields in the RX descriptor */ 2688 if ((sc->sc_flags & UATH_FLAG_INVALID) == 0 && 2689 ieee80211_radiotap_active(ic)) { 2690 struct uath_rx_radiotap_header *tap = &sc->sc_rxtap; 2691 uint32_t tsf_hi = be32toh(desc->tstamp_high); 2692 uint32_t tsf_lo = be32toh(desc->tstamp_low); 2693 2694 /* XXX only get low order 24bits of tsf from h/w */ 2695 tap->wr_tsf = htole64(((uint64_t)tsf_hi << 32) | tsf_lo); 2696 tap->wr_flags = 0; 2697 if (be32toh(desc->status) == UATH_STATUS_CRC_ERR) 2698 tap->wr_flags |= IEEE80211_RADIOTAP_F_BADFCS; 2699 /* XXX map other status to BADFCS? */ 2700 /* XXX ath h/w rate code, need to map */ 2701 tap->wr_rate = be32toh(desc->rate); 2702 tap->wr_antenna = be32toh(desc->antenna); 2703 tap->wr_antsignal = -95 + be32toh(desc->rssi); 2704 tap->wr_antnoise = -95; 2705 } 2706 2707 UATH_RESET_INTRX(sc); 2708 2709 return (m); 2710 } 2711 2712 static void 2713 uath_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 2714 { 2715 struct uath_softc *sc = usbd_xfer_softc(xfer); 2716 struct ieee80211com *ic = &sc->sc_ic; 2717 struct ieee80211_frame *wh; 2718 struct ieee80211_node *ni; 2719 struct mbuf *m = NULL; 2720 struct uath_data *data; 2721 struct uath_rx_desc *desc = NULL; 2722 int8_t nf; 2723 2724 UATH_ASSERT_LOCKED(sc); 2725 2726 switch (USB_GET_STATE(xfer)) { 2727 case USB_ST_TRANSFERRED: 2728 data = STAILQ_FIRST(&sc->sc_rx_active); 2729 if (data == NULL) 2730 goto setup; 2731 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 2732 UATH_STAT_DEC(sc, st_rx_active); 2733 m = uath_data_rxeof(xfer, data, &desc); 2734 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 2735 UATH_STAT_INC(sc, st_rx_inactive); 2736 /* FALLTHROUGH */ 2737 case USB_ST_SETUP: 2738 setup: 2739 data = STAILQ_FIRST(&sc->sc_rx_inactive); 2740 if (data == NULL) 2741 return; 2742 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 2743 UATH_STAT_DEC(sc, st_rx_inactive); 2744 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 2745 UATH_STAT_INC(sc, st_rx_active); 2746 usbd_xfer_set_frame_data(xfer, 0, data->buf, MCLBYTES); 2747 usbd_transfer_submit(xfer); 2748 2749 /* 2750 * To avoid LOR we should unlock our private mutex here to call 2751 * ieee80211_input() because here is at the end of a USB 2752 * callback and safe to unlock. 2753 */ 2754 if (sc->sc_flags & UATH_FLAG_INVALID) { 2755 if (m != NULL) 2756 m_freem(m); 2757 return; 2758 } 2759 UATH_UNLOCK(sc); 2760 if (m != NULL && desc != NULL) { 2761 wh = mtod(m, struct ieee80211_frame *); 2762 ni = ieee80211_find_rxnode(ic, 2763 (struct ieee80211_frame_min *)wh); 2764 nf = -95; /* XXX */ 2765 if (ni != NULL) { 2766 (void) ieee80211_input(ni, m, 2767 (int)be32toh(desc->rssi), nf); 2768 /* node is no longer needed */ 2769 ieee80211_free_node(ni); 2770 } else 2771 (void) ieee80211_input_all(ic, m, 2772 (int)be32toh(desc->rssi), nf); 2773 m = NULL; 2774 desc = NULL; 2775 } 2776 UATH_LOCK(sc); 2777 uath_start(sc); 2778 break; 2779 default: 2780 /* needs it to the inactive queue due to a error. */ 2781 data = STAILQ_FIRST(&sc->sc_rx_active); 2782 if (data != NULL) { 2783 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 2784 UATH_STAT_DEC(sc, st_rx_active); 2785 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 2786 UATH_STAT_INC(sc, st_rx_inactive); 2787 } 2788 if (error != USB_ERR_CANCELLED) { 2789 usbd_xfer_set_stall(xfer); 2790 counter_u64_add(ic->ic_ierrors, 1); 2791 goto setup; 2792 } 2793 break; 2794 } 2795 } 2796 2797 static void 2798 uath_data_txeof(struct usb_xfer *xfer, struct uath_data *data) 2799 { 2800 struct uath_softc *sc = usbd_xfer_softc(xfer); 2801 2802 UATH_ASSERT_LOCKED(sc); 2803 2804 if (data->m) { 2805 /* XXX status? */ 2806 ieee80211_tx_complete(data->ni, data->m, 0); 2807 data->m = NULL; 2808 data->ni = NULL; 2809 } 2810 sc->sc_tx_timer = 0; 2811 } 2812 2813 static void 2814 uath_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 2815 { 2816 struct uath_softc *sc = usbd_xfer_softc(xfer); 2817 struct uath_data *data; 2818 2819 UATH_ASSERT_LOCKED(sc); 2820 2821 switch (USB_GET_STATE(xfer)) { 2822 case USB_ST_TRANSFERRED: 2823 data = STAILQ_FIRST(&sc->sc_tx_active); 2824 if (data == NULL) 2825 goto setup; 2826 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 2827 UATH_STAT_DEC(sc, st_tx_active); 2828 uath_data_txeof(xfer, data); 2829 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 2830 UATH_STAT_INC(sc, st_tx_inactive); 2831 /* FALLTHROUGH */ 2832 case USB_ST_SETUP: 2833 setup: 2834 data = STAILQ_FIRST(&sc->sc_tx_pending); 2835 if (data == NULL) { 2836 DPRINTF(sc, UATH_DEBUG_XMIT, "%s: empty pending queue\n", 2837 __func__); 2838 return; 2839 } 2840 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 2841 UATH_STAT_DEC(sc, st_tx_pending); 2842 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 2843 UATH_STAT_INC(sc, st_tx_active); 2844 2845 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 2846 usbd_transfer_submit(xfer); 2847 2848 uath_start(sc); 2849 break; 2850 default: 2851 data = STAILQ_FIRST(&sc->sc_tx_active); 2852 if (data == NULL) 2853 goto setup; 2854 if (data->ni != NULL) { 2855 if_inc_counter(data->ni->ni_vap->iv_ifp, 2856 IFCOUNTER_OERRORS, 1); 2857 if ((sc->sc_flags & UATH_FLAG_INVALID) == 0) 2858 ieee80211_free_node(data->ni); 2859 data->ni = NULL; 2860 } 2861 if (error != USB_ERR_CANCELLED) { 2862 usbd_xfer_set_stall(xfer); 2863 goto setup; 2864 } 2865 break; 2866 } 2867 } 2868 2869 static device_method_t uath_methods[] = { 2870 DEVMETHOD(device_probe, uath_match), 2871 DEVMETHOD(device_attach, uath_attach), 2872 DEVMETHOD(device_detach, uath_detach), 2873 DEVMETHOD_END 2874 }; 2875 2876 static driver_t uath_driver = { 2877 .name = "uath", 2878 .methods = uath_methods, 2879 .size = sizeof(struct uath_softc) 2880 }; 2881 2882 DRIVER_MODULE(uath, uhub, uath_driver, NULL, NULL); 2883 MODULE_DEPEND(uath, wlan, 1, 1, 1); 2884 MODULE_DEPEND(uath, usb, 1, 1, 1); 2885 MODULE_VERSION(uath, 1); 2886 USB_PNP_HOST_INFO(uath_devs); 2887