1 /*- 2 * Copyright (c) 2006 Sam Leffler, Errno Consulting 3 * Copyright (c) 2008-2009 Weongyo Jeong <weongyo@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 13 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 14 * redistribution must be conditioned upon including a substantially 15 * similar Disclaimer requirement for further binary redistribution. 16 * 17 * NO WARRANTY 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 21 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 22 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 23 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 26 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 * THE POSSIBILITY OF SUCH DAMAGES. 29 */ 30 31 /* 32 * This driver is distantly derived from a driver of the same name 33 * by Damien Bergamini. The original copyright is included below: 34 * 35 * Copyright (c) 2006 36 * Damien Bergamini <damien.bergamini@free.fr> 37 * 38 * Permission to use, copy, modify, and distribute this software for any 39 * purpose with or without fee is hereby granted, provided that the above 40 * copyright notice and this permission notice appear in all copies. 41 * 42 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 43 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 44 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 45 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 46 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 47 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 48 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 49 */ 50 51 #include <sys/cdefs.h> 52 __FBSDID("$FreeBSD$"); 53 54 /*- 55 * Driver for Atheros AR5523 USB parts. 56 * 57 * The driver requires firmware to be loaded into the device. This 58 * is done on device discovery from a user application (uathload) 59 * that is launched by devd when a device with suitable product ID 60 * is recognized. Once firmware has been loaded the device will 61 * reset the USB port and re-attach with the original product ID+1 62 * and this driver will be attached. The firmware is licensed for 63 * general use (royalty free) and may be incorporated in products. 64 * Note that the firmware normally packaged with the NDIS drivers 65 * for these devices does not work in this way and so does not work 66 * with this driver. 67 */ 68 #include <sys/param.h> 69 #include <sys/sockio.h> 70 #include <sys/sysctl.h> 71 #include <sys/lock.h> 72 #include <sys/mutex.h> 73 #include <sys/mbuf.h> 74 #include <sys/kernel.h> 75 #include <sys/socket.h> 76 #include <sys/systm.h> 77 #include <sys/malloc.h> 78 #include <sys/module.h> 79 #include <sys/bus.h> 80 #include <sys/endian.h> 81 #include <sys/kdb.h> 82 83 #include <machine/bus.h> 84 #include <machine/resource.h> 85 #include <sys/rman.h> 86 87 #include <net/bpf.h> 88 #include <net/if.h> 89 #include <net/if_var.h> 90 #include <net/if_arp.h> 91 #include <net/ethernet.h> 92 #include <net/if_dl.h> 93 #include <net/if_media.h> 94 #include <net/if_types.h> 95 96 #ifdef INET 97 #include <netinet/in.h> 98 #include <netinet/in_systm.h> 99 #include <netinet/in_var.h> 100 #include <netinet/if_ether.h> 101 #include <netinet/ip.h> 102 #endif 103 104 #include <net80211/ieee80211_var.h> 105 #include <net80211/ieee80211_input.h> 106 #include <net80211/ieee80211_regdomain.h> 107 #include <net80211/ieee80211_radiotap.h> 108 109 #include <dev/usb/usb.h> 110 #include <dev/usb/usbdi.h> 111 #include "usbdevs.h" 112 113 #include <dev/usb/wlan/if_uathreg.h> 114 #include <dev/usb/wlan/if_uathvar.h> 115 116 static SYSCTL_NODE(_hw_usb, OID_AUTO, uath, CTLFLAG_RW, 0, "USB Atheros"); 117 118 static int uath_countrycode = CTRY_DEFAULT; /* country code */ 119 SYSCTL_INT(_hw_usb_uath, OID_AUTO, countrycode, CTLFLAG_RWTUN, &uath_countrycode, 120 0, "country code"); 121 static int uath_regdomain = 0; /* regulatory domain */ 122 SYSCTL_INT(_hw_usb_uath, OID_AUTO, regdomain, CTLFLAG_RD, &uath_regdomain, 123 0, "regulatory domain"); 124 125 #ifdef UATH_DEBUG 126 int uath_debug = 0; 127 SYSCTL_INT(_hw_usb_uath, OID_AUTO, debug, CTLFLAG_RWTUN, &uath_debug, 0, 128 "uath debug level"); 129 enum { 130 UATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 131 UATH_DEBUG_XMIT_DUMP = 0x00000002, /* xmit dump */ 132 UATH_DEBUG_RECV = 0x00000004, /* basic recv operation */ 133 UATH_DEBUG_TX_PROC = 0x00000008, /* tx ISR proc */ 134 UATH_DEBUG_RX_PROC = 0x00000010, /* rx ISR proc */ 135 UATH_DEBUG_RECV_ALL = 0x00000020, /* trace all frames (beacons) */ 136 UATH_DEBUG_INIT = 0x00000040, /* initialization of dev */ 137 UATH_DEBUG_DEVCAP = 0x00000080, /* dev caps */ 138 UATH_DEBUG_CMDS = 0x00000100, /* commands */ 139 UATH_DEBUG_CMDS_DUMP = 0x00000200, /* command buffer dump */ 140 UATH_DEBUG_RESET = 0x00000400, /* reset processing */ 141 UATH_DEBUG_STATE = 0x00000800, /* 802.11 state transitions */ 142 UATH_DEBUG_MULTICAST = 0x00001000, /* multicast */ 143 UATH_DEBUG_WME = 0x00002000, /* WME */ 144 UATH_DEBUG_CHANNEL = 0x00004000, /* channel */ 145 UATH_DEBUG_RATES = 0x00008000, /* rates */ 146 UATH_DEBUG_CRYPTO = 0x00010000, /* crypto */ 147 UATH_DEBUG_LED = 0x00020000, /* LED */ 148 UATH_DEBUG_ANY = 0xffffffff 149 }; 150 #define DPRINTF(sc, m, fmt, ...) do { \ 151 if (sc->sc_debug & (m)) \ 152 printf(fmt, __VA_ARGS__); \ 153 } while (0) 154 #else 155 #define DPRINTF(sc, m, fmt, ...) do { \ 156 (void) sc; \ 157 } while (0) 158 #endif 159 160 /* recognized device vendors/products */ 161 static const STRUCT_USB_HOST_ID uath_devs[] = { 162 #define UATH_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 163 UATH_DEV(ACCTON, SMCWUSBTG2), 164 UATH_DEV(ATHEROS, AR5523), 165 UATH_DEV(ATHEROS2, AR5523_1), 166 UATH_DEV(ATHEROS2, AR5523_2), 167 UATH_DEV(ATHEROS2, AR5523_3), 168 UATH_DEV(CONCEPTRONIC, AR5523_1), 169 UATH_DEV(CONCEPTRONIC, AR5523_2), 170 UATH_DEV(DLINK, DWLAG122), 171 UATH_DEV(DLINK, DWLAG132), 172 UATH_DEV(DLINK, DWLG132), 173 UATH_DEV(DLINK2, DWA120), 174 UATH_DEV(GIGASET, AR5523), 175 UATH_DEV(GIGASET, SMCWUSBTG), 176 UATH_DEV(GLOBALSUN, AR5523_1), 177 UATH_DEV(GLOBALSUN, AR5523_2), 178 UATH_DEV(NETGEAR, WG111U), 179 UATH_DEV(NETGEAR3, WG111T), 180 UATH_DEV(NETGEAR3, WPN111), 181 UATH_DEV(NETGEAR3, WPN111_2), 182 UATH_DEV(UMEDIA, TEW444UBEU), 183 UATH_DEV(UMEDIA, AR5523_2), 184 UATH_DEV(WISTRONNEWEB, AR5523_1), 185 UATH_DEV(WISTRONNEWEB, AR5523_2), 186 UATH_DEV(ZCOM, AR5523) 187 #undef UATH_DEV 188 }; 189 190 static usb_callback_t uath_intr_rx_callback; 191 static usb_callback_t uath_intr_tx_callback; 192 static usb_callback_t uath_bulk_rx_callback; 193 static usb_callback_t uath_bulk_tx_callback; 194 195 static const struct usb_config uath_usbconfig[UATH_N_XFERS] = { 196 [UATH_INTR_RX] = { 197 .type = UE_BULK, 198 .endpoint = 0x1, 199 .direction = UE_DIR_IN, 200 .bufsize = UATH_MAX_CMDSZ, 201 .flags = { 202 .pipe_bof = 1, 203 .short_xfer_ok = 1 204 }, 205 .callback = uath_intr_rx_callback 206 }, 207 [UATH_INTR_TX] = { 208 .type = UE_BULK, 209 .endpoint = 0x1, 210 .direction = UE_DIR_OUT, 211 .bufsize = UATH_MAX_CMDSZ * UATH_CMD_LIST_COUNT, 212 .flags = { 213 .force_short_xfer = 1, 214 .pipe_bof = 1, 215 }, 216 .callback = uath_intr_tx_callback, 217 .timeout = UATH_CMD_TIMEOUT 218 }, 219 [UATH_BULK_RX] = { 220 .type = UE_BULK, 221 .endpoint = 0x2, 222 .direction = UE_DIR_IN, 223 .bufsize = MCLBYTES, 224 .flags = { 225 .ext_buffer = 1, 226 .pipe_bof = 1, 227 .short_xfer_ok = 1 228 }, 229 .callback = uath_bulk_rx_callback 230 }, 231 [UATH_BULK_TX] = { 232 .type = UE_BULK, 233 .endpoint = 0x2, 234 .direction = UE_DIR_OUT, 235 .bufsize = UATH_MAX_TXBUFSZ * UATH_TX_DATA_LIST_COUNT, 236 .flags = { 237 .force_short_xfer = 1, 238 .pipe_bof = 1 239 }, 240 .callback = uath_bulk_tx_callback, 241 .timeout = UATH_DATA_TIMEOUT 242 } 243 }; 244 245 static struct ieee80211vap *uath_vap_create(struct ieee80211com *, 246 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 247 const uint8_t [IEEE80211_ADDR_LEN], 248 const uint8_t [IEEE80211_ADDR_LEN]); 249 static void uath_vap_delete(struct ieee80211vap *); 250 static int uath_alloc_cmd_list(struct uath_softc *, struct uath_cmd []); 251 static void uath_free_cmd_list(struct uath_softc *, struct uath_cmd []); 252 static int uath_host_available(struct uath_softc *); 253 static int uath_get_capability(struct uath_softc *, uint32_t, uint32_t *); 254 static int uath_get_devcap(struct uath_softc *); 255 static struct uath_cmd * 256 uath_get_cmdbuf(struct uath_softc *); 257 static int uath_cmd_read(struct uath_softc *, uint32_t, const void *, 258 int, void *, int, int); 259 static int uath_cmd_write(struct uath_softc *, uint32_t, const void *, 260 int, int); 261 static void uath_stat(void *); 262 #ifdef UATH_DEBUG 263 static void uath_dump_cmd(const uint8_t *, int, char); 264 static const char * 265 uath_codename(int); 266 #endif 267 static int uath_get_devstatus(struct uath_softc *, 268 uint8_t macaddr[IEEE80211_ADDR_LEN]); 269 static int uath_get_status(struct uath_softc *, uint32_t, void *, int); 270 static int uath_alloc_rx_data_list(struct uath_softc *); 271 static int uath_alloc_tx_data_list(struct uath_softc *); 272 static void uath_free_rx_data_list(struct uath_softc *); 273 static void uath_free_tx_data_list(struct uath_softc *); 274 static int uath_init(struct uath_softc *); 275 static void uath_stop(struct uath_softc *); 276 static void uath_parent(struct ieee80211com *); 277 static int uath_transmit(struct ieee80211com *, struct mbuf *); 278 static void uath_start(struct uath_softc *); 279 static int uath_raw_xmit(struct ieee80211_node *, struct mbuf *, 280 const struct ieee80211_bpf_params *); 281 static void uath_scan_start(struct ieee80211com *); 282 static void uath_scan_end(struct ieee80211com *); 283 static void uath_set_channel(struct ieee80211com *); 284 static void uath_update_mcast(struct ieee80211com *); 285 static void uath_update_promisc(struct ieee80211com *); 286 static int uath_config(struct uath_softc *, uint32_t, uint32_t); 287 static int uath_config_multi(struct uath_softc *, uint32_t, const void *, 288 int); 289 static int uath_switch_channel(struct uath_softc *, 290 struct ieee80211_channel *); 291 static int uath_set_rxfilter(struct uath_softc *, uint32_t, uint32_t); 292 static void uath_watchdog(void *); 293 static void uath_abort_xfers(struct uath_softc *); 294 static int uath_dataflush(struct uath_softc *); 295 static int uath_cmdflush(struct uath_softc *); 296 static int uath_flush(struct uath_softc *); 297 static int uath_set_ledstate(struct uath_softc *, int); 298 static int uath_set_chan(struct uath_softc *, struct ieee80211_channel *); 299 static int uath_reset_tx_queues(struct uath_softc *); 300 static int uath_wme_init(struct uath_softc *); 301 static struct uath_data * 302 uath_getbuf(struct uath_softc *); 303 static int uath_newstate(struct ieee80211vap *, enum ieee80211_state, 304 int); 305 static int uath_set_key(struct uath_softc *, 306 const struct ieee80211_key *, int); 307 static int uath_set_keys(struct uath_softc *, struct ieee80211vap *); 308 static void uath_sysctl_node(struct uath_softc *); 309 310 static int 311 uath_match(device_t dev) 312 { 313 struct usb_attach_arg *uaa = device_get_ivars(dev); 314 315 if (uaa->usb_mode != USB_MODE_HOST) 316 return (ENXIO); 317 if (uaa->info.bConfigIndex != UATH_CONFIG_INDEX) 318 return (ENXIO); 319 if (uaa->info.bIfaceIndex != UATH_IFACE_INDEX) 320 return (ENXIO); 321 322 return (usbd_lookup_id_by_uaa(uath_devs, sizeof(uath_devs), uaa)); 323 } 324 325 static int 326 uath_attach(device_t dev) 327 { 328 struct uath_softc *sc = device_get_softc(dev); 329 struct usb_attach_arg *uaa = device_get_ivars(dev); 330 struct ieee80211com *ic = &sc->sc_ic; 331 uint8_t bands, iface_index = UATH_IFACE_INDEX; /* XXX */ 332 usb_error_t error; 333 334 sc->sc_dev = dev; 335 sc->sc_udev = uaa->device; 336 #ifdef UATH_DEBUG 337 sc->sc_debug = uath_debug; 338 #endif 339 device_set_usb_desc(dev); 340 341 /* 342 * Only post-firmware devices here. 343 */ 344 mtx_init(&sc->sc_mtx, device_get_nameunit(sc->sc_dev), MTX_NETWORK_LOCK, 345 MTX_DEF); 346 callout_init(&sc->stat_ch, 0); 347 callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0); 348 mbufq_init(&sc->sc_snd, ifqmaxlen); 349 350 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 351 uath_usbconfig, UATH_N_XFERS, sc, &sc->sc_mtx); 352 if (error) { 353 device_printf(dev, "could not allocate USB transfers, " 354 "err=%s\n", usbd_errstr(error)); 355 goto fail; 356 } 357 358 sc->sc_cmd_dma_buf = 359 usbd_xfer_get_frame_buffer(sc->sc_xfer[UATH_INTR_TX], 0); 360 sc->sc_tx_dma_buf = 361 usbd_xfer_get_frame_buffer(sc->sc_xfer[UATH_BULK_TX], 0); 362 363 /* 364 * Setup buffers for firmware commands. 365 */ 366 error = uath_alloc_cmd_list(sc, sc->sc_cmd); 367 if (error != 0) { 368 device_printf(sc->sc_dev, 369 "could not allocate Tx command list\n"); 370 goto fail1; 371 } 372 373 /* 374 * We're now ready to send+receive firmware commands. 375 */ 376 UATH_LOCK(sc); 377 error = uath_host_available(sc); 378 if (error != 0) { 379 device_printf(sc->sc_dev, "could not initialize adapter\n"); 380 goto fail2; 381 } 382 error = uath_get_devcap(sc); 383 if (error != 0) { 384 device_printf(sc->sc_dev, 385 "could not get device capabilities\n"); 386 goto fail2; 387 } 388 UATH_UNLOCK(sc); 389 390 /* Create device sysctl node. */ 391 uath_sysctl_node(sc); 392 393 UATH_LOCK(sc); 394 error = uath_get_devstatus(sc, ic->ic_macaddr); 395 if (error != 0) { 396 device_printf(sc->sc_dev, "could not get device status\n"); 397 goto fail2; 398 } 399 400 /* 401 * Allocate xfers for Rx/Tx data pipes. 402 */ 403 error = uath_alloc_rx_data_list(sc); 404 if (error != 0) { 405 device_printf(sc->sc_dev, "could not allocate Rx data list\n"); 406 goto fail2; 407 } 408 error = uath_alloc_tx_data_list(sc); 409 if (error != 0) { 410 device_printf(sc->sc_dev, "could not allocate Tx data list\n"); 411 goto fail2; 412 } 413 UATH_UNLOCK(sc); 414 415 ic->ic_softc = sc; 416 ic->ic_name = device_get_nameunit(dev); 417 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 418 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 419 420 /* set device capabilities */ 421 ic->ic_caps = 422 IEEE80211_C_STA | /* station mode */ 423 IEEE80211_C_MONITOR | /* monitor mode supported */ 424 IEEE80211_C_TXPMGT | /* tx power management */ 425 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 426 IEEE80211_C_SHSLOT | /* short slot time supported */ 427 IEEE80211_C_WPA | /* 802.11i */ 428 IEEE80211_C_BGSCAN | /* capable of bg scanning */ 429 IEEE80211_C_TXFRAG; /* handle tx frags */ 430 431 /* put a regulatory domain to reveal informations. */ 432 uath_regdomain = sc->sc_devcap.regDomain; 433 434 bands = 0; 435 setbit(&bands, IEEE80211_MODE_11B); 436 setbit(&bands, IEEE80211_MODE_11G); 437 if ((sc->sc_devcap.analog5GhzRevision & 0xf0) == 0x30) 438 setbit(&bands, IEEE80211_MODE_11A); 439 /* XXX turbo */ 440 ieee80211_init_channels(ic, NULL, &bands); 441 442 ieee80211_ifattach(ic); 443 ic->ic_raw_xmit = uath_raw_xmit; 444 ic->ic_scan_start = uath_scan_start; 445 ic->ic_scan_end = uath_scan_end; 446 ic->ic_set_channel = uath_set_channel; 447 ic->ic_vap_create = uath_vap_create; 448 ic->ic_vap_delete = uath_vap_delete; 449 ic->ic_update_mcast = uath_update_mcast; 450 ic->ic_update_promisc = uath_update_promisc; 451 ic->ic_transmit = uath_transmit; 452 ic->ic_parent = uath_parent; 453 454 ieee80211_radiotap_attach(ic, 455 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 456 UATH_TX_RADIOTAP_PRESENT, 457 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 458 UATH_RX_RADIOTAP_PRESENT); 459 460 if (bootverbose) 461 ieee80211_announce(ic); 462 463 return (0); 464 465 fail2: UATH_UNLOCK(sc); 466 uath_free_cmd_list(sc, sc->sc_cmd); 467 fail1: usbd_transfer_unsetup(sc->sc_xfer, UATH_N_XFERS); 468 fail: 469 return (error); 470 } 471 472 static int 473 uath_detach(device_t dev) 474 { 475 struct uath_softc *sc = device_get_softc(dev); 476 struct ieee80211com *ic = &sc->sc_ic; 477 unsigned int x; 478 479 /* 480 * Prevent further allocations from RX/TX/CMD 481 * data lists and ioctls 482 */ 483 UATH_LOCK(sc); 484 sc->sc_flags |= UATH_FLAG_INVALID; 485 486 STAILQ_INIT(&sc->sc_rx_active); 487 STAILQ_INIT(&sc->sc_rx_inactive); 488 489 STAILQ_INIT(&sc->sc_tx_active); 490 STAILQ_INIT(&sc->sc_tx_inactive); 491 STAILQ_INIT(&sc->sc_tx_pending); 492 493 STAILQ_INIT(&sc->sc_cmd_active); 494 STAILQ_INIT(&sc->sc_cmd_pending); 495 STAILQ_INIT(&sc->sc_cmd_waiting); 496 STAILQ_INIT(&sc->sc_cmd_inactive); 497 498 uath_stop(sc); 499 UATH_UNLOCK(sc); 500 501 callout_drain(&sc->stat_ch); 502 callout_drain(&sc->watchdog_ch); 503 504 /* drain USB transfers */ 505 for (x = 0; x != UATH_N_XFERS; x++) 506 usbd_transfer_drain(sc->sc_xfer[x]); 507 508 /* free data buffers */ 509 UATH_LOCK(sc); 510 uath_free_rx_data_list(sc); 511 uath_free_tx_data_list(sc); 512 uath_free_cmd_list(sc, sc->sc_cmd); 513 UATH_UNLOCK(sc); 514 515 /* free USB transfers and some data buffers */ 516 usbd_transfer_unsetup(sc->sc_xfer, UATH_N_XFERS); 517 518 ieee80211_ifdetach(ic); 519 mbufq_drain(&sc->sc_snd); 520 mtx_destroy(&sc->sc_mtx); 521 return (0); 522 } 523 524 static void 525 uath_free_cmd_list(struct uath_softc *sc, struct uath_cmd cmds[]) 526 { 527 int i; 528 529 for (i = 0; i != UATH_CMD_LIST_COUNT; i++) 530 cmds[i].buf = NULL; 531 } 532 533 static int 534 uath_alloc_cmd_list(struct uath_softc *sc, struct uath_cmd cmds[]) 535 { 536 int i; 537 538 STAILQ_INIT(&sc->sc_cmd_active); 539 STAILQ_INIT(&sc->sc_cmd_pending); 540 STAILQ_INIT(&sc->sc_cmd_waiting); 541 STAILQ_INIT(&sc->sc_cmd_inactive); 542 543 for (i = 0; i != UATH_CMD_LIST_COUNT; i++) { 544 struct uath_cmd *cmd = &cmds[i]; 545 546 cmd->sc = sc; /* backpointer for callbacks */ 547 cmd->msgid = i; 548 cmd->buf = ((uint8_t *)sc->sc_cmd_dma_buf) + 549 (i * UATH_MAX_CMDSZ); 550 STAILQ_INSERT_TAIL(&sc->sc_cmd_inactive, cmd, next); 551 UATH_STAT_INC(sc, st_cmd_inactive); 552 } 553 return (0); 554 } 555 556 static int 557 uath_host_available(struct uath_softc *sc) 558 { 559 struct uath_cmd_host_available setup; 560 561 UATH_ASSERT_LOCKED(sc); 562 563 /* inform target the host is available */ 564 setup.sw_ver_major = htobe32(ATH_SW_VER_MAJOR); 565 setup.sw_ver_minor = htobe32(ATH_SW_VER_MINOR); 566 setup.sw_ver_patch = htobe32(ATH_SW_VER_PATCH); 567 setup.sw_ver_build = htobe32(ATH_SW_VER_BUILD); 568 return uath_cmd_read(sc, WDCMSG_HOST_AVAILABLE, 569 &setup, sizeof setup, NULL, 0, 0); 570 } 571 572 #ifdef UATH_DEBUG 573 static void 574 uath_dump_cmd(const uint8_t *buf, int len, char prefix) 575 { 576 const char *sep = ""; 577 int i; 578 579 for (i = 0; i < len; i++) { 580 if ((i % 16) == 0) { 581 printf("%s%c ", sep, prefix); 582 sep = "\n"; 583 } 584 else if ((i % 4) == 0) 585 printf(" "); 586 printf("%02x", buf[i]); 587 } 588 printf("\n"); 589 } 590 591 static const char * 592 uath_codename(int code) 593 { 594 static const char *names[] = { 595 "0x00", 596 "HOST_AVAILABLE", 597 "BIND", 598 "TARGET_RESET", 599 "TARGET_GET_CAPABILITY", 600 "TARGET_SET_CONFIG", 601 "TARGET_GET_STATUS", 602 "TARGET_GET_STATS", 603 "TARGET_START", 604 "TARGET_STOP", 605 "TARGET_ENABLE", 606 "TARGET_DISABLE", 607 "CREATE_CONNECTION", 608 "UPDATE_CONNECT_ATTR", 609 "DELETE_CONNECT", 610 "SEND", 611 "FLUSH", 612 "STATS_UPDATE", 613 "BMISS", 614 "DEVICE_AVAIL", 615 "SEND_COMPLETE", 616 "DATA_AVAIL", 617 "SET_PWR_MODE", 618 "BMISS_ACK", 619 "SET_LED_STEADY", 620 "SET_LED_BLINK", 621 "SETUP_BEACON_DESC", 622 "BEACON_INIT", 623 "RESET_KEY_CACHE", 624 "RESET_KEY_CACHE_ENTRY", 625 "SET_KEY_CACHE_ENTRY", 626 "SET_DECOMP_MASK", 627 "SET_REGULATORY_DOMAIN", 628 "SET_LED_STATE", 629 "WRITE_ASSOCID", 630 "SET_STA_BEACON_TIMERS", 631 "GET_TSF", 632 "RESET_TSF", 633 "SET_ADHOC_MODE", 634 "SET_BASIC_RATE", 635 "MIB_CONTROL", 636 "GET_CHANNEL_DATA", 637 "GET_CUR_RSSI", 638 "SET_ANTENNA_SWITCH", 639 "0x2c", "0x2d", "0x2e", 640 "USE_SHORT_SLOT_TIME", 641 "SET_POWER_MODE", 642 "SETUP_PSPOLL_DESC", 643 "SET_RX_MULTICAST_FILTER", 644 "RX_FILTER", 645 "PER_CALIBRATION", 646 "RESET", 647 "DISABLE", 648 "PHY_DISABLE", 649 "SET_TX_POWER_LIMIT", 650 "SET_TX_QUEUE_PARAMS", 651 "SETUP_TX_QUEUE", 652 "RELEASE_TX_QUEUE", 653 }; 654 static char buf[8]; 655 656 if (code < nitems(names)) 657 return names[code]; 658 if (code == WDCMSG_SET_DEFAULT_KEY) 659 return "SET_DEFAULT_KEY"; 660 snprintf(buf, sizeof(buf), "0x%02x", code); 661 return buf; 662 } 663 #endif 664 665 /* 666 * Low-level function to send read or write commands to the firmware. 667 */ 668 static int 669 uath_cmdsend(struct uath_softc *sc, uint32_t code, const void *idata, int ilen, 670 void *odata, int olen, int flags) 671 { 672 struct uath_cmd_hdr *hdr; 673 struct uath_cmd *cmd; 674 int error; 675 676 UATH_ASSERT_LOCKED(sc); 677 678 /* grab a xfer */ 679 cmd = uath_get_cmdbuf(sc); 680 if (cmd == NULL) { 681 device_printf(sc->sc_dev, "%s: empty inactive queue\n", 682 __func__); 683 return (ENOBUFS); 684 } 685 cmd->flags = flags; 686 /* always bulk-out a multiple of 4 bytes */ 687 cmd->buflen = roundup2(sizeof(struct uath_cmd_hdr) + ilen, 4); 688 689 hdr = (struct uath_cmd_hdr *)cmd->buf; 690 memset(hdr, 0, sizeof(struct uath_cmd_hdr)); 691 hdr->len = htobe32(cmd->buflen); 692 hdr->code = htobe32(code); 693 hdr->msgid = cmd->msgid; /* don't care about endianness */ 694 hdr->magic = htobe32((cmd->flags & UATH_CMD_FLAG_MAGIC) ? 1 << 24 : 0); 695 memcpy((uint8_t *)(hdr + 1), idata, ilen); 696 697 #ifdef UATH_DEBUG 698 if (sc->sc_debug & UATH_DEBUG_CMDS) { 699 printf("%s: send %s [flags 0x%x] olen %d\n", 700 __func__, uath_codename(code), cmd->flags, olen); 701 if (sc->sc_debug & UATH_DEBUG_CMDS_DUMP) 702 uath_dump_cmd(cmd->buf, cmd->buflen, '+'); 703 } 704 #endif 705 cmd->odata = odata; 706 KASSERT(odata == NULL || 707 olen < UATH_MAX_CMDSZ - sizeof(*hdr) + sizeof(uint32_t), 708 ("odata %p olen %u", odata, olen)); 709 cmd->olen = olen; 710 711 STAILQ_INSERT_TAIL(&sc->sc_cmd_pending, cmd, next); 712 UATH_STAT_INC(sc, st_cmd_pending); 713 usbd_transfer_start(sc->sc_xfer[UATH_INTR_TX]); 714 715 if (cmd->flags & UATH_CMD_FLAG_READ) { 716 usbd_transfer_start(sc->sc_xfer[UATH_INTR_RX]); 717 718 /* wait at most two seconds for command reply */ 719 error = mtx_sleep(cmd, &sc->sc_mtx, 0, "uathcmd", 2 * hz); 720 cmd->odata = NULL; /* in case reply comes too late */ 721 if (error != 0) { 722 device_printf(sc->sc_dev, "timeout waiting for reply " 723 "to cmd 0x%x (%u)\n", code, code); 724 } else if (cmd->olen != olen) { 725 device_printf(sc->sc_dev, "unexpected reply data count " 726 "to cmd 0x%x (%u), got %u, expected %u\n", 727 code, code, cmd->olen, olen); 728 error = EINVAL; 729 } 730 return (error); 731 } 732 return (0); 733 } 734 735 static int 736 uath_cmd_read(struct uath_softc *sc, uint32_t code, const void *idata, 737 int ilen, void *odata, int olen, int flags) 738 { 739 740 flags |= UATH_CMD_FLAG_READ; 741 return uath_cmdsend(sc, code, idata, ilen, odata, olen, flags); 742 } 743 744 static int 745 uath_cmd_write(struct uath_softc *sc, uint32_t code, const void *data, int len, 746 int flags) 747 { 748 749 flags &= ~UATH_CMD_FLAG_READ; 750 return uath_cmdsend(sc, code, data, len, NULL, 0, flags); 751 } 752 753 static struct uath_cmd * 754 uath_get_cmdbuf(struct uath_softc *sc) 755 { 756 struct uath_cmd *uc; 757 758 UATH_ASSERT_LOCKED(sc); 759 760 uc = STAILQ_FIRST(&sc->sc_cmd_inactive); 761 if (uc != NULL) { 762 STAILQ_REMOVE_HEAD(&sc->sc_cmd_inactive, next); 763 UATH_STAT_DEC(sc, st_cmd_inactive); 764 } else 765 uc = NULL; 766 if (uc == NULL) 767 DPRINTF(sc, UATH_DEBUG_XMIT, "%s: %s\n", __func__, 768 "out of command xmit buffers"); 769 return (uc); 770 } 771 772 /* 773 * This function is called periodically (every second) when associated to 774 * query device statistics. 775 */ 776 static void 777 uath_stat(void *arg) 778 { 779 struct uath_softc *sc = arg; 780 int error; 781 782 UATH_LOCK(sc); 783 /* 784 * Send request for statistics asynchronously. The timer will be 785 * restarted when we'll get the stats notification. 786 */ 787 error = uath_cmd_write(sc, WDCMSG_TARGET_GET_STATS, NULL, 0, 788 UATH_CMD_FLAG_ASYNC); 789 if (error != 0) { 790 device_printf(sc->sc_dev, 791 "could not query stats, error %d\n", error); 792 } 793 UATH_UNLOCK(sc); 794 } 795 796 static int 797 uath_get_capability(struct uath_softc *sc, uint32_t cap, uint32_t *val) 798 { 799 int error; 800 801 cap = htobe32(cap); 802 error = uath_cmd_read(sc, WDCMSG_TARGET_GET_CAPABILITY, 803 &cap, sizeof cap, val, sizeof(uint32_t), UATH_CMD_FLAG_MAGIC); 804 if (error != 0) { 805 device_printf(sc->sc_dev, "could not read capability %u\n", 806 be32toh(cap)); 807 return (error); 808 } 809 *val = be32toh(*val); 810 return (error); 811 } 812 813 static int 814 uath_get_devcap(struct uath_softc *sc) 815 { 816 #define GETCAP(x, v) do { \ 817 error = uath_get_capability(sc, x, &v); \ 818 if (error != 0) \ 819 return (error); \ 820 DPRINTF(sc, UATH_DEBUG_DEVCAP, \ 821 "%s: %s=0x%08x\n", __func__, #x, v); \ 822 } while (0) 823 struct uath_devcap *cap = &sc->sc_devcap; 824 int error; 825 826 /* collect device capabilities */ 827 GETCAP(CAP_TARGET_VERSION, cap->targetVersion); 828 GETCAP(CAP_TARGET_REVISION, cap->targetRevision); 829 GETCAP(CAP_MAC_VERSION, cap->macVersion); 830 GETCAP(CAP_MAC_REVISION, cap->macRevision); 831 GETCAP(CAP_PHY_REVISION, cap->phyRevision); 832 GETCAP(CAP_ANALOG_5GHz_REVISION, cap->analog5GhzRevision); 833 GETCAP(CAP_ANALOG_2GHz_REVISION, cap->analog2GhzRevision); 834 835 GETCAP(CAP_REG_DOMAIN, cap->regDomain); 836 GETCAP(CAP_REG_CAP_BITS, cap->regCapBits); 837 #if 0 838 /* NB: not supported in rev 1.5 */ 839 GETCAP(CAP_COUNTRY_CODE, cap->countryCode); 840 #endif 841 GETCAP(CAP_WIRELESS_MODES, cap->wirelessModes); 842 GETCAP(CAP_CHAN_SPREAD_SUPPORT, cap->chanSpreadSupport); 843 GETCAP(CAP_COMPRESS_SUPPORT, cap->compressSupport); 844 GETCAP(CAP_BURST_SUPPORT, cap->burstSupport); 845 GETCAP(CAP_FAST_FRAMES_SUPPORT, cap->fastFramesSupport); 846 GETCAP(CAP_CHAP_TUNING_SUPPORT, cap->chapTuningSupport); 847 GETCAP(CAP_TURBOG_SUPPORT, cap->turboGSupport); 848 GETCAP(CAP_TURBO_PRIME_SUPPORT, cap->turboPrimeSupport); 849 GETCAP(CAP_DEVICE_TYPE, cap->deviceType); 850 GETCAP(CAP_WME_SUPPORT, cap->wmeSupport); 851 GETCAP(CAP_TOTAL_QUEUES, cap->numTxQueues); 852 GETCAP(CAP_CONNECTION_ID_MAX, cap->connectionIdMax); 853 854 GETCAP(CAP_LOW_5GHZ_CHAN, cap->low5GhzChan); 855 GETCAP(CAP_HIGH_5GHZ_CHAN, cap->high5GhzChan); 856 GETCAP(CAP_LOW_2GHZ_CHAN, cap->low2GhzChan); 857 GETCAP(CAP_HIGH_2GHZ_CHAN, cap->high2GhzChan); 858 GETCAP(CAP_TWICE_ANTENNAGAIN_5G, cap->twiceAntennaGain5G); 859 GETCAP(CAP_TWICE_ANTENNAGAIN_2G, cap->twiceAntennaGain2G); 860 861 GETCAP(CAP_CIPHER_AES_CCM, cap->supportCipherAES_CCM); 862 GETCAP(CAP_CIPHER_TKIP, cap->supportCipherTKIP); 863 GETCAP(CAP_MIC_TKIP, cap->supportMicTKIP); 864 865 cap->supportCipherWEP = 1; /* NB: always available */ 866 867 return (0); 868 } 869 870 static int 871 uath_get_devstatus(struct uath_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 872 { 873 int error; 874 875 /* retrieve MAC address */ 876 error = uath_get_status(sc, ST_MAC_ADDR, macaddr, IEEE80211_ADDR_LEN); 877 if (error != 0) { 878 device_printf(sc->sc_dev, "could not read MAC address\n"); 879 return (error); 880 } 881 882 error = uath_get_status(sc, ST_SERIAL_NUMBER, 883 &sc->sc_serial[0], sizeof(sc->sc_serial)); 884 if (error != 0) { 885 device_printf(sc->sc_dev, 886 "could not read device serial number\n"); 887 return (error); 888 } 889 return (0); 890 } 891 892 static int 893 uath_get_status(struct uath_softc *sc, uint32_t which, void *odata, int olen) 894 { 895 int error; 896 897 which = htobe32(which); 898 error = uath_cmd_read(sc, WDCMSG_TARGET_GET_STATUS, 899 &which, sizeof(which), odata, olen, UATH_CMD_FLAG_MAGIC); 900 if (error != 0) 901 device_printf(sc->sc_dev, 902 "could not read EEPROM offset 0x%02x\n", be32toh(which)); 903 return (error); 904 } 905 906 static void 907 uath_free_data_list(struct uath_softc *sc, struct uath_data data[], int ndata, 908 int fillmbuf) 909 { 910 int i; 911 912 for (i = 0; i < ndata; i++) { 913 struct uath_data *dp = &data[i]; 914 915 if (fillmbuf == 1) { 916 if (dp->m != NULL) { 917 m_freem(dp->m); 918 dp->m = NULL; 919 dp->buf = NULL; 920 } 921 } else { 922 dp->buf = NULL; 923 } 924 if (dp->ni != NULL) { 925 ieee80211_free_node(dp->ni); 926 dp->ni = NULL; 927 } 928 } 929 } 930 931 static int 932 uath_alloc_data_list(struct uath_softc *sc, struct uath_data data[], 933 int ndata, int maxsz, void *dma_buf) 934 { 935 int i, error; 936 937 for (i = 0; i < ndata; i++) { 938 struct uath_data *dp = &data[i]; 939 940 dp->sc = sc; 941 if (dma_buf == NULL) { 942 /* XXX check maxsz */ 943 dp->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 944 if (dp->m == NULL) { 945 device_printf(sc->sc_dev, 946 "could not allocate rx mbuf\n"); 947 error = ENOMEM; 948 goto fail; 949 } 950 dp->buf = mtod(dp->m, uint8_t *); 951 } else { 952 dp->m = NULL; 953 dp->buf = ((uint8_t *)dma_buf) + (i * maxsz); 954 } 955 dp->ni = NULL; 956 } 957 958 return (0); 959 960 fail: uath_free_data_list(sc, data, ndata, 1 /* free mbufs */); 961 return (error); 962 } 963 964 static int 965 uath_alloc_rx_data_list(struct uath_softc *sc) 966 { 967 int error, i; 968 969 /* XXX is it enough to store the RX packet with MCLBYTES bytes? */ 970 error = uath_alloc_data_list(sc, 971 sc->sc_rx, UATH_RX_DATA_LIST_COUNT, MCLBYTES, 972 NULL /* setup mbufs */); 973 if (error != 0) 974 return (error); 975 976 STAILQ_INIT(&sc->sc_rx_active); 977 STAILQ_INIT(&sc->sc_rx_inactive); 978 979 for (i = 0; i < UATH_RX_DATA_LIST_COUNT; i++) { 980 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], 981 next); 982 UATH_STAT_INC(sc, st_rx_inactive); 983 } 984 985 return (0); 986 } 987 988 static int 989 uath_alloc_tx_data_list(struct uath_softc *sc) 990 { 991 int error, i; 992 993 error = uath_alloc_data_list(sc, 994 sc->sc_tx, UATH_TX_DATA_LIST_COUNT, UATH_MAX_TXBUFSZ, 995 sc->sc_tx_dma_buf); 996 if (error != 0) 997 return (error); 998 999 STAILQ_INIT(&sc->sc_tx_active); 1000 STAILQ_INIT(&sc->sc_tx_inactive); 1001 STAILQ_INIT(&sc->sc_tx_pending); 1002 1003 for (i = 0; i < UATH_TX_DATA_LIST_COUNT; i++) { 1004 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], 1005 next); 1006 UATH_STAT_INC(sc, st_tx_inactive); 1007 } 1008 1009 return (0); 1010 } 1011 1012 static void 1013 uath_free_rx_data_list(struct uath_softc *sc) 1014 { 1015 uath_free_data_list(sc, sc->sc_rx, UATH_RX_DATA_LIST_COUNT, 1016 1 /* free mbufs */); 1017 } 1018 1019 static void 1020 uath_free_tx_data_list(struct uath_softc *sc) 1021 { 1022 uath_free_data_list(sc, sc->sc_tx, UATH_TX_DATA_LIST_COUNT, 1023 0 /* no mbufs */); 1024 } 1025 1026 static struct ieee80211vap * 1027 uath_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 1028 enum ieee80211_opmode opmode, int flags, 1029 const uint8_t bssid[IEEE80211_ADDR_LEN], 1030 const uint8_t mac[IEEE80211_ADDR_LEN]) 1031 { 1032 struct uath_vap *uvp; 1033 struct ieee80211vap *vap; 1034 1035 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 1036 return (NULL); 1037 uvp = malloc(sizeof(struct uath_vap), M_80211_VAP, M_WAITOK | M_ZERO); 1038 vap = &uvp->vap; 1039 /* enable s/w bmiss handling for sta mode */ 1040 1041 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 1042 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 1043 /* out of memory */ 1044 free(uvp, M_80211_VAP); 1045 return (NULL); 1046 } 1047 1048 /* override state transition machine */ 1049 uvp->newstate = vap->iv_newstate; 1050 vap->iv_newstate = uath_newstate; 1051 1052 /* complete setup */ 1053 ieee80211_vap_attach(vap, ieee80211_media_change, 1054 ieee80211_media_status, mac); 1055 ic->ic_opmode = opmode; 1056 return (vap); 1057 } 1058 1059 static void 1060 uath_vap_delete(struct ieee80211vap *vap) 1061 { 1062 struct uath_vap *uvp = UATH_VAP(vap); 1063 1064 ieee80211_vap_detach(vap); 1065 free(uvp, M_80211_VAP); 1066 } 1067 1068 static int 1069 uath_init(struct uath_softc *sc) 1070 { 1071 struct ieee80211com *ic = &sc->sc_ic; 1072 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1073 uint32_t val; 1074 int error; 1075 1076 UATH_ASSERT_LOCKED(sc); 1077 1078 if (sc->sc_flags & UATH_FLAG_INITDONE) 1079 uath_stop(sc); 1080 1081 /* reset variables */ 1082 sc->sc_intrx_nextnum = sc->sc_msgid = 0; 1083 1084 val = htobe32(0); 1085 uath_cmd_write(sc, WDCMSG_BIND, &val, sizeof val, 0); 1086 1087 /* set MAC address */ 1088 uath_config_multi(sc, CFG_MAC_ADDR, 1089 vap ? vap->iv_myaddr : ic->ic_macaddr, IEEE80211_ADDR_LEN); 1090 1091 /* XXX honor net80211 state */ 1092 uath_config(sc, CFG_RATE_CONTROL_ENABLE, 0x00000001); 1093 uath_config(sc, CFG_DIVERSITY_CTL, 0x00000001); 1094 uath_config(sc, CFG_ABOLT, 0x0000003f); 1095 uath_config(sc, CFG_WME_ENABLED, 0x00000001); 1096 1097 uath_config(sc, CFG_SERVICE_TYPE, 1); 1098 uath_config(sc, CFG_TP_SCALE, 0x00000000); 1099 uath_config(sc, CFG_TPC_HALF_DBM5, 0x0000003c); 1100 uath_config(sc, CFG_TPC_HALF_DBM2, 0x0000003c); 1101 uath_config(sc, CFG_OVERRD_TX_POWER, 0x00000000); 1102 uath_config(sc, CFG_GMODE_PROTECTION, 0x00000000); 1103 uath_config(sc, CFG_GMODE_PROTECT_RATE_INDEX, 0x00000003); 1104 uath_config(sc, CFG_PROTECTION_TYPE, 0x00000000); 1105 uath_config(sc, CFG_MODE_CTS, 0x00000002); 1106 1107 error = uath_cmd_read(sc, WDCMSG_TARGET_START, NULL, 0, 1108 &val, sizeof(val), UATH_CMD_FLAG_MAGIC); 1109 if (error) { 1110 device_printf(sc->sc_dev, 1111 "could not start target, error %d\n", error); 1112 goto fail; 1113 } 1114 DPRINTF(sc, UATH_DEBUG_INIT, "%s returns handle: 0x%x\n", 1115 uath_codename(WDCMSG_TARGET_START), be32toh(val)); 1116 1117 /* set default channel */ 1118 error = uath_switch_channel(sc, ic->ic_curchan); 1119 if (error) { 1120 device_printf(sc->sc_dev, 1121 "could not switch channel, error %d\n", error); 1122 goto fail; 1123 } 1124 1125 val = htobe32(TARGET_DEVICE_AWAKE); 1126 uath_cmd_write(sc, WDCMSG_SET_PWR_MODE, &val, sizeof val, 0); 1127 /* XXX? check */ 1128 uath_cmd_write(sc, WDCMSG_RESET_KEY_CACHE, NULL, 0, 0); 1129 1130 usbd_transfer_start(sc->sc_xfer[UATH_BULK_RX]); 1131 /* enable Rx */ 1132 uath_set_rxfilter(sc, 0x0, UATH_FILTER_OP_INIT); 1133 uath_set_rxfilter(sc, 1134 UATH_FILTER_RX_UCAST | UATH_FILTER_RX_MCAST | 1135 UATH_FILTER_RX_BCAST | UATH_FILTER_RX_BEACON, 1136 UATH_FILTER_OP_SET); 1137 1138 sc->sc_flags |= UATH_FLAG_INITDONE; 1139 1140 callout_reset(&sc->watchdog_ch, hz, uath_watchdog, sc); 1141 1142 return (0); 1143 1144 fail: 1145 uath_stop(sc); 1146 return (error); 1147 } 1148 1149 static void 1150 uath_stop(struct uath_softc *sc) 1151 { 1152 1153 UATH_ASSERT_LOCKED(sc); 1154 1155 sc->sc_flags &= ~UATH_FLAG_INITDONE; 1156 1157 callout_stop(&sc->stat_ch); 1158 callout_stop(&sc->watchdog_ch); 1159 sc->sc_tx_timer = 0; 1160 /* abort pending transmits */ 1161 uath_abort_xfers(sc); 1162 /* flush data & control requests into the target */ 1163 (void)uath_flush(sc); 1164 /* set a LED status to the disconnected. */ 1165 uath_set_ledstate(sc, 0); 1166 /* stop the target */ 1167 uath_cmd_write(sc, WDCMSG_TARGET_STOP, NULL, 0, 0); 1168 } 1169 1170 static int 1171 uath_config(struct uath_softc *sc, uint32_t reg, uint32_t val) 1172 { 1173 struct uath_write_mac write; 1174 int error; 1175 1176 write.reg = htobe32(reg); 1177 write.len = htobe32(0); /* 0 = single write */ 1178 *(uint32_t *)write.data = htobe32(val); 1179 1180 error = uath_cmd_write(sc, WDCMSG_TARGET_SET_CONFIG, &write, 1181 3 * sizeof (uint32_t), 0); 1182 if (error != 0) { 1183 device_printf(sc->sc_dev, "could not write register 0x%02x\n", 1184 reg); 1185 } 1186 return (error); 1187 } 1188 1189 static int 1190 uath_config_multi(struct uath_softc *sc, uint32_t reg, const void *data, 1191 int len) 1192 { 1193 struct uath_write_mac write; 1194 int error; 1195 1196 write.reg = htobe32(reg); 1197 write.len = htobe32(len); 1198 bcopy(data, write.data, len); 1199 1200 /* properly handle the case where len is zero (reset) */ 1201 error = uath_cmd_write(sc, WDCMSG_TARGET_SET_CONFIG, &write, 1202 (len == 0) ? sizeof (uint32_t) : 2 * sizeof (uint32_t) + len, 0); 1203 if (error != 0) { 1204 device_printf(sc->sc_dev, 1205 "could not write %d bytes to register 0x%02x\n", len, reg); 1206 } 1207 return (error); 1208 } 1209 1210 static int 1211 uath_switch_channel(struct uath_softc *sc, struct ieee80211_channel *c) 1212 { 1213 int error; 1214 1215 UATH_ASSERT_LOCKED(sc); 1216 1217 /* set radio frequency */ 1218 error = uath_set_chan(sc, c); 1219 if (error) { 1220 device_printf(sc->sc_dev, 1221 "could not set channel, error %d\n", error); 1222 goto failed; 1223 } 1224 /* reset Tx rings */ 1225 error = uath_reset_tx_queues(sc); 1226 if (error) { 1227 device_printf(sc->sc_dev, 1228 "could not reset Tx queues, error %d\n", error); 1229 goto failed; 1230 } 1231 /* set Tx rings WME properties */ 1232 error = uath_wme_init(sc); 1233 if (error) { 1234 device_printf(sc->sc_dev, 1235 "could not init Tx queues, error %d\n", error); 1236 goto failed; 1237 } 1238 error = uath_set_ledstate(sc, 0); 1239 if (error) { 1240 device_printf(sc->sc_dev, 1241 "could not set led state, error %d\n", error); 1242 goto failed; 1243 } 1244 error = uath_flush(sc); 1245 if (error) { 1246 device_printf(sc->sc_dev, 1247 "could not flush pipes, error %d\n", error); 1248 goto failed; 1249 } 1250 failed: 1251 return (error); 1252 } 1253 1254 static int 1255 uath_set_rxfilter(struct uath_softc *sc, uint32_t bits, uint32_t op) 1256 { 1257 struct uath_cmd_rx_filter rxfilter; 1258 1259 rxfilter.bits = htobe32(bits); 1260 rxfilter.op = htobe32(op); 1261 1262 DPRINTF(sc, UATH_DEBUG_RECV | UATH_DEBUG_RECV_ALL, 1263 "setting Rx filter=0x%x flags=0x%x\n", bits, op); 1264 return uath_cmd_write(sc, WDCMSG_RX_FILTER, &rxfilter, 1265 sizeof rxfilter, 0); 1266 } 1267 1268 static void 1269 uath_watchdog(void *arg) 1270 { 1271 struct uath_softc *sc = arg; 1272 struct ieee80211com *ic = &sc->sc_ic; 1273 1274 if (sc->sc_tx_timer > 0) { 1275 if (--sc->sc_tx_timer == 0) { 1276 device_printf(sc->sc_dev, "device timeout\n"); 1277 /*uath_init(sc); XXX needs a process context! */ 1278 counter_u64_add(ic->ic_oerrors, 1); 1279 return; 1280 } 1281 callout_reset(&sc->watchdog_ch, hz, uath_watchdog, sc); 1282 } 1283 } 1284 1285 static void 1286 uath_abort_xfers(struct uath_softc *sc) 1287 { 1288 int i; 1289 1290 UATH_ASSERT_LOCKED(sc); 1291 /* abort any pending transfers */ 1292 for (i = 0; i < UATH_N_XFERS; i++) 1293 usbd_transfer_stop(sc->sc_xfer[i]); 1294 } 1295 1296 static int 1297 uath_flush(struct uath_softc *sc) 1298 { 1299 int error; 1300 1301 error = uath_dataflush(sc); 1302 if (error != 0) 1303 goto failed; 1304 1305 error = uath_cmdflush(sc); 1306 if (error != 0) 1307 goto failed; 1308 1309 failed: 1310 return (error); 1311 } 1312 1313 static int 1314 uath_cmdflush(struct uath_softc *sc) 1315 { 1316 1317 return uath_cmd_write(sc, WDCMSG_FLUSH, NULL, 0, 0); 1318 } 1319 1320 static int 1321 uath_dataflush(struct uath_softc *sc) 1322 { 1323 struct uath_data *data; 1324 struct uath_chunk *chunk; 1325 struct uath_tx_desc *desc; 1326 1327 UATH_ASSERT_LOCKED(sc); 1328 1329 data = uath_getbuf(sc); 1330 if (data == NULL) 1331 return (ENOBUFS); 1332 data->buflen = sizeof(struct uath_chunk) + sizeof(struct uath_tx_desc); 1333 data->m = NULL; 1334 data->ni = NULL; 1335 chunk = (struct uath_chunk *)data->buf; 1336 desc = (struct uath_tx_desc *)(chunk + 1); 1337 1338 /* one chunk only */ 1339 chunk->seqnum = 0; 1340 chunk->flags = UATH_CFLAGS_FINAL; 1341 chunk->length = htobe16(sizeof (struct uath_tx_desc)); 1342 1343 memset(desc, 0, sizeof(struct uath_tx_desc)); 1344 desc->msglen = htobe32(sizeof(struct uath_tx_desc)); 1345 desc->msgid = (sc->sc_msgid++) + 1; /* don't care about endianness */ 1346 desc->type = htobe32(WDCMSG_FLUSH); 1347 desc->txqid = htobe32(0); 1348 desc->connid = htobe32(0); 1349 desc->flags = htobe32(0); 1350 1351 #ifdef UATH_DEBUG 1352 if (sc->sc_debug & UATH_DEBUG_CMDS) { 1353 DPRINTF(sc, UATH_DEBUG_RESET, "send flush ix %d\n", 1354 desc->msgid); 1355 if (sc->sc_debug & UATH_DEBUG_CMDS_DUMP) 1356 uath_dump_cmd(data->buf, data->buflen, '+'); 1357 } 1358 #endif 1359 1360 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 1361 UATH_STAT_INC(sc, st_tx_pending); 1362 sc->sc_tx_timer = 5; 1363 usbd_transfer_start(sc->sc_xfer[UATH_BULK_TX]); 1364 1365 return (0); 1366 } 1367 1368 static struct uath_data * 1369 _uath_getbuf(struct uath_softc *sc) 1370 { 1371 struct uath_data *bf; 1372 1373 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 1374 if (bf != NULL) { 1375 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 1376 UATH_STAT_DEC(sc, st_tx_inactive); 1377 } else 1378 bf = NULL; 1379 if (bf == NULL) 1380 DPRINTF(sc, UATH_DEBUG_XMIT, "%s: %s\n", __func__, 1381 "out of xmit buffers"); 1382 return (bf); 1383 } 1384 1385 static struct uath_data * 1386 uath_getbuf(struct uath_softc *sc) 1387 { 1388 struct uath_data *bf; 1389 1390 UATH_ASSERT_LOCKED(sc); 1391 1392 bf = _uath_getbuf(sc); 1393 if (bf == NULL) 1394 DPRINTF(sc, UATH_DEBUG_XMIT, "%s: stop queue\n", __func__); 1395 return (bf); 1396 } 1397 1398 static int 1399 uath_set_ledstate(struct uath_softc *sc, int connected) 1400 { 1401 1402 DPRINTF(sc, UATH_DEBUG_LED, 1403 "set led state %sconnected\n", connected ? "" : "!"); 1404 connected = htobe32(connected); 1405 return uath_cmd_write(sc, WDCMSG_SET_LED_STATE, 1406 &connected, sizeof connected, 0); 1407 } 1408 1409 static int 1410 uath_set_chan(struct uath_softc *sc, struct ieee80211_channel *c) 1411 { 1412 #ifdef UATH_DEBUG 1413 struct ieee80211com *ic = &sc->sc_ic; 1414 #endif 1415 struct uath_cmd_reset reset; 1416 1417 memset(&reset, 0, sizeof(reset)); 1418 if (IEEE80211_IS_CHAN_2GHZ(c)) 1419 reset.flags |= htobe32(UATH_CHAN_2GHZ); 1420 if (IEEE80211_IS_CHAN_5GHZ(c)) 1421 reset.flags |= htobe32(UATH_CHAN_5GHZ); 1422 /* NB: 11g =>'s 11b so don't specify both OFDM and CCK */ 1423 if (IEEE80211_IS_CHAN_OFDM(c)) 1424 reset.flags |= htobe32(UATH_CHAN_OFDM); 1425 else if (IEEE80211_IS_CHAN_CCK(c)) 1426 reset.flags |= htobe32(UATH_CHAN_CCK); 1427 /* turbo can be used in either 2GHz or 5GHz */ 1428 if (c->ic_flags & IEEE80211_CHAN_TURBO) 1429 reset.flags |= htobe32(UATH_CHAN_TURBO); 1430 reset.freq = htobe32(c->ic_freq); 1431 reset.maxrdpower = htobe32(50); /* XXX */ 1432 reset.channelchange = htobe32(1); 1433 reset.keeprccontent = htobe32(0); 1434 1435 DPRINTF(sc, UATH_DEBUG_CHANNEL, "set channel %d, flags 0x%x freq %u\n", 1436 ieee80211_chan2ieee(ic, c), 1437 be32toh(reset.flags), be32toh(reset.freq)); 1438 return uath_cmd_write(sc, WDCMSG_RESET, &reset, sizeof reset, 0); 1439 } 1440 1441 static int 1442 uath_reset_tx_queues(struct uath_softc *sc) 1443 { 1444 int ac, error; 1445 1446 DPRINTF(sc, UATH_DEBUG_RESET, "%s: reset Tx queues\n", __func__); 1447 for (ac = 0; ac < 4; ac++) { 1448 const uint32_t qid = htobe32(ac); 1449 1450 error = uath_cmd_write(sc, WDCMSG_RELEASE_TX_QUEUE, &qid, 1451 sizeof qid, 0); 1452 if (error != 0) 1453 break; 1454 } 1455 return (error); 1456 } 1457 1458 static int 1459 uath_wme_init(struct uath_softc *sc) 1460 { 1461 /* XXX get from net80211 */ 1462 static const struct uath_wme_settings uath_wme_11g[4] = { 1463 { 7, 4, 10, 0, 0 }, /* Background */ 1464 { 3, 4, 10, 0, 0 }, /* Best-Effort */ 1465 { 3, 3, 4, 26, 0 }, /* Video */ 1466 { 2, 2, 3, 47, 0 } /* Voice */ 1467 }; 1468 struct uath_cmd_txq_setup qinfo; 1469 int ac, error; 1470 1471 DPRINTF(sc, UATH_DEBUG_WME, "%s: setup Tx queues\n", __func__); 1472 for (ac = 0; ac < 4; ac++) { 1473 qinfo.qid = htobe32(ac); 1474 qinfo.len = htobe32(sizeof(qinfo.attr)); 1475 qinfo.attr.priority = htobe32(ac); /* XXX */ 1476 qinfo.attr.aifs = htobe32(uath_wme_11g[ac].aifsn); 1477 qinfo.attr.logcwmin = htobe32(uath_wme_11g[ac].logcwmin); 1478 qinfo.attr.logcwmax = htobe32(uath_wme_11g[ac].logcwmax); 1479 qinfo.attr.bursttime = htobe32(IEEE80211_TXOP_TO_US( 1480 uath_wme_11g[ac].txop)); 1481 qinfo.attr.mode = htobe32(uath_wme_11g[ac].acm);/*XXX? */ 1482 qinfo.attr.qflags = htobe32(1); /* XXX? */ 1483 1484 error = uath_cmd_write(sc, WDCMSG_SETUP_TX_QUEUE, &qinfo, 1485 sizeof qinfo, 0); 1486 if (error != 0) 1487 break; 1488 } 1489 return (error); 1490 } 1491 1492 static void 1493 uath_parent(struct ieee80211com *ic) 1494 { 1495 struct uath_softc *sc = ic->ic_softc; 1496 int startall = 0; 1497 1498 UATH_LOCK(sc); 1499 if (sc->sc_flags & UATH_FLAG_INVALID) { 1500 UATH_UNLOCK(sc); 1501 return; 1502 } 1503 1504 if (ic->ic_nrunning > 0) { 1505 if (!(sc->sc_flags & UATH_FLAG_INITDONE)) { 1506 uath_init(sc); 1507 startall = 1; 1508 } 1509 } else if (sc->sc_flags & UATH_FLAG_INITDONE) 1510 uath_stop(sc); 1511 UATH_UNLOCK(sc); 1512 if (startall) 1513 ieee80211_start_all(ic); 1514 } 1515 1516 static int 1517 uath_tx_start(struct uath_softc *sc, struct mbuf *m0, struct ieee80211_node *ni, 1518 struct uath_data *data) 1519 { 1520 struct ieee80211vap *vap = ni->ni_vap; 1521 struct uath_chunk *chunk; 1522 struct uath_tx_desc *desc; 1523 const struct ieee80211_frame *wh; 1524 struct ieee80211_key *k; 1525 int framelen, msglen; 1526 1527 UATH_ASSERT_LOCKED(sc); 1528 1529 data->ni = ni; 1530 data->m = m0; 1531 chunk = (struct uath_chunk *)data->buf; 1532 desc = (struct uath_tx_desc *)(chunk + 1); 1533 1534 if (ieee80211_radiotap_active_vap(vap)) { 1535 struct uath_tx_radiotap_header *tap = &sc->sc_txtap; 1536 1537 tap->wt_flags = 0; 1538 if (m0->m_flags & M_FRAG) 1539 tap->wt_flags |= IEEE80211_RADIOTAP_F_FRAG; 1540 1541 ieee80211_radiotap_tx(vap, m0); 1542 } 1543 1544 wh = mtod(m0, struct ieee80211_frame *); 1545 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1546 k = ieee80211_crypto_encap(ni, m0); 1547 if (k == NULL) { 1548 m_freem(m0); 1549 return (ENOBUFS); 1550 } 1551 1552 /* packet header may have moved, reset our local pointer */ 1553 wh = mtod(m0, struct ieee80211_frame *); 1554 } 1555 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)(desc + 1)); 1556 1557 framelen = m0->m_pkthdr.len + IEEE80211_CRC_LEN; 1558 msglen = framelen + sizeof (struct uath_tx_desc); 1559 data->buflen = msglen + sizeof (struct uath_chunk); 1560 1561 /* one chunk only for now */ 1562 chunk->seqnum = sc->sc_seqnum++; 1563 chunk->flags = (m0->m_flags & M_FRAG) ? 0 : UATH_CFLAGS_FINAL; 1564 if (m0->m_flags & M_LASTFRAG) 1565 chunk->flags |= UATH_CFLAGS_FINAL; 1566 chunk->flags = UATH_CFLAGS_FINAL; 1567 chunk->length = htobe16(msglen); 1568 1569 /* fill Tx descriptor */ 1570 desc->msglen = htobe32(msglen); 1571 /* NB: to get UATH_TX_NOTIFY reply, `msgid' must be larger than 0 */ 1572 desc->msgid = (sc->sc_msgid++) + 1; /* don't care about endianness */ 1573 desc->type = htobe32(WDCMSG_SEND); 1574 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 1575 case IEEE80211_FC0_TYPE_CTL: 1576 case IEEE80211_FC0_TYPE_MGT: 1577 /* NB: force all management frames to highest queue */ 1578 if (ni->ni_flags & IEEE80211_NODE_QOS) { 1579 /* NB: force all management frames to highest queue */ 1580 desc->txqid = htobe32(WME_AC_VO | UATH_TXQID_MINRATE); 1581 } else 1582 desc->txqid = htobe32(WME_AC_BE | UATH_TXQID_MINRATE); 1583 break; 1584 case IEEE80211_FC0_TYPE_DATA: 1585 /* XXX multicast frames should honor mcastrate */ 1586 desc->txqid = htobe32(M_WME_GETAC(m0)); 1587 break; 1588 default: 1589 device_printf(sc->sc_dev, "bogus frame type 0x%x (%s)\n", 1590 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__); 1591 m_freem(m0); 1592 return (EIO); 1593 } 1594 if (vap->iv_state == IEEE80211_S_AUTH || 1595 vap->iv_state == IEEE80211_S_ASSOC || 1596 vap->iv_state == IEEE80211_S_RUN) 1597 desc->connid = htobe32(UATH_ID_BSS); 1598 else 1599 desc->connid = htobe32(UATH_ID_INVALID); 1600 desc->flags = htobe32(0 /* no UATH_TX_NOTIFY */); 1601 desc->buflen = htobe32(m0->m_pkthdr.len); 1602 1603 #ifdef UATH_DEBUG 1604 DPRINTF(sc, UATH_DEBUG_XMIT, 1605 "send frame ix %u framelen %d msglen %d connid 0x%x txqid 0x%x\n", 1606 desc->msgid, framelen, msglen, be32toh(desc->connid), 1607 be32toh(desc->txqid)); 1608 if (sc->sc_debug & UATH_DEBUG_XMIT_DUMP) 1609 uath_dump_cmd(data->buf, data->buflen, '+'); 1610 #endif 1611 1612 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 1613 UATH_STAT_INC(sc, st_tx_pending); 1614 usbd_transfer_start(sc->sc_xfer[UATH_BULK_TX]); 1615 1616 return (0); 1617 } 1618 1619 /* 1620 * Cleanup driver resources when we run out of buffers while processing 1621 * fragments; return the tx buffers allocated and drop node references. 1622 */ 1623 static void 1624 uath_txfrag_cleanup(struct uath_softc *sc, 1625 uath_datahead *frags, struct ieee80211_node *ni) 1626 { 1627 struct uath_data *bf, *next; 1628 1629 UATH_ASSERT_LOCKED(sc); 1630 1631 STAILQ_FOREACH_SAFE(bf, frags, next, next) { 1632 /* NB: bf assumed clean */ 1633 STAILQ_REMOVE_HEAD(frags, next); 1634 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 1635 UATH_STAT_INC(sc, st_tx_inactive); 1636 ieee80211_node_decref(ni); 1637 } 1638 } 1639 1640 /* 1641 * Setup xmit of a fragmented frame. Allocate a buffer for each frag and bump 1642 * the node reference count to reflect the held reference to be setup by 1643 * uath_tx_start. 1644 */ 1645 static int 1646 uath_txfrag_setup(struct uath_softc *sc, uath_datahead *frags, 1647 struct mbuf *m0, struct ieee80211_node *ni) 1648 { 1649 struct mbuf *m; 1650 struct uath_data *bf; 1651 1652 UATH_ASSERT_LOCKED(sc); 1653 for (m = m0->m_nextpkt; m != NULL; m = m->m_nextpkt) { 1654 bf = uath_getbuf(sc); 1655 if (bf == NULL) { /* out of buffers, cleanup */ 1656 uath_txfrag_cleanup(sc, frags, ni); 1657 break; 1658 } 1659 ieee80211_node_incref(ni); 1660 STAILQ_INSERT_TAIL(frags, bf, next); 1661 } 1662 1663 return !STAILQ_EMPTY(frags); 1664 } 1665 1666 /* 1667 * Reclaim mbuf resources. For fragmented frames we need to claim each frag 1668 * chained with m_nextpkt. 1669 */ 1670 static void 1671 uath_freetx(struct mbuf *m) 1672 { 1673 struct mbuf *next; 1674 1675 do { 1676 next = m->m_nextpkt; 1677 m->m_nextpkt = NULL; 1678 m_freem(m); 1679 } while ((m = next) != NULL); 1680 } 1681 1682 static int 1683 uath_transmit(struct ieee80211com *ic, struct mbuf *m) 1684 { 1685 struct uath_softc *sc = ic->ic_softc; 1686 int error; 1687 1688 UATH_LOCK(sc); 1689 if ((sc->sc_flags & UATH_FLAG_INITDONE) == 0) { 1690 UATH_UNLOCK(sc); 1691 return (ENXIO); 1692 } 1693 error = mbufq_enqueue(&sc->sc_snd, m); 1694 if (error) { 1695 UATH_UNLOCK(sc); 1696 return (error); 1697 } 1698 uath_start(sc); 1699 UATH_UNLOCK(sc); 1700 1701 return (0); 1702 } 1703 1704 static void 1705 uath_start(struct uath_softc *sc) 1706 { 1707 struct uath_data *bf; 1708 struct ieee80211_node *ni; 1709 struct mbuf *m, *next; 1710 uath_datahead frags; 1711 1712 UATH_ASSERT_LOCKED(sc); 1713 1714 if ((sc->sc_flags & UATH_FLAG_INITDONE) == 0 || 1715 (sc->sc_flags & UATH_FLAG_INVALID)) 1716 return; 1717 1718 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1719 bf = uath_getbuf(sc); 1720 if (bf == NULL) { 1721 mbufq_prepend(&sc->sc_snd, m); 1722 break; 1723 } 1724 1725 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1726 m->m_pkthdr.rcvif = NULL; 1727 1728 /* 1729 * Check for fragmentation. If this frame has been broken up 1730 * verify we have enough buffers to send all the fragments 1731 * so all go out or none... 1732 */ 1733 STAILQ_INIT(&frags); 1734 if ((m->m_flags & M_FRAG) && 1735 !uath_txfrag_setup(sc, &frags, m, ni)) { 1736 DPRINTF(sc, UATH_DEBUG_XMIT, 1737 "%s: out of txfrag buffers\n", __func__); 1738 uath_freetx(m); 1739 goto bad; 1740 } 1741 sc->sc_seqnum = 0; 1742 nextfrag: 1743 /* 1744 * Pass the frame to the h/w for transmission. 1745 * Fragmented frames have each frag chained together 1746 * with m_nextpkt. We know there are sufficient uath_data's 1747 * to send all the frags because of work done by 1748 * uath_txfrag_setup. 1749 */ 1750 next = m->m_nextpkt; 1751 if (uath_tx_start(sc, m, ni, bf) != 0) { 1752 bad: 1753 if_inc_counter(ni->ni_vap->iv_ifp, 1754 IFCOUNTER_OERRORS, 1); 1755 reclaim: 1756 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 1757 UATH_STAT_INC(sc, st_tx_inactive); 1758 uath_txfrag_cleanup(sc, &frags, ni); 1759 ieee80211_free_node(ni); 1760 continue; 1761 } 1762 1763 if (next != NULL) { 1764 /* 1765 * Beware of state changing between frags. 1766 XXX check sta power-save state? 1767 */ 1768 if (ni->ni_vap->iv_state != IEEE80211_S_RUN) { 1769 DPRINTF(sc, UATH_DEBUG_XMIT, 1770 "%s: flush fragmented packet, state %s\n", 1771 __func__, 1772 ieee80211_state_name[ni->ni_vap->iv_state]); 1773 uath_freetx(next); 1774 goto reclaim; 1775 } 1776 m = next; 1777 bf = STAILQ_FIRST(&frags); 1778 KASSERT(bf != NULL, ("no buf for txfrag")); 1779 STAILQ_REMOVE_HEAD(&frags, next); 1780 goto nextfrag; 1781 } 1782 1783 sc->sc_tx_timer = 5; 1784 } 1785 } 1786 1787 static int 1788 uath_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1789 const struct ieee80211_bpf_params *params) 1790 { 1791 struct ieee80211com *ic = ni->ni_ic; 1792 struct uath_data *bf; 1793 struct uath_softc *sc = ic->ic_softc; 1794 1795 UATH_LOCK(sc); 1796 /* prevent management frames from being sent if we're not ready */ 1797 if ((sc->sc_flags & UATH_FLAG_INVALID) || 1798 !(sc->sc_flags & UATH_FLAG_INITDONE)) { 1799 m_freem(m); 1800 ieee80211_free_node(ni); 1801 UATH_UNLOCK(sc); 1802 return (ENETDOWN); 1803 } 1804 1805 /* grab a TX buffer */ 1806 bf = uath_getbuf(sc); 1807 if (bf == NULL) { 1808 ieee80211_free_node(ni); 1809 m_freem(m); 1810 UATH_UNLOCK(sc); 1811 return (ENOBUFS); 1812 } 1813 1814 sc->sc_seqnum = 0; 1815 if (uath_tx_start(sc, m, ni, bf) != 0) { 1816 ieee80211_free_node(ni); 1817 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 1818 UATH_STAT_INC(sc, st_tx_inactive); 1819 UATH_UNLOCK(sc); 1820 return (EIO); 1821 } 1822 UATH_UNLOCK(sc); 1823 1824 sc->sc_tx_timer = 5; 1825 return (0); 1826 } 1827 1828 static void 1829 uath_scan_start(struct ieee80211com *ic) 1830 { 1831 /* do nothing */ 1832 } 1833 1834 static void 1835 uath_scan_end(struct ieee80211com *ic) 1836 { 1837 /* do nothing */ 1838 } 1839 1840 static void 1841 uath_set_channel(struct ieee80211com *ic) 1842 { 1843 struct uath_softc *sc = ic->ic_softc; 1844 1845 UATH_LOCK(sc); 1846 if ((sc->sc_flags & UATH_FLAG_INVALID) || 1847 (sc->sc_flags & UATH_FLAG_INITDONE) == 0) { 1848 UATH_UNLOCK(sc); 1849 return; 1850 } 1851 (void)uath_switch_channel(sc, ic->ic_curchan); 1852 UATH_UNLOCK(sc); 1853 } 1854 1855 static int 1856 uath_set_rxmulti_filter(struct uath_softc *sc) 1857 { 1858 /* XXX broken */ 1859 return (0); 1860 } 1861 static void 1862 uath_update_mcast(struct ieee80211com *ic) 1863 { 1864 struct uath_softc *sc = ic->ic_softc; 1865 1866 UATH_LOCK(sc); 1867 if ((sc->sc_flags & UATH_FLAG_INVALID) || 1868 (sc->sc_flags & UATH_FLAG_INITDONE) == 0) { 1869 UATH_UNLOCK(sc); 1870 return; 1871 } 1872 /* 1873 * this is for avoiding the race condition when we're try to 1874 * connect to the AP with WPA. 1875 */ 1876 if (sc->sc_flags & UATH_FLAG_INITDONE) 1877 (void)uath_set_rxmulti_filter(sc); 1878 UATH_UNLOCK(sc); 1879 } 1880 1881 static void 1882 uath_update_promisc(struct ieee80211com *ic) 1883 { 1884 struct uath_softc *sc = ic->ic_softc; 1885 1886 UATH_LOCK(sc); 1887 if ((sc->sc_flags & UATH_FLAG_INVALID) || 1888 (sc->sc_flags & UATH_FLAG_INITDONE) == 0) { 1889 UATH_UNLOCK(sc); 1890 return; 1891 } 1892 if (sc->sc_flags & UATH_FLAG_INITDONE) { 1893 uath_set_rxfilter(sc, 1894 UATH_FILTER_RX_UCAST | UATH_FILTER_RX_MCAST | 1895 UATH_FILTER_RX_BCAST | UATH_FILTER_RX_BEACON | 1896 UATH_FILTER_RX_PROM, UATH_FILTER_OP_SET); 1897 } 1898 UATH_UNLOCK(sc); 1899 } 1900 1901 static int 1902 uath_create_connection(struct uath_softc *sc, uint32_t connid) 1903 { 1904 const struct ieee80211_rateset *rs; 1905 struct ieee80211com *ic = &sc->sc_ic; 1906 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1907 struct ieee80211_node *ni; 1908 struct uath_cmd_create_connection create; 1909 1910 ni = ieee80211_ref_node(vap->iv_bss); 1911 memset(&create, 0, sizeof(create)); 1912 create.connid = htobe32(connid); 1913 create.bssid = htobe32(0); 1914 /* XXX packed or not? */ 1915 create.size = htobe32(sizeof(struct uath_cmd_rateset)); 1916 1917 rs = &ni->ni_rates; 1918 create.connattr.rateset.length = rs->rs_nrates; 1919 bcopy(rs->rs_rates, &create.connattr.rateset.set[0], 1920 rs->rs_nrates); 1921 1922 /* XXX turbo */ 1923 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) 1924 create.connattr.wlanmode = htobe32(WLAN_MODE_11a); 1925 else if (IEEE80211_IS_CHAN_ANYG(ni->ni_chan)) 1926 create.connattr.wlanmode = htobe32(WLAN_MODE_11g); 1927 else 1928 create.connattr.wlanmode = htobe32(WLAN_MODE_11b); 1929 ieee80211_free_node(ni); 1930 1931 return uath_cmd_write(sc, WDCMSG_CREATE_CONNECTION, &create, 1932 sizeof create, 0); 1933 } 1934 1935 static int 1936 uath_set_rates(struct uath_softc *sc, const struct ieee80211_rateset *rs) 1937 { 1938 struct uath_cmd_rates rates; 1939 1940 memset(&rates, 0, sizeof(rates)); 1941 rates.connid = htobe32(UATH_ID_BSS); /* XXX */ 1942 rates.size = htobe32(sizeof(struct uath_cmd_rateset)); 1943 /* XXX bounds check rs->rs_nrates */ 1944 rates.rateset.length = rs->rs_nrates; 1945 bcopy(rs->rs_rates, &rates.rateset.set[0], rs->rs_nrates); 1946 1947 DPRINTF(sc, UATH_DEBUG_RATES, 1948 "setting supported rates nrates=%d\n", rs->rs_nrates); 1949 return uath_cmd_write(sc, WDCMSG_SET_BASIC_RATE, 1950 &rates, sizeof rates, 0); 1951 } 1952 1953 static int 1954 uath_write_associd(struct uath_softc *sc) 1955 { 1956 struct ieee80211com *ic = &sc->sc_ic; 1957 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1958 struct ieee80211_node *ni; 1959 struct uath_cmd_set_associd associd; 1960 1961 ni = ieee80211_ref_node(vap->iv_bss); 1962 memset(&associd, 0, sizeof(associd)); 1963 associd.defaultrateix = htobe32(1); /* XXX */ 1964 associd.associd = htobe32(ni->ni_associd); 1965 associd.timoffset = htobe32(0x3b); /* XXX */ 1966 IEEE80211_ADDR_COPY(associd.bssid, ni->ni_bssid); 1967 ieee80211_free_node(ni); 1968 return uath_cmd_write(sc, WDCMSG_WRITE_ASSOCID, &associd, 1969 sizeof associd, 0); 1970 } 1971 1972 static int 1973 uath_set_ledsteady(struct uath_softc *sc, int lednum, int ledmode) 1974 { 1975 struct uath_cmd_ledsteady led; 1976 1977 led.lednum = htobe32(lednum); 1978 led.ledmode = htobe32(ledmode); 1979 1980 DPRINTF(sc, UATH_DEBUG_LED, "set %s led %s (steady)\n", 1981 (lednum == UATH_LED_LINK) ? "link" : "activity", 1982 ledmode ? "on" : "off"); 1983 return uath_cmd_write(sc, WDCMSG_SET_LED_STEADY, &led, sizeof led, 0); 1984 } 1985 1986 static int 1987 uath_set_ledblink(struct uath_softc *sc, int lednum, int ledmode, 1988 int blinkrate, int slowmode) 1989 { 1990 struct uath_cmd_ledblink led; 1991 1992 led.lednum = htobe32(lednum); 1993 led.ledmode = htobe32(ledmode); 1994 led.blinkrate = htobe32(blinkrate); 1995 led.slowmode = htobe32(slowmode); 1996 1997 DPRINTF(sc, UATH_DEBUG_LED, "set %s led %s (blink)\n", 1998 (lednum == UATH_LED_LINK) ? "link" : "activity", 1999 ledmode ? "on" : "off"); 2000 return uath_cmd_write(sc, WDCMSG_SET_LED_BLINK, &led, sizeof led, 0); 2001 } 2002 2003 static int 2004 uath_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 2005 { 2006 enum ieee80211_state ostate = vap->iv_state; 2007 int error; 2008 struct ieee80211_node *ni; 2009 struct ieee80211com *ic = vap->iv_ic; 2010 struct uath_softc *sc = ic->ic_softc; 2011 struct uath_vap *uvp = UATH_VAP(vap); 2012 2013 DPRINTF(sc, UATH_DEBUG_STATE, 2014 "%s: %s -> %s\n", __func__, ieee80211_state_name[vap->iv_state], 2015 ieee80211_state_name[nstate]); 2016 2017 IEEE80211_UNLOCK(ic); 2018 UATH_LOCK(sc); 2019 callout_stop(&sc->stat_ch); 2020 callout_stop(&sc->watchdog_ch); 2021 ni = ieee80211_ref_node(vap->iv_bss); 2022 2023 switch (nstate) { 2024 case IEEE80211_S_INIT: 2025 if (ostate == IEEE80211_S_RUN) { 2026 /* turn link and activity LEDs off */ 2027 uath_set_ledstate(sc, 0); 2028 } 2029 break; 2030 2031 case IEEE80211_S_SCAN: 2032 break; 2033 2034 case IEEE80211_S_AUTH: 2035 /* XXX good place? set RTS threshold */ 2036 uath_config(sc, CFG_USER_RTS_THRESHOLD, vap->iv_rtsthreshold); 2037 /* XXX bad place */ 2038 error = uath_set_keys(sc, vap); 2039 if (error != 0) { 2040 device_printf(sc->sc_dev, 2041 "could not set crypto keys, error %d\n", error); 2042 break; 2043 } 2044 if (uath_switch_channel(sc, ni->ni_chan) != 0) { 2045 device_printf(sc->sc_dev, "could not switch channel\n"); 2046 break; 2047 } 2048 if (uath_create_connection(sc, UATH_ID_BSS) != 0) { 2049 device_printf(sc->sc_dev, 2050 "could not create connection\n"); 2051 break; 2052 } 2053 break; 2054 2055 case IEEE80211_S_ASSOC: 2056 if (uath_set_rates(sc, &ni->ni_rates) != 0) { 2057 device_printf(sc->sc_dev, 2058 "could not set negotiated rate set\n"); 2059 break; 2060 } 2061 break; 2062 2063 case IEEE80211_S_RUN: 2064 /* XXX monitor mode doesn't be tested */ 2065 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2066 uath_set_ledstate(sc, 1); 2067 break; 2068 } 2069 2070 /* 2071 * Tx rate is controlled by firmware, report the maximum 2072 * negotiated rate in ifconfig output. 2073 */ 2074 ni->ni_txrate = ni->ni_rates.rs_rates[ni->ni_rates.rs_nrates-1]; 2075 2076 if (uath_write_associd(sc) != 0) { 2077 device_printf(sc->sc_dev, 2078 "could not write association id\n"); 2079 break; 2080 } 2081 /* turn link LED on */ 2082 uath_set_ledsteady(sc, UATH_LED_LINK, UATH_LED_ON); 2083 /* make activity LED blink */ 2084 uath_set_ledblink(sc, UATH_LED_ACTIVITY, UATH_LED_ON, 1, 2); 2085 /* set state to associated */ 2086 uath_set_ledstate(sc, 1); 2087 2088 /* start statistics timer */ 2089 callout_reset(&sc->stat_ch, hz, uath_stat, sc); 2090 break; 2091 default: 2092 break; 2093 } 2094 ieee80211_free_node(ni); 2095 UATH_UNLOCK(sc); 2096 IEEE80211_LOCK(ic); 2097 return (uvp->newstate(vap, nstate, arg)); 2098 } 2099 2100 static int 2101 uath_set_key(struct uath_softc *sc, const struct ieee80211_key *wk, 2102 int index) 2103 { 2104 #if 0 2105 struct uath_cmd_crypto crypto; 2106 int i; 2107 2108 memset(&crypto, 0, sizeof(crypto)); 2109 crypto.keyidx = htobe32(index); 2110 crypto.magic1 = htobe32(1); 2111 crypto.size = htobe32(368); 2112 crypto.mask = htobe32(0xffff); 2113 crypto.flags = htobe32(0x80000068); 2114 if (index != UATH_DEFAULT_KEY) 2115 crypto.flags |= htobe32(index << 16); 2116 memset(crypto.magic2, 0xff, sizeof(crypto.magic2)); 2117 2118 /* 2119 * Each byte of the key must be XOR'ed with 10101010 before being 2120 * transmitted to the firmware. 2121 */ 2122 for (i = 0; i < wk->wk_keylen; i++) 2123 crypto.key[i] = wk->wk_key[i] ^ 0xaa; 2124 2125 DPRINTF(sc, UATH_DEBUG_CRYPTO, 2126 "setting crypto key index=%d len=%d\n", index, wk->wk_keylen); 2127 return uath_cmd_write(sc, WDCMSG_SET_KEY_CACHE_ENTRY, &crypto, 2128 sizeof crypto, 0); 2129 #else 2130 /* XXX support H/W cryto */ 2131 return (0); 2132 #endif 2133 } 2134 2135 static int 2136 uath_set_keys(struct uath_softc *sc, struct ieee80211vap *vap) 2137 { 2138 int i, error; 2139 2140 error = 0; 2141 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2142 const struct ieee80211_key *wk = &vap->iv_nw_keys[i]; 2143 2144 if (wk->wk_flags & (IEEE80211_KEY_XMIT|IEEE80211_KEY_RECV)) { 2145 error = uath_set_key(sc, wk, i); 2146 if (error) 2147 return (error); 2148 } 2149 } 2150 if (vap->iv_def_txkey != IEEE80211_KEYIX_NONE) { 2151 error = uath_set_key(sc, &vap->iv_nw_keys[vap->iv_def_txkey], 2152 UATH_DEFAULT_KEY); 2153 } 2154 return (error); 2155 } 2156 2157 #define UATH_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 2158 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 2159 2160 static void 2161 uath_sysctl_node(struct uath_softc *sc) 2162 { 2163 struct sysctl_ctx_list *ctx; 2164 struct sysctl_oid_list *child; 2165 struct sysctl_oid *tree; 2166 struct uath_stat *stats; 2167 2168 stats = &sc->sc_stat; 2169 ctx = device_get_sysctl_ctx(sc->sc_dev); 2170 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->sc_dev)); 2171 2172 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 2173 NULL, "UATH statistics"); 2174 child = SYSCTL_CHILDREN(tree); 2175 UATH_SYSCTL_STAT_ADD32(ctx, child, "badchunkseqnum", 2176 &stats->st_badchunkseqnum, "Bad chunk sequence numbers"); 2177 UATH_SYSCTL_STAT_ADD32(ctx, child, "invalidlen", &stats->st_invalidlen, 2178 "Invalid length"); 2179 UATH_SYSCTL_STAT_ADD32(ctx, child, "multichunk", &stats->st_multichunk, 2180 "Multi chunks"); 2181 UATH_SYSCTL_STAT_ADD32(ctx, child, "toobigrxpkt", 2182 &stats->st_toobigrxpkt, "Too big rx packets"); 2183 UATH_SYSCTL_STAT_ADD32(ctx, child, "stopinprogress", 2184 &stats->st_stopinprogress, "Stop in progress"); 2185 UATH_SYSCTL_STAT_ADD32(ctx, child, "crcerrs", &stats->st_crcerr, 2186 "CRC errors"); 2187 UATH_SYSCTL_STAT_ADD32(ctx, child, "phyerr", &stats->st_phyerr, 2188 "PHY errors"); 2189 UATH_SYSCTL_STAT_ADD32(ctx, child, "decrypt_crcerr", 2190 &stats->st_decrypt_crcerr, "Decryption CRC errors"); 2191 UATH_SYSCTL_STAT_ADD32(ctx, child, "decrypt_micerr", 2192 &stats->st_decrypt_micerr, "Decryption Misc errors"); 2193 UATH_SYSCTL_STAT_ADD32(ctx, child, "decomperr", &stats->st_decomperr, 2194 "Decomp errors"); 2195 UATH_SYSCTL_STAT_ADD32(ctx, child, "keyerr", &stats->st_keyerr, 2196 "Key errors"); 2197 UATH_SYSCTL_STAT_ADD32(ctx, child, "err", &stats->st_err, 2198 "Unknown errors"); 2199 2200 UATH_SYSCTL_STAT_ADD32(ctx, child, "cmd_active", 2201 &stats->st_cmd_active, "Active numbers in Command queue"); 2202 UATH_SYSCTL_STAT_ADD32(ctx, child, "cmd_inactive", 2203 &stats->st_cmd_inactive, "Inactive numbers in Command queue"); 2204 UATH_SYSCTL_STAT_ADD32(ctx, child, "cmd_pending", 2205 &stats->st_cmd_pending, "Pending numbers in Command queue"); 2206 UATH_SYSCTL_STAT_ADD32(ctx, child, "cmd_waiting", 2207 &stats->st_cmd_waiting, "Waiting numbers in Command queue"); 2208 UATH_SYSCTL_STAT_ADD32(ctx, child, "rx_active", 2209 &stats->st_rx_active, "Active numbers in RX queue"); 2210 UATH_SYSCTL_STAT_ADD32(ctx, child, "rx_inactive", 2211 &stats->st_rx_inactive, "Inactive numbers in RX queue"); 2212 UATH_SYSCTL_STAT_ADD32(ctx, child, "tx_active", 2213 &stats->st_tx_active, "Active numbers in TX queue"); 2214 UATH_SYSCTL_STAT_ADD32(ctx, child, "tx_inactive", 2215 &stats->st_tx_inactive, "Inactive numbers in TX queue"); 2216 UATH_SYSCTL_STAT_ADD32(ctx, child, "tx_pending", 2217 &stats->st_tx_pending, "Pending numbers in TX queue"); 2218 } 2219 2220 #undef UATH_SYSCTL_STAT_ADD32 2221 2222 static void 2223 uath_cmdeof(struct uath_softc *sc, struct uath_cmd *cmd) 2224 { 2225 struct uath_cmd_hdr *hdr; 2226 int dlen; 2227 2228 hdr = (struct uath_cmd_hdr *)cmd->buf; 2229 /* NB: msgid is passed thru w/o byte swapping */ 2230 #ifdef UATH_DEBUG 2231 if (sc->sc_debug & UATH_DEBUG_CMDS) { 2232 int len = be32toh(hdr->len); 2233 printf("%s: %s [ix %u] len %u status %u\n", 2234 __func__, uath_codename(be32toh(hdr->code)), 2235 hdr->msgid, len, be32toh(hdr->magic)); 2236 if (sc->sc_debug & UATH_DEBUG_CMDS_DUMP) 2237 uath_dump_cmd(cmd->buf, 2238 len > UATH_MAX_CMDSZ ? sizeof(*hdr) : len, '-'); 2239 } 2240 #endif 2241 hdr->code = be32toh(hdr->code); 2242 hdr->len = be32toh(hdr->len); 2243 hdr->magic = be32toh(hdr->magic); /* target status on return */ 2244 2245 switch (hdr->code & 0xff) { 2246 /* reply to a read command */ 2247 default: 2248 dlen = hdr->len - sizeof(*hdr); 2249 if (dlen < 0) { 2250 device_printf(sc->sc_dev, 2251 "Invalid header length %d\n", dlen); 2252 return; 2253 } 2254 DPRINTF(sc, UATH_DEBUG_RX_PROC | UATH_DEBUG_RECV_ALL, 2255 "%s: code %d data len %u\n", 2256 __func__, hdr->code & 0xff, dlen); 2257 /* 2258 * The first response from the target after the 2259 * HOST_AVAILABLE has an invalid msgid so we must 2260 * treat it specially. 2261 */ 2262 if (hdr->msgid < UATH_CMD_LIST_COUNT) { 2263 uint32_t *rp = (uint32_t *)(hdr+1); 2264 u_int olen; 2265 2266 if (!(sizeof(*hdr) <= hdr->len && 2267 hdr->len < UATH_MAX_CMDSZ)) { 2268 device_printf(sc->sc_dev, 2269 "%s: invalid WDC msg length %u; " 2270 "msg ignored\n", __func__, hdr->len); 2271 return; 2272 } 2273 /* 2274 * Calculate return/receive payload size; the 2275 * first word, if present, always gives the 2276 * number of bytes--unless it's 0 in which 2277 * case a single 32-bit word should be present. 2278 */ 2279 if (dlen >= (int)sizeof(uint32_t)) { 2280 olen = be32toh(rp[0]); 2281 dlen -= sizeof(uint32_t); 2282 if (olen == 0) { 2283 /* convention is 0 =>'s one word */ 2284 olen = sizeof(uint32_t); 2285 /* XXX KASSERT(olen == dlen ) */ 2286 } 2287 } else 2288 olen = 0; 2289 if (cmd->odata != NULL) { 2290 /* NB: cmd->olen validated in uath_cmd */ 2291 if (olen > (u_int)cmd->olen) { 2292 /* XXX complain? */ 2293 device_printf(sc->sc_dev, 2294 "%s: cmd 0x%x olen %u cmd olen %u\n", 2295 __func__, hdr->code, olen, 2296 cmd->olen); 2297 olen = cmd->olen; 2298 } 2299 if (olen > (u_int)dlen) { 2300 /* XXX complain, shouldn't happen */ 2301 device_printf(sc->sc_dev, 2302 "%s: cmd 0x%x olen %u dlen %u\n", 2303 __func__, hdr->code, olen, dlen); 2304 olen = dlen; 2305 } 2306 /* XXX have submitter do this */ 2307 /* copy answer into caller's supplied buffer */ 2308 bcopy(&rp[1], cmd->odata, olen); 2309 cmd->olen = olen; 2310 } 2311 } 2312 wakeup_one(cmd); /* wake up caller */ 2313 break; 2314 2315 case WDCMSG_TARGET_START: 2316 if (hdr->msgid >= UATH_CMD_LIST_COUNT) { 2317 /* XXX */ 2318 return; 2319 } 2320 dlen = hdr->len - sizeof(*hdr); 2321 if (dlen != (int)sizeof(uint32_t)) { 2322 /* XXX something wrong */ 2323 return; 2324 } 2325 /* XXX have submitter do this */ 2326 /* copy answer into caller's supplied buffer */ 2327 bcopy(hdr+1, cmd->odata, sizeof(uint32_t)); 2328 cmd->olen = sizeof(uint32_t); 2329 wakeup_one(cmd); /* wake up caller */ 2330 break; 2331 2332 case WDCMSG_SEND_COMPLETE: 2333 /* this notification is sent when UATH_TX_NOTIFY is set */ 2334 DPRINTF(sc, UATH_DEBUG_RX_PROC | UATH_DEBUG_RECV_ALL, 2335 "%s: received Tx notification\n", __func__); 2336 break; 2337 2338 case WDCMSG_TARGET_GET_STATS: 2339 DPRINTF(sc, UATH_DEBUG_RX_PROC | UATH_DEBUG_RECV_ALL, 2340 "%s: received device statistics\n", __func__); 2341 callout_reset(&sc->stat_ch, hz, uath_stat, sc); 2342 break; 2343 } 2344 } 2345 2346 static void 2347 uath_intr_rx_callback(struct usb_xfer *xfer, usb_error_t error) 2348 { 2349 struct uath_softc *sc = usbd_xfer_softc(xfer); 2350 struct uath_cmd *cmd; 2351 struct usb_page_cache *pc; 2352 int actlen; 2353 2354 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 2355 2356 UATH_ASSERT_LOCKED(sc); 2357 2358 switch (USB_GET_STATE(xfer)) { 2359 case USB_ST_TRANSFERRED: 2360 cmd = STAILQ_FIRST(&sc->sc_cmd_waiting); 2361 if (cmd == NULL) 2362 goto setup; 2363 STAILQ_REMOVE_HEAD(&sc->sc_cmd_waiting, next); 2364 UATH_STAT_DEC(sc, st_cmd_waiting); 2365 STAILQ_INSERT_TAIL(&sc->sc_cmd_inactive, cmd, next); 2366 UATH_STAT_INC(sc, st_cmd_inactive); 2367 2368 KASSERT(actlen >= (int)sizeof(struct uath_cmd_hdr), 2369 ("short xfer error")); 2370 pc = usbd_xfer_get_frame(xfer, 0); 2371 usbd_copy_out(pc, 0, cmd->buf, actlen); 2372 uath_cmdeof(sc, cmd); 2373 case USB_ST_SETUP: 2374 setup: 2375 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 2376 usbd_transfer_submit(xfer); 2377 break; 2378 default: 2379 if (error != USB_ERR_CANCELLED) { 2380 usbd_xfer_set_stall(xfer); 2381 goto setup; 2382 } 2383 break; 2384 } 2385 } 2386 2387 static void 2388 uath_intr_tx_callback(struct usb_xfer *xfer, usb_error_t error) 2389 { 2390 struct uath_softc *sc = usbd_xfer_softc(xfer); 2391 struct uath_cmd *cmd; 2392 2393 UATH_ASSERT_LOCKED(sc); 2394 2395 cmd = STAILQ_FIRST(&sc->sc_cmd_active); 2396 if (cmd != NULL && USB_GET_STATE(xfer) != USB_ST_SETUP) { 2397 STAILQ_REMOVE_HEAD(&sc->sc_cmd_active, next); 2398 UATH_STAT_DEC(sc, st_cmd_active); 2399 STAILQ_INSERT_TAIL((cmd->flags & UATH_CMD_FLAG_READ) ? 2400 &sc->sc_cmd_waiting : &sc->sc_cmd_inactive, cmd, next); 2401 if (cmd->flags & UATH_CMD_FLAG_READ) 2402 UATH_STAT_INC(sc, st_cmd_waiting); 2403 else 2404 UATH_STAT_INC(sc, st_cmd_inactive); 2405 } 2406 2407 switch (USB_GET_STATE(xfer)) { 2408 case USB_ST_TRANSFERRED: 2409 case USB_ST_SETUP: 2410 setup: 2411 cmd = STAILQ_FIRST(&sc->sc_cmd_pending); 2412 if (cmd == NULL) { 2413 DPRINTF(sc, UATH_DEBUG_XMIT, "%s: empty pending queue\n", 2414 __func__); 2415 return; 2416 } 2417 STAILQ_REMOVE_HEAD(&sc->sc_cmd_pending, next); 2418 UATH_STAT_DEC(sc, st_cmd_pending); 2419 STAILQ_INSERT_TAIL((cmd->flags & UATH_CMD_FLAG_ASYNC) ? 2420 &sc->sc_cmd_inactive : &sc->sc_cmd_active, cmd, next); 2421 if (cmd->flags & UATH_CMD_FLAG_ASYNC) 2422 UATH_STAT_INC(sc, st_cmd_inactive); 2423 else 2424 UATH_STAT_INC(sc, st_cmd_active); 2425 2426 usbd_xfer_set_frame_data(xfer, 0, cmd->buf, cmd->buflen); 2427 usbd_transfer_submit(xfer); 2428 break; 2429 default: 2430 if (error != USB_ERR_CANCELLED) { 2431 usbd_xfer_set_stall(xfer); 2432 goto setup; 2433 } 2434 break; 2435 } 2436 } 2437 2438 static void 2439 uath_update_rxstat(struct uath_softc *sc, uint32_t status) 2440 { 2441 2442 switch (status) { 2443 case UATH_STATUS_STOP_IN_PROGRESS: 2444 UATH_STAT_INC(sc, st_stopinprogress); 2445 break; 2446 case UATH_STATUS_CRC_ERR: 2447 UATH_STAT_INC(sc, st_crcerr); 2448 break; 2449 case UATH_STATUS_PHY_ERR: 2450 UATH_STAT_INC(sc, st_phyerr); 2451 break; 2452 case UATH_STATUS_DECRYPT_CRC_ERR: 2453 UATH_STAT_INC(sc, st_decrypt_crcerr); 2454 break; 2455 case UATH_STATUS_DECRYPT_MIC_ERR: 2456 UATH_STAT_INC(sc, st_decrypt_micerr); 2457 break; 2458 case UATH_STATUS_DECOMP_ERR: 2459 UATH_STAT_INC(sc, st_decomperr); 2460 break; 2461 case UATH_STATUS_KEY_ERR: 2462 UATH_STAT_INC(sc, st_keyerr); 2463 break; 2464 case UATH_STATUS_ERR: 2465 UATH_STAT_INC(sc, st_err); 2466 break; 2467 default: 2468 break; 2469 } 2470 } 2471 2472 static struct mbuf * 2473 uath_data_rxeof(struct usb_xfer *xfer, struct uath_data *data, 2474 struct uath_rx_desc **pdesc) 2475 { 2476 struct uath_softc *sc = usbd_xfer_softc(xfer); 2477 struct ieee80211com *ic = &sc->sc_ic; 2478 struct uath_chunk *chunk; 2479 struct uath_rx_desc *desc; 2480 struct mbuf *m = data->m, *mnew, *mp; 2481 uint16_t chunklen; 2482 int actlen; 2483 2484 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 2485 2486 if (actlen < (int)UATH_MIN_RXBUFSZ) { 2487 DPRINTF(sc, UATH_DEBUG_RECV | UATH_DEBUG_RECV_ALL, 2488 "%s: wrong xfer size (len=%d)\n", __func__, actlen); 2489 counter_u64_add(ic->ic_ierrors, 1); 2490 return (NULL); 2491 } 2492 2493 chunk = (struct uath_chunk *)data->buf; 2494 if (chunk->seqnum == 0 && chunk->flags == 0 && chunk->length == 0) { 2495 device_printf(sc->sc_dev, "%s: strange response\n", __func__); 2496 counter_u64_add(ic->ic_ierrors, 1); 2497 UATH_RESET_INTRX(sc); 2498 return (NULL); 2499 } 2500 2501 if (chunk->seqnum != sc->sc_intrx_nextnum) { 2502 DPRINTF(sc, UATH_DEBUG_XMIT, "invalid seqnum %d, expected %d\n", 2503 chunk->seqnum, sc->sc_intrx_nextnum); 2504 UATH_STAT_INC(sc, st_badchunkseqnum); 2505 if (sc->sc_intrx_head != NULL) 2506 m_freem(sc->sc_intrx_head); 2507 UATH_RESET_INTRX(sc); 2508 return (NULL); 2509 } 2510 2511 /* check multi-chunk frames */ 2512 if ((chunk->seqnum == 0 && !(chunk->flags & UATH_CFLAGS_FINAL)) || 2513 (chunk->seqnum != 0 && (chunk->flags & UATH_CFLAGS_FINAL)) || 2514 chunk->flags & UATH_CFLAGS_RXMSG) 2515 UATH_STAT_INC(sc, st_multichunk); 2516 2517 chunklen = be16toh(chunk->length); 2518 if (chunk->flags & UATH_CFLAGS_FINAL) 2519 chunklen -= sizeof(struct uath_rx_desc); 2520 2521 if (chunklen > 0 && 2522 (!(chunk->flags & UATH_CFLAGS_FINAL) || !(chunk->seqnum == 0))) { 2523 /* we should use intermediate RX buffer */ 2524 if (chunk->seqnum == 0) 2525 UATH_RESET_INTRX(sc); 2526 if ((sc->sc_intrx_len + sizeof(struct uath_rx_desc) + 2527 chunklen) > UATH_MAX_INTRX_SIZE) { 2528 UATH_STAT_INC(sc, st_invalidlen); 2529 counter_u64_add(ic->ic_ierrors, 1); 2530 if (sc->sc_intrx_head != NULL) 2531 m_freem(sc->sc_intrx_head); 2532 UATH_RESET_INTRX(sc); 2533 return (NULL); 2534 } 2535 2536 m->m_len = chunklen; 2537 m->m_data += sizeof(struct uath_chunk); 2538 2539 if (sc->sc_intrx_head == NULL) { 2540 sc->sc_intrx_head = m; 2541 sc->sc_intrx_tail = m; 2542 } else { 2543 m->m_flags &= ~M_PKTHDR; 2544 sc->sc_intrx_tail->m_next = m; 2545 sc->sc_intrx_tail = m; 2546 } 2547 } 2548 sc->sc_intrx_len += chunklen; 2549 2550 mnew = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 2551 if (mnew == NULL) { 2552 DPRINTF(sc, UATH_DEBUG_RECV | UATH_DEBUG_RECV_ALL, 2553 "%s: can't get new mbuf, drop frame\n", __func__); 2554 counter_u64_add(ic->ic_ierrors, 1); 2555 if (sc->sc_intrx_head != NULL) 2556 m_freem(sc->sc_intrx_head); 2557 UATH_RESET_INTRX(sc); 2558 return (NULL); 2559 } 2560 2561 data->m = mnew; 2562 data->buf = mtod(mnew, uint8_t *); 2563 2564 /* if the frame is not final continue the transfer */ 2565 if (!(chunk->flags & UATH_CFLAGS_FINAL)) { 2566 sc->sc_intrx_nextnum++; 2567 UATH_RESET_INTRX(sc); 2568 return (NULL); 2569 } 2570 2571 /* 2572 * if the frame is not set UATH_CFLAGS_RXMSG, then rx descriptor is 2573 * located at the end, 32-bit aligned 2574 */ 2575 desc = (chunk->flags & UATH_CFLAGS_RXMSG) ? 2576 (struct uath_rx_desc *)(chunk + 1) : 2577 (struct uath_rx_desc *)(((uint8_t *)chunk) + 2578 sizeof(struct uath_chunk) + be16toh(chunk->length) - 2579 sizeof(struct uath_rx_desc)); 2580 *pdesc = desc; 2581 2582 DPRINTF(sc, UATH_DEBUG_RECV | UATH_DEBUG_RECV_ALL, 2583 "%s: frame len %u code %u status %u rate %u antenna %u " 2584 "rssi %d channel %u phyerror %u connix %u decrypterror %u " 2585 "keycachemiss %u\n", __func__, be32toh(desc->framelen) 2586 , be32toh(desc->code), be32toh(desc->status), be32toh(desc->rate) 2587 , be32toh(desc->antenna), be32toh(desc->rssi), be32toh(desc->channel) 2588 , be32toh(desc->phyerror), be32toh(desc->connix) 2589 , be32toh(desc->decrypterror), be32toh(desc->keycachemiss)); 2590 2591 if (be32toh(desc->len) > MCLBYTES) { 2592 DPRINTF(sc, UATH_DEBUG_RECV | UATH_DEBUG_RECV_ALL, 2593 "%s: bad descriptor (len=%d)\n", __func__, 2594 be32toh(desc->len)); 2595 counter_u64_add(ic->ic_ierrors, 1); 2596 UATH_STAT_INC(sc, st_toobigrxpkt); 2597 if (sc->sc_intrx_head != NULL) 2598 m_freem(sc->sc_intrx_head); 2599 UATH_RESET_INTRX(sc); 2600 return (NULL); 2601 } 2602 2603 uath_update_rxstat(sc, be32toh(desc->status)); 2604 2605 /* finalize mbuf */ 2606 if (sc->sc_intrx_head == NULL) { 2607 m->m_pkthdr.len = m->m_len = 2608 be32toh(desc->framelen) - UATH_RX_DUMMYSIZE; 2609 m->m_data += sizeof(struct uath_chunk); 2610 } else { 2611 mp = sc->sc_intrx_head; 2612 mp->m_flags |= M_PKTHDR; 2613 mp->m_pkthdr.len = sc->sc_intrx_len; 2614 m = mp; 2615 } 2616 2617 /* there are a lot more fields in the RX descriptor */ 2618 if ((sc->sc_flags & UATH_FLAG_INVALID) == 0 && 2619 ieee80211_radiotap_active(ic)) { 2620 struct uath_rx_radiotap_header *tap = &sc->sc_rxtap; 2621 uint32_t tsf_hi = be32toh(desc->tstamp_high); 2622 uint32_t tsf_lo = be32toh(desc->tstamp_low); 2623 2624 /* XXX only get low order 24bits of tsf from h/w */ 2625 tap->wr_tsf = htole64(((uint64_t)tsf_hi << 32) | tsf_lo); 2626 tap->wr_flags = 0; 2627 if (be32toh(desc->status) == UATH_STATUS_CRC_ERR) 2628 tap->wr_flags |= IEEE80211_RADIOTAP_F_BADFCS; 2629 /* XXX map other status to BADFCS? */ 2630 /* XXX ath h/w rate code, need to map */ 2631 tap->wr_rate = be32toh(desc->rate); 2632 tap->wr_antenna = be32toh(desc->antenna); 2633 tap->wr_antsignal = -95 + be32toh(desc->rssi); 2634 tap->wr_antnoise = -95; 2635 } 2636 2637 UATH_RESET_INTRX(sc); 2638 2639 return (m); 2640 } 2641 2642 static void 2643 uath_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 2644 { 2645 struct uath_softc *sc = usbd_xfer_softc(xfer); 2646 struct ieee80211com *ic = &sc->sc_ic; 2647 struct ieee80211_frame *wh; 2648 struct ieee80211_node *ni; 2649 struct mbuf *m = NULL; 2650 struct uath_data *data; 2651 struct uath_rx_desc *desc = NULL; 2652 int8_t nf; 2653 2654 UATH_ASSERT_LOCKED(sc); 2655 2656 switch (USB_GET_STATE(xfer)) { 2657 case USB_ST_TRANSFERRED: 2658 data = STAILQ_FIRST(&sc->sc_rx_active); 2659 if (data == NULL) 2660 goto setup; 2661 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 2662 UATH_STAT_DEC(sc, st_rx_active); 2663 m = uath_data_rxeof(xfer, data, &desc); 2664 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 2665 UATH_STAT_INC(sc, st_rx_inactive); 2666 /* FALLTHROUGH */ 2667 case USB_ST_SETUP: 2668 setup: 2669 data = STAILQ_FIRST(&sc->sc_rx_inactive); 2670 if (data == NULL) 2671 return; 2672 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 2673 UATH_STAT_DEC(sc, st_rx_inactive); 2674 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 2675 UATH_STAT_INC(sc, st_rx_active); 2676 usbd_xfer_set_frame_data(xfer, 0, data->buf, MCLBYTES); 2677 usbd_transfer_submit(xfer); 2678 2679 /* 2680 * To avoid LOR we should unlock our private mutex here to call 2681 * ieee80211_input() because here is at the end of a USB 2682 * callback and safe to unlock. 2683 */ 2684 if (sc->sc_flags & UATH_FLAG_INVALID) { 2685 if (m != NULL) 2686 m_freem(m); 2687 return; 2688 } 2689 UATH_UNLOCK(sc); 2690 if (m != NULL && desc != NULL) { 2691 wh = mtod(m, struct ieee80211_frame *); 2692 ni = ieee80211_find_rxnode(ic, 2693 (struct ieee80211_frame_min *)wh); 2694 nf = -95; /* XXX */ 2695 if (ni != NULL) { 2696 (void) ieee80211_input(ni, m, 2697 (int)be32toh(desc->rssi), nf); 2698 /* node is no longer needed */ 2699 ieee80211_free_node(ni); 2700 } else 2701 (void) ieee80211_input_all(ic, m, 2702 (int)be32toh(desc->rssi), nf); 2703 m = NULL; 2704 desc = NULL; 2705 } 2706 UATH_LOCK(sc); 2707 uath_start(sc); 2708 break; 2709 default: 2710 /* needs it to the inactive queue due to a error. */ 2711 data = STAILQ_FIRST(&sc->sc_rx_active); 2712 if (data != NULL) { 2713 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 2714 UATH_STAT_DEC(sc, st_rx_active); 2715 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 2716 UATH_STAT_INC(sc, st_rx_inactive); 2717 } 2718 if (error != USB_ERR_CANCELLED) { 2719 usbd_xfer_set_stall(xfer); 2720 counter_u64_add(ic->ic_ierrors, 1); 2721 goto setup; 2722 } 2723 break; 2724 } 2725 } 2726 2727 static void 2728 uath_data_txeof(struct usb_xfer *xfer, struct uath_data *data) 2729 { 2730 struct uath_softc *sc = usbd_xfer_softc(xfer); 2731 2732 UATH_ASSERT_LOCKED(sc); 2733 2734 if (data->m) { 2735 /* XXX status? */ 2736 ieee80211_tx_complete(data->ni, data->m, 0); 2737 data->m = NULL; 2738 data->ni = NULL; 2739 } 2740 sc->sc_tx_timer = 0; 2741 } 2742 2743 static void 2744 uath_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 2745 { 2746 struct uath_softc *sc = usbd_xfer_softc(xfer); 2747 struct uath_data *data; 2748 2749 UATH_ASSERT_LOCKED(sc); 2750 2751 switch (USB_GET_STATE(xfer)) { 2752 case USB_ST_TRANSFERRED: 2753 data = STAILQ_FIRST(&sc->sc_tx_active); 2754 if (data == NULL) 2755 goto setup; 2756 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 2757 UATH_STAT_DEC(sc, st_tx_active); 2758 uath_data_txeof(xfer, data); 2759 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 2760 UATH_STAT_INC(sc, st_tx_inactive); 2761 /* FALLTHROUGH */ 2762 case USB_ST_SETUP: 2763 setup: 2764 data = STAILQ_FIRST(&sc->sc_tx_pending); 2765 if (data == NULL) { 2766 DPRINTF(sc, UATH_DEBUG_XMIT, "%s: empty pending queue\n", 2767 __func__); 2768 return; 2769 } 2770 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 2771 UATH_STAT_DEC(sc, st_tx_pending); 2772 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 2773 UATH_STAT_INC(sc, st_tx_active); 2774 2775 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 2776 usbd_transfer_submit(xfer); 2777 2778 uath_start(sc); 2779 break; 2780 default: 2781 data = STAILQ_FIRST(&sc->sc_tx_active); 2782 if (data == NULL) 2783 goto setup; 2784 if (data->ni != NULL) { 2785 if_inc_counter(data->ni->ni_vap->iv_ifp, 2786 IFCOUNTER_OERRORS, 1); 2787 if ((sc->sc_flags & UATH_FLAG_INVALID) == 0) 2788 ieee80211_free_node(data->ni); 2789 data->ni = NULL; 2790 } 2791 if (error != USB_ERR_CANCELLED) { 2792 usbd_xfer_set_stall(xfer); 2793 goto setup; 2794 } 2795 break; 2796 } 2797 } 2798 2799 static device_method_t uath_methods[] = { 2800 DEVMETHOD(device_probe, uath_match), 2801 DEVMETHOD(device_attach, uath_attach), 2802 DEVMETHOD(device_detach, uath_detach), 2803 DEVMETHOD_END 2804 }; 2805 static driver_t uath_driver = { 2806 .name = "uath", 2807 .methods = uath_methods, 2808 .size = sizeof(struct uath_softc) 2809 }; 2810 static devclass_t uath_devclass; 2811 2812 DRIVER_MODULE(uath, uhub, uath_driver, uath_devclass, NULL, 0); 2813 MODULE_DEPEND(uath, wlan, 1, 1, 1); 2814 MODULE_DEPEND(uath, usb, 1, 1, 1); 2815 MODULE_VERSION(uath, 1); 2816