1 /*- 2 * Copyright (c) 2006 Sam Leffler, Errno Consulting 3 * Copyright (c) 2008-2009 Weongyo Jeong <weongyo@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 13 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 14 * redistribution must be conditioned upon including a substantially 15 * similar Disclaimer requirement for further binary redistribution. 16 * 17 * NO WARRANTY 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 21 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 22 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 23 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 26 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 * THE POSSIBILITY OF SUCH DAMAGES. 29 */ 30 31 /* 32 * This driver is distantly derived from a driver of the same name 33 * by Damien Bergamini. The original copyright is included below: 34 * 35 * Copyright (c) 2006 36 * Damien Bergamini <damien.bergamini@free.fr> 37 * 38 * Permission to use, copy, modify, and distribute this software for any 39 * purpose with or without fee is hereby granted, provided that the above 40 * copyright notice and this permission notice appear in all copies. 41 * 42 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 43 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 44 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 45 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 46 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 47 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 48 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 49 */ 50 51 #include <sys/cdefs.h> 52 __FBSDID("$FreeBSD$"); 53 54 /*- 55 * Driver for Atheros AR5523 USB parts. 56 * 57 * The driver requires firmware to be loaded into the device. This 58 * is done on device discovery from a user application (uathload) 59 * that is launched by devd when a device with suitable product ID 60 * is recognized. Once firmware has been loaded the device will 61 * reset the USB port and re-attach with the original product ID+1 62 * and this driver will be attached. The firmware is licensed for 63 * general use (royalty free) and may be incorporated in products. 64 * Note that the firmware normally packaged with the NDIS drivers 65 * for these devices does not work in this way and so does not work 66 * with this driver. 67 */ 68 #include <sys/param.h> 69 #include <sys/sockio.h> 70 #include <sys/sysctl.h> 71 #include <sys/lock.h> 72 #include <sys/mutex.h> 73 #include <sys/mbuf.h> 74 #include <sys/kernel.h> 75 #include <sys/socket.h> 76 #include <sys/systm.h> 77 #include <sys/malloc.h> 78 #include <sys/module.h> 79 #include <sys/bus.h> 80 #include <sys/endian.h> 81 #include <sys/kdb.h> 82 83 #include <machine/bus.h> 84 #include <machine/resource.h> 85 #include <sys/rman.h> 86 87 #include <net/bpf.h> 88 #include <net/if.h> 89 #include <net/if_arp.h> 90 #include <net/ethernet.h> 91 #include <net/if_dl.h> 92 #include <net/if_media.h> 93 #include <net/if_types.h> 94 95 #ifdef INET 96 #include <netinet/in.h> 97 #include <netinet/in_systm.h> 98 #include <netinet/in_var.h> 99 #include <netinet/if_ether.h> 100 #include <netinet/ip.h> 101 #endif 102 103 #include <net80211/ieee80211_var.h> 104 #include <net80211/ieee80211_regdomain.h> 105 #include <net80211/ieee80211_radiotap.h> 106 107 #include <dev/usb/usb.h> 108 #include <dev/usb/usb_core.h> 109 #include <dev/usb/usb_busdma.h> 110 #include <dev/usb/usb_debug.h> 111 #include <dev/usb/usb_error.h> 112 #include <dev/usb/usb_lookup.h> 113 #include <dev/usb/usb_util.h> 114 #include "usbdevs.h" 115 116 #include <dev/usb/wlan/if_uathreg.h> 117 #include <dev/usb/wlan/if_uathvar.h> 118 119 SYSCTL_NODE(_hw_usb, OID_AUTO, uath, CTLFLAG_RW, 0, "USB Atheros"); 120 121 static int uath_countrycode = CTRY_DEFAULT; /* country code */ 122 SYSCTL_INT(_hw_usb_uath, OID_AUTO, countrycode, CTLFLAG_RW, &uath_countrycode, 123 0, "country code"); 124 TUNABLE_INT("hw.usb.uath.countrycode", &uath_countrycode); 125 static int uath_regdomain = 0; /* regulatory domain */ 126 SYSCTL_INT(_hw_usb_uath, OID_AUTO, regdomain, CTLFLAG_RD, &uath_regdomain, 127 0, "regulatory domain"); 128 129 #ifdef UATH_DEBUG 130 int uath_debug = 0; 131 SYSCTL_INT(_hw_usb_uath, OID_AUTO, debug, CTLFLAG_RW, &uath_debug, 0, 132 "uath debug level"); 133 TUNABLE_INT("hw.usb.uath.debug", &uath_debug); 134 enum { 135 UATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 136 UATH_DEBUG_XMIT_DUMP = 0x00000002, /* xmit dump */ 137 UATH_DEBUG_RECV = 0x00000004, /* basic recv operation */ 138 UATH_DEBUG_TX_PROC = 0x00000008, /* tx ISR proc */ 139 UATH_DEBUG_RX_PROC = 0x00000010, /* rx ISR proc */ 140 UATH_DEBUG_RECV_ALL = 0x00000020, /* trace all frames (beacons) */ 141 UATH_DEBUG_INIT = 0x00000040, /* initialization of dev */ 142 UATH_DEBUG_DEVCAP = 0x00000080, /* dev caps */ 143 UATH_DEBUG_CMDS = 0x00000100, /* commands */ 144 UATH_DEBUG_CMDS_DUMP = 0x00000200, /* command buffer dump */ 145 UATH_DEBUG_RESET = 0x00000400, /* reset processing */ 146 UATH_DEBUG_STATE = 0x00000800, /* 802.11 state transitions */ 147 UATH_DEBUG_MULTICAST = 0x00001000, /* multicast */ 148 UATH_DEBUG_WME = 0x00002000, /* WME */ 149 UATH_DEBUG_CHANNEL = 0x00004000, /* channel */ 150 UATH_DEBUG_RATES = 0x00008000, /* rates */ 151 UATH_DEBUG_CRYPTO = 0x00010000, /* crypto */ 152 UATH_DEBUG_LED = 0x00020000, /* LED */ 153 UATH_DEBUG_ANY = 0xffffffff 154 }; 155 #define DPRINTF(sc, m, fmt, ...) do { \ 156 if (sc->sc_debug & (m)) \ 157 printf(fmt, __VA_ARGS__); \ 158 } while (0) 159 #else 160 #define DPRINTF(sc, m, fmt, ...) do { \ 161 (void) sc; \ 162 } while (0) 163 #endif 164 165 /* unaligned little endian access */ 166 #define LE_READ_2(p) \ 167 ((u_int16_t) \ 168 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8))) 169 #define LE_READ_4(p) \ 170 ((u_int32_t) \ 171 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \ 172 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24))) 173 174 /* recognized device vendors/products */ 175 static const struct usb_device_id uath_devs[] = { 176 #define UATH_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 177 UATH_DEV(ACCTON, SMCWUSBG), 178 UATH_DEV(ACCTON, SMCWUSBTG2), 179 UATH_DEV(ATHEROS, AR5523), 180 UATH_DEV(ATHEROS2, AR5523_1), 181 UATH_DEV(ATHEROS2, AR5523_2), 182 UATH_DEV(ATHEROS2, AR5523_3), 183 UATH_DEV(CONCEPTRONIC, AR5523_1), 184 UATH_DEV(CONCEPTRONIC, AR5523_2), 185 UATH_DEV(DLINK, DWLAG122), 186 UATH_DEV(DLINK, DWLAG132), 187 UATH_DEV(DLINK, DWLG132), 188 UATH_DEV(GIGASET, AR5523), 189 UATH_DEV(GIGASET, SMCWUSBTG), 190 UATH_DEV(GLOBALSUN, AR5523_1), 191 UATH_DEV(GLOBALSUN, AR5523_2), 192 UATH_DEV(NETGEAR, WG111U), 193 UATH_DEV(NETGEAR3, WG111T), 194 UATH_DEV(NETGEAR3, WPN111), 195 UATH_DEV(UMEDIA, TEW444UBEU), 196 UATH_DEV(UMEDIA, AR5523_2), 197 UATH_DEV(UMEDIA, AR5523_3), 198 UATH_DEV(WISTRONNEWEB, AR5523_1), 199 UATH_DEV(WISTRONNEWEB, AR5523_2), 200 UATH_DEV(ZCOM, AR5523) 201 #undef UATH_DEV 202 }; 203 204 static usb_callback_t uath_intr_rx_callback; 205 static usb_callback_t uath_intr_tx_callback; 206 static usb_callback_t uath_bulk_rx_callback; 207 static usb_callback_t uath_bulk_tx_callback; 208 209 static const struct usb_config uath_usbconfig[UATH_N_XFERS] = { 210 [UATH_INTR_RX] = { 211 .type = UE_BULK, 212 .endpoint = 0x1, 213 .direction = UE_DIR_IN, 214 .bufsize = UATH_MAX_CMDSZ, 215 .flags = { 216 .pipe_bof = 1, 217 .short_xfer_ok = 1 218 }, 219 .callback = uath_intr_rx_callback 220 }, 221 [UATH_INTR_TX] = { 222 .type = UE_BULK, 223 .endpoint = 0x1, 224 .direction = UE_DIR_OUT, 225 .bufsize = UATH_MAX_CMDSZ, 226 .flags = { 227 .ext_buffer = 1, 228 .force_short_xfer = 1, 229 .pipe_bof = 1, 230 }, 231 .callback = uath_intr_tx_callback, 232 .timeout = UATH_CMD_TIMEOUT 233 }, 234 [UATH_BULK_RX] = { 235 .type = UE_BULK, 236 .endpoint = 0x2, 237 .direction = UE_DIR_IN, 238 .bufsize = MCLBYTES, 239 .flags = { 240 .ext_buffer = 1, 241 .pipe_bof = 1, 242 .short_xfer_ok = 1 243 }, 244 .callback = uath_bulk_rx_callback 245 }, 246 [UATH_BULK_TX] = { 247 .type = UE_BULK, 248 .endpoint = 0x2, 249 .direction = UE_DIR_OUT, 250 .bufsize = UATH_MAX_TXBUFSZ, 251 .flags = { 252 .ext_buffer = 1, 253 .force_short_xfer = 1, 254 .pipe_bof = 1 255 }, 256 .callback = uath_bulk_tx_callback, 257 .timeout = UATH_DATA_TIMEOUT 258 } 259 }; 260 261 static struct ieee80211vap *uath_vap_create(struct ieee80211com *, 262 const char name[IFNAMSIZ], int unit, int opmode, 263 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN], 264 const uint8_t mac[IEEE80211_ADDR_LEN]); 265 static void uath_vap_delete(struct ieee80211vap *); 266 static int uath_alloc_cmd_list(struct uath_softc *, struct uath_cmd [], 267 int, int); 268 static void uath_free_cmd_list(struct uath_softc *, struct uath_cmd [], 269 int); 270 static int uath_host_available(struct uath_softc *); 271 static int uath_get_capability(struct uath_softc *, uint32_t, uint32_t *); 272 static int uath_get_devcap(struct uath_softc *); 273 static struct uath_cmd * 274 uath_get_cmdbuf(struct uath_softc *); 275 static int uath_cmd_read(struct uath_softc *, uint32_t, const void *, 276 int, void *, int, int); 277 static int uath_cmd_write(struct uath_softc *, uint32_t, const void *, 278 int, int); 279 static void uath_stat(void *); 280 #ifdef UATH_DEBUG 281 static void uath_dump_cmd(const uint8_t *, int, char); 282 static const char * 283 uath_codename(int); 284 #endif 285 static int uath_get_devstatus(struct uath_softc *, 286 uint8_t macaddr[IEEE80211_ADDR_LEN]); 287 static int uath_get_status(struct uath_softc *, uint32_t, void *, int); 288 static int uath_alloc_rx_data_list(struct uath_softc *); 289 static int uath_alloc_tx_data_list(struct uath_softc *); 290 static void uath_free_rx_data_list(struct uath_softc *); 291 static void uath_free_tx_data_list(struct uath_softc *); 292 static int uath_init_locked(void *); 293 static void uath_init(void *); 294 static void uath_stop_locked(struct ifnet *); 295 static void uath_stop(struct ifnet *); 296 static int uath_ioctl(struct ifnet *, u_long, caddr_t); 297 static void uath_start(struct ifnet *); 298 static int uath_raw_xmit(struct ieee80211_node *, struct mbuf *, 299 const struct ieee80211_bpf_params *); 300 static void uath_scan_start(struct ieee80211com *); 301 static void uath_scan_end(struct ieee80211com *); 302 static void uath_set_channel(struct ieee80211com *); 303 static void uath_update_mcast(struct ifnet *); 304 static void uath_update_promisc(struct ifnet *); 305 static int uath_config(struct uath_softc *, uint32_t, uint32_t); 306 static int uath_config_multi(struct uath_softc *, uint32_t, const void *, 307 int); 308 static int uath_switch_channel(struct uath_softc *, 309 struct ieee80211_channel *); 310 static int uath_set_rxfilter(struct uath_softc *, uint32_t, uint32_t); 311 static void uath_watchdog(void *); 312 static void uath_abort_xfers(struct uath_softc *); 313 static int uath_dataflush(struct uath_softc *); 314 static int uath_cmdflush(struct uath_softc *); 315 static int uath_flush(struct uath_softc *); 316 static int uath_set_ledstate(struct uath_softc *, int); 317 static int uath_set_chan(struct uath_softc *, struct ieee80211_channel *); 318 static int uath_reset_tx_queues(struct uath_softc *); 319 static int uath_wme_init(struct uath_softc *); 320 static struct uath_data * 321 uath_getbuf(struct uath_softc *); 322 static int uath_newstate(struct ieee80211vap *, enum ieee80211_state, 323 int); 324 static int uath_set_key(struct uath_softc *, 325 const struct ieee80211_key *, int); 326 static int uath_set_keys(struct uath_softc *, struct ieee80211vap *); 327 static void uath_sysctl_node(struct uath_softc *); 328 329 static int 330 uath_match(device_t dev) 331 { 332 struct usb_attach_arg *uaa = device_get_ivars(dev); 333 334 if (uaa->usb_mode != USB_MODE_HOST) 335 return (ENXIO); 336 if (uaa->info.bConfigIndex != UATH_CONFIG_INDEX) 337 return (ENXIO); 338 if (uaa->info.bIfaceIndex != UATH_IFACE_INDEX) 339 return (ENXIO); 340 341 return (usbd_lookup_id_by_uaa(uath_devs, sizeof(uath_devs), uaa)); 342 } 343 344 static int 345 uath_attach(device_t dev) 346 { 347 struct uath_softc *sc = device_get_softc(dev); 348 struct usb_attach_arg *uaa = device_get_ivars(dev); 349 struct ieee80211com *ic; 350 struct ifnet *ifp; 351 uint8_t bands, iface_index = UATH_IFACE_INDEX; /* XXX */ 352 usb_error_t error; 353 uint8_t macaddr[IEEE80211_ADDR_LEN]; 354 355 sc->sc_dev = dev; 356 sc->sc_udev = uaa->device; 357 #ifdef UATH_DEBUG 358 sc->sc_debug = uath_debug; 359 #endif 360 device_set_usb_desc(dev); 361 362 /* 363 * Only post-firmware devices here. 364 */ 365 mtx_init(&sc->sc_mtx, device_get_nameunit(sc->sc_dev), MTX_NETWORK_LOCK, 366 MTX_DEF); 367 callout_init(&sc->stat_ch, 0); 368 callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0); 369 370 /* 371 * Allocate xfers for firmware commands. 372 */ 373 error = uath_alloc_cmd_list(sc, sc->sc_cmd, UATH_CMD_LIST_COUNT, 374 UATH_MAX_CMDSZ); 375 if (error != 0) { 376 device_printf(sc->sc_dev, 377 "could not allocate Tx command list\n"); 378 goto fail; 379 } 380 381 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 382 uath_usbconfig, UATH_N_XFERS, sc, &sc->sc_mtx); 383 if (error) { 384 device_printf(dev, "could not allocate USB transfers, " 385 "err=%s\n", usbd_errstr(error)); 386 goto fail1; 387 } 388 389 /* 390 * We're now ready to send+receive firmware commands. 391 */ 392 UATH_LOCK(sc); 393 error = uath_host_available(sc); 394 if (error != 0) { 395 device_printf(sc->sc_dev, "could not initialize adapter\n"); 396 goto fail3; 397 } 398 error = uath_get_devcap(sc); 399 if (error != 0) { 400 device_printf(sc->sc_dev, 401 "could not get device capabilities\n"); 402 goto fail3; 403 } 404 UATH_UNLOCK(sc); 405 406 /* Create device sysctl node. */ 407 uath_sysctl_node(sc); 408 409 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 410 if (ifp == NULL) { 411 device_printf(sc->sc_dev, "can not allocate ifnet\n"); 412 error = ENXIO; 413 goto fail2; 414 } 415 416 UATH_LOCK(sc); 417 error = uath_get_devstatus(sc, macaddr); 418 if (error != 0) { 419 device_printf(sc->sc_dev, "could not get device status\n"); 420 goto fail4; 421 } 422 423 /* 424 * Allocate xfers for Rx/Tx data pipes. 425 */ 426 error = uath_alloc_rx_data_list(sc); 427 if (error != 0) { 428 device_printf(sc->sc_dev, "could not allocate Rx data list\n"); 429 goto fail4; 430 } 431 error = uath_alloc_tx_data_list(sc); 432 if (error != 0) { 433 device_printf(sc->sc_dev, "could not allocate Tx data list\n"); 434 goto fail4; 435 } 436 UATH_UNLOCK(sc); 437 438 ifp->if_softc = sc; 439 if_initname(ifp, "uath", device_get_unit(sc->sc_dev)); 440 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 441 ifp->if_init = uath_init; 442 ifp->if_ioctl = uath_ioctl; 443 ifp->if_start = uath_start; 444 /* XXX UATH_TX_DATA_LIST_COUNT */ 445 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 446 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 447 IFQ_SET_READY(&ifp->if_snd); 448 449 ic = ifp->if_l2com; 450 ic->ic_ifp = ifp; 451 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 452 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 453 454 /* set device capabilities */ 455 ic->ic_caps = 456 IEEE80211_C_STA | /* station mode */ 457 IEEE80211_C_MONITOR | /* monitor mode supported */ 458 IEEE80211_C_TXPMGT | /* tx power management */ 459 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 460 IEEE80211_C_SHSLOT | /* short slot time supported */ 461 IEEE80211_C_WPA | /* 802.11i */ 462 IEEE80211_C_BGSCAN | /* capable of bg scanning */ 463 IEEE80211_C_TXFRAG; /* handle tx frags */ 464 465 /* put a regulatory domain to reveal informations. */ 466 uath_regdomain = sc->sc_devcap.regDomain; 467 468 bands = 0; 469 setbit(&bands, IEEE80211_MODE_11B); 470 setbit(&bands, IEEE80211_MODE_11G); 471 if ((sc->sc_devcap.analog5GhzRevision & 0xf0) == 0x30) 472 setbit(&bands, IEEE80211_MODE_11A); 473 /* XXX turbo */ 474 ieee80211_init_channels(ic, NULL, &bands); 475 476 ieee80211_ifattach(ic, macaddr); 477 ic->ic_raw_xmit = uath_raw_xmit; 478 ic->ic_scan_start = uath_scan_start; 479 ic->ic_scan_end = uath_scan_end; 480 ic->ic_set_channel = uath_set_channel; 481 482 ic->ic_vap_create = uath_vap_create; 483 ic->ic_vap_delete = uath_vap_delete; 484 ic->ic_update_mcast = uath_update_mcast; 485 ic->ic_update_promisc = uath_update_promisc; 486 487 ieee80211_radiotap_attach(ic, 488 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 489 UATH_TX_RADIOTAP_PRESENT, 490 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 491 UATH_RX_RADIOTAP_PRESENT); 492 493 if (bootverbose) 494 ieee80211_announce(ic); 495 496 return (0); 497 498 fail4: if_free(ifp); 499 fail3: UATH_UNLOCK(sc); 500 fail2: usbd_transfer_unsetup(sc->sc_xfer, UATH_N_XFERS); 501 fail1: uath_free_cmd_list(sc, sc->sc_cmd, UATH_CMD_LIST_COUNT); 502 fail: 503 return (error); 504 } 505 506 static int 507 uath_detach(device_t dev) 508 { 509 struct uath_softc *sc = device_get_softc(dev); 510 struct ifnet *ifp = sc->sc_ifp; 511 struct ieee80211com *ic = ifp->if_l2com; 512 513 if (!device_is_attached(dev)) 514 return (0); 515 516 UATH_LOCK(sc); 517 sc->sc_flags |= UATH_FLAG_INVALID; 518 UATH_UNLOCK(sc); 519 520 ieee80211_ifdetach(ic); 521 uath_stop(ifp); 522 523 callout_drain(&sc->stat_ch); 524 callout_drain(&sc->watchdog_ch); 525 526 usbd_transfer_unsetup(sc->sc_xfer, UATH_N_XFERS); 527 528 /* free buffers */ 529 UATH_LOCK(sc); 530 uath_free_rx_data_list(sc); 531 uath_free_tx_data_list(sc); 532 uath_free_cmd_list(sc, sc->sc_cmd, UATH_CMD_LIST_COUNT); 533 UATH_UNLOCK(sc); 534 535 if_free(ifp); 536 mtx_destroy(&sc->sc_mtx); 537 return (0); 538 } 539 540 static void 541 uath_free_cmd_list(struct uath_softc *sc, struct uath_cmd cmds[], int ncmd) 542 { 543 int i; 544 545 for (i = 0; i < ncmd; i++) 546 if (cmds[i].buf != NULL) 547 free(cmds[i].buf, M_USBDEV); 548 } 549 550 static int 551 uath_alloc_cmd_list(struct uath_softc *sc, struct uath_cmd cmds[], 552 int ncmd, int maxsz) 553 { 554 int i, error; 555 556 STAILQ_INIT(&sc->sc_cmd_active); 557 STAILQ_INIT(&sc->sc_cmd_pending); 558 STAILQ_INIT(&sc->sc_cmd_waiting); 559 STAILQ_INIT(&sc->sc_cmd_inactive); 560 561 for (i = 0; i < ncmd; i++) { 562 struct uath_cmd *cmd = &cmds[i]; 563 564 cmd->sc = sc; /* backpointer for callbacks */ 565 cmd->msgid = i; 566 cmd->buf = malloc(maxsz, M_USBDEV, M_NOWAIT); 567 if (cmd->buf == NULL) { 568 device_printf(sc->sc_dev, 569 "could not allocate xfer buffer\n"); 570 error = ENOMEM; 571 goto fail; 572 } 573 STAILQ_INSERT_TAIL(&sc->sc_cmd_inactive, cmd, next); 574 UATH_STAT_INC(sc, st_cmd_inactive); 575 } 576 return (0); 577 578 fail: uath_free_cmd_list(sc, cmds, ncmd); 579 return (error); 580 } 581 582 static int 583 uath_host_available(struct uath_softc *sc) 584 { 585 struct uath_cmd_host_available setup; 586 587 UATH_ASSERT_LOCKED(sc); 588 589 /* inform target the host is available */ 590 setup.sw_ver_major = htobe32(ATH_SW_VER_MAJOR); 591 setup.sw_ver_minor = htobe32(ATH_SW_VER_MINOR); 592 setup.sw_ver_patch = htobe32(ATH_SW_VER_PATCH); 593 setup.sw_ver_build = htobe32(ATH_SW_VER_BUILD); 594 return uath_cmd_read(sc, WDCMSG_HOST_AVAILABLE, 595 &setup, sizeof setup, NULL, 0, 0); 596 } 597 598 #ifdef UATH_DEBUG 599 static void 600 uath_dump_cmd(const uint8_t *buf, int len, char prefix) 601 { 602 const char *sep = ""; 603 int i; 604 605 for (i = 0; i < len; i++) { 606 if ((i % 16) == 0) { 607 printf("%s%c ", sep, prefix); 608 sep = "\n"; 609 } 610 else if ((i % 4) == 0) 611 printf(" "); 612 printf("%02x", buf[i]); 613 } 614 printf("\n"); 615 } 616 617 static const char * 618 uath_codename(int code) 619 { 620 #define N(a) (sizeof(a)/sizeof(a[0])) 621 static const char *names[] = { 622 "0x00", 623 "HOST_AVAILABLE", 624 "BIND", 625 "TARGET_RESET", 626 "TARGET_GET_CAPABILITY", 627 "TARGET_SET_CONFIG", 628 "TARGET_GET_STATUS", 629 "TARGET_GET_STATS", 630 "TARGET_START", 631 "TARGET_STOP", 632 "TARGET_ENABLE", 633 "TARGET_DISABLE", 634 "CREATE_CONNECTION", 635 "UPDATE_CONNECT_ATTR", 636 "DELETE_CONNECT", 637 "SEND", 638 "FLUSH", 639 "STATS_UPDATE", 640 "BMISS", 641 "DEVICE_AVAIL", 642 "SEND_COMPLETE", 643 "DATA_AVAIL", 644 "SET_PWR_MODE", 645 "BMISS_ACK", 646 "SET_LED_STEADY", 647 "SET_LED_BLINK", 648 "SETUP_BEACON_DESC", 649 "BEACON_INIT", 650 "RESET_KEY_CACHE", 651 "RESET_KEY_CACHE_ENTRY", 652 "SET_KEY_CACHE_ENTRY", 653 "SET_DECOMP_MASK", 654 "SET_REGULATORY_DOMAIN", 655 "SET_LED_STATE", 656 "WRITE_ASSOCID", 657 "SET_STA_BEACON_TIMERS", 658 "GET_TSF", 659 "RESET_TSF", 660 "SET_ADHOC_MODE", 661 "SET_BASIC_RATE", 662 "MIB_CONTROL", 663 "GET_CHANNEL_DATA", 664 "GET_CUR_RSSI", 665 "SET_ANTENNA_SWITCH", 666 "0x2c", "0x2d", "0x2e", 667 "USE_SHORT_SLOT_TIME", 668 "SET_POWER_MODE", 669 "SETUP_PSPOLL_DESC", 670 "SET_RX_MULTICAST_FILTER", 671 "RX_FILTER", 672 "PER_CALIBRATION", 673 "RESET", 674 "DISABLE", 675 "PHY_DISABLE", 676 "SET_TX_POWER_LIMIT", 677 "SET_TX_QUEUE_PARAMS", 678 "SETUP_TX_QUEUE", 679 "RELEASE_TX_QUEUE", 680 }; 681 static char buf[8]; 682 683 if (code < N(names)) 684 return names[code]; 685 if (code == WDCMSG_SET_DEFAULT_KEY) 686 return "SET_DEFAULT_KEY"; 687 snprintf(buf, sizeof(buf), "0x%02x", code); 688 return buf; 689 #undef N 690 } 691 #endif 692 693 /* 694 * Low-level function to send read or write commands to the firmware. 695 */ 696 static int 697 uath_cmdsend(struct uath_softc *sc, uint32_t code, const void *idata, int ilen, 698 void *odata, int olen, int flags) 699 { 700 struct uath_cmd_hdr *hdr; 701 struct uath_cmd *cmd; 702 int error; 703 704 UATH_ASSERT_LOCKED(sc); 705 706 /* grab a xfer */ 707 cmd = uath_get_cmdbuf(sc); 708 if (cmd == NULL) { 709 device_printf(sc->sc_dev, "%s: empty inactive queue\n", 710 __func__); 711 return (ENOBUFS); 712 } 713 cmd->flags = flags; 714 /* always bulk-out a multiple of 4 bytes */ 715 cmd->buflen = roundup2(sizeof(struct uath_cmd_hdr) + ilen, 4); 716 717 hdr = (struct uath_cmd_hdr *)cmd->buf; 718 bzero(hdr, sizeof (struct uath_cmd_hdr)); /* XXX not needed */ 719 hdr->len = htobe32(cmd->buflen); 720 hdr->code = htobe32(code); 721 hdr->msgid = cmd->msgid; /* don't care about endianness */ 722 hdr->magic = htobe32((cmd->flags & UATH_CMD_FLAG_MAGIC) ? 1 << 24 : 0); 723 bcopy(idata, (uint8_t *)(hdr + 1), ilen); 724 725 #ifdef UATH_DEBUG 726 if (sc->sc_debug & UATH_DEBUG_CMDS) { 727 printf("%s: send %s [flags 0x%x] olen %d\n", 728 __func__, uath_codename(code), cmd->flags, olen); 729 if (sc->sc_debug & UATH_DEBUG_CMDS_DUMP) 730 uath_dump_cmd(cmd->buf, cmd->buflen, '+'); 731 } 732 #endif 733 cmd->odata = odata; 734 KASSERT(odata == NULL || 735 olen < UATH_MAX_CMDSZ - sizeof(*hdr) + sizeof(uint32_t), 736 ("odata %p olen %u", odata, olen)); 737 cmd->olen = olen; 738 739 STAILQ_INSERT_TAIL(&sc->sc_cmd_pending, cmd, next); 740 UATH_STAT_INC(sc, st_cmd_pending); 741 usbd_transfer_start(sc->sc_xfer[UATH_INTR_TX]); 742 743 if (cmd->flags & UATH_CMD_FLAG_READ) { 744 usbd_transfer_start(sc->sc_xfer[UATH_INTR_RX]); 745 746 /* wait at most two seconds for command reply */ 747 error = mtx_sleep(cmd, &sc->sc_mtx, 0, "uathcmd", 2 * hz); 748 cmd->odata = NULL; /* in case reply comes too late */ 749 if (error != 0) { 750 device_printf(sc->sc_dev, "timeout waiting for reply " 751 "to cmd 0x%x (%u)\n", code, code); 752 } else if (cmd->olen != olen) { 753 device_printf(sc->sc_dev, "unexpected reply data count " 754 "to cmd 0x%x (%u), got %u, expected %u\n", 755 code, code, cmd->olen, olen); 756 error = EINVAL; 757 } 758 return (error); 759 } 760 return (0); 761 } 762 763 static int 764 uath_cmd_read(struct uath_softc *sc, uint32_t code, const void *idata, 765 int ilen, void *odata, int olen, int flags) 766 { 767 768 flags |= UATH_CMD_FLAG_READ; 769 return uath_cmdsend(sc, code, idata, ilen, odata, olen, flags); 770 } 771 772 static int 773 uath_cmd_write(struct uath_softc *sc, uint32_t code, const void *data, int len, 774 int flags) 775 { 776 777 flags &= ~UATH_CMD_FLAG_READ; 778 return uath_cmdsend(sc, code, data, len, NULL, 0, flags); 779 } 780 781 static struct uath_cmd * 782 uath_get_cmdbuf(struct uath_softc *sc) 783 { 784 struct uath_cmd *uc; 785 786 UATH_ASSERT_LOCKED(sc); 787 788 uc = STAILQ_FIRST(&sc->sc_cmd_inactive); 789 if (uc != NULL) { 790 STAILQ_REMOVE_HEAD(&sc->sc_cmd_inactive, next); 791 UATH_STAT_DEC(sc, st_cmd_inactive); 792 } else 793 uc = NULL; 794 if (uc == NULL) 795 DPRINTF(sc, UATH_DEBUG_XMIT, "%s: %s\n", __func__, 796 "out of command xmit buffers"); 797 return (uc); 798 } 799 800 /* 801 * This function is called periodically (every second) when associated to 802 * query device statistics. 803 */ 804 static void 805 uath_stat(void *arg) 806 { 807 struct uath_softc *sc = arg; 808 int error; 809 810 UATH_LOCK(sc); 811 /* 812 * Send request for statistics asynchronously. The timer will be 813 * restarted when we'll get the stats notification. 814 */ 815 error = uath_cmd_write(sc, WDCMSG_TARGET_GET_STATS, NULL, 0, 816 UATH_CMD_FLAG_ASYNC); 817 if (error != 0) { 818 device_printf(sc->sc_dev, 819 "could not query stats, error %d\n", error); 820 } 821 UATH_UNLOCK(sc); 822 } 823 824 static int 825 uath_get_capability(struct uath_softc *sc, uint32_t cap, uint32_t *val) 826 { 827 int error; 828 829 cap = htobe32(cap); 830 error = uath_cmd_read(sc, WDCMSG_TARGET_GET_CAPABILITY, 831 &cap, sizeof cap, val, sizeof(uint32_t), UATH_CMD_FLAG_MAGIC); 832 if (error != 0) { 833 device_printf(sc->sc_dev, "could not read capability %u\n", 834 be32toh(cap)); 835 return (error); 836 } 837 *val = be32toh(*val); 838 return (error); 839 } 840 841 static int 842 uath_get_devcap(struct uath_softc *sc) 843 { 844 #define GETCAP(x, v) do { \ 845 error = uath_get_capability(sc, x, &v); \ 846 if (error != 0) \ 847 return (error); \ 848 DPRINTF(sc, UATH_DEBUG_DEVCAP, \ 849 "%s: %s=0x%08x\n", __func__, #x, v); \ 850 } while (0) 851 struct uath_devcap *cap = &sc->sc_devcap; 852 int error; 853 854 /* collect device capabilities */ 855 GETCAP(CAP_TARGET_VERSION, cap->targetVersion); 856 GETCAP(CAP_TARGET_REVISION, cap->targetRevision); 857 GETCAP(CAP_MAC_VERSION, cap->macVersion); 858 GETCAP(CAP_MAC_REVISION, cap->macRevision); 859 GETCAP(CAP_PHY_REVISION, cap->phyRevision); 860 GETCAP(CAP_ANALOG_5GHz_REVISION, cap->analog5GhzRevision); 861 GETCAP(CAP_ANALOG_2GHz_REVISION, cap->analog2GhzRevision); 862 863 GETCAP(CAP_REG_DOMAIN, cap->regDomain); 864 GETCAP(CAP_REG_CAP_BITS, cap->regCapBits); 865 #if 0 866 /* NB: not supported in rev 1.5 */ 867 GETCAP(CAP_COUNTRY_CODE, cap->countryCode); 868 #endif 869 GETCAP(CAP_WIRELESS_MODES, cap->wirelessModes); 870 GETCAP(CAP_CHAN_SPREAD_SUPPORT, cap->chanSpreadSupport); 871 GETCAP(CAP_COMPRESS_SUPPORT, cap->compressSupport); 872 GETCAP(CAP_BURST_SUPPORT, cap->burstSupport); 873 GETCAP(CAP_FAST_FRAMES_SUPPORT, cap->fastFramesSupport); 874 GETCAP(CAP_CHAP_TUNING_SUPPORT, cap->chapTuningSupport); 875 GETCAP(CAP_TURBOG_SUPPORT, cap->turboGSupport); 876 GETCAP(CAP_TURBO_PRIME_SUPPORT, cap->turboPrimeSupport); 877 GETCAP(CAP_DEVICE_TYPE, cap->deviceType); 878 GETCAP(CAP_WME_SUPPORT, cap->wmeSupport); 879 GETCAP(CAP_TOTAL_QUEUES, cap->numTxQueues); 880 GETCAP(CAP_CONNECTION_ID_MAX, cap->connectionIdMax); 881 882 GETCAP(CAP_LOW_5GHZ_CHAN, cap->low5GhzChan); 883 GETCAP(CAP_HIGH_5GHZ_CHAN, cap->high5GhzChan); 884 GETCAP(CAP_LOW_2GHZ_CHAN, cap->low2GhzChan); 885 GETCAP(CAP_HIGH_2GHZ_CHAN, cap->high2GhzChan); 886 GETCAP(CAP_TWICE_ANTENNAGAIN_5G, cap->twiceAntennaGain5G); 887 GETCAP(CAP_TWICE_ANTENNAGAIN_2G, cap->twiceAntennaGain2G); 888 889 GETCAP(CAP_CIPHER_AES_CCM, cap->supportCipherAES_CCM); 890 GETCAP(CAP_CIPHER_TKIP, cap->supportCipherTKIP); 891 GETCAP(CAP_MIC_TKIP, cap->supportMicTKIP); 892 893 cap->supportCipherWEP = 1; /* NB: always available */ 894 895 return (0); 896 } 897 898 static int 899 uath_get_devstatus(struct uath_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 900 { 901 int error; 902 903 /* retrieve MAC address */ 904 error = uath_get_status(sc, ST_MAC_ADDR, macaddr, IEEE80211_ADDR_LEN); 905 if (error != 0) { 906 device_printf(sc->sc_dev, "could not read MAC address\n"); 907 return (error); 908 } 909 910 error = uath_get_status(sc, ST_SERIAL_NUMBER, 911 &sc->sc_serial[0], sizeof(sc->sc_serial)); 912 if (error != 0) { 913 device_printf(sc->sc_dev, 914 "could not read device serial number\n"); 915 return (error); 916 } 917 return (0); 918 } 919 920 static int 921 uath_get_status(struct uath_softc *sc, uint32_t which, void *odata, int olen) 922 { 923 int error; 924 925 which = htobe32(which); 926 error = uath_cmd_read(sc, WDCMSG_TARGET_GET_STATUS, 927 &which, sizeof(which), odata, olen, UATH_CMD_FLAG_MAGIC); 928 if (error != 0) 929 device_printf(sc->sc_dev, 930 "could not read EEPROM offset 0x%02x\n", be32toh(which)); 931 return (error); 932 } 933 934 static void 935 uath_free_data_list(struct uath_softc *sc, struct uath_data data[], int ndata, 936 int fillmbuf) 937 { 938 int i; 939 940 for (i = 0; i < ndata; i++) { 941 struct uath_data *dp = &data[i]; 942 943 if (fillmbuf == 1) { 944 if (dp->m != NULL) { 945 m_freem(dp->m); 946 dp->m = NULL; 947 dp->buf = NULL; 948 } 949 } else { 950 if (dp->buf != NULL) { 951 free(dp->buf, M_USBDEV); 952 dp->buf = NULL; 953 } 954 } 955 #ifdef UATH_DEBUG 956 if (dp->ni != NULL) 957 device_printf(sc->sc_dev, "Node isn't NULL\n"); 958 #endif 959 } 960 } 961 962 static int 963 uath_alloc_data_list(struct uath_softc *sc, struct uath_data data[], 964 int ndata, int maxsz, int fillmbuf) 965 { 966 int i, error; 967 968 for (i = 0; i < ndata; i++) { 969 struct uath_data *dp = &data[i]; 970 971 dp->sc = sc; 972 if (fillmbuf) { 973 /* XXX check maxsz */ 974 dp->m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 975 if (dp->m == NULL) { 976 device_printf(sc->sc_dev, 977 "could not allocate rx mbuf\n"); 978 error = ENOMEM; 979 goto fail; 980 } 981 dp->buf = mtod(dp->m, uint8_t *); 982 } else { 983 dp->m = NULL; 984 dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT); 985 if (dp->buf == NULL) { 986 device_printf(sc->sc_dev, 987 "could not allocate buffer\n"); 988 error = ENOMEM; 989 goto fail; 990 } 991 } 992 dp->ni = NULL; 993 } 994 995 return (0); 996 997 fail: uath_free_data_list(sc, data, ndata, fillmbuf); 998 return (error); 999 } 1000 1001 static int 1002 uath_alloc_rx_data_list(struct uath_softc *sc) 1003 { 1004 int error, i; 1005 1006 /* XXX is it enough to store the RX packet with MCLBYTES bytes? */ 1007 error = uath_alloc_data_list(sc, 1008 sc->sc_rx, UATH_RX_DATA_LIST_COUNT, MCLBYTES, 1009 1 /* setup mbufs */); 1010 if (error != 0) 1011 return (error); 1012 1013 STAILQ_INIT(&sc->sc_rx_active); 1014 STAILQ_INIT(&sc->sc_rx_inactive); 1015 1016 for (i = 0; i < UATH_RX_DATA_LIST_COUNT; i++) { 1017 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], 1018 next); 1019 UATH_STAT_INC(sc, st_rx_inactive); 1020 } 1021 1022 return (0); 1023 } 1024 1025 static int 1026 uath_alloc_tx_data_list(struct uath_softc *sc) 1027 { 1028 int error, i; 1029 1030 error = uath_alloc_data_list(sc, 1031 sc->sc_tx, UATH_TX_DATA_LIST_COUNT, UATH_MAX_TXBUFSZ, 1032 0 /* no mbufs */); 1033 if (error != 0) 1034 return (error); 1035 1036 STAILQ_INIT(&sc->sc_tx_active); 1037 STAILQ_INIT(&sc->sc_tx_inactive); 1038 STAILQ_INIT(&sc->sc_tx_pending); 1039 1040 for (i = 0; i < UATH_TX_DATA_LIST_COUNT; i++) { 1041 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], 1042 next); 1043 UATH_STAT_INC(sc, st_tx_inactive); 1044 } 1045 1046 return (0); 1047 } 1048 1049 static void 1050 uath_free_rx_data_list(struct uath_softc *sc) 1051 { 1052 1053 STAILQ_INIT(&sc->sc_rx_active); 1054 STAILQ_INIT(&sc->sc_rx_inactive); 1055 1056 uath_free_data_list(sc, sc->sc_rx, UATH_RX_DATA_LIST_COUNT, 1057 1 /* free mbufs */); 1058 } 1059 1060 static void 1061 uath_free_tx_data_list(struct uath_softc *sc) 1062 { 1063 1064 STAILQ_INIT(&sc->sc_tx_active); 1065 STAILQ_INIT(&sc->sc_tx_inactive); 1066 STAILQ_INIT(&sc->sc_tx_pending); 1067 1068 uath_free_data_list(sc, sc->sc_tx, UATH_TX_DATA_LIST_COUNT, 1069 0 /* no mbufs */); 1070 } 1071 1072 static struct ieee80211vap * 1073 uath_vap_create(struct ieee80211com *ic, 1074 const char name[IFNAMSIZ], int unit, int opmode, int flags, 1075 const uint8_t bssid[IEEE80211_ADDR_LEN], 1076 const uint8_t mac[IEEE80211_ADDR_LEN]) 1077 { 1078 struct uath_vap *uvp; 1079 struct ieee80211vap *vap; 1080 1081 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 1082 return (NULL); 1083 uvp = (struct uath_vap *) malloc(sizeof(struct uath_vap), 1084 M_80211_VAP, M_NOWAIT | M_ZERO); 1085 if (uvp == NULL) 1086 return (NULL); 1087 vap = &uvp->vap; 1088 /* enable s/w bmiss handling for sta mode */ 1089 ieee80211_vap_setup(ic, vap, name, unit, opmode, 1090 flags | IEEE80211_CLONE_NOBEACONS, bssid, mac); 1091 1092 /* override state transition machine */ 1093 uvp->newstate = vap->iv_newstate; 1094 vap->iv_newstate = uath_newstate; 1095 1096 /* complete setup */ 1097 ieee80211_vap_attach(vap, ieee80211_media_change, 1098 ieee80211_media_status); 1099 ic->ic_opmode = opmode; 1100 return (vap); 1101 } 1102 1103 static void 1104 uath_vap_delete(struct ieee80211vap *vap) 1105 { 1106 struct uath_vap *uvp = UATH_VAP(vap); 1107 1108 ieee80211_vap_detach(vap); 1109 free(uvp, M_80211_VAP); 1110 } 1111 1112 static int 1113 uath_init_locked(void *arg) 1114 { 1115 struct uath_softc *sc = arg; 1116 struct ifnet *ifp = sc->sc_ifp; 1117 struct ieee80211com *ic = ifp->if_l2com; 1118 uint32_t val; 1119 int error; 1120 1121 UATH_ASSERT_LOCKED(sc); 1122 1123 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1124 uath_stop_locked(ifp); 1125 1126 /* reset variables */ 1127 sc->sc_intrx_nextnum = sc->sc_msgid = 0; 1128 1129 val = htobe32(0); 1130 uath_cmd_write(sc, WDCMSG_BIND, &val, sizeof val, 0); 1131 1132 /* set MAC address */ 1133 uath_config_multi(sc, CFG_MAC_ADDR, IF_LLADDR(ifp), IEEE80211_ADDR_LEN); 1134 1135 /* XXX honor net80211 state */ 1136 uath_config(sc, CFG_RATE_CONTROL_ENABLE, 0x00000001); 1137 uath_config(sc, CFG_DIVERSITY_CTL, 0x00000001); 1138 uath_config(sc, CFG_ABOLT, 0x0000003f); 1139 uath_config(sc, CFG_WME_ENABLED, 0x00000001); 1140 1141 uath_config(sc, CFG_SERVICE_TYPE, 1); 1142 uath_config(sc, CFG_TP_SCALE, 0x00000000); 1143 uath_config(sc, CFG_TPC_HALF_DBM5, 0x0000003c); 1144 uath_config(sc, CFG_TPC_HALF_DBM2, 0x0000003c); 1145 uath_config(sc, CFG_OVERRD_TX_POWER, 0x00000000); 1146 uath_config(sc, CFG_GMODE_PROTECTION, 0x00000000); 1147 uath_config(sc, CFG_GMODE_PROTECT_RATE_INDEX, 0x00000003); 1148 uath_config(sc, CFG_PROTECTION_TYPE, 0x00000000); 1149 uath_config(sc, CFG_MODE_CTS, 0x00000002); 1150 1151 error = uath_cmd_read(sc, WDCMSG_TARGET_START, NULL, 0, 1152 &val, sizeof(val), UATH_CMD_FLAG_MAGIC); 1153 if (error) { 1154 device_printf(sc->sc_dev, 1155 "could not start target, error %d\n", error); 1156 goto fail; 1157 } 1158 DPRINTF(sc, UATH_DEBUG_INIT, "%s returns handle: 0x%x\n", 1159 uath_codename(WDCMSG_TARGET_START), be32toh(val)); 1160 1161 /* set default channel */ 1162 error = uath_switch_channel(sc, ic->ic_curchan); 1163 if (error) { 1164 device_printf(sc->sc_dev, 1165 "could not switch channel, error %d\n", error); 1166 goto fail; 1167 } 1168 1169 val = htobe32(TARGET_DEVICE_AWAKE); 1170 uath_cmd_write(sc, WDCMSG_SET_PWR_MODE, &val, sizeof val, 0); 1171 /* XXX? check */ 1172 uath_cmd_write(sc, WDCMSG_RESET_KEY_CACHE, NULL, 0, 0); 1173 1174 usbd_transfer_start(sc->sc_xfer[UATH_BULK_RX]); 1175 /* enable Rx */ 1176 uath_set_rxfilter(sc, 0x0, UATH_FILTER_OP_INIT); 1177 uath_set_rxfilter(sc, 1178 UATH_FILTER_RX_UCAST | UATH_FILTER_RX_MCAST | 1179 UATH_FILTER_RX_BCAST | UATH_FILTER_RX_BEACON, 1180 UATH_FILTER_OP_SET); 1181 1182 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1183 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1184 sc->sc_flags |= UATH_FLAG_INITDONE; 1185 1186 callout_reset(&sc->watchdog_ch, hz, uath_watchdog, sc); 1187 1188 return (0); 1189 1190 fail: 1191 uath_stop_locked(ifp); 1192 return (error); 1193 } 1194 1195 static void 1196 uath_init(void *arg) 1197 { 1198 struct uath_softc *sc = arg; 1199 1200 UATH_LOCK(sc); 1201 (void)uath_init_locked(sc); 1202 UATH_UNLOCK(sc); 1203 } 1204 1205 static void 1206 uath_stop_locked(struct ifnet *ifp) 1207 { 1208 struct uath_softc *sc = ifp->if_softc; 1209 1210 UATH_ASSERT_LOCKED(sc); 1211 1212 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1213 sc->sc_flags &= ~UATH_FLAG_INITDONE; 1214 1215 callout_stop(&sc->stat_ch); 1216 callout_stop(&sc->watchdog_ch); 1217 sc->sc_tx_timer = 0; 1218 /* abort pending transmits */ 1219 uath_abort_xfers(sc); 1220 /* flush data & control requests into the target */ 1221 (void)uath_flush(sc); 1222 /* set a LED status to the disconnected. */ 1223 uath_set_ledstate(sc, 0); 1224 /* stop the target */ 1225 uath_cmd_write(sc, WDCMSG_TARGET_STOP, NULL, 0, 0); 1226 } 1227 1228 static void 1229 uath_stop(struct ifnet *ifp) 1230 { 1231 struct uath_softc *sc = ifp->if_softc; 1232 1233 UATH_LOCK(sc); 1234 uath_stop_locked(ifp); 1235 UATH_UNLOCK(sc); 1236 } 1237 1238 static int 1239 uath_config(struct uath_softc *sc, uint32_t reg, uint32_t val) 1240 { 1241 struct uath_write_mac write; 1242 int error; 1243 1244 write.reg = htobe32(reg); 1245 write.len = htobe32(0); /* 0 = single write */ 1246 *(uint32_t *)write.data = htobe32(val); 1247 1248 error = uath_cmd_write(sc, WDCMSG_TARGET_SET_CONFIG, &write, 1249 3 * sizeof (uint32_t), 0); 1250 if (error != 0) { 1251 device_printf(sc->sc_dev, "could not write register 0x%02x\n", 1252 reg); 1253 } 1254 return (error); 1255 } 1256 1257 static int 1258 uath_config_multi(struct uath_softc *sc, uint32_t reg, const void *data, 1259 int len) 1260 { 1261 struct uath_write_mac write; 1262 int error; 1263 1264 write.reg = htobe32(reg); 1265 write.len = htobe32(len); 1266 bcopy(data, write.data, len); 1267 1268 /* properly handle the case where len is zero (reset) */ 1269 error = uath_cmd_write(sc, WDCMSG_TARGET_SET_CONFIG, &write, 1270 (len == 0) ? sizeof (uint32_t) : 2 * sizeof (uint32_t) + len, 0); 1271 if (error != 0) { 1272 device_printf(sc->sc_dev, 1273 "could not write %d bytes to register 0x%02x\n", len, reg); 1274 } 1275 return (error); 1276 } 1277 1278 static int 1279 uath_switch_channel(struct uath_softc *sc, struct ieee80211_channel *c) 1280 { 1281 int error; 1282 1283 UATH_ASSERT_LOCKED(sc); 1284 1285 /* set radio frequency */ 1286 error = uath_set_chan(sc, c); 1287 if (error) { 1288 device_printf(sc->sc_dev, 1289 "could not set channel, error %d\n", error); 1290 goto failed; 1291 } 1292 /* reset Tx rings */ 1293 error = uath_reset_tx_queues(sc); 1294 if (error) { 1295 device_printf(sc->sc_dev, 1296 "could not reset Tx queues, error %d\n", error); 1297 goto failed; 1298 } 1299 /* set Tx rings WME properties */ 1300 error = uath_wme_init(sc); 1301 if (error) { 1302 device_printf(sc->sc_dev, 1303 "could not init Tx queues, error %d\n", error); 1304 goto failed; 1305 } 1306 error = uath_set_ledstate(sc, 0); 1307 if (error) { 1308 device_printf(sc->sc_dev, 1309 "could not set led state, error %d\n", error); 1310 goto failed; 1311 } 1312 error = uath_flush(sc); 1313 if (error) { 1314 device_printf(sc->sc_dev, 1315 "could not flush pipes, error %d\n", error); 1316 goto failed; 1317 } 1318 failed: 1319 return (error); 1320 } 1321 1322 static int 1323 uath_set_rxfilter(struct uath_softc *sc, uint32_t bits, uint32_t op) 1324 { 1325 struct uath_cmd_rx_filter rxfilter; 1326 1327 rxfilter.bits = htobe32(bits); 1328 rxfilter.op = htobe32(op); 1329 1330 DPRINTF(sc, UATH_DEBUG_RECV | UATH_DEBUG_RECV_ALL, 1331 "setting Rx filter=0x%x flags=0x%x\n", bits, op); 1332 return uath_cmd_write(sc, WDCMSG_RX_FILTER, &rxfilter, 1333 sizeof rxfilter, 0); 1334 } 1335 1336 static void 1337 uath_watchdog(void *arg) 1338 { 1339 struct uath_softc *sc = arg; 1340 struct ifnet *ifp = sc->sc_ifp; 1341 1342 if (sc->sc_tx_timer > 0) { 1343 if (--sc->sc_tx_timer == 0) { 1344 device_printf(sc->sc_dev, "device timeout\n"); 1345 /*uath_init(ifp); XXX needs a process context! */ 1346 ifp->if_oerrors++; 1347 return; 1348 } 1349 callout_reset(&sc->watchdog_ch, hz, uath_watchdog, sc); 1350 } 1351 } 1352 1353 static void 1354 uath_abort_xfers(struct uath_softc *sc) 1355 { 1356 int i; 1357 1358 UATH_ASSERT_LOCKED(sc); 1359 /* abort any pending transfers */ 1360 for (i = 0; i < UATH_N_XFERS; i++) 1361 usbd_transfer_stop(sc->sc_xfer[i]); 1362 } 1363 1364 static int 1365 uath_flush(struct uath_softc *sc) 1366 { 1367 int error; 1368 1369 error = uath_dataflush(sc); 1370 if (error != 0) 1371 goto failed; 1372 1373 error = uath_cmdflush(sc); 1374 if (error != 0) 1375 goto failed; 1376 1377 failed: 1378 return (error); 1379 } 1380 1381 static int 1382 uath_cmdflush(struct uath_softc *sc) 1383 { 1384 1385 return uath_cmd_write(sc, WDCMSG_FLUSH, NULL, 0, 0); 1386 } 1387 1388 static int 1389 uath_dataflush(struct uath_softc *sc) 1390 { 1391 struct uath_data *data; 1392 struct uath_chunk *chunk; 1393 struct uath_tx_desc *desc; 1394 1395 UATH_ASSERT_LOCKED(sc); 1396 1397 data = uath_getbuf(sc); 1398 if (data == NULL) 1399 return (ENOBUFS); 1400 data->buflen = sizeof(struct uath_chunk) + sizeof(struct uath_tx_desc); 1401 data->m = NULL; 1402 data->ni = NULL; 1403 chunk = (struct uath_chunk *)data->buf; 1404 desc = (struct uath_tx_desc *)(chunk + 1); 1405 1406 /* one chunk only */ 1407 chunk->seqnum = 0; 1408 chunk->flags = UATH_CFLAGS_FINAL; 1409 chunk->length = htobe16(sizeof (struct uath_tx_desc)); 1410 1411 bzero(desc, sizeof(struct uath_tx_desc)); 1412 desc->msglen = htobe32(sizeof(struct uath_tx_desc)); 1413 desc->msgid = (sc->sc_msgid++) + 1; /* don't care about endianness */ 1414 desc->type = htobe32(WDCMSG_FLUSH); 1415 desc->txqid = htobe32(0); 1416 desc->connid = htobe32(0); 1417 desc->flags = htobe32(0); 1418 1419 #ifdef UATH_DEBUG 1420 if (sc->sc_debug & UATH_DEBUG_CMDS) { 1421 DPRINTF(sc, UATH_DEBUG_RESET, "send flush ix %d\n", 1422 desc->msgid); 1423 if (sc->sc_debug & UATH_DEBUG_CMDS_DUMP) 1424 uath_dump_cmd(data->buf, data->buflen, '+'); 1425 } 1426 #endif 1427 1428 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 1429 UATH_STAT_INC(sc, st_tx_pending); 1430 sc->sc_tx_timer = 5; 1431 usbd_transfer_start(sc->sc_xfer[UATH_BULK_TX]); 1432 1433 return (0); 1434 } 1435 1436 static struct uath_data * 1437 _uath_getbuf(struct uath_softc *sc) 1438 { 1439 struct uath_data *bf; 1440 1441 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 1442 if (bf != NULL) { 1443 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 1444 UATH_STAT_DEC(sc, st_tx_inactive); 1445 } else 1446 bf = NULL; 1447 if (bf == NULL) 1448 DPRINTF(sc, UATH_DEBUG_XMIT, "%s: %s\n", __func__, 1449 "out of xmit buffers"); 1450 return (bf); 1451 } 1452 1453 static struct uath_data * 1454 uath_getbuf(struct uath_softc *sc) 1455 { 1456 struct uath_data *bf; 1457 1458 UATH_ASSERT_LOCKED(sc); 1459 1460 bf = _uath_getbuf(sc); 1461 if (bf == NULL) { 1462 struct ifnet *ifp = sc->sc_ifp; 1463 1464 DPRINTF(sc, UATH_DEBUG_XMIT, "%s: stop queue\n", __func__); 1465 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1466 } 1467 return (bf); 1468 } 1469 1470 static int 1471 uath_set_ledstate(struct uath_softc *sc, int connected) 1472 { 1473 1474 DPRINTF(sc, UATH_DEBUG_LED, 1475 "set led state %sconnected\n", connected ? "" : "!"); 1476 connected = htobe32(connected); 1477 return uath_cmd_write(sc, WDCMSG_SET_LED_STATE, 1478 &connected, sizeof connected, 0); 1479 } 1480 1481 static int 1482 uath_set_chan(struct uath_softc *sc, struct ieee80211_channel *c) 1483 { 1484 #ifdef UATH_DEBUG 1485 struct ifnet *ifp = sc->sc_ifp; 1486 struct ieee80211com *ic = ifp->if_l2com; 1487 #endif 1488 struct uath_cmd_reset reset; 1489 1490 bzero(&reset, sizeof reset); 1491 if (IEEE80211_IS_CHAN_2GHZ(c)) 1492 reset.flags |= htobe32(UATH_CHAN_2GHZ); 1493 if (IEEE80211_IS_CHAN_5GHZ(c)) 1494 reset.flags |= htobe32(UATH_CHAN_5GHZ); 1495 /* NB: 11g =>'s 11b so don't specify both OFDM and CCK */ 1496 if (IEEE80211_IS_CHAN_OFDM(c)) 1497 reset.flags |= htobe32(UATH_CHAN_OFDM); 1498 else if (IEEE80211_IS_CHAN_CCK(c)) 1499 reset.flags |= htobe32(UATH_CHAN_CCK); 1500 /* turbo can be used in either 2GHz or 5GHz */ 1501 if (c->ic_flags & IEEE80211_CHAN_TURBO) 1502 reset.flags |= htobe32(UATH_CHAN_TURBO); 1503 reset.freq = htobe32(c->ic_freq); 1504 reset.maxrdpower = htobe32(50); /* XXX */ 1505 reset.channelchange = htobe32(1); 1506 reset.keeprccontent = htobe32(0); 1507 1508 DPRINTF(sc, UATH_DEBUG_CHANNEL, "set channel %d, flags 0x%x freq %u\n", 1509 ieee80211_chan2ieee(ic, c), 1510 be32toh(reset.flags), be32toh(reset.freq)); 1511 return uath_cmd_write(sc, WDCMSG_RESET, &reset, sizeof reset, 0); 1512 } 1513 1514 static int 1515 uath_reset_tx_queues(struct uath_softc *sc) 1516 { 1517 int ac, error; 1518 1519 DPRINTF(sc, UATH_DEBUG_RESET, "%s: reset Tx queues\n", __func__); 1520 for (ac = 0; ac < 4; ac++) { 1521 const uint32_t qid = htobe32(ac); 1522 1523 error = uath_cmd_write(sc, WDCMSG_RELEASE_TX_QUEUE, &qid, 1524 sizeof qid, 0); 1525 if (error != 0) 1526 break; 1527 } 1528 return (error); 1529 } 1530 1531 static int 1532 uath_wme_init(struct uath_softc *sc) 1533 { 1534 /* XXX get from net80211 */ 1535 static const struct uath_wme_settings uath_wme_11g[4] = { 1536 { 7, 4, 10, 0, 0 }, /* Background */ 1537 { 3, 4, 10, 0, 0 }, /* Best-Effort */ 1538 { 3, 3, 4, 26, 0 }, /* Video */ 1539 { 2, 2, 3, 47, 0 } /* Voice */ 1540 }; 1541 struct uath_cmd_txq_setup qinfo; 1542 int ac, error; 1543 1544 DPRINTF(sc, UATH_DEBUG_WME, "%s: setup Tx queues\n", __func__); 1545 for (ac = 0; ac < 4; ac++) { 1546 qinfo.qid = htobe32(ac); 1547 qinfo.len = htobe32(sizeof(qinfo.attr)); 1548 qinfo.attr.priority = htobe32(ac); /* XXX */ 1549 qinfo.attr.aifs = htobe32(uath_wme_11g[ac].aifsn); 1550 qinfo.attr.logcwmin = htobe32(uath_wme_11g[ac].logcwmin); 1551 qinfo.attr.logcwmax = htobe32(uath_wme_11g[ac].logcwmax); 1552 qinfo.attr.bursttime = htobe32(UATH_TXOP_TO_US( 1553 uath_wme_11g[ac].txop)); 1554 qinfo.attr.mode = htobe32(uath_wme_11g[ac].acm);/*XXX? */ 1555 qinfo.attr.qflags = htobe32(1); /* XXX? */ 1556 1557 error = uath_cmd_write(sc, WDCMSG_SETUP_TX_QUEUE, &qinfo, 1558 sizeof qinfo, 0); 1559 if (error != 0) 1560 break; 1561 } 1562 return (error); 1563 } 1564 1565 static int 1566 uath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1567 { 1568 struct ieee80211com *ic = ifp->if_l2com; 1569 struct ifreq *ifr = (struct ifreq *) data; 1570 int error = 0, startall = 0; 1571 1572 switch (cmd) { 1573 case SIOCSIFFLAGS: 1574 if (ifp->if_flags & IFF_UP) { 1575 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1576 uath_init(ifp->if_softc); 1577 startall = 1; 1578 } 1579 } else { 1580 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1581 uath_stop(ifp); 1582 } 1583 if (startall) 1584 ieee80211_start_all(ic); 1585 break; 1586 case SIOCGIFMEDIA: 1587 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 1588 break; 1589 case SIOCGIFADDR: 1590 error = ether_ioctl(ifp, cmd, data); 1591 break; 1592 default: 1593 error = EINVAL; 1594 break; 1595 } 1596 1597 return (error); 1598 } 1599 1600 static int 1601 uath_tx_start(struct uath_softc *sc, struct mbuf *m0, struct ieee80211_node *ni, 1602 struct uath_data *data) 1603 { 1604 struct ieee80211vap *vap = ni->ni_vap; 1605 struct uath_chunk *chunk; 1606 struct uath_tx_desc *desc; 1607 const struct ieee80211_frame *wh; 1608 struct ieee80211_key *k; 1609 int framelen, msglen; 1610 1611 UATH_ASSERT_LOCKED(sc); 1612 1613 data->ni = ni; 1614 data->m = m0; 1615 chunk = (struct uath_chunk *)data->buf; 1616 desc = (struct uath_tx_desc *)(chunk + 1); 1617 1618 if (ieee80211_radiotap_active_vap(vap)) { 1619 struct uath_tx_radiotap_header *tap = &sc->sc_txtap; 1620 1621 tap->wt_flags = 0; 1622 if (m0->m_flags & M_FRAG) 1623 tap->wt_flags |= IEEE80211_RADIOTAP_F_FRAG; 1624 1625 ieee80211_radiotap_tx(vap, m0); 1626 } 1627 1628 wh = mtod(m0, struct ieee80211_frame *); 1629 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1630 k = ieee80211_crypto_encap(ni, m0); 1631 if (k == NULL) { 1632 m_freem(m0); 1633 return (ENOBUFS); 1634 } 1635 1636 /* packet header may have moved, reset our local pointer */ 1637 wh = mtod(m0, struct ieee80211_frame *); 1638 } 1639 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)(desc + 1)); 1640 1641 framelen = m0->m_pkthdr.len + IEEE80211_CRC_LEN; 1642 msglen = framelen + sizeof (struct uath_tx_desc); 1643 data->buflen = msglen + sizeof (struct uath_chunk); 1644 1645 /* one chunk only for now */ 1646 chunk->seqnum = sc->sc_seqnum++; 1647 chunk->flags = (m0->m_flags & M_FRAG) ? 0 : UATH_CFLAGS_FINAL; 1648 if (m0->m_flags & M_LASTFRAG) 1649 chunk->flags |= UATH_CFLAGS_FINAL; 1650 chunk->flags = UATH_CFLAGS_FINAL; 1651 chunk->length = htobe16(msglen); 1652 1653 /* fill Tx descriptor */ 1654 desc->msglen = htobe32(msglen); 1655 /* NB: to get UATH_TX_NOTIFY reply, `msgid' must be larger than 0 */ 1656 desc->msgid = (sc->sc_msgid++) + 1; /* don't care about endianness */ 1657 desc->type = htobe32(WDCMSG_SEND); 1658 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 1659 case IEEE80211_FC0_TYPE_CTL: 1660 case IEEE80211_FC0_TYPE_MGT: 1661 /* NB: force all management frames to highest queue */ 1662 if (ni->ni_flags & IEEE80211_NODE_QOS) { 1663 /* NB: force all management frames to highest queue */ 1664 desc->txqid = htobe32(WME_AC_VO | UATH_TXQID_MINRATE); 1665 } else 1666 desc->txqid = htobe32(WME_AC_BE | UATH_TXQID_MINRATE); 1667 break; 1668 case IEEE80211_FC0_TYPE_DATA: 1669 /* XXX multicast frames should honor mcastrate */ 1670 desc->txqid = htobe32(M_WME_GETAC(m0)); 1671 break; 1672 default: 1673 device_printf(sc->sc_dev, "bogus frame type 0x%x (%s)\n", 1674 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__); 1675 m_freem(m0); 1676 return (EIO); 1677 } 1678 if (vap->iv_state == IEEE80211_S_AUTH || 1679 vap->iv_state == IEEE80211_S_ASSOC || 1680 vap->iv_state == IEEE80211_S_RUN) 1681 desc->connid = htobe32(UATH_ID_BSS); 1682 else 1683 desc->connid = htobe32(UATH_ID_INVALID); 1684 desc->flags = htobe32(0 /* no UATH_TX_NOTIFY */); 1685 desc->buflen = htobe32(m0->m_pkthdr.len); 1686 1687 #ifdef UATH_DEBUG 1688 DPRINTF(sc, UATH_DEBUG_XMIT, 1689 "send frame ix %u framelen %d msglen %d connid 0x%x txqid 0x%x\n", 1690 desc->msgid, framelen, msglen, be32toh(desc->connid), 1691 be32toh(desc->txqid)); 1692 if (sc->sc_debug & UATH_DEBUG_XMIT_DUMP) 1693 uath_dump_cmd(data->buf, data->buflen, '+'); 1694 #endif 1695 1696 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 1697 UATH_STAT_INC(sc, st_tx_pending); 1698 usbd_transfer_start(sc->sc_xfer[UATH_BULK_TX]); 1699 1700 return (0); 1701 } 1702 1703 /* 1704 * Cleanup driver resources when we run out of buffers while processing 1705 * fragments; return the tx buffers allocated and drop node references. 1706 */ 1707 static void 1708 uath_txfrag_cleanup(struct uath_softc *sc, 1709 uath_datahead *frags, struct ieee80211_node *ni) 1710 { 1711 struct uath_data *bf, *next; 1712 1713 UATH_ASSERT_LOCKED(sc); 1714 1715 STAILQ_FOREACH_SAFE(bf, frags, next, next) { 1716 /* NB: bf assumed clean */ 1717 STAILQ_REMOVE_HEAD(frags, next); 1718 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 1719 UATH_STAT_INC(sc, st_tx_inactive); 1720 ieee80211_node_decref(ni); 1721 } 1722 } 1723 1724 /* 1725 * Setup xmit of a fragmented frame. Allocate a buffer for each frag and bump 1726 * the node reference count to reflect the held reference to be setup by 1727 * uath_tx_start. 1728 */ 1729 static int 1730 uath_txfrag_setup(struct uath_softc *sc, uath_datahead *frags, 1731 struct mbuf *m0, struct ieee80211_node *ni) 1732 { 1733 struct mbuf *m; 1734 struct uath_data *bf; 1735 1736 UATH_ASSERT_LOCKED(sc); 1737 for (m = m0->m_nextpkt; m != NULL; m = m->m_nextpkt) { 1738 bf = uath_getbuf(sc); 1739 if (bf == NULL) { /* out of buffers, cleanup */ 1740 uath_txfrag_cleanup(sc, frags, ni); 1741 break; 1742 } 1743 ieee80211_node_incref(ni); 1744 STAILQ_INSERT_TAIL(frags, bf, next); 1745 } 1746 1747 return !STAILQ_EMPTY(frags); 1748 } 1749 1750 /* 1751 * Reclaim mbuf resources. For fragmented frames we need to claim each frag 1752 * chained with m_nextpkt. 1753 */ 1754 static void 1755 uath_freetx(struct mbuf *m) 1756 { 1757 struct mbuf *next; 1758 1759 do { 1760 next = m->m_nextpkt; 1761 m->m_nextpkt = NULL; 1762 m_freem(m); 1763 } while ((m = next) != NULL); 1764 } 1765 1766 static void 1767 uath_start(struct ifnet *ifp) 1768 { 1769 struct uath_data *bf; 1770 struct uath_softc *sc = ifp->if_softc; 1771 struct ieee80211_node *ni; 1772 struct mbuf *m, *next; 1773 uath_datahead frags; 1774 1775 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || 1776 (sc->sc_flags & UATH_FLAG_INVALID)) 1777 return; 1778 1779 UATH_LOCK(sc); 1780 for (;;) { 1781 bf = uath_getbuf(sc); 1782 if (bf == NULL) 1783 break; 1784 1785 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1786 if (m == NULL) { 1787 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 1788 UATH_STAT_INC(sc, st_tx_inactive); 1789 break; 1790 } 1791 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1792 m->m_pkthdr.rcvif = NULL; 1793 1794 /* 1795 * Check for fragmentation. If this frame has been broken up 1796 * verify we have enough buffers to send all the fragments 1797 * so all go out or none... 1798 */ 1799 STAILQ_INIT(&frags); 1800 if ((m->m_flags & M_FRAG) && 1801 !uath_txfrag_setup(sc, &frags, m, ni)) { 1802 DPRINTF(sc, UATH_DEBUG_XMIT, 1803 "%s: out of txfrag buffers\n", __func__); 1804 uath_freetx(m); 1805 goto bad; 1806 } 1807 sc->sc_seqnum = 0; 1808 nextfrag: 1809 /* 1810 * Pass the frame to the h/w for transmission. 1811 * Fragmented frames have each frag chained together 1812 * with m_nextpkt. We know there are sufficient uath_data's 1813 * to send all the frags because of work done by 1814 * uath_txfrag_setup. 1815 */ 1816 next = m->m_nextpkt; 1817 if (uath_tx_start(sc, m, ni, bf) != 0) { 1818 bad: 1819 ifp->if_oerrors++; 1820 reclaim: 1821 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 1822 UATH_STAT_INC(sc, st_tx_inactive); 1823 uath_txfrag_cleanup(sc, &frags, ni); 1824 ieee80211_free_node(ni); 1825 continue; 1826 } 1827 1828 if (next != NULL) { 1829 /* 1830 * Beware of state changing between frags. 1831 XXX check sta power-save state? 1832 */ 1833 if (ni->ni_vap->iv_state != IEEE80211_S_RUN) { 1834 DPRINTF(sc, UATH_DEBUG_XMIT, 1835 "%s: flush fragmented packet, state %s\n", 1836 __func__, 1837 ieee80211_state_name[ni->ni_vap->iv_state]); 1838 uath_freetx(next); 1839 goto reclaim; 1840 } 1841 m = next; 1842 bf = STAILQ_FIRST(&frags); 1843 KASSERT(bf != NULL, ("no buf for txfrag")); 1844 STAILQ_REMOVE_HEAD(&frags, next); 1845 goto nextfrag; 1846 } 1847 1848 sc->sc_tx_timer = 5; 1849 } 1850 UATH_UNLOCK(sc); 1851 } 1852 1853 static int 1854 uath_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1855 const struct ieee80211_bpf_params *params) 1856 { 1857 struct ieee80211com *ic = ni->ni_ic; 1858 struct ifnet *ifp = ic->ic_ifp; 1859 struct uath_data *bf; 1860 struct uath_softc *sc = ifp->if_softc; 1861 1862 /* prevent management frames from being sent if we're not ready */ 1863 if ((sc->sc_flags & UATH_FLAG_INVALID) || 1864 !(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1865 m_freem(m); 1866 ieee80211_free_node(ni); 1867 return (ENETDOWN); 1868 } 1869 1870 UATH_LOCK(sc); 1871 /* grab a TX buffer */ 1872 bf = uath_getbuf(sc); 1873 if (bf == NULL) { 1874 ieee80211_free_node(ni); 1875 m_freem(m); 1876 UATH_UNLOCK(sc); 1877 return (ENOBUFS); 1878 } 1879 1880 sc->sc_seqnum = 0; 1881 if (uath_tx_start(sc, m, ni, bf) != 0) { 1882 ieee80211_free_node(ni); 1883 ifp->if_oerrors++; 1884 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 1885 UATH_STAT_INC(sc, st_tx_inactive); 1886 UATH_UNLOCK(sc); 1887 return (EIO); 1888 } 1889 UATH_UNLOCK(sc); 1890 1891 sc->sc_tx_timer = 5; 1892 return (0); 1893 } 1894 1895 static void 1896 uath_scan_start(struct ieee80211com *ic) 1897 { 1898 /* do nothing */ 1899 } 1900 1901 static void 1902 uath_scan_end(struct ieee80211com *ic) 1903 { 1904 /* do nothing */ 1905 } 1906 1907 static void 1908 uath_set_channel(struct ieee80211com *ic) 1909 { 1910 struct ifnet *ifp = ic->ic_ifp; 1911 struct uath_softc *sc = ifp->if_softc; 1912 1913 UATH_LOCK(sc); 1914 if ((sc->sc_flags & UATH_FLAG_INVALID) || 1915 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1916 UATH_UNLOCK(sc); 1917 return; 1918 } 1919 (void)uath_switch_channel(sc, ic->ic_curchan); 1920 UATH_UNLOCK(sc); 1921 } 1922 1923 static int 1924 uath_set_rxmulti_filter(struct uath_softc *sc) 1925 { 1926 /* XXX broken */ 1927 return (0); 1928 } 1929 static void 1930 uath_update_mcast(struct ifnet *ifp) 1931 { 1932 struct uath_softc *sc = ifp->if_softc; 1933 1934 UATH_LOCK(sc); 1935 if ((sc->sc_flags & UATH_FLAG_INVALID) || 1936 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1937 UATH_UNLOCK(sc); 1938 return; 1939 } 1940 /* 1941 * this is for avoiding the race condition when we're try to 1942 * connect to the AP with WPA. 1943 */ 1944 if (sc->sc_flags & UATH_FLAG_INITDONE) 1945 (void)uath_set_rxmulti_filter(sc); 1946 UATH_UNLOCK(sc); 1947 } 1948 1949 static void 1950 uath_update_promisc(struct ifnet *ifp) 1951 { 1952 struct uath_softc *sc = ifp->if_softc; 1953 1954 UATH_LOCK(sc); 1955 if ((sc->sc_flags & UATH_FLAG_INVALID) || 1956 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1957 UATH_UNLOCK(sc); 1958 return; 1959 } 1960 if (sc->sc_flags & UATH_FLAG_INITDONE) { 1961 uath_set_rxfilter(sc, 1962 UATH_FILTER_RX_UCAST | UATH_FILTER_RX_MCAST | 1963 UATH_FILTER_RX_BCAST | UATH_FILTER_RX_BEACON | 1964 UATH_FILTER_RX_PROM, UATH_FILTER_OP_SET); 1965 } 1966 UATH_UNLOCK(sc); 1967 } 1968 1969 static int 1970 uath_create_connection(struct uath_softc *sc, uint32_t connid) 1971 { 1972 const struct ieee80211_rateset *rs; 1973 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 1974 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1975 struct ieee80211_node *ni = vap->iv_bss; 1976 struct uath_cmd_create_connection create; 1977 1978 bzero(&create, sizeof create); 1979 create.connid = htobe32(connid); 1980 create.bssid = htobe32(0); 1981 /* XXX packed or not? */ 1982 create.size = htobe32(sizeof(struct uath_cmd_rateset)); 1983 1984 rs = &ni->ni_rates; 1985 create.connattr.rateset.length = rs->rs_nrates; 1986 bcopy(rs->rs_rates, &create.connattr.rateset.set[0], 1987 rs->rs_nrates); 1988 1989 /* XXX turbo */ 1990 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) 1991 create.connattr.wlanmode = htobe32(WLAN_MODE_11a); 1992 else if (IEEE80211_IS_CHAN_ANYG(ni->ni_chan)) 1993 create.connattr.wlanmode = htobe32(WLAN_MODE_11g); 1994 else 1995 create.connattr.wlanmode = htobe32(WLAN_MODE_11b); 1996 1997 return uath_cmd_write(sc, WDCMSG_CREATE_CONNECTION, &create, 1998 sizeof create, 0); 1999 } 2000 2001 static int 2002 uath_set_rates(struct uath_softc *sc, const struct ieee80211_rateset *rs) 2003 { 2004 struct uath_cmd_rates rates; 2005 2006 bzero(&rates, sizeof rates); 2007 rates.connid = htobe32(UATH_ID_BSS); /* XXX */ 2008 rates.size = htobe32(sizeof(struct uath_cmd_rateset)); 2009 /* XXX bounds check rs->rs_nrates */ 2010 rates.rateset.length = rs->rs_nrates; 2011 bcopy(rs->rs_rates, &rates.rateset.set[0], rs->rs_nrates); 2012 2013 DPRINTF(sc, UATH_DEBUG_RATES, 2014 "setting supported rates nrates=%d\n", rs->rs_nrates); 2015 return uath_cmd_write(sc, WDCMSG_SET_BASIC_RATE, 2016 &rates, sizeof rates, 0); 2017 } 2018 2019 static int 2020 uath_write_associd(struct uath_softc *sc) 2021 { 2022 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 2023 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2024 struct ieee80211_node *ni = vap->iv_bss; 2025 struct uath_cmd_set_associd associd; 2026 2027 bzero(&associd, sizeof associd); 2028 associd.defaultrateix = htobe32(1); /* XXX */ 2029 associd.associd = htobe32(ni->ni_associd); 2030 associd.timoffset = htobe32(0x3b); /* XXX */ 2031 IEEE80211_ADDR_COPY(associd.bssid, ni->ni_bssid); 2032 return uath_cmd_write(sc, WDCMSG_WRITE_ASSOCID, &associd, 2033 sizeof associd, 0); 2034 } 2035 2036 static int 2037 uath_set_ledsteady(struct uath_softc *sc, int lednum, int ledmode) 2038 { 2039 struct uath_cmd_ledsteady led; 2040 2041 led.lednum = htobe32(lednum); 2042 led.ledmode = htobe32(ledmode); 2043 2044 DPRINTF(sc, UATH_DEBUG_LED, "set %s led %s (steady)\n", 2045 (lednum == UATH_LED_LINK) ? "link" : "activity", 2046 ledmode ? "on" : "off"); 2047 return uath_cmd_write(sc, WDCMSG_SET_LED_STEADY, &led, sizeof led, 0); 2048 } 2049 2050 static int 2051 uath_set_ledblink(struct uath_softc *sc, int lednum, int ledmode, 2052 int blinkrate, int slowmode) 2053 { 2054 struct uath_cmd_ledblink led; 2055 2056 led.lednum = htobe32(lednum); 2057 led.ledmode = htobe32(ledmode); 2058 led.blinkrate = htobe32(blinkrate); 2059 led.slowmode = htobe32(slowmode); 2060 2061 DPRINTF(sc, UATH_DEBUG_LED, "set %s led %s (blink)\n", 2062 (lednum == UATH_LED_LINK) ? "link" : "activity", 2063 ledmode ? "on" : "off"); 2064 return uath_cmd_write(sc, WDCMSG_SET_LED_BLINK, &led, sizeof led, 0); 2065 } 2066 2067 static int 2068 uath_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 2069 { 2070 enum ieee80211_state ostate = vap->iv_state; 2071 int error; 2072 struct ieee80211_node *ni = vap->iv_bss; 2073 struct ieee80211com *ic = vap->iv_ic; 2074 struct uath_softc *sc = ic->ic_ifp->if_softc; 2075 struct uath_vap *uvp = UATH_VAP(vap); 2076 2077 DPRINTF(sc, UATH_DEBUG_STATE, 2078 "%s: %s -> %s\n", __func__, ieee80211_state_name[vap->iv_state], 2079 ieee80211_state_name[nstate]); 2080 2081 IEEE80211_UNLOCK(ic); 2082 UATH_LOCK(sc); 2083 callout_stop(&sc->stat_ch); 2084 callout_stop(&sc->watchdog_ch); 2085 2086 switch (nstate) { 2087 case IEEE80211_S_INIT: 2088 if (ostate == IEEE80211_S_RUN) { 2089 /* turn link and activity LEDs off */ 2090 uath_set_ledstate(sc, 0); 2091 } 2092 break; 2093 2094 case IEEE80211_S_SCAN: 2095 break; 2096 2097 case IEEE80211_S_AUTH: 2098 /* XXX good place? set RTS threshold */ 2099 uath_config(sc, CFG_USER_RTS_THRESHOLD, vap->iv_rtsthreshold); 2100 /* XXX bad place */ 2101 error = uath_set_keys(sc, vap); 2102 if (error != 0) { 2103 device_printf(sc->sc_dev, 2104 "could not set crypto keys, error %d\n", error); 2105 break; 2106 } 2107 if (uath_switch_channel(sc, ni->ni_chan) != 0) { 2108 device_printf(sc->sc_dev, "could not switch channel\n"); 2109 break; 2110 } 2111 if (uath_create_connection(sc, UATH_ID_BSS) != 0) { 2112 device_printf(sc->sc_dev, 2113 "could not create connection\n"); 2114 break; 2115 } 2116 break; 2117 2118 case IEEE80211_S_ASSOC: 2119 if (uath_set_rates(sc, &ni->ni_rates) != 0) { 2120 device_printf(sc->sc_dev, 2121 "could not set negotiated rate set\n"); 2122 break; 2123 } 2124 break; 2125 2126 case IEEE80211_S_RUN: 2127 /* XXX monitor mode doesn't be tested */ 2128 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2129 uath_set_ledstate(sc, 1); 2130 break; 2131 } 2132 2133 /* 2134 * Tx rate is controlled by firmware, report the maximum 2135 * negotiated rate in ifconfig output. 2136 */ 2137 ni->ni_txrate = ni->ni_rates.rs_rates[ni->ni_rates.rs_nrates-1]; 2138 2139 if (uath_write_associd(sc) != 0) { 2140 device_printf(sc->sc_dev, 2141 "could not write association id\n"); 2142 break; 2143 } 2144 /* turn link LED on */ 2145 uath_set_ledsteady(sc, UATH_LED_LINK, UATH_LED_ON); 2146 /* make activity LED blink */ 2147 uath_set_ledblink(sc, UATH_LED_ACTIVITY, UATH_LED_ON, 1, 2); 2148 /* set state to associated */ 2149 uath_set_ledstate(sc, 1); 2150 2151 /* start statistics timer */ 2152 callout_reset(&sc->stat_ch, hz, uath_stat, sc); 2153 break; 2154 default: 2155 break; 2156 } 2157 UATH_UNLOCK(sc); 2158 IEEE80211_LOCK(ic); 2159 return (uvp->newstate(vap, nstate, arg)); 2160 } 2161 2162 static int 2163 uath_set_key(struct uath_softc *sc, const struct ieee80211_key *wk, 2164 int index) 2165 { 2166 #if 0 2167 struct uath_cmd_crypto crypto; 2168 int i; 2169 2170 bzero(&crypto, sizeof crypto); 2171 crypto.keyidx = htobe32(index); 2172 crypto.magic1 = htobe32(1); 2173 crypto.size = htobe32(368); 2174 crypto.mask = htobe32(0xffff); 2175 crypto.flags = htobe32(0x80000068); 2176 if (index != UATH_DEFAULT_KEY) 2177 crypto.flags |= htobe32(index << 16); 2178 memset(crypto.magic2, 0xff, sizeof crypto.magic2); 2179 2180 /* 2181 * Each byte of the key must be XOR'ed with 10101010 before being 2182 * transmitted to the firmware. 2183 */ 2184 for (i = 0; i < wk->wk_keylen; i++) 2185 crypto.key[i] = wk->wk_key[i] ^ 0xaa; 2186 2187 DPRINTF(sc, UATH_DEBUG_CRYPTO, 2188 "setting crypto key index=%d len=%d\n", index, wk->wk_keylen); 2189 return uath_cmd_write(sc, WDCMSG_SET_KEY_CACHE_ENTRY, &crypto, 2190 sizeof crypto, 0); 2191 #else 2192 /* XXX support H/W cryto */ 2193 return (0); 2194 #endif 2195 } 2196 2197 static int 2198 uath_set_keys(struct uath_softc *sc, struct ieee80211vap *vap) 2199 { 2200 int i, error; 2201 2202 error = 0; 2203 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2204 const struct ieee80211_key *wk = &vap->iv_nw_keys[i]; 2205 2206 if (wk->wk_flags & (IEEE80211_KEY_XMIT|IEEE80211_KEY_RECV)) { 2207 error = uath_set_key(sc, wk, i); 2208 if (error) 2209 return (error); 2210 } 2211 } 2212 if (vap->iv_def_txkey != IEEE80211_KEYIX_NONE) { 2213 error = uath_set_key(sc, &vap->iv_nw_keys[vap->iv_def_txkey], 2214 UATH_DEFAULT_KEY); 2215 } 2216 return (error); 2217 } 2218 2219 #define UATH_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 2220 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 2221 2222 static void 2223 uath_sysctl_node(struct uath_softc *sc) 2224 { 2225 struct sysctl_ctx_list *ctx; 2226 struct sysctl_oid_list *child; 2227 struct sysctl_oid *tree; 2228 struct uath_stat *stats; 2229 2230 stats = &sc->sc_stat; 2231 ctx = device_get_sysctl_ctx(sc->sc_dev); 2232 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->sc_dev)); 2233 2234 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 2235 NULL, "UATH statistics"); 2236 child = SYSCTL_CHILDREN(tree); 2237 UATH_SYSCTL_STAT_ADD32(ctx, child, "badchunkseqnum", 2238 &stats->st_badchunkseqnum, "Bad chunk sequence numbers"); 2239 UATH_SYSCTL_STAT_ADD32(ctx, child, "invalidlen", &stats->st_invalidlen, 2240 "Invalid length"); 2241 UATH_SYSCTL_STAT_ADD32(ctx, child, "multichunk", &stats->st_multichunk, 2242 "Multi chunks"); 2243 UATH_SYSCTL_STAT_ADD32(ctx, child, "toobigrxpkt", 2244 &stats->st_toobigrxpkt, "Too big rx packets"); 2245 UATH_SYSCTL_STAT_ADD32(ctx, child, "stopinprogress", 2246 &stats->st_stopinprogress, "Stop in progress"); 2247 UATH_SYSCTL_STAT_ADD32(ctx, child, "crcerrs", &stats->st_crcerr, 2248 "CRC errors"); 2249 UATH_SYSCTL_STAT_ADD32(ctx, child, "phyerr", &stats->st_phyerr, 2250 "PHY errors"); 2251 UATH_SYSCTL_STAT_ADD32(ctx, child, "decrypt_crcerr", 2252 &stats->st_decrypt_crcerr, "Decryption CRC errors"); 2253 UATH_SYSCTL_STAT_ADD32(ctx, child, "decrypt_micerr", 2254 &stats->st_decrypt_micerr, "Decryption Misc errors"); 2255 UATH_SYSCTL_STAT_ADD32(ctx, child, "decomperr", &stats->st_decomperr, 2256 "Decomp errors"); 2257 UATH_SYSCTL_STAT_ADD32(ctx, child, "keyerr", &stats->st_keyerr, 2258 "Key errors"); 2259 UATH_SYSCTL_STAT_ADD32(ctx, child, "err", &stats->st_err, 2260 "Unknown errors"); 2261 2262 UATH_SYSCTL_STAT_ADD32(ctx, child, "cmd_active", 2263 &stats->st_cmd_active, "Active numbers in Command queue"); 2264 UATH_SYSCTL_STAT_ADD32(ctx, child, "cmd_inactive", 2265 &stats->st_cmd_inactive, "Inactive numbers in Command queue"); 2266 UATH_SYSCTL_STAT_ADD32(ctx, child, "cmd_pending", 2267 &stats->st_cmd_pending, "Pending numbers in Command queue"); 2268 UATH_SYSCTL_STAT_ADD32(ctx, child, "cmd_waiting", 2269 &stats->st_cmd_waiting, "Waiting numbers in Command queue"); 2270 UATH_SYSCTL_STAT_ADD32(ctx, child, "rx_active", 2271 &stats->st_rx_active, "Active numbers in RX queue"); 2272 UATH_SYSCTL_STAT_ADD32(ctx, child, "rx_inactive", 2273 &stats->st_rx_inactive, "Inactive numbers in RX queue"); 2274 UATH_SYSCTL_STAT_ADD32(ctx, child, "tx_active", 2275 &stats->st_tx_active, "Active numbers in TX queue"); 2276 UATH_SYSCTL_STAT_ADD32(ctx, child, "tx_inactive", 2277 &stats->st_tx_inactive, "Inactive numbers in TX queue"); 2278 UATH_SYSCTL_STAT_ADD32(ctx, child, "tx_pending", 2279 &stats->st_tx_pending, "Pending numbers in TX queue"); 2280 } 2281 2282 #undef UATH_SYSCTL_STAT_ADD32 2283 2284 static void 2285 uath_cmdeof(struct uath_softc *sc, struct uath_cmd *cmd) 2286 { 2287 struct uath_cmd_hdr *hdr; 2288 int dlen; 2289 2290 hdr = (struct uath_cmd_hdr *)cmd->buf; 2291 /* NB: msgid is passed thru w/o byte swapping */ 2292 #ifdef UATH_DEBUG 2293 if (sc->sc_debug & UATH_DEBUG_CMDS) { 2294 int len = be32toh(hdr->len); 2295 printf("%s: %s [ix %u] len %u status %u\n", 2296 __func__, uath_codename(be32toh(hdr->code)), 2297 hdr->msgid, len, be32toh(hdr->magic)); 2298 if (sc->sc_debug & UATH_DEBUG_CMDS_DUMP) 2299 uath_dump_cmd(cmd->buf, 2300 len > UATH_MAX_CMDSZ ? sizeof(*hdr) : len, '-'); 2301 } 2302 #endif 2303 hdr->code = be32toh(hdr->code); 2304 hdr->len = be32toh(hdr->len); 2305 hdr->magic = be32toh(hdr->magic); /* target status on return */ 2306 2307 switch (hdr->code & 0xff) { 2308 /* reply to a read command */ 2309 default: 2310 dlen = hdr->len - sizeof(*hdr); 2311 DPRINTF(sc, UATH_DEBUG_RX_PROC | UATH_DEBUG_RECV_ALL, 2312 "%s: code %d data len %u\n", 2313 __func__, hdr->code & 0xff, dlen); 2314 /* 2315 * The first response from the target after the 2316 * HOST_AVAILABLE has an invalid msgid so we must 2317 * treat it specially. 2318 */ 2319 if (hdr->msgid < UATH_CMD_LIST_COUNT) { 2320 uint32_t *rp = (uint32_t *)(hdr+1); 2321 u_int olen; 2322 2323 if (!(sizeof(*hdr) <= hdr->len && 2324 hdr->len < UATH_MAX_CMDSZ)) { 2325 device_printf(sc->sc_dev, 2326 "%s: invalid WDC msg length %u; " 2327 "msg ignored\n", __func__, hdr->len); 2328 return; 2329 } 2330 /* 2331 * Calculate return/receive payload size; the 2332 * first word, if present, always gives the 2333 * number of bytes--unless it's 0 in which 2334 * case a single 32-bit word should be present. 2335 */ 2336 if (dlen >= sizeof(uint32_t)) { 2337 olen = be32toh(rp[0]); 2338 dlen -= sizeof(uint32_t); 2339 if (olen == 0) { 2340 /* convention is 0 =>'s one word */ 2341 olen = sizeof(uint32_t); 2342 /* XXX KASSERT(olen == dlen ) */ 2343 } 2344 } else 2345 olen = 0; 2346 if (cmd->odata != NULL) { 2347 /* NB: cmd->olen validated in uath_cmd */ 2348 if (olen > cmd->olen) { 2349 /* XXX complain? */ 2350 device_printf(sc->sc_dev, 2351 "%s: cmd 0x%x olen %u cmd olen %u\n", 2352 __func__, hdr->code, olen, 2353 cmd->olen); 2354 olen = cmd->olen; 2355 } 2356 if (olen > dlen) { 2357 /* XXX complain, shouldn't happen */ 2358 device_printf(sc->sc_dev, 2359 "%s: cmd 0x%x olen %u dlen %u\n", 2360 __func__, hdr->code, olen, dlen); 2361 olen = dlen; 2362 } 2363 /* XXX have submitter do this */ 2364 /* copy answer into caller's supplied buffer */ 2365 bcopy(&rp[1], cmd->odata, olen); 2366 cmd->olen = olen; 2367 } 2368 } 2369 wakeup_one(cmd); /* wake up caller */ 2370 break; 2371 2372 case WDCMSG_TARGET_START: 2373 if (hdr->msgid >= UATH_CMD_LIST_COUNT) { 2374 /* XXX */ 2375 return; 2376 } 2377 dlen = hdr->len - sizeof(*hdr); 2378 if (dlen != sizeof(uint32_t)) { 2379 /* XXX something wrong */ 2380 return; 2381 } 2382 /* XXX have submitter do this */ 2383 /* copy answer into caller's supplied buffer */ 2384 bcopy(hdr+1, cmd->odata, sizeof(uint32_t)); 2385 cmd->olen = sizeof(uint32_t); 2386 wakeup_one(cmd); /* wake up caller */ 2387 break; 2388 2389 case WDCMSG_SEND_COMPLETE: 2390 /* this notification is sent when UATH_TX_NOTIFY is set */ 2391 DPRINTF(sc, UATH_DEBUG_RX_PROC | UATH_DEBUG_RECV_ALL, 2392 "%s: received Tx notification\n", __func__); 2393 break; 2394 2395 case WDCMSG_TARGET_GET_STATS: 2396 DPRINTF(sc, UATH_DEBUG_RX_PROC | UATH_DEBUG_RECV_ALL, 2397 "%s: received device statistics\n", __func__); 2398 callout_reset(&sc->stat_ch, hz, uath_stat, sc); 2399 break; 2400 } 2401 } 2402 2403 static void 2404 uath_intr_rx_callback(struct usb_xfer *xfer) 2405 { 2406 struct uath_softc *sc = xfer->priv_sc; 2407 struct uath_cmd *cmd; 2408 2409 UATH_ASSERT_LOCKED(sc); 2410 2411 switch (USB_GET_STATE(xfer)) { 2412 case USB_ST_TRANSFERRED: 2413 cmd = STAILQ_FIRST(&sc->sc_cmd_waiting); 2414 if (cmd == NULL) 2415 goto setup; 2416 STAILQ_REMOVE_HEAD(&sc->sc_cmd_waiting, next); 2417 UATH_STAT_DEC(sc, st_cmd_waiting); 2418 STAILQ_INSERT_TAIL(&sc->sc_cmd_inactive, cmd, next); 2419 UATH_STAT_INC(sc, st_cmd_inactive); 2420 2421 KASSERT(xfer->actlen >= sizeof(struct uath_cmd_hdr), 2422 ("short xfer error")); 2423 usbd_copy_out(xfer->frbuffers, 0, cmd->buf, xfer->actlen); 2424 uath_cmdeof(sc, cmd); 2425 case USB_ST_SETUP: 2426 setup: 2427 xfer->frlengths[0] = xfer->max_data_length; 2428 usbd_transfer_submit(xfer); 2429 break; 2430 default: 2431 if (xfer->error != USB_ERR_CANCELLED) { 2432 xfer->flags.stall_pipe = 1; 2433 goto setup; 2434 } 2435 break; 2436 } 2437 } 2438 2439 static void 2440 uath_intr_tx_callback(struct usb_xfer *xfer) 2441 { 2442 struct uath_softc *sc = xfer->priv_sc; 2443 struct uath_cmd *cmd; 2444 2445 UATH_ASSERT_LOCKED(sc); 2446 2447 switch (USB_GET_STATE(xfer)) { 2448 case USB_ST_TRANSFERRED: 2449 cmd = STAILQ_FIRST(&sc->sc_cmd_active); 2450 if (cmd == NULL) 2451 goto setup; 2452 STAILQ_REMOVE_HEAD(&sc->sc_cmd_active, next); 2453 UATH_STAT_DEC(sc, st_cmd_active); 2454 STAILQ_INSERT_TAIL((cmd->flags & UATH_CMD_FLAG_READ) ? 2455 &sc->sc_cmd_waiting : &sc->sc_cmd_inactive, cmd, next); 2456 if (cmd->flags & UATH_CMD_FLAG_READ) 2457 UATH_STAT_INC(sc, st_cmd_waiting); 2458 else 2459 UATH_STAT_INC(sc, st_cmd_inactive); 2460 /* FALLTHROUGH */ 2461 case USB_ST_SETUP: 2462 setup: 2463 cmd = STAILQ_FIRST(&sc->sc_cmd_pending); 2464 if (cmd == NULL) { 2465 DPRINTF(sc, UATH_DEBUG_XMIT, "%s: empty pending queue\n", 2466 __func__); 2467 return; 2468 } 2469 STAILQ_REMOVE_HEAD(&sc->sc_cmd_pending, next); 2470 UATH_STAT_DEC(sc, st_cmd_pending); 2471 STAILQ_INSERT_TAIL((cmd->flags & UATH_CMD_FLAG_ASYNC) ? 2472 &sc->sc_cmd_inactive : &sc->sc_cmd_active, cmd, next); 2473 if (cmd->flags & UATH_CMD_FLAG_ASYNC) 2474 UATH_STAT_INC(sc, st_cmd_inactive); 2475 else 2476 UATH_STAT_INC(sc, st_cmd_active); 2477 2478 usbd_set_frame_data(xfer, cmd->buf, 0); 2479 xfer->frlengths[0] = cmd->buflen; 2480 usbd_transfer_submit(xfer); 2481 break; 2482 default: 2483 if (xfer->error != USB_ERR_CANCELLED) { 2484 xfer->flags.stall_pipe = 1; 2485 goto setup; 2486 } 2487 break; 2488 } 2489 } 2490 2491 static void 2492 uath_update_rxstat(struct uath_softc *sc, uint32_t status) 2493 { 2494 2495 switch (status) { 2496 case UATH_STATUS_STOP_IN_PROGRESS: 2497 UATH_STAT_INC(sc, st_stopinprogress); 2498 break; 2499 case UATH_STATUS_CRC_ERR: 2500 UATH_STAT_INC(sc, st_crcerr); 2501 break; 2502 case UATH_STATUS_PHY_ERR: 2503 UATH_STAT_INC(sc, st_phyerr); 2504 break; 2505 case UATH_STATUS_DECRYPT_CRC_ERR: 2506 UATH_STAT_INC(sc, st_decrypt_crcerr); 2507 break; 2508 case UATH_STATUS_DECRYPT_MIC_ERR: 2509 UATH_STAT_INC(sc, st_decrypt_micerr); 2510 break; 2511 case UATH_STATUS_DECOMP_ERR: 2512 UATH_STAT_INC(sc, st_decomperr); 2513 break; 2514 case UATH_STATUS_KEY_ERR: 2515 UATH_STAT_INC(sc, st_keyerr); 2516 break; 2517 case UATH_STATUS_ERR: 2518 UATH_STAT_INC(sc, st_err); 2519 break; 2520 default: 2521 break; 2522 } 2523 } 2524 2525 static struct mbuf * 2526 uath_data_rxeof(struct usb_xfer *xfer, struct uath_data *data, 2527 struct uath_rx_desc **pdesc) 2528 { 2529 struct uath_softc *sc = xfer->priv_sc; 2530 struct ifnet *ifp = sc->sc_ifp; 2531 struct ieee80211com *ic = ifp->if_l2com; 2532 struct uath_chunk *chunk; 2533 struct uath_rx_desc *desc; 2534 struct mbuf *m = data->m, *mnew, *mp; 2535 uint16_t chunklen; 2536 2537 if (xfer->actlen < UATH_MIN_RXBUFSZ) { 2538 DPRINTF(sc, UATH_DEBUG_RECV | UATH_DEBUG_RECV_ALL, 2539 "%s: wrong xfer size (len=%d)\n", __func__, xfer->actlen); 2540 ifp->if_ierrors++; 2541 return (NULL); 2542 } 2543 2544 chunk = (struct uath_chunk *)data->buf; 2545 if (chunk->seqnum == 0 && chunk->flags == 0 && chunk->length == 0) { 2546 device_printf(sc->sc_dev, "%s: strange response\n", __func__); 2547 ifp->if_ierrors++; 2548 UATH_RESET_INTRX(sc); 2549 return (NULL); 2550 } 2551 2552 if (chunk->seqnum != sc->sc_intrx_nextnum) { 2553 DPRINTF(sc, UATH_DEBUG_XMIT, "invalid seqnum %d, expected %d\n", 2554 chunk->seqnum, sc->sc_intrx_nextnum); 2555 UATH_STAT_INC(sc, st_badchunkseqnum); 2556 if (sc->sc_intrx_head != NULL) 2557 m_freem(sc->sc_intrx_head); 2558 UATH_RESET_INTRX(sc); 2559 return (NULL); 2560 } 2561 2562 /* check multi-chunk frames */ 2563 if ((chunk->seqnum == 0 && !(chunk->flags & UATH_CFLAGS_FINAL)) || 2564 (chunk->seqnum != 0 && (chunk->flags & UATH_CFLAGS_FINAL)) || 2565 chunk->flags & UATH_CFLAGS_RXMSG) 2566 UATH_STAT_INC(sc, st_multichunk); 2567 2568 chunklen = be16toh(chunk->length); 2569 if (chunk->flags & UATH_CFLAGS_FINAL) 2570 chunklen -= sizeof(struct uath_rx_desc); 2571 2572 if (chunklen > 0 && 2573 (!(chunk->flags & UATH_CFLAGS_FINAL) || !(chunk->seqnum == 0))) { 2574 /* we should use intermediate RX buffer */ 2575 if (chunk->seqnum == 0) 2576 UATH_RESET_INTRX(sc); 2577 if ((sc->sc_intrx_len + sizeof(struct uath_rx_desc) + 2578 chunklen) > UATH_MAX_INTRX_SIZE) { 2579 UATH_STAT_INC(sc, st_invalidlen); 2580 ifp->if_iqdrops++; 2581 if (sc->sc_intrx_head != NULL) 2582 m_freem(sc->sc_intrx_head); 2583 UATH_RESET_INTRX(sc); 2584 return (NULL); 2585 } 2586 2587 m->m_len = chunklen; 2588 m->m_data += sizeof(struct uath_chunk); 2589 2590 if (sc->sc_intrx_head == NULL) { 2591 sc->sc_intrx_head = m; 2592 sc->sc_intrx_tail = m; 2593 } else { 2594 m->m_flags &= ~M_PKTHDR; 2595 sc->sc_intrx_tail->m_next = m; 2596 sc->sc_intrx_tail = m; 2597 } 2598 } 2599 sc->sc_intrx_len += chunklen; 2600 2601 mnew = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2602 if (mnew == NULL) { 2603 DPRINTF(sc, UATH_DEBUG_RECV | UATH_DEBUG_RECV_ALL, 2604 "%s: can't get new mbuf, drop frame\n", __func__); 2605 ifp->if_ierrors++; 2606 if (sc->sc_intrx_head != NULL) 2607 m_freem(sc->sc_intrx_head); 2608 UATH_RESET_INTRX(sc); 2609 return (NULL); 2610 } 2611 2612 data->m = mnew; 2613 data->buf = mtod(mnew, uint8_t *); 2614 2615 /* if the frame is not final continue the transfer */ 2616 if (!(chunk->flags & UATH_CFLAGS_FINAL)) { 2617 sc->sc_intrx_nextnum++; 2618 UATH_RESET_INTRX(sc); 2619 return (NULL); 2620 } 2621 2622 /* 2623 * if the frame is not set UATH_CFLAGS_RXMSG, then rx descriptor is 2624 * located at the end, 32-bit aligned 2625 */ 2626 desc = (chunk->flags & UATH_CFLAGS_RXMSG) ? 2627 (struct uath_rx_desc *)(chunk + 1) : 2628 (struct uath_rx_desc *)(((uint8_t *)chunk) + 2629 sizeof(struct uath_chunk) + be16toh(chunk->length) - 2630 sizeof(struct uath_rx_desc)); 2631 *pdesc = desc; 2632 2633 DPRINTF(sc, UATH_DEBUG_RECV | UATH_DEBUG_RECV_ALL, 2634 "%s: frame len %u code %u status %u rate %u antenna %u " 2635 "rssi %d channel %u phyerror %u connix %u decrypterror %u " 2636 "keycachemiss %u\n", __func__, be32toh(desc->framelen) 2637 , be32toh(desc->code), be32toh(desc->status), be32toh(desc->rate) 2638 , be32toh(desc->antenna), be32toh(desc->rssi), be32toh(desc->channel) 2639 , be32toh(desc->phyerror), be32toh(desc->connix) 2640 , be32toh(desc->decrypterror), be32toh(desc->keycachemiss)); 2641 2642 if (be32toh(desc->len) > MCLBYTES) { 2643 DPRINTF(sc, UATH_DEBUG_RECV | UATH_DEBUG_RECV_ALL, 2644 "%s: bad descriptor (len=%d)\n", __func__, 2645 be32toh(desc->len)); 2646 ifp->if_iqdrops++; 2647 UATH_STAT_INC(sc, st_toobigrxpkt); 2648 if (sc->sc_intrx_head != NULL) 2649 m_freem(sc->sc_intrx_head); 2650 UATH_RESET_INTRX(sc); 2651 return (NULL); 2652 } 2653 2654 uath_update_rxstat(sc, be32toh(desc->status)); 2655 2656 /* finalize mbuf */ 2657 if (sc->sc_intrx_head == NULL) { 2658 m->m_pkthdr.rcvif = ifp; 2659 m->m_pkthdr.len = m->m_len = 2660 be32toh(desc->framelen) - UATH_RX_DUMMYSIZE; 2661 m->m_data += sizeof(struct uath_chunk); 2662 } else { 2663 mp = sc->sc_intrx_head; 2664 mp->m_pkthdr.rcvif = ifp; 2665 mp->m_flags |= M_PKTHDR; 2666 mp->m_pkthdr.len = sc->sc_intrx_len; 2667 m = mp; 2668 } 2669 2670 /* there are a lot more fields in the RX descriptor */ 2671 if ((sc->sc_flags & UATH_FLAG_INVALID) == 0 && 2672 ieee80211_radiotap_active(ic)) { 2673 struct uath_rx_radiotap_header *tap = &sc->sc_rxtap; 2674 uint32_t tsf_hi = be32toh(desc->tstamp_high); 2675 uint32_t tsf_lo = be32toh(desc->tstamp_low); 2676 2677 /* XXX only get low order 24bits of tsf from h/w */ 2678 tap->wr_tsf = htole64(((uint64_t)tsf_hi << 32) | tsf_lo); 2679 tap->wr_flags = 0; 2680 if (be32toh(desc->status) == UATH_STATUS_CRC_ERR) 2681 tap->wr_flags |= IEEE80211_RADIOTAP_F_BADFCS; 2682 /* XXX map other status to BADFCS? */ 2683 /* XXX ath h/w rate code, need to map */ 2684 tap->wr_rate = be32toh(desc->rate); 2685 tap->wr_antenna = be32toh(desc->antenna); 2686 tap->wr_antsignal = -95 + be32toh(desc->rssi); 2687 tap->wr_antnoise = -95; 2688 } 2689 2690 ifp->if_ipackets++; 2691 UATH_RESET_INTRX(sc); 2692 2693 return (m); 2694 } 2695 2696 static void 2697 uath_bulk_rx_callback(struct usb_xfer *xfer) 2698 { 2699 struct uath_softc *sc = xfer->priv_sc; 2700 struct ifnet *ifp = sc->sc_ifp; 2701 struct ieee80211com *ic = ifp->if_l2com; 2702 struct ieee80211_frame *wh; 2703 struct ieee80211_node *ni; 2704 struct mbuf *m = NULL; 2705 struct uath_data *data; 2706 struct uath_rx_desc *desc = NULL; 2707 int8_t nf; 2708 2709 UATH_ASSERT_LOCKED(sc); 2710 2711 switch (USB_GET_STATE(xfer)) { 2712 case USB_ST_TRANSFERRED: 2713 data = STAILQ_FIRST(&sc->sc_rx_active); 2714 if (data == NULL) 2715 goto setup; 2716 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 2717 UATH_STAT_DEC(sc, st_rx_active); 2718 m = uath_data_rxeof(xfer, data, &desc); 2719 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 2720 UATH_STAT_INC(sc, st_rx_inactive); 2721 /* FALLTHROUGH */ 2722 case USB_ST_SETUP: 2723 setup: 2724 data = STAILQ_FIRST(&sc->sc_rx_inactive); 2725 if (data == NULL) 2726 return; 2727 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 2728 UATH_STAT_DEC(sc, st_rx_inactive); 2729 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 2730 UATH_STAT_INC(sc, st_rx_active); 2731 usbd_set_frame_data(xfer, data->buf, 0); 2732 xfer->frlengths[0] = xfer->max_data_length; 2733 usbd_transfer_submit(xfer); 2734 2735 /* 2736 * To avoid LOR we should unlock our private mutex here to call 2737 * ieee80211_input() because here is at the end of a USB 2738 * callback and safe to unlock. 2739 */ 2740 if (sc->sc_flags & UATH_FLAG_INVALID) { 2741 if (m != NULL) 2742 m_freem(m); 2743 return; 2744 } 2745 UATH_UNLOCK(sc); 2746 if (m != NULL && desc != NULL) { 2747 wh = mtod(m, struct ieee80211_frame *); 2748 ni = ieee80211_find_rxnode(ic, 2749 (struct ieee80211_frame_min *)wh); 2750 nf = -95; /* XXX */ 2751 if (ni != NULL) { 2752 (void) ieee80211_input(ni, m, 2753 (int)be32toh(desc->rssi), nf); 2754 /* node is no longer needed */ 2755 ieee80211_free_node(ni); 2756 } else 2757 (void) ieee80211_input_all(ic, m, 2758 (int)be32toh(desc->rssi), nf); 2759 m = NULL; 2760 desc = NULL; 2761 } 2762 UATH_LOCK(sc); 2763 break; 2764 default: 2765 /* needs it to the inactive queue due to a error. */ 2766 data = STAILQ_FIRST(&sc->sc_rx_active); 2767 if (data != NULL) { 2768 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 2769 UATH_STAT_DEC(sc, st_rx_active); 2770 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 2771 UATH_STAT_INC(sc, st_rx_inactive); 2772 } 2773 if (xfer->error != USB_ERR_CANCELLED) { 2774 xfer->flags.stall_pipe = 1; 2775 ifp->if_ierrors++; 2776 goto setup; 2777 } 2778 break; 2779 } 2780 } 2781 2782 static void 2783 uath_data_txeof(struct usb_xfer *xfer, struct uath_data *data) 2784 { 2785 struct uath_softc *sc = xfer->priv_sc; 2786 struct ifnet *ifp = sc->sc_ifp; 2787 struct mbuf *m; 2788 2789 UATH_ASSERT_LOCKED(sc); 2790 2791 /* 2792 * Do any tx complete callback. Note this must be done before releasing 2793 * the node reference. 2794 */ 2795 if (data->m) { 2796 m = data->m; 2797 if (m->m_flags & M_TXCB && 2798 (sc->sc_flags & UATH_FLAG_INVALID) == 0) { 2799 /* XXX status? */ 2800 ieee80211_process_callback(data->ni, m, 0); 2801 } 2802 m_freem(m); 2803 data->m = NULL; 2804 } 2805 if (data->ni) { 2806 if ((sc->sc_flags & UATH_FLAG_INVALID) == 0) 2807 ieee80211_free_node(data->ni); 2808 data->ni = NULL; 2809 } 2810 sc->sc_tx_timer = 0; 2811 ifp->if_opackets++; 2812 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2813 } 2814 2815 static void 2816 uath_bulk_tx_callback(struct usb_xfer *xfer) 2817 { 2818 struct uath_softc *sc = xfer->priv_sc; 2819 struct ifnet *ifp = sc->sc_ifp; 2820 struct uath_data *data; 2821 2822 UATH_ASSERT_LOCKED(sc); 2823 2824 switch (USB_GET_STATE(xfer)) { 2825 case USB_ST_TRANSFERRED: 2826 data = STAILQ_FIRST(&sc->sc_tx_active); 2827 if (data == NULL) 2828 goto setup; 2829 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 2830 UATH_STAT_DEC(sc, st_tx_active); 2831 uath_data_txeof(xfer, data); 2832 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 2833 UATH_STAT_INC(sc, st_tx_inactive); 2834 /* FALLTHROUGH */ 2835 case USB_ST_SETUP: 2836 setup: 2837 data = STAILQ_FIRST(&sc->sc_tx_pending); 2838 if (data == NULL) { 2839 DPRINTF(sc, UATH_DEBUG_XMIT, "%s: empty pending queue\n", 2840 __func__); 2841 return; 2842 } 2843 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 2844 UATH_STAT_DEC(sc, st_tx_pending); 2845 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 2846 UATH_STAT_INC(sc, st_tx_active); 2847 2848 usbd_set_frame_data(xfer, data->buf, 0); 2849 xfer->frlengths[0] = data->buflen; 2850 usbd_transfer_submit(xfer); 2851 2852 UATH_UNLOCK(sc); 2853 uath_start(ifp); 2854 UATH_LOCK(sc); 2855 break; 2856 default: 2857 data = STAILQ_FIRST(&sc->sc_tx_active); 2858 if (data == NULL) 2859 goto setup; 2860 if (data->ni != NULL) { 2861 if ((sc->sc_flags & UATH_FLAG_INVALID) == 0) 2862 ieee80211_free_node(data->ni); 2863 data->ni = NULL; 2864 ifp->if_oerrors++; 2865 } 2866 if (xfer->error != USB_ERR_CANCELLED) { 2867 xfer->flags.stall_pipe = 1; 2868 goto setup; 2869 } 2870 break; 2871 } 2872 } 2873 2874 static device_method_t uath_methods[] = { 2875 DEVMETHOD(device_probe, uath_match), 2876 DEVMETHOD(device_attach, uath_attach), 2877 DEVMETHOD(device_detach, uath_detach), 2878 { 0, 0 } 2879 }; 2880 static driver_t uath_driver = { 2881 "uath", 2882 uath_methods, 2883 sizeof(struct uath_softc) 2884 }; 2885 static devclass_t uath_devclass; 2886 2887 DRIVER_MODULE(uath, uhub, uath_driver, uath_devclass, NULL, 0); 2888 MODULE_DEPEND(uath, wlan, 1, 1, 1); 2889 MODULE_DEPEND(uath, usb, 1, 1, 1); 2890