1 /*- 2 * Copyright (c) 2015-2016 Kevin Lo <kevlo@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/condvar.h> 34 #include <sys/kernel.h> 35 #include <sys/lock.h> 36 #include <sys/module.h> 37 #include <sys/mutex.h> 38 #include <sys/sbuf.h> 39 #include <sys/socket.h> 40 #include <sys/sysctl.h> 41 #include <sys/unistd.h> 42 43 #include <net/if.h> 44 #include <net/if_var.h> 45 #include <net/if_media.h> 46 47 /* needed for checksum offload */ 48 #include <netinet/in.h> 49 #include <netinet/ip.h> 50 51 #include <dev/mii/mii.h> 52 #include <dev/mii/miivar.h> 53 54 #include <dev/usb/usb.h> 55 #include <dev/usb/usbdi.h> 56 #include <dev/usb/usbdi_util.h> 57 #include "usbdevs.h" 58 59 #define USB_DEBUG_VAR ure_debug 60 #include <dev/usb/usb_debug.h> 61 #include <dev/usb/usb_process.h> 62 63 #include <dev/usb/net/usb_ethernet.h> 64 #include <dev/usb/net/if_urereg.h> 65 66 #include "miibus_if.h" 67 68 #include "opt_inet6.h" 69 70 #ifdef USB_DEBUG 71 static int ure_debug = 0; 72 73 static SYSCTL_NODE(_hw_usb, OID_AUTO, ure, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 74 "USB ure"); 75 SYSCTL_INT(_hw_usb_ure, OID_AUTO, debug, CTLFLAG_RWTUN, &ure_debug, 0, 76 "Debug level"); 77 #endif 78 79 #ifdef USB_DEBUG_VAR 80 #ifdef USB_DEBUG 81 #define DEVPRINTFN(n,dev,fmt,...) do { \ 82 if ((USB_DEBUG_VAR) >= (n)) { \ 83 device_printf((dev), "%s: " fmt, \ 84 __FUNCTION__ ,##__VA_ARGS__); \ 85 } \ 86 } while (0) 87 #define DEVPRINTF(...) DEVPRINTFN(1, __VA_ARGS__) 88 #else 89 #define DEVPRINTF(...) do { } while (0) 90 #define DEVPRINTFN(...) do { } while (0) 91 #endif 92 #endif 93 94 /* 95 * Various supported device vendors/products. 96 */ 97 static const STRUCT_USB_HOST_ID ure_devs[] = { 98 #define URE_DEV(v,p,i) { \ 99 USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i), \ 100 USB_IFACE_CLASS(UICLASS_VENDOR), \ 101 USB_IFACE_SUBCLASS(UISUBCLASS_VENDOR) } 102 URE_DEV(LENOVO, RTL8153, URE_FLAG_8153), 103 URE_DEV(LENOVO, TBT3LAN, 0), 104 URE_DEV(LENOVO, TBT3LANGEN2, 0), 105 URE_DEV(LENOVO, ONELINK, 0), 106 URE_DEV(LENOVO, USBCLAN, 0), 107 URE_DEV(LENOVO, USBCLANGEN2, 0), 108 URE_DEV(NVIDIA, RTL8153, URE_FLAG_8153), 109 URE_DEV(REALTEK, RTL8152, URE_FLAG_8152), 110 URE_DEV(REALTEK, RTL8153, URE_FLAG_8153), 111 URE_DEV(TPLINK, RTL8153, URE_FLAG_8153), 112 URE_DEV(REALTEK, RTL8156, URE_FLAG_8156), 113 #undef URE_DEV 114 }; 115 116 static device_probe_t ure_probe; 117 static device_attach_t ure_attach; 118 static device_detach_t ure_detach; 119 120 static usb_callback_t ure_bulk_read_callback; 121 static usb_callback_t ure_bulk_write_callback; 122 123 static miibus_readreg_t ure_miibus_readreg; 124 static miibus_writereg_t ure_miibus_writereg; 125 static miibus_statchg_t ure_miibus_statchg; 126 127 static uether_fn_t ure_attach_post; 128 static uether_fn_t ure_init; 129 static uether_fn_t ure_stop; 130 static uether_fn_t ure_start; 131 static uether_fn_t ure_tick; 132 static uether_fn_t ure_rxfilter; 133 134 static int ure_ctl(struct ure_softc *, uint8_t, uint16_t, uint16_t, 135 void *, int); 136 static int ure_read_mem(struct ure_softc *, uint16_t, uint16_t, void *, 137 int); 138 static int ure_write_mem(struct ure_softc *, uint16_t, uint16_t, void *, 139 int); 140 static uint8_t ure_read_1(struct ure_softc *, uint16_t, uint16_t); 141 static uint16_t ure_read_2(struct ure_softc *, uint16_t, uint16_t); 142 static uint32_t ure_read_4(struct ure_softc *, uint16_t, uint16_t); 143 static int ure_write_1(struct ure_softc *, uint16_t, uint16_t, uint32_t); 144 static int ure_write_2(struct ure_softc *, uint16_t, uint16_t, uint32_t); 145 static int ure_write_4(struct ure_softc *, uint16_t, uint16_t, uint32_t); 146 static uint16_t ure_ocp_reg_read(struct ure_softc *, uint16_t); 147 static void ure_ocp_reg_write(struct ure_softc *, uint16_t, uint16_t); 148 static void ure_sram_write(struct ure_softc *, uint16_t, uint16_t); 149 150 static int ure_sysctl_chipver(SYSCTL_HANDLER_ARGS); 151 152 static void ure_read_chipver(struct ure_softc *); 153 static int ure_attach_post_sub(struct usb_ether *); 154 static void ure_reset(struct ure_softc *); 155 static int ure_ifmedia_upd(struct ifnet *); 156 static void ure_ifmedia_sts(struct ifnet *, struct ifmediareq *); 157 static void ure_add_media_types(struct ure_softc *); 158 static void ure_link_state(struct ure_softc *sc); 159 static int ure_get_link_status(struct ure_softc *); 160 static int ure_ioctl(struct ifnet *, u_long, caddr_t); 161 static void ure_rtl8152_init(struct ure_softc *); 162 static void ure_rtl8152_nic_reset(struct ure_softc *); 163 static void ure_rtl8153_init(struct ure_softc *); 164 static void ure_rtl8153b_init(struct ure_softc *); 165 static void ure_rtl8153b_nic_reset(struct ure_softc *); 166 static void ure_disable_teredo(struct ure_softc *); 167 static void ure_enable_aldps(struct ure_softc *, bool); 168 static uint16_t ure_phy_status(struct ure_softc *, uint16_t); 169 static void ure_rxcsum(int capenb, struct ure_rxpkt *rp, struct mbuf *m); 170 static int ure_txcsum(struct mbuf *m, int caps, uint32_t *regout); 171 172 static device_method_t ure_methods[] = { 173 /* Device interface. */ 174 DEVMETHOD(device_probe, ure_probe), 175 DEVMETHOD(device_attach, ure_attach), 176 DEVMETHOD(device_detach, ure_detach), 177 178 /* MII interface. */ 179 DEVMETHOD(miibus_readreg, ure_miibus_readreg), 180 DEVMETHOD(miibus_writereg, ure_miibus_writereg), 181 DEVMETHOD(miibus_statchg, ure_miibus_statchg), 182 183 DEVMETHOD_END 184 }; 185 186 static driver_t ure_driver = { 187 .name = "ure", 188 .methods = ure_methods, 189 .size = sizeof(struct ure_softc), 190 }; 191 192 DRIVER_MODULE(ure, uhub, ure_driver, NULL, NULL); 193 DRIVER_MODULE(miibus, ure, miibus_driver, NULL, NULL); 194 MODULE_DEPEND(ure, uether, 1, 1, 1); 195 MODULE_DEPEND(ure, usb, 1, 1, 1); 196 MODULE_DEPEND(ure, ether, 1, 1, 1); 197 MODULE_DEPEND(ure, miibus, 1, 1, 1); 198 MODULE_VERSION(ure, 1); 199 USB_PNP_HOST_INFO(ure_devs); 200 201 static const struct usb_ether_methods ure_ue_methods = { 202 .ue_attach_post = ure_attach_post, 203 .ue_attach_post_sub = ure_attach_post_sub, 204 .ue_start = ure_start, 205 .ue_init = ure_init, 206 .ue_stop = ure_stop, 207 .ue_tick = ure_tick, 208 .ue_setmulti = ure_rxfilter, 209 .ue_setpromisc = ure_rxfilter, 210 .ue_mii_upd = ure_ifmedia_upd, 211 .ue_mii_sts = ure_ifmedia_sts, 212 }; 213 214 #define URE_SETBIT_1(sc, reg, index, x) \ 215 ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) | (x)) 216 #define URE_SETBIT_2(sc, reg, index, x) \ 217 ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) | (x)) 218 #define URE_SETBIT_4(sc, reg, index, x) \ 219 ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) | (x)) 220 221 #define URE_CLRBIT_1(sc, reg, index, x) \ 222 ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) & ~(x)) 223 #define URE_CLRBIT_2(sc, reg, index, x) \ 224 ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) & ~(x)) 225 #define URE_CLRBIT_4(sc, reg, index, x) \ 226 ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) & ~(x)) 227 228 static int 229 ure_ctl(struct ure_softc *sc, uint8_t rw, uint16_t val, uint16_t index, 230 void *buf, int len) 231 { 232 struct usb_device_request req; 233 234 URE_LOCK_ASSERT(sc, MA_OWNED); 235 236 if (rw == URE_CTL_WRITE) 237 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 238 else 239 req.bmRequestType = UT_READ_VENDOR_DEVICE; 240 req.bRequest = UR_SET_ADDRESS; 241 USETW(req.wValue, val); 242 USETW(req.wIndex, index); 243 USETW(req.wLength, len); 244 245 return (uether_do_request(&sc->sc_ue, &req, buf, 1000)); 246 } 247 248 static int 249 ure_read_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, 250 void *buf, int len) 251 { 252 253 return (ure_ctl(sc, URE_CTL_READ, addr, index, buf, len)); 254 } 255 256 static int 257 ure_write_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, 258 void *buf, int len) 259 { 260 261 return (ure_ctl(sc, URE_CTL_WRITE, addr, index, buf, len)); 262 } 263 264 static uint8_t 265 ure_read_1(struct ure_softc *sc, uint16_t reg, uint16_t index) 266 { 267 uint32_t val; 268 uint8_t temp[4]; 269 uint8_t shift; 270 271 shift = (reg & 3) << 3; 272 reg &= ~3; 273 274 ure_read_mem(sc, reg, index, &temp, 4); 275 val = UGETDW(temp); 276 val >>= shift; 277 278 return (val & 0xff); 279 } 280 281 static uint16_t 282 ure_read_2(struct ure_softc *sc, uint16_t reg, uint16_t index) 283 { 284 uint32_t val; 285 uint8_t temp[4]; 286 uint8_t shift; 287 288 shift = (reg & 2) << 3; 289 reg &= ~3; 290 291 ure_read_mem(sc, reg, index, &temp, 4); 292 val = UGETDW(temp); 293 val >>= shift; 294 295 return (val & 0xffff); 296 } 297 298 static uint32_t 299 ure_read_4(struct ure_softc *sc, uint16_t reg, uint16_t index) 300 { 301 uint8_t temp[4]; 302 303 ure_read_mem(sc, reg, index, &temp, 4); 304 return (UGETDW(temp)); 305 } 306 307 static int 308 ure_write_1(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 309 { 310 uint16_t byen; 311 uint8_t temp[4]; 312 uint8_t shift; 313 314 byen = URE_BYTE_EN_BYTE; 315 shift = reg & 3; 316 val &= 0xff; 317 318 if (reg & 3) { 319 byen <<= shift; 320 val <<= (shift << 3); 321 reg &= ~3; 322 } 323 324 USETDW(temp, val); 325 return (ure_write_mem(sc, reg, index | byen, &temp, 4)); 326 } 327 328 static int 329 ure_write_2(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 330 { 331 uint16_t byen; 332 uint8_t temp[4]; 333 uint8_t shift; 334 335 byen = URE_BYTE_EN_WORD; 336 shift = reg & 2; 337 val &= 0xffff; 338 339 if (reg & 2) { 340 byen <<= shift; 341 val <<= (shift << 3); 342 reg &= ~3; 343 } 344 345 USETDW(temp, val); 346 return (ure_write_mem(sc, reg, index | byen, &temp, 4)); 347 } 348 349 static int 350 ure_write_4(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 351 { 352 uint8_t temp[4]; 353 354 USETDW(temp, val); 355 return (ure_write_mem(sc, reg, index | URE_BYTE_EN_DWORD, &temp, 4)); 356 } 357 358 static uint16_t 359 ure_ocp_reg_read(struct ure_softc *sc, uint16_t addr) 360 { 361 uint16_t reg; 362 363 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 364 reg = (addr & 0x0fff) | 0xb000; 365 366 return (ure_read_2(sc, reg, URE_MCU_TYPE_PLA)); 367 } 368 369 static void 370 ure_ocp_reg_write(struct ure_softc *sc, uint16_t addr, uint16_t data) 371 { 372 uint16_t reg; 373 374 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 375 reg = (addr & 0x0fff) | 0xb000; 376 377 ure_write_2(sc, reg, URE_MCU_TYPE_PLA, data); 378 } 379 380 static void 381 ure_sram_write(struct ure_softc *sc, uint16_t addr, uint16_t data) 382 { 383 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, addr); 384 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, data); 385 } 386 387 static int 388 ure_miibus_readreg(device_t dev, int phy, int reg) 389 { 390 struct ure_softc *sc; 391 uint16_t val; 392 int locked; 393 394 sc = device_get_softc(dev); 395 locked = mtx_owned(&sc->sc_mtx); 396 if (!locked) 397 URE_LOCK(sc); 398 399 /* Let the rgephy driver read the URE_GMEDIASTAT register. */ 400 if (reg == URE_GMEDIASTAT) { 401 if (!locked) 402 URE_UNLOCK(sc); 403 return (ure_read_1(sc, URE_GMEDIASTAT, URE_MCU_TYPE_PLA)); 404 } 405 406 val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + reg * 2); 407 408 if (!locked) 409 URE_UNLOCK(sc); 410 return (val); 411 } 412 413 static int 414 ure_miibus_writereg(device_t dev, int phy, int reg, int val) 415 { 416 struct ure_softc *sc; 417 int locked; 418 419 sc = device_get_softc(dev); 420 if (sc->sc_phyno != phy) 421 return (0); 422 423 locked = mtx_owned(&sc->sc_mtx); 424 if (!locked) 425 URE_LOCK(sc); 426 427 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + reg * 2, val); 428 429 if (!locked) 430 URE_UNLOCK(sc); 431 return (0); 432 } 433 434 static void 435 ure_miibus_statchg(device_t dev) 436 { 437 struct ure_softc *sc; 438 struct mii_data *mii; 439 struct ifnet *ifp; 440 int locked; 441 442 sc = device_get_softc(dev); 443 mii = GET_MII(sc); 444 locked = mtx_owned(&sc->sc_mtx); 445 if (!locked) 446 URE_LOCK(sc); 447 448 ifp = uether_getifp(&sc->sc_ue); 449 if (mii == NULL || ifp == NULL || 450 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 451 goto done; 452 453 sc->sc_flags &= ~URE_FLAG_LINK; 454 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 455 (IFM_ACTIVE | IFM_AVALID)) { 456 switch (IFM_SUBTYPE(mii->mii_media_active)) { 457 case IFM_10_T: 458 case IFM_100_TX: 459 sc->sc_flags |= URE_FLAG_LINK; 460 sc->sc_rxstarted = 0; 461 break; 462 case IFM_1000_T: 463 if ((sc->sc_flags & URE_FLAG_8152) != 0) 464 break; 465 sc->sc_flags |= URE_FLAG_LINK; 466 sc->sc_rxstarted = 0; 467 break; 468 default: 469 break; 470 } 471 } 472 473 /* Lost link, do nothing. */ 474 if ((sc->sc_flags & URE_FLAG_LINK) == 0) 475 goto done; 476 done: 477 if (!locked) 478 URE_UNLOCK(sc); 479 } 480 481 /* 482 * Probe for a RTL8152/RTL8153 chip. 483 */ 484 static int 485 ure_probe(device_t dev) 486 { 487 struct usb_attach_arg *uaa; 488 489 uaa = device_get_ivars(dev); 490 if (uaa->usb_mode != USB_MODE_HOST) 491 return (ENXIO); 492 if (uaa->info.bIfaceIndex != URE_IFACE_IDX) 493 return (ENXIO); 494 495 return (usbd_lookup_id_by_uaa(ure_devs, sizeof(ure_devs), uaa)); 496 } 497 498 /* 499 * Attach the interface. Allocate softc structures, do ifmedia 500 * setup and ethernet/BPF attach. 501 */ 502 static int 503 ure_attach(device_t dev) 504 { 505 struct usb_attach_arg *uaa = device_get_ivars(dev); 506 struct ure_softc *sc = device_get_softc(dev); 507 struct usb_ether *ue = &sc->sc_ue; 508 struct usb_config ure_config_rx[URE_MAX_RX]; 509 struct usb_config ure_config_tx[URE_MAX_TX]; 510 uint8_t iface_index; 511 int error; 512 int i; 513 514 sc->sc_flags = USB_GET_DRIVER_INFO(uaa); 515 device_set_usb_desc(dev); 516 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 517 518 iface_index = URE_IFACE_IDX; 519 520 if (sc->sc_flags & (URE_FLAG_8153 | URE_FLAG_8153B)) 521 sc->sc_rxbufsz = URE_8153_RX_BUFSZ; 522 else if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) 523 sc->sc_rxbufsz = URE_8156_RX_BUFSZ; 524 else 525 sc->sc_rxbufsz = URE_8152_RX_BUFSZ; 526 527 for (i = 0; i < URE_MAX_RX; i++) { 528 ure_config_rx[i] = (struct usb_config) { 529 .type = UE_BULK, 530 .endpoint = UE_ADDR_ANY, 531 .direction = UE_DIR_IN, 532 .bufsize = sc->sc_rxbufsz, 533 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 534 .callback = ure_bulk_read_callback, 535 .timeout = 0, /* no timeout */ 536 }; 537 } 538 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_rx_xfer, 539 ure_config_rx, URE_MAX_RX, sc, &sc->sc_mtx); 540 if (error != 0) { 541 device_printf(dev, "allocating USB RX transfers failed\n"); 542 goto detach; 543 } 544 545 for (i = 0; i < URE_MAX_TX; i++) { 546 ure_config_tx[i] = (struct usb_config) { 547 .type = UE_BULK, 548 .endpoint = UE_ADDR_ANY, 549 .direction = UE_DIR_OUT, 550 .bufsize = URE_TX_BUFSZ, 551 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 552 .callback = ure_bulk_write_callback, 553 .timeout = 10000, /* 10 seconds */ 554 }; 555 } 556 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_tx_xfer, 557 ure_config_tx, URE_MAX_TX, sc, &sc->sc_mtx); 558 if (error != 0) { 559 usbd_transfer_unsetup(sc->sc_rx_xfer, URE_MAX_RX); 560 device_printf(dev, "allocating USB TX transfers failed\n"); 561 goto detach; 562 } 563 564 ue->ue_sc = sc; 565 ue->ue_dev = dev; 566 ue->ue_udev = uaa->device; 567 ue->ue_mtx = &sc->sc_mtx; 568 ue->ue_methods = &ure_ue_methods; 569 570 error = uether_ifattach(ue); 571 if (error != 0) { 572 device_printf(dev, "could not attach interface\n"); 573 goto detach; 574 } 575 return (0); /* success */ 576 577 detach: 578 ure_detach(dev); 579 return (ENXIO); /* failure */ 580 } 581 582 static int 583 ure_detach(device_t dev) 584 { 585 struct ure_softc *sc = device_get_softc(dev); 586 struct usb_ether *ue = &sc->sc_ue; 587 588 usbd_transfer_unsetup(sc->sc_tx_xfer, URE_MAX_TX); 589 usbd_transfer_unsetup(sc->sc_rx_xfer, URE_MAX_RX); 590 uether_ifdetach(ue); 591 mtx_destroy(&sc->sc_mtx); 592 593 return (0); 594 } 595 596 /* 597 * Copy from USB buffers to a new mbuf chain with pkt header. 598 * 599 * This will use m_getm2 to get a mbuf chain w/ properly sized mbuf 600 * clusters as necessary. 601 */ 602 static struct mbuf * 603 ure_makembuf(struct usb_page_cache *pc, usb_frlength_t offset, 604 usb_frlength_t len) 605 { 606 struct usb_page_search_res; 607 struct mbuf *m, *mb; 608 usb_frlength_t tlen; 609 610 m = m_getm2(NULL, len + ETHER_ALIGN, M_NOWAIT, MT_DATA, M_PKTHDR); 611 if (m == NULL) 612 return (m); 613 614 /* uether_newbuf does this. */ 615 m_adj(m, ETHER_ALIGN); 616 617 m->m_pkthdr.len = len; 618 619 for (mb = m; len > 0; mb = mb->m_next) { 620 tlen = MIN(len, M_TRAILINGSPACE(mb)); 621 622 usbd_copy_out(pc, offset, mtod(mb, uint8_t *), tlen); 623 mb->m_len = tlen; 624 625 offset += tlen; 626 len -= tlen; 627 } 628 629 return (m); 630 } 631 632 static void 633 ure_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) 634 { 635 struct ure_softc *sc = usbd_xfer_softc(xfer); 636 struct usb_ether *ue = &sc->sc_ue; 637 struct ifnet *ifp = uether_getifp(ue); 638 struct usb_page_cache *pc; 639 struct mbuf *m; 640 struct ure_rxpkt pkt; 641 int actlen, off, len; 642 int caps; 643 uint32_t pktcsum; 644 645 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 646 647 switch (USB_GET_STATE(xfer)) { 648 case USB_ST_TRANSFERRED: 649 off = 0; 650 pc = usbd_xfer_get_frame(xfer, 0); 651 caps = if_getcapenable(ifp); 652 DEVPRINTFN(13, sc->sc_ue.ue_dev, "rcb start\n"); 653 while (actlen > 0) { 654 if (actlen < (int)(sizeof(pkt))) { 655 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 656 goto tr_setup; 657 } 658 usbd_copy_out(pc, off, &pkt, sizeof(pkt)); 659 660 off += sizeof(pkt); 661 actlen -= sizeof(pkt); 662 663 len = le32toh(pkt.ure_pktlen) & URE_RXPKT_LEN_MASK; 664 665 DEVPRINTFN(13, sc->sc_ue.ue_dev, 666 "rxpkt: %#x, %#x, %#x, %#x, %#x, %#x\n", 667 pkt.ure_pktlen, pkt.ure_csum, pkt.ure_misc, 668 pkt.ure_rsvd2, pkt.ure_rsvd3, pkt.ure_rsvd4); 669 DEVPRINTFN(13, sc->sc_ue.ue_dev, "len: %d\n", len); 670 671 if (len >= URE_RXPKT_LEN_MASK) { 672 /* 673 * drop the rest of this segment. With out 674 * more information, we cannot know where next 675 * packet starts. Blindly continuing would 676 * cause a packet in packet attack, allowing 677 * one VLAN to inject packets w/o a VLAN tag, 678 * or injecting packets into other VLANs. 679 */ 680 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 681 goto tr_setup; 682 } 683 684 if (actlen < len) { 685 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 686 goto tr_setup; 687 } 688 689 if (len >= (ETHER_HDR_LEN + ETHER_CRC_LEN)) 690 m = ure_makembuf(pc, off, len - ETHER_CRC_LEN); 691 else 692 m = NULL; 693 if (m == NULL) { 694 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 695 } else { 696 /* make mbuf and queue */ 697 pktcsum = le32toh(pkt.ure_csum); 698 if (caps & IFCAP_VLAN_HWTAGGING && 699 pktcsum & URE_RXPKT_RX_VLAN_TAG) { 700 m->m_pkthdr.ether_vtag = 701 bswap16(pktcsum & 702 URE_RXPKT_VLAN_MASK); 703 m->m_flags |= M_VLANTAG; 704 } 705 706 /* set the necessary flags for rx checksum */ 707 ure_rxcsum(caps, &pkt, m); 708 709 uether_rxmbuf(ue, m, len - ETHER_CRC_LEN); 710 } 711 712 off += roundup(len, URE_RXPKT_ALIGN); 713 actlen -= roundup(len, URE_RXPKT_ALIGN); 714 } 715 DEVPRINTFN(13, sc->sc_ue.ue_dev, "rcb end\n"); 716 717 /* FALLTHROUGH */ 718 case USB_ST_SETUP: 719 tr_setup: 720 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 721 usbd_transfer_submit(xfer); 722 uether_rxflush(ue); 723 return; 724 725 default: /* Error */ 726 DPRINTF("bulk read error, %s\n", 727 usbd_errstr(error)); 728 729 if (error != USB_ERR_CANCELLED) { 730 /* try to clear stall first */ 731 usbd_xfer_set_stall(xfer); 732 goto tr_setup; 733 } 734 return; 735 } 736 } 737 738 static void 739 ure_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) 740 { 741 struct ure_softc *sc = usbd_xfer_softc(xfer); 742 struct ifnet *ifp = uether_getifp(&sc->sc_ue); 743 struct usb_page_cache *pc; 744 struct mbuf *m; 745 struct ure_txpkt txpkt; 746 uint32_t regtmp; 747 int len, pos; 748 int rem; 749 int caps; 750 751 switch (USB_GET_STATE(xfer)) { 752 case USB_ST_TRANSFERRED: 753 DPRINTFN(11, "transfer complete\n"); 754 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 755 756 /* FALLTHROUGH */ 757 case USB_ST_SETUP: 758 tr_setup: 759 if ((sc->sc_flags & URE_FLAG_LINK) == 0) { 760 /* don't send anything if there is no link! */ 761 break; 762 } 763 764 pc = usbd_xfer_get_frame(xfer, 0); 765 caps = if_getcapenable(ifp); 766 767 pos = 0; 768 rem = URE_TX_BUFSZ; 769 while (rem > sizeof(txpkt)) { 770 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 771 if (m == NULL) 772 break; 773 774 /* 775 * make sure we don't ever send too large of a 776 * packet 777 */ 778 len = m->m_pkthdr.len; 779 if ((len & URE_TXPKT_LEN_MASK) != len) { 780 device_printf(sc->sc_ue.ue_dev, 781 "pkt len too large: %#x", len); 782 pkterror: 783 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 784 m_freem(m); 785 continue; 786 } 787 788 if (sizeof(txpkt) + 789 roundup(len, URE_TXPKT_ALIGN) > rem) { 790 /* out of space */ 791 IFQ_DRV_PREPEND(&ifp->if_snd, m); 792 m = NULL; 793 break; 794 } 795 796 txpkt = (struct ure_txpkt){}; 797 txpkt.ure_pktlen = htole32((len & URE_TXPKT_LEN_MASK) | 798 URE_TKPKT_TX_FS | URE_TKPKT_TX_LS); 799 if (m->m_flags & M_VLANTAG) { 800 txpkt.ure_csum = htole32( 801 bswap16(m->m_pkthdr.ether_vtag & 802 URE_TXPKT_VLAN_MASK) | URE_TXPKT_VLAN); 803 } 804 if (ure_txcsum(m, caps, ®tmp)) { 805 device_printf(sc->sc_ue.ue_dev, 806 "pkt l4 off too large"); 807 goto pkterror; 808 } 809 txpkt.ure_csum |= htole32(regtmp); 810 811 DEVPRINTFN(13, sc->sc_ue.ue_dev, 812 "txpkt: mbflg: %#x, %#x, %#x\n", 813 m->m_pkthdr.csum_flags, le32toh(txpkt.ure_pktlen), 814 le32toh(txpkt.ure_csum)); 815 816 usbd_copy_in(pc, pos, &txpkt, sizeof(txpkt)); 817 818 pos += sizeof(txpkt); 819 rem -= sizeof(txpkt); 820 821 usbd_m_copy_in(pc, pos, m, 0, len); 822 823 pos += roundup(len, URE_TXPKT_ALIGN); 824 rem -= roundup(len, URE_TXPKT_ALIGN); 825 826 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 827 828 /* 829 * If there's a BPF listener, bounce a copy 830 * of this frame to him. 831 */ 832 BPF_MTAP(ifp, m); 833 834 m_freem(m); 835 } 836 837 /* no packets to send */ 838 if (pos == 0) 839 break; 840 841 /* Set frame length. */ 842 usbd_xfer_set_frame_len(xfer, 0, pos); 843 844 usbd_transfer_submit(xfer); 845 846 return; 847 848 default: /* Error */ 849 DPRINTFN(11, "transfer error, %s\n", 850 usbd_errstr(error)); 851 852 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 853 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 854 855 if (error == USB_ERR_TIMEOUT) { 856 DEVPRINTFN(12, sc->sc_ue.ue_dev, 857 "pkt tx timeout\n"); 858 } 859 860 if (error != USB_ERR_CANCELLED) { 861 /* try to clear stall first */ 862 usbd_xfer_set_stall(xfer); 863 goto tr_setup; 864 } 865 } 866 } 867 868 static void 869 ure_read_chipver(struct ure_softc *sc) 870 { 871 uint16_t ver; 872 873 ver = ure_read_2(sc, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK; 874 sc->sc_ver = ver; 875 switch (ver) { 876 case 0x4c00: 877 sc->sc_chip |= URE_CHIP_VER_4C00; 878 sc->sc_flags = URE_FLAG_8152; 879 break; 880 case 0x4c10: 881 sc->sc_chip |= URE_CHIP_VER_4C10; 882 sc->sc_flags = URE_FLAG_8152; 883 break; 884 case 0x5c00: 885 sc->sc_chip |= URE_CHIP_VER_5C00; 886 sc->sc_flags = URE_FLAG_8153; 887 break; 888 case 0x5c10: 889 sc->sc_chip |= URE_CHIP_VER_5C10; 890 sc->sc_flags = URE_FLAG_8153; 891 break; 892 case 0x5c20: 893 sc->sc_chip |= URE_CHIP_VER_5C20; 894 sc->sc_flags = URE_FLAG_8153; 895 break; 896 case 0x5c30: 897 sc->sc_chip |= URE_CHIP_VER_5C30; 898 sc->sc_flags = URE_FLAG_8153; 899 break; 900 case 0x6000: 901 sc->sc_flags = URE_FLAG_8153B; 902 sc->sc_chip |= URE_CHIP_VER_6000; 903 break; 904 case 0x6010: 905 sc->sc_flags = URE_FLAG_8153B; 906 sc->sc_chip |= URE_CHIP_VER_6010; 907 break; 908 case 0x7020: 909 sc->sc_flags = URE_FLAG_8156; 910 sc->sc_chip |= URE_CHIP_VER_7020; 911 break; 912 case 0x7030: 913 sc->sc_flags = URE_FLAG_8156; 914 sc->sc_chip |= URE_CHIP_VER_7030; 915 break; 916 case 0x7400: 917 sc->sc_flags = URE_FLAG_8156B; 918 sc->sc_chip |= URE_CHIP_VER_7400; 919 break; 920 case 0x7410: 921 sc->sc_flags = URE_FLAG_8156B; 922 sc->sc_chip |= URE_CHIP_VER_7410; 923 break; 924 default: 925 device_printf(sc->sc_ue.ue_dev, 926 "unknown version 0x%04x\n", ver); 927 break; 928 } 929 } 930 931 static int 932 ure_sysctl_chipver(SYSCTL_HANDLER_ARGS) 933 { 934 struct sbuf sb; 935 struct ure_softc *sc = arg1; 936 int error; 937 938 sbuf_new_for_sysctl(&sb, NULL, 0, req); 939 940 sbuf_printf(&sb, "%04x", sc->sc_ver); 941 942 error = sbuf_finish(&sb); 943 sbuf_delete(&sb); 944 945 return (error); 946 } 947 948 static void 949 ure_attach_post(struct usb_ether *ue) 950 { 951 struct ure_softc *sc = uether_getsc(ue); 952 953 sc->sc_rxstarted = 0; 954 sc->sc_phyno = 0; 955 956 /* Determine the chip version. */ 957 ure_read_chipver(sc); 958 959 /* Initialize controller and get station address. */ 960 if (sc->sc_flags & URE_FLAG_8152) 961 ure_rtl8152_init(sc); 962 else if (sc->sc_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B)) 963 ure_rtl8153b_init(sc); 964 else 965 ure_rtl8153_init(sc); 966 967 if ((sc->sc_chip & URE_CHIP_VER_4C00) || 968 (sc->sc_chip & URE_CHIP_VER_4C10)) 969 ure_read_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA, 970 ue->ue_eaddr, 8); 971 else 972 ure_read_mem(sc, URE_PLA_BACKUP, URE_MCU_TYPE_PLA, 973 ue->ue_eaddr, 8); 974 975 if (ETHER_IS_ZERO(sc->sc_ue.ue_eaddr)) { 976 device_printf(sc->sc_ue.ue_dev, "MAC assigned randomly\n"); 977 arc4rand(sc->sc_ue.ue_eaddr, ETHER_ADDR_LEN, 0); 978 sc->sc_ue.ue_eaddr[0] &= ~0x01; /* unicast */ 979 sc->sc_ue.ue_eaddr[0] |= 0x02; /* locally administered */ 980 } 981 } 982 983 static int 984 ure_attach_post_sub(struct usb_ether *ue) 985 { 986 struct sysctl_ctx_list *sctx; 987 struct sysctl_oid *soid; 988 struct ure_softc *sc; 989 struct ifnet *ifp; 990 int error; 991 992 sc = uether_getsc(ue); 993 ifp = ue->ue_ifp; 994 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 995 ifp->if_start = uether_start; 996 ifp->if_ioctl = ure_ioctl; 997 ifp->if_init = uether_init; 998 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 999 /* 1000 * Try to keep two transfers full at a time. 1001 * ~(TRANSFER_SIZE / 80 bytes/pkt * 2 buffers in flight) 1002 */ 1003 ifp->if_snd.ifq_drv_maxlen = 512; 1004 IFQ_SET_READY(&ifp->if_snd); 1005 1006 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0); 1007 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWTAGGING, 0); 1008 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM|IFCAP_HWCSUM, 0); 1009 if_sethwassist(ifp, CSUM_IP|CSUM_IP_UDP|CSUM_IP_TCP); 1010 #ifdef INET6 1011 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM_IPV6, 0); 1012 #endif 1013 if_setcapenable(ifp, if_getcapabilities(ifp)); 1014 1015 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1016 ifmedia_init(&sc->sc_ifmedia, IFM_IMASK, ure_ifmedia_upd, 1017 ure_ifmedia_sts); 1018 ure_add_media_types(sc); 1019 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 1020 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER | IFM_AUTO); 1021 sc->sc_ifmedia.ifm_media = IFM_ETHER | IFM_AUTO; 1022 error = 0; 1023 } else { 1024 bus_topo_lock(); 1025 error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp, 1026 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts, 1027 BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, 0); 1028 bus_topo_unlock(); 1029 } 1030 1031 sctx = device_get_sysctl_ctx(sc->sc_ue.ue_dev); 1032 soid = device_get_sysctl_tree(sc->sc_ue.ue_dev); 1033 SYSCTL_ADD_PROC(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "chipver", 1034 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 1035 ure_sysctl_chipver, "A", 1036 "Return string with chip version."); 1037 1038 return (error); 1039 } 1040 1041 static void 1042 ure_init(struct usb_ether *ue) 1043 { 1044 struct ure_softc *sc = uether_getsc(ue); 1045 struct ifnet *ifp = uether_getifp(ue); 1046 uint16_t cpcr; 1047 uint32_t reg; 1048 1049 URE_LOCK_ASSERT(sc, MA_OWNED); 1050 1051 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1052 return; 1053 1054 /* Cancel pending I/O. */ 1055 ure_stop(ue); 1056 1057 if (sc->sc_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B)) 1058 ure_rtl8153b_nic_reset(sc); 1059 else 1060 ure_reset(sc); 1061 1062 /* Set MAC address. */ 1063 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG); 1064 ure_write_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES, 1065 IF_LLADDR(ifp), 8); 1066 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 1067 1068 /* Set RX EARLY timeout and size */ 1069 if (sc->sc_flags & URE_FLAG_8153) { 1070 switch (usbd_get_speed(sc->sc_ue.ue_udev)) { 1071 case USB_SPEED_SUPER: 1072 reg = URE_COALESCE_SUPER / 8; 1073 break; 1074 case USB_SPEED_HIGH: 1075 reg = URE_COALESCE_HIGH / 8; 1076 break; 1077 default: 1078 reg = URE_COALESCE_SLOW / 8; 1079 break; 1080 } 1081 ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB, reg); 1082 reg = URE_8153_RX_BUFSZ - (URE_FRAMELEN(if_getmtu(ifp)) + 1083 sizeof(struct ure_rxpkt) + URE_RXPKT_ALIGN); 1084 ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, reg / 4); 1085 } else if (sc->sc_flags & URE_FLAG_8153B) { 1086 ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB, 158); 1087 ure_write_2(sc, URE_USB_RX_EXTRA_AGG_TMR, URE_MCU_TYPE_USB, 1875); 1088 reg = URE_8153_RX_BUFSZ - (URE_FRAMELEN(if_getmtu(ifp)) + 1089 sizeof(struct ure_rxpkt) + URE_RXPKT_ALIGN); 1090 ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, reg / 8); 1091 ure_write_1(sc, URE_USB_UPT_RXDMA_OWN, URE_MCU_TYPE_USB, 1092 URE_OWN_UPDATE | URE_OWN_CLEAR); 1093 } else if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1094 ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB, 80); 1095 ure_write_2(sc, URE_USB_RX_EXTRA_AGG_TMR, URE_MCU_TYPE_USB, 1875); 1096 reg = URE_8156_RX_BUFSZ - (URE_FRAMELEN(if_getmtu(ifp)) + 1097 sizeof(struct ure_rxpkt) + URE_RXPKT_ALIGN); 1098 ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, reg / 8); 1099 ure_write_1(sc, URE_USB_UPT_RXDMA_OWN, URE_MCU_TYPE_USB, 1100 URE_OWN_UPDATE | URE_OWN_CLEAR); 1101 } 1102 1103 if (sc->sc_flags & URE_FLAG_8156B) { 1104 URE_CLRBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, URE_FC_PATCH_TASK); 1105 uether_pause(&sc->sc_ue, hz / 500); 1106 URE_SETBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, URE_FC_PATCH_TASK); 1107 } 1108 1109 /* Reset the packet filter. */ 1110 URE_CLRBIT_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, URE_FMC_FCR_MCU_EN); 1111 URE_SETBIT_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, URE_FMC_FCR_MCU_EN); 1112 1113 /* Enable RX VLANs if enabled */ 1114 cpcr = ure_read_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA); 1115 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) { 1116 DEVPRINTFN(12, sc->sc_ue.ue_dev, "enabled hw vlan tag\n"); 1117 cpcr |= URE_CPCR_RX_VLAN; 1118 } else { 1119 DEVPRINTFN(12, sc->sc_ue.ue_dev, "disabled hw vlan tag\n"); 1120 cpcr &= ~URE_CPCR_RX_VLAN; 1121 } 1122 ure_write_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, cpcr); 1123 1124 /* Enable transmit and receive. */ 1125 URE_SETBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RE | URE_CR_TE); 1126 1127 URE_CLRBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN); 1128 1129 /* Configure RX filters. */ 1130 ure_rxfilter(ue); 1131 1132 usbd_xfer_set_stall(sc->sc_tx_xfer[0]); 1133 1134 /* Indicate we are up and running. */ 1135 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1136 1137 /* Switch to selected media. */ 1138 ure_ifmedia_upd(ifp); 1139 } 1140 1141 static void 1142 ure_tick(struct usb_ether *ue) 1143 { 1144 struct ure_softc *sc = uether_getsc(ue); 1145 struct ifnet *ifp = uether_getifp(ue); 1146 struct mii_data *mii; 1147 1148 URE_LOCK_ASSERT(sc, MA_OWNED); 1149 1150 (void)ifp; 1151 for (int i = 0; i < URE_MAX_RX; i++) 1152 DEVPRINTFN(13, sc->sc_ue.ue_dev, 1153 "rx[%d] = %d\n", i, USB_GET_STATE(sc->sc_rx_xfer[i])); 1154 1155 for (int i = 0; i < URE_MAX_TX; i++) 1156 DEVPRINTFN(13, sc->sc_ue.ue_dev, 1157 "tx[%d] = %d\n", i, USB_GET_STATE(sc->sc_tx_xfer[i])); 1158 1159 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1160 ure_link_state(sc); 1161 } else { 1162 mii = GET_MII(sc); 1163 mii_tick(mii); 1164 if ((sc->sc_flags & URE_FLAG_LINK) == 0 1165 && mii->mii_media_status & IFM_ACTIVE && 1166 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1167 sc->sc_flags |= URE_FLAG_LINK; 1168 sc->sc_rxstarted = 0; 1169 ure_start(ue); 1170 } 1171 } 1172 } 1173 1174 static u_int 1175 ure_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 1176 { 1177 uint32_t h, *hashes = arg; 1178 1179 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26; 1180 if (h < 32) 1181 hashes[0] |= (1 << h); 1182 else 1183 hashes[1] |= (1 << (h - 32)); 1184 return (1); 1185 } 1186 1187 /* 1188 * Program the 64-bit multicast hash filter. 1189 */ 1190 static void 1191 ure_rxfilter(struct usb_ether *ue) 1192 { 1193 struct ure_softc *sc = uether_getsc(ue); 1194 struct ifnet *ifp = uether_getifp(ue); 1195 uint32_t rxmode; 1196 uint32_t h, hashes[2] = { 0, 0 }; 1197 1198 URE_LOCK_ASSERT(sc, MA_OWNED); 1199 1200 rxmode = ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA); 1201 rxmode &= ~(URE_RCR_AAP | URE_RCR_AM); 1202 rxmode |= URE_RCR_APM; /* accept physical match packets */ 1203 rxmode |= URE_RCR_AB; /* always accept broadcasts */ 1204 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 1205 if (ifp->if_flags & IFF_PROMISC) 1206 rxmode |= URE_RCR_AAP; 1207 rxmode |= URE_RCR_AM; 1208 hashes[0] = hashes[1] = 0xffffffff; 1209 goto done; 1210 } 1211 1212 /* calculate multicast masks */ 1213 if_foreach_llmaddr(ifp, ure_hash_maddr, &hashes); 1214 1215 h = bswap32(hashes[0]); 1216 hashes[0] = bswap32(hashes[1]); 1217 hashes[1] = h; 1218 rxmode |= URE_RCR_AM; /* accept multicast packets */ 1219 1220 done: 1221 DEVPRINTFN(14, ue->ue_dev, "rxfilt: RCR: %#x\n", 1222 ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA)); 1223 ure_write_4(sc, URE_PLA_MAR0, URE_MCU_TYPE_PLA, hashes[0]); 1224 ure_write_4(sc, URE_PLA_MAR4, URE_MCU_TYPE_PLA, hashes[1]); 1225 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); 1226 } 1227 1228 static void 1229 ure_start(struct usb_ether *ue) 1230 { 1231 struct ure_softc *sc = uether_getsc(ue); 1232 unsigned i; 1233 1234 URE_LOCK_ASSERT(sc, MA_OWNED); 1235 1236 if (!sc->sc_rxstarted) { 1237 sc->sc_rxstarted = 1; 1238 for (i = 0; i != URE_MAX_RX; i++) 1239 usbd_transfer_start(sc->sc_rx_xfer[i]); 1240 } 1241 1242 for (i = 0; i != URE_MAX_TX; i++) 1243 usbd_transfer_start(sc->sc_tx_xfer[i]); 1244 } 1245 1246 static void 1247 ure_reset(struct ure_softc *sc) 1248 { 1249 int i; 1250 1251 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST); 1252 1253 for (i = 0; i < URE_TIMEOUT; i++) { 1254 if (!(ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) & 1255 URE_CR_RST)) 1256 break; 1257 uether_pause(&sc->sc_ue, hz / 100); 1258 } 1259 if (i == URE_TIMEOUT) 1260 device_printf(sc->sc_ue.ue_dev, "reset never completed\n"); 1261 } 1262 1263 /* 1264 * Set media options. 1265 */ 1266 static int 1267 ure_ifmedia_upd(struct ifnet *ifp) 1268 { 1269 struct ure_softc *sc = ifp->if_softc; 1270 struct ifmedia *ifm; 1271 struct mii_data *mii; 1272 struct mii_softc *miisc; 1273 int gig; 1274 int reg; 1275 int anar; 1276 int locked; 1277 int error; 1278 1279 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1280 ifm = &sc->sc_ifmedia; 1281 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1282 return (EINVAL); 1283 1284 locked = mtx_owned(&sc->sc_mtx); 1285 if (!locked) 1286 URE_LOCK(sc); 1287 reg = ure_ocp_reg_read(sc, 0xa5d4); 1288 reg &= ~URE_ADV_2500TFDX; 1289 1290 anar = gig = 0; 1291 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1292 case IFM_AUTO: 1293 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10; 1294 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; 1295 reg |= URE_ADV_2500TFDX; 1296 break; 1297 case IFM_2500_T: 1298 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10; 1299 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; 1300 reg |= URE_ADV_2500TFDX; 1301 ifp->if_baudrate = IF_Mbps(2500); 1302 break; 1303 case IFM_1000_T: 1304 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10; 1305 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; 1306 ifp->if_baudrate = IF_Gbps(1); 1307 break; 1308 case IFM_100_TX: 1309 anar |= ANAR_TX | ANAR_TX_FD; 1310 ifp->if_baudrate = IF_Mbps(100); 1311 break; 1312 case IFM_10_T: 1313 anar |= ANAR_10 | ANAR_10_FD; 1314 ifp->if_baudrate = IF_Mbps(10); 1315 break; 1316 default: 1317 device_printf(sc->sc_ue.ue_dev, "unsupported media type\n"); 1318 if (!locked) 1319 URE_UNLOCK(sc); 1320 return (EINVAL); 1321 } 1322 1323 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_ANAR * 2, 1324 anar | ANAR_PAUSE_ASYM | ANAR_FC); 1325 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_100T2CR * 2, gig); 1326 ure_ocp_reg_write(sc, 0xa5d4, reg); 1327 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_BMCR, 1328 BMCR_AUTOEN | BMCR_STARTNEG); 1329 if (!locked) 1330 URE_UNLOCK(sc); 1331 return (0); 1332 } 1333 1334 mii = GET_MII(sc); 1335 1336 URE_LOCK_ASSERT(sc, MA_OWNED); 1337 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1338 PHY_RESET(miisc); 1339 error = mii_mediachg(mii); 1340 return (error); 1341 } 1342 1343 /* 1344 * Report current media status. 1345 */ 1346 static void 1347 ure_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1348 { 1349 struct ure_softc *sc; 1350 struct mii_data *mii; 1351 uint16_t status; 1352 1353 sc = ifp->if_softc; 1354 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1355 URE_LOCK(sc); 1356 ifmr->ifm_status = IFM_AVALID; 1357 if (ure_get_link_status(sc)) { 1358 ifmr->ifm_status |= IFM_ACTIVE; 1359 status = ure_read_2(sc, URE_PLA_PHYSTATUS, 1360 URE_MCU_TYPE_PLA); 1361 if ((status & URE_PHYSTATUS_FDX) || 1362 (status & URE_PHYSTATUS_2500MBPS)) 1363 ifmr->ifm_active |= IFM_FDX; 1364 else 1365 ifmr->ifm_active |= IFM_HDX; 1366 if (status & URE_PHYSTATUS_10MBPS) 1367 ifmr->ifm_active |= IFM_10_T; 1368 else if (status & URE_PHYSTATUS_100MBPS) 1369 ifmr->ifm_active |= IFM_100_TX; 1370 else if (status & URE_PHYSTATUS_1000MBPS) 1371 ifmr->ifm_active |= IFM_1000_T; 1372 else if (status & URE_PHYSTATUS_2500MBPS) 1373 ifmr->ifm_active |= IFM_2500_T; 1374 } 1375 URE_UNLOCK(sc); 1376 return; 1377 } 1378 1379 mii = GET_MII(sc); 1380 1381 URE_LOCK(sc); 1382 mii_pollstat(mii); 1383 ifmr->ifm_active = mii->mii_media_active; 1384 ifmr->ifm_status = mii->mii_media_status; 1385 URE_UNLOCK(sc); 1386 } 1387 1388 static void 1389 ure_add_media_types(struct ure_softc *sc) 1390 { 1391 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 1392 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 1393 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 1394 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 1395 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 1396 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_2500_T | IFM_FDX, 0, NULL); 1397 } 1398 1399 static void 1400 ure_link_state(struct ure_softc *sc) 1401 { 1402 struct ifnet *ifp = uether_getifp(&sc->sc_ue); 1403 1404 if (ure_get_link_status(sc)) { 1405 if (ifp->if_link_state != LINK_STATE_UP) { 1406 if_link_state_change(ifp, LINK_STATE_UP); 1407 /* Enable transmit and receive. */ 1408 URE_SETBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RE | URE_CR_TE); 1409 1410 if (ure_read_2(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA) & 1411 URE_PHYSTATUS_2500MBPS) 1412 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 0x40); 1413 else 1414 URE_SETBIT_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 0x40); 1415 } 1416 } else { 1417 if (ifp->if_link_state != LINK_STATE_DOWN) { 1418 if_link_state_change(ifp, LINK_STATE_DOWN); 1419 } 1420 } 1421 } 1422 1423 static int 1424 ure_get_link_status(struct ure_softc *sc) 1425 { 1426 if (ure_read_2(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA) & 1427 URE_PHYSTATUS_LINK) { 1428 sc->sc_flags |= URE_FLAG_LINK; 1429 return (1); 1430 } else { 1431 sc->sc_flags &= ~URE_FLAG_LINK; 1432 return (0); 1433 } 1434 } 1435 1436 static int 1437 ure_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1438 { 1439 struct usb_ether *ue = ifp->if_softc; 1440 struct ure_softc *sc; 1441 struct ifreq *ifr; 1442 int error, mask, reinit; 1443 1444 sc = uether_getsc(ue); 1445 ifr = (struct ifreq *)data; 1446 error = 0; 1447 reinit = 0; 1448 switch (cmd) { 1449 case SIOCSIFCAP: 1450 URE_LOCK(sc); 1451 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1452 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1453 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 1454 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1455 reinit++; 1456 } 1457 if ((mask & IFCAP_TXCSUM) != 0 && 1458 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 1459 ifp->if_capenable ^= IFCAP_TXCSUM; 1460 } 1461 if ((mask & IFCAP_RXCSUM) != 0 && 1462 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 1463 ifp->if_capenable ^= IFCAP_RXCSUM; 1464 } 1465 if ((mask & IFCAP_TXCSUM_IPV6) != 0 && 1466 (ifp->if_capabilities & IFCAP_TXCSUM_IPV6) != 0) { 1467 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6; 1468 } 1469 if ((mask & IFCAP_RXCSUM_IPV6) != 0 && 1470 (ifp->if_capabilities & IFCAP_RXCSUM_IPV6) != 0) { 1471 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6; 1472 } 1473 if (reinit > 0 && ifp->if_drv_flags & IFF_DRV_RUNNING) 1474 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1475 else 1476 reinit = 0; 1477 URE_UNLOCK(sc); 1478 if (reinit > 0) 1479 uether_init(ue); 1480 break; 1481 1482 case SIOCSIFMTU: 1483 /* 1484 * in testing large MTUs "crashes" the device, it 1485 * leaves the device w/ a broken state where link 1486 * is in a bad state. 1487 */ 1488 if (ifr->ifr_mtu < ETHERMIN || 1489 ifr->ifr_mtu > (4096 - ETHER_HDR_LEN - 1490 ETHER_VLAN_ENCAP_LEN - ETHER_CRC_LEN)) { 1491 error = EINVAL; 1492 break; 1493 } 1494 URE_LOCK(sc); 1495 if (if_getmtu(ifp) != ifr->ifr_mtu) 1496 if_setmtu(ifp, ifr->ifr_mtu); 1497 URE_UNLOCK(sc); 1498 break; 1499 1500 case SIOCGIFMEDIA: 1501 case SIOCSIFMEDIA: 1502 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) 1503 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, cmd); 1504 else 1505 error = uether_ioctl(ifp, cmd, data); 1506 break; 1507 1508 default: 1509 error = uether_ioctl(ifp, cmd, data); 1510 break; 1511 } 1512 1513 return (error); 1514 } 1515 1516 static void 1517 ure_rtl8152_init(struct ure_softc *sc) 1518 { 1519 uint32_t pwrctrl; 1520 1521 ure_enable_aldps(sc, false); 1522 1523 if (sc->sc_chip & URE_CHIP_VER_4C00) { 1524 URE_CLRBIT_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, URE_LED_MODE_MASK); 1525 } 1526 1527 URE_CLRBIT_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, URE_POWER_CUT); 1528 1529 URE_CLRBIT_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB, URE_RESUME_INDICATE); 1530 1531 URE_SETBIT_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH); 1532 1533 pwrctrl = ure_read_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA); 1534 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK; 1535 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN; 1536 ure_write_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl); 1537 ure_write_2(sc, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA, 1538 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK | 1539 URE_SPDWN_LINKCHG_MSK); 1540 1541 /* Enable Rx aggregation. */ 1542 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, URE_RX_AGG_DISABLE | URE_RX_ZERO_EN); 1543 1544 ure_enable_aldps(sc, false); 1545 1546 ure_rtl8152_nic_reset(sc); 1547 1548 ure_write_1(sc, URE_USB_TX_AGG, URE_MCU_TYPE_USB, 1549 URE_TX_AGG_MAX_THRESHOLD); 1550 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH); 1551 ure_write_4(sc, URE_USB_TX_DMA, URE_MCU_TYPE_USB, 1552 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1); 1553 } 1554 1555 static void 1556 ure_rtl8153_init(struct ure_softc *sc) 1557 { 1558 uint16_t val; 1559 uint8_t u1u2[8]; 1560 int i; 1561 1562 ure_enable_aldps(sc, false); 1563 1564 memset(u1u2, 0x00, sizeof(u1u2)); 1565 ure_write_mem(sc, URE_USB_TOLERANCE, 1566 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 1567 1568 for (i = 0; i < URE_TIMEOUT; i++) { 1569 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 1570 URE_AUTOLOAD_DONE) 1571 break; 1572 uether_pause(&sc->sc_ue, hz / 100); 1573 } 1574 if (i == URE_TIMEOUT) 1575 device_printf(sc->sc_ue.ue_dev, 1576 "timeout waiting for chip autoload\n"); 1577 1578 for (i = 0; i < URE_TIMEOUT; i++) { 1579 val = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) & 1580 URE_PHY_STAT_MASK; 1581 if (val == URE_PHY_STAT_LAN_ON || val == URE_PHY_STAT_PWRDN) 1582 break; 1583 uether_pause(&sc->sc_ue, hz / 100); 1584 } 1585 if (i == URE_TIMEOUT) 1586 device_printf(sc->sc_ue.ue_dev, 1587 "timeout waiting for phy to stabilize\n"); 1588 1589 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE); 1590 1591 if (sc->sc_chip & URE_CHIP_VER_5C10) { 1592 val = ure_read_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB); 1593 val &= ~URE_PWD_DN_SCALE_MASK; 1594 val |= URE_PWD_DN_SCALE(96); 1595 ure_write_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, val); 1596 1597 URE_SETBIT_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB, URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND); 1598 } else if (sc->sc_chip & URE_CHIP_VER_5C20) 1599 URE_CLRBIT_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA, URE_ECM_ALDPS); 1600 1601 if (sc->sc_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) { 1602 val = ure_read_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB); 1603 if (ure_read_2(sc, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB) == 1604 0) 1605 val &= ~URE_DYNAMIC_BURST; 1606 else 1607 val |= URE_DYNAMIC_BURST; 1608 ure_write_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, val); 1609 } 1610 1611 URE_SETBIT_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, URE_EP4_FULL_FC); 1612 1613 URE_CLRBIT_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, URE_TIMER11_EN); 1614 1615 URE_CLRBIT_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, URE_LED_MODE_MASK); 1616 1617 if ((sc->sc_chip & URE_CHIP_VER_5C10) && 1618 usbd_get_speed(sc->sc_ue.ue_udev) != USB_SPEED_SUPER) 1619 val = URE_LPM_TIMER_500MS; 1620 else 1621 val = URE_LPM_TIMER_500US; 1622 ure_write_1(sc, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB, 1623 val | URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM); 1624 1625 val = ure_read_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB); 1626 val &= ~URE_SEN_VAL_MASK; 1627 val |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE; 1628 ure_write_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, val); 1629 1630 ure_write_2(sc, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001); 1631 1632 URE_CLRBIT_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, URE_PWR_EN | URE_PHASE2_EN); 1633 1634 URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, URE_PCUT_STATUS); 1635 1636 memset(u1u2, 0xff, sizeof(u1u2)); 1637 ure_write_mem(sc, URE_USB_TOLERANCE, 1638 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 1639 1640 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 1641 URE_ALDPS_SPDWN_RATIO); 1642 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 1643 URE_EEE_SPDWN_RATIO); 1644 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 1645 URE_PKT_AVAIL_SPDWN_EN | URE_SUSPEND_SPDWN_EN | 1646 URE_U1U2_SPDWN_EN | URE_L1_SPDWN_EN); 1647 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 1648 URE_PWRSAVE_SPDWN_EN | URE_RXDV_SPDWN_EN | URE_TX10MIDLE_EN | 1649 URE_TP100_SPDWN_EN | URE_TP500_SPDWN_EN | URE_TP1000_SPDWN_EN | 1650 URE_EEE_SPDWN_EN); 1651 1652 val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 1653 if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10))) 1654 val |= URE_U2P3_ENABLE; 1655 else 1656 val &= ~URE_U2P3_ENABLE; 1657 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 1658 1659 memset(u1u2, 0x00, sizeof(u1u2)); 1660 ure_write_mem(sc, URE_USB_TOLERANCE, 1661 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 1662 1663 ure_enable_aldps(sc, false); 1664 1665 if (sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10 | 1666 URE_CHIP_VER_5C20)) { 1667 ure_ocp_reg_write(sc, URE_OCP_ADC_CFG, 1668 URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L); 1669 } 1670 if (sc->sc_chip & URE_CHIP_VER_5C00) { 1671 ure_ocp_reg_write(sc, URE_OCP_EEE_CFG, 1672 ure_ocp_reg_read(sc, URE_OCP_EEE_CFG) & 1673 ~URE_CTAP_SHORT_EN); 1674 } 1675 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1676 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | 1677 URE_EEE_CLKDIV_EN); 1678 ure_ocp_reg_write(sc, URE_OCP_DOWN_SPEED, 1679 ure_ocp_reg_read(sc, URE_OCP_DOWN_SPEED) | 1680 URE_EN_10M_BGOFF); 1681 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1682 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | 1683 URE_EN_10M_PLLOFF); 1684 ure_sram_write(sc, URE_SRAM_IMPEDANCE, 0x0b13); 1685 URE_SETBIT_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, URE_PFM_PWM_SWITCH); 1686 1687 /* Enable LPF corner auto tune. */ 1688 ure_sram_write(sc, URE_SRAM_LPF_CFG, 0xf70f); 1689 1690 /* Adjust 10M amplitude. */ 1691 ure_sram_write(sc, URE_SRAM_10M_AMP1, 0x00af); 1692 ure_sram_write(sc, URE_SRAM_10M_AMP2, 0x0208); 1693 1694 ure_rtl8152_nic_reset(sc); 1695 1696 /* Enable Rx aggregation. */ 1697 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, URE_RX_AGG_DISABLE | URE_RX_ZERO_EN); 1698 1699 val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 1700 if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10))) 1701 val |= URE_U2P3_ENABLE; 1702 else 1703 val &= ~URE_U2P3_ENABLE; 1704 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 1705 1706 memset(u1u2, 0xff, sizeof(u1u2)); 1707 ure_write_mem(sc, URE_USB_TOLERANCE, 1708 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 1709 } 1710 1711 static void 1712 ure_rtl8153b_init(struct ure_softc *sc) 1713 { 1714 uint16_t val; 1715 int i; 1716 1717 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1718 URE_CLRBIT_1(sc, 0xd26b, URE_MCU_TYPE_USB, 0x01); 1719 ure_write_2(sc, 0xd32a, URE_MCU_TYPE_USB, 0); 1720 URE_SETBIT_2(sc, 0xcfee, URE_MCU_TYPE_USB, 0x0020); 1721 } 1722 1723 if (sc->sc_flags & URE_FLAG_8156B) { 1724 URE_SETBIT_2(sc, 0xb460, URE_MCU_TYPE_USB, 0x08); 1725 } 1726 1727 ure_enable_aldps(sc, false); 1728 1729 /* Disable U1U2 */ 1730 URE_CLRBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, URE_LPM_U1U2_EN); 1731 1732 /* Wait loading flash */ 1733 if (sc->sc_chip == URE_CHIP_VER_7410) { 1734 if ((ure_read_2(sc, 0xd3ae, URE_MCU_TYPE_PLA) & 0x0002) && 1735 !(ure_read_2(sc, 0xd284, URE_MCU_TYPE_USB) & 0x0020)) { 1736 for (i=0; i < 100; i++) { 1737 if (ure_read_2(sc, 0xd284, URE_MCU_TYPE_USB) & 0x0004) 1738 break; 1739 uether_pause(&sc->sc_ue, hz / 1000); 1740 } 1741 } 1742 } 1743 1744 for (i = 0; i < URE_TIMEOUT; i++) { 1745 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 1746 URE_AUTOLOAD_DONE) 1747 break; 1748 uether_pause(&sc->sc_ue, hz / 100); 1749 } 1750 if (i == URE_TIMEOUT) 1751 device_printf(sc->sc_ue.ue_dev, 1752 "timeout waiting for chip autoload\n"); 1753 1754 val = ure_phy_status(sc, 0); 1755 if ((val == URE_PHY_STAT_EXT_INIT) & 1756 (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B))) { 1757 ure_ocp_reg_write(sc, 0xa468, 1758 ure_ocp_reg_read(sc, 0xa468) & ~0x0a); 1759 if (sc->sc_flags & URE_FLAG_8156B) 1760 ure_ocp_reg_write(sc, 0xa466, 1761 ure_ocp_reg_read(sc, 0xa466) & ~0x01); 1762 } 1763 1764 val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + MII_BMCR); 1765 if (val & BMCR_PDOWN) { 1766 val &= ~BMCR_PDOWN; 1767 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_BMCR, val); 1768 } 1769 1770 ure_phy_status(sc, URE_PHY_STAT_LAN_ON); 1771 1772 /* Disable U2P3 */ 1773 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE); 1774 1775 /* MSC timer, 32760 ms. */ 1776 ure_write_2(sc, URE_USB_MSC_TIMER, URE_MCU_TYPE_USB, 0x0fff); 1777 1778 /* U1/U2/L1 idle timer, 500 us. */ 1779 ure_write_2(sc, URE_USB_U1U2_TIMER, URE_MCU_TYPE_USB, 500); 1780 1781 /* Disable power cut */ 1782 URE_CLRBIT_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, URE_PWR_EN); 1783 URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, URE_PCUT_STATUS); 1784 1785 /* Disable ups */ 1786 URE_CLRBIT_1(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, URE_UPS_EN | URE_USP_PREWAKE); 1787 URE_CLRBIT_1(sc, 0xcfff, URE_MCU_TYPE_USB, 0x01); 1788 1789 /* Disable queue wake */ 1790 URE_CLRBIT_1(sc, URE_PLA_INDICATE_FALG, URE_MCU_TYPE_USB, URE_UPCOMING_RUNTIME_D3); 1791 URE_CLRBIT_1(sc, URE_PLA_SUSPEND_FLAG, URE_MCU_TYPE_USB, URE_LINK_CHG_EVENT); 1792 URE_CLRBIT_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_USB, URE_LINK_CHANGE_FLAG); 1793 1794 /* Disable runtime suspend */ 1795 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG); 1796 URE_CLRBIT_2(sc, URE_PLA_CONFIG34, URE_MCU_TYPE_USB, URE_LINK_OFF_WAKE_EN); 1797 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 1798 1799 /* Enable U1U2 */ 1800 if (usbd_get_speed(sc->sc_ue.ue_udev) == USB_SPEED_SUPER) 1801 URE_SETBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, URE_LPM_U1U2_EN); 1802 1803 if (sc->sc_flags & URE_FLAG_8156B) { 1804 URE_CLRBIT_2(sc, 0xc010, URE_MCU_TYPE_PLA, 0x0800); 1805 URE_SETBIT_2(sc, 0xe854, URE_MCU_TYPE_PLA, 0x0001); 1806 1807 /* enable fc timer and set timer to 600 ms. */ 1808 ure_write_2(sc, URE_USB_FC_TIMER, URE_MCU_TYPE_USB, URE_CTRL_TIMER_EN | (600 / 8)); 1809 1810 if (!(ure_read_1(sc, 0xdc6b, URE_MCU_TYPE_PLA) & 0x80)) { 1811 val = ure_read_2(sc, URE_USB_FW_CTRL, URE_MCU_TYPE_USB); 1812 val |= URE_FLOW_CTRL_PATCH_OPT | 0x0100; 1813 val &= ~0x08; 1814 ure_write_2(sc, URE_USB_FW_CTRL, URE_MCU_TYPE_USB, val); 1815 } 1816 1817 URE_SETBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, URE_FC_PATCH_TASK); 1818 } 1819 1820 val = ure_read_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA); 1821 if (ure_get_link_status(sc)) 1822 val |= URE_CUR_LINK_OK; 1823 else 1824 val &= ~URE_CUR_LINK_OK; 1825 val |= URE_POLL_LINK_CHG; 1826 ure_write_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA, val); 1827 1828 /* MAC clock speed down */ 1829 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1830 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 0x0403); 1831 val = ure_read_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA); 1832 val &= ~0xff; 1833 val |= URE_MAC_CLK_SPDWN_EN | 0x03; 1834 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, val); 1835 } else { 1836 URE_SETBIT_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_USB, URE_MAC_CLK_SPDWN_EN); 1837 } 1838 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, URE_PLA_MCU_SPDWN_EN); 1839 1840 /* Enable Rx aggregation. */ 1841 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, URE_RX_AGG_DISABLE | URE_RX_ZERO_EN); 1842 1843 if (sc->sc_flags & URE_FLAG_8156) 1844 URE_SETBIT_1(sc, 0xd4b4, URE_MCU_TYPE_USB, 0x02); 1845 1846 /* Reset tally */ 1847 URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_USB, URE_TALLY_RESET); 1848 } 1849 1850 static void 1851 ure_rtl8153b_nic_reset(struct ure_softc *sc) 1852 { 1853 struct ifnet *ifp = uether_getifp(&sc->sc_ue); 1854 uint16_t val; 1855 int i; 1856 1857 /* Disable U1U2 */ 1858 URE_CLRBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, URE_LPM_U1U2_EN); 1859 1860 /* Disable U2P3 */ 1861 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE); 1862 1863 ure_enable_aldps(sc, false); 1864 1865 /* Enable rxdy_gated */ 1866 URE_SETBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN); 1867 1868 /* Disable teredo */ 1869 ure_disable_teredo(sc); 1870 1871 DEVPRINTFN(14, sc->sc_ue.ue_dev, "rtl8153b_nic_reset: RCR: %#x\n", ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA)); 1872 URE_CLRBIT_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_RCR_ACPT_ALL); 1873 1874 ure_reset(sc); 1875 1876 /* Reset BMU */ 1877 URE_CLRBIT_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, URE_BMU_RESET_EP_IN | URE_BMU_RESET_EP_OUT); 1878 URE_SETBIT_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, URE_BMU_RESET_EP_IN | URE_BMU_RESET_EP_OUT); 1879 1880 URE_CLRBIT_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, URE_NOW_IS_OOB); 1881 URE_CLRBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_MCU_BORW_EN); 1882 if (sc->sc_flags & URE_FLAG_8153B) { 1883 for (i = 0; i < URE_TIMEOUT; i++) { 1884 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1885 URE_LINK_LIST_READY) 1886 break; 1887 uether_pause(&sc->sc_ue, hz / 100); 1888 } 1889 if (i == URE_TIMEOUT) 1890 device_printf(sc->sc_ue.ue_dev, 1891 "timeout waiting for OOB control\n"); 1892 1893 URE_SETBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_RE_INIT_LL); 1894 for (i = 0; i < URE_TIMEOUT; i++) { 1895 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1896 URE_LINK_LIST_READY) 1897 break; 1898 uether_pause(&sc->sc_ue, hz / 100); 1899 } 1900 if (i == URE_TIMEOUT) 1901 device_printf(sc->sc_ue.ue_dev, 1902 "timeout waiting for OOB control\n"); 1903 } 1904 1905 /* Configure rxvlan */ 1906 val = ure_read_2(sc, 0xc012, URE_MCU_TYPE_PLA); 1907 val &= ~0x00c0; 1908 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 1909 val |= 0x00c0; 1910 ure_write_2(sc, 0xc012, URE_MCU_TYPE_PLA, val); 1911 1912 val = if_getmtu(ifp); 1913 ure_write_2(sc, URE_PLA_RMS, URE_MCU_TYPE_PLA, URE_FRAMELEN(val)); 1914 ure_write_1(sc, URE_PLA_MTPS, URE_MCU_TYPE_PLA, URE_MTPS_JUMBO); 1915 1916 if (sc->sc_flags & URE_FLAG_8153B) { 1917 URE_SETBIT_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, URE_TCR0_AUTO_FIFO); 1918 ure_reset(sc); 1919 } 1920 1921 /* Configure fc parameter */ 1922 if (sc->sc_flags & URE_FLAG_8156) { 1923 ure_write_2(sc, 0xc0a6, URE_MCU_TYPE_PLA, 0x0400); 1924 ure_write_2(sc, 0xc0aa, URE_MCU_TYPE_PLA, 0x0800); 1925 } else if (sc->sc_flags & URE_FLAG_8156B) { 1926 ure_write_2(sc, 0xc0a6, URE_MCU_TYPE_PLA, 0x0200); 1927 ure_write_2(sc, 0xc0aa, URE_MCU_TYPE_PLA, 0x0400); 1928 } 1929 1930 /* Configure Rx FIFO threshold. */ 1931 if (sc->sc_flags & URE_FLAG_8153B) { 1932 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, URE_RXFIFO_THR1_NORMAL); 1933 ure_write_2(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, URE_RXFIFO_THR2_NORMAL); 1934 ure_write_2(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, URE_RXFIFO_THR3_NORMAL); 1935 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_B); 1936 } else { 1937 ure_write_2(sc, 0xc0a2, URE_MCU_TYPE_PLA, 1938 (ure_read_2(sc, 0xc0a2, URE_MCU_TYPE_PLA) & ~0xfff) | 0x08); 1939 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, 0x00600400); 1940 } 1941 1942 /* Configure Tx FIFO threshold. */ 1943 if (sc->sc_flags & URE_FLAG_8153B) { 1944 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, URE_TXFIFO_THR_NORMAL2); 1945 } else if (sc->sc_flags & URE_FLAG_8156) { 1946 ure_write_2(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, URE_TXFIFO_THR_NORMAL2); 1947 URE_SETBIT_2(sc, 0xd4b4, URE_MCU_TYPE_USB, 0x0002); 1948 } else if (sc->sc_flags & URE_FLAG_8156B) { 1949 ure_write_2(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 0x0008); 1950 ure_write_2(sc, 0xe61a, URE_MCU_TYPE_PLA, 1951 (URE_FRAMELEN(val) + 0x100) / 16 ); 1952 } 1953 1954 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, URE_PLA_MCU_SPDWN_EN); 1955 1956 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) 1957 URE_CLRBIT_2(sc, 0xd32a, URE_MCU_TYPE_USB, 0x300); 1958 1959 ure_enable_aldps(sc, true); 1960 1961 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1962 /* Enable U2P3 */ 1963 URE_SETBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE); 1964 } 1965 1966 /* Enable U1U2 */ 1967 if (usbd_get_speed(sc->sc_ue.ue_udev) == USB_SPEED_SUPER) 1968 URE_SETBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, URE_LPM_U1U2_EN); 1969 } 1970 1971 static void 1972 ure_stop(struct usb_ether *ue) 1973 { 1974 struct ure_softc *sc = uether_getsc(ue); 1975 struct ifnet *ifp = uether_getifp(ue); 1976 1977 URE_LOCK_ASSERT(sc, MA_OWNED); 1978 1979 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1980 sc->sc_flags &= ~URE_FLAG_LINK; 1981 sc->sc_rxstarted = 0; 1982 1983 /* 1984 * stop all the transfers, if not already stopped: 1985 */ 1986 for (int i = 0; i < URE_MAX_RX; i++) 1987 usbd_transfer_stop(sc->sc_rx_xfer[i]); 1988 for (int i = 0; i < URE_MAX_TX; i++) 1989 usbd_transfer_stop(sc->sc_tx_xfer[i]); 1990 } 1991 1992 static void 1993 ure_disable_teredo(struct ure_softc *sc) 1994 { 1995 1996 if (sc->sc_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B)) 1997 ure_write_1(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 0xff); 1998 else { 1999 URE_CLRBIT_2(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 2000 (URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | URE_OOB_TEREDO_EN)); 2001 } 2002 ure_write_2(sc, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA, URE_WDT6_SET_MODE); 2003 ure_write_2(sc, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0); 2004 ure_write_4(sc, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0); 2005 } 2006 2007 static void 2008 ure_enable_aldps(struct ure_softc *sc, bool enable) 2009 { 2010 int i; 2011 2012 if (enable) { 2013 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 2014 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | URE_EN_ALDPS); 2015 } else { 2016 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 2017 URE_DIS_SDSAVE); 2018 for (i = 0; i < 20; i++) { 2019 uether_pause(&sc->sc_ue, hz / 1000); 2020 if (ure_ocp_reg_read(sc, 0xe000) & 0x0100) 2021 break; 2022 } 2023 } 2024 } 2025 2026 static uint16_t 2027 ure_phy_status(struct ure_softc *sc, uint16_t desired) 2028 { 2029 uint16_t val; 2030 int i; 2031 2032 for (i = 0; i < URE_TIMEOUT; i++) { 2033 val = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) & 2034 URE_PHY_STAT_MASK; 2035 if (desired) { 2036 if (val == desired) 2037 break; 2038 } else { 2039 if (val == URE_PHY_STAT_LAN_ON || 2040 val == URE_PHY_STAT_PWRDN || 2041 val == URE_PHY_STAT_EXT_INIT) 2042 break; 2043 } 2044 uether_pause(&sc->sc_ue, hz / 100); 2045 } 2046 if (i == URE_TIMEOUT) 2047 device_printf(sc->sc_ue.ue_dev, 2048 "timeout waiting for phy to stabilize\n"); 2049 2050 return (val); 2051 } 2052 2053 static void 2054 ure_rtl8152_nic_reset(struct ure_softc *sc) 2055 { 2056 uint32_t rx_fifo1, rx_fifo2; 2057 int i; 2058 2059 URE_SETBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN); 2060 2061 ure_disable_teredo(sc); 2062 2063 DEVPRINTFN(14, sc->sc_ue.ue_dev, "rtl8152_nic_reset: RCR: %#x\n", ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA)); 2064 URE_CLRBIT_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_RCR_ACPT_ALL); 2065 2066 ure_reset(sc); 2067 2068 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 0); 2069 2070 URE_CLRBIT_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, URE_NOW_IS_OOB); 2071 2072 URE_CLRBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_MCU_BORW_EN); 2073 for (i = 0; i < URE_TIMEOUT; i++) { 2074 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 2075 URE_LINK_LIST_READY) 2076 break; 2077 uether_pause(&sc->sc_ue, hz / 100); 2078 } 2079 if (i == URE_TIMEOUT) 2080 device_printf(sc->sc_ue.ue_dev, 2081 "timeout waiting for OOB control\n"); 2082 URE_SETBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_RE_INIT_LL); 2083 for (i = 0; i < URE_TIMEOUT; i++) { 2084 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 2085 URE_LINK_LIST_READY) 2086 break; 2087 uether_pause(&sc->sc_ue, hz / 100); 2088 } 2089 if (i == URE_TIMEOUT) 2090 device_printf(sc->sc_ue.ue_dev, 2091 "timeout waiting for OOB control\n"); 2092 2093 URE_CLRBIT_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, URE_CPCR_RX_VLAN); 2094 2095 URE_SETBIT_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, URE_TCR0_AUTO_FIFO); 2096 2097 /* Configure Rx FIFO threshold. */ 2098 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, 2099 URE_RXFIFO_THR1_NORMAL); 2100 if (usbd_get_speed(sc->sc_ue.ue_udev) == USB_SPEED_FULL) { 2101 rx_fifo1 = URE_RXFIFO_THR2_FULL; 2102 rx_fifo2 = URE_RXFIFO_THR3_FULL; 2103 } else { 2104 rx_fifo1 = URE_RXFIFO_THR2_HIGH; 2105 rx_fifo2 = URE_RXFIFO_THR3_HIGH; 2106 } 2107 ure_write_4(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1); 2108 ure_write_4(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2); 2109 2110 /* Configure Tx FIFO threshold. */ 2111 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 2112 URE_TXFIFO_THR_NORMAL); 2113 } 2114 2115 /* 2116 * Update mbuf for rx checksum from hardware 2117 */ 2118 static void 2119 ure_rxcsum(int capenb, struct ure_rxpkt *rp, struct mbuf *m) 2120 { 2121 int flags; 2122 uint32_t csum, misc; 2123 int tcp, udp; 2124 2125 m->m_pkthdr.csum_flags = 0; 2126 2127 if (!(capenb & IFCAP_RXCSUM)) 2128 return; 2129 2130 csum = le32toh(rp->ure_csum); 2131 misc = le32toh(rp->ure_misc); 2132 2133 tcp = udp = 0; 2134 2135 flags = 0; 2136 if (csum & URE_RXPKT_IPV4_CS) 2137 flags |= CSUM_IP_CHECKED; 2138 else if (csum & URE_RXPKT_IPV6_CS) 2139 flags = 0; 2140 2141 tcp = rp->ure_csum & URE_RXPKT_TCP_CS; 2142 udp = rp->ure_csum & URE_RXPKT_UDP_CS; 2143 2144 if (__predict_true((flags & CSUM_IP_CHECKED) && 2145 !(misc & URE_RXPKT_IP_F))) { 2146 flags |= CSUM_IP_VALID; 2147 } 2148 if (__predict_true( 2149 (tcp && !(misc & URE_RXPKT_TCP_F)) || 2150 (udp && !(misc & URE_RXPKT_UDP_F)))) { 2151 flags |= CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2152 m->m_pkthdr.csum_data = 0xFFFF; 2153 } 2154 2155 m->m_pkthdr.csum_flags = flags; 2156 } 2157 2158 /* 2159 * If the L4 checksum offset is larger than 0x7ff (2047), return failure. 2160 * We currently restrict MTU such that it can't happen, and even if we 2161 * did have a large enough MTU, only a very specially crafted IPv6 packet 2162 * with MANY headers could possibly come close. 2163 * 2164 * Returns 0 for success, and 1 if the packet cannot be checksummed and 2165 * should be dropped. 2166 */ 2167 static int 2168 ure_txcsum(struct mbuf *m, int caps, uint32_t *regout) 2169 { 2170 struct ip ip; 2171 struct ether_header *eh; 2172 int flags; 2173 uint32_t data; 2174 uint32_t reg; 2175 int l3off, l4off; 2176 uint16_t type; 2177 2178 *regout = 0; 2179 flags = m->m_pkthdr.csum_flags; 2180 if (flags == 0) 2181 return (0); 2182 2183 if (__predict_true(m->m_len >= (int)sizeof(*eh))) { 2184 eh = mtod(m, struct ether_header *); 2185 type = eh->ether_type; 2186 } else 2187 m_copydata(m, offsetof(struct ether_header, ether_type), 2188 sizeof(type), (caddr_t)&type); 2189 2190 switch (type = htons(type)) { 2191 case ETHERTYPE_IP: 2192 case ETHERTYPE_IPV6: 2193 l3off = ETHER_HDR_LEN; 2194 break; 2195 case ETHERTYPE_VLAN: 2196 /* XXX - what about QinQ? */ 2197 l3off = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2198 break; 2199 default: 2200 return (0); 2201 } 2202 2203 reg = 0; 2204 2205 if (flags & CSUM_IP) 2206 reg |= URE_TXPKT_IPV4_CS; 2207 2208 data = m->m_pkthdr.csum_data; 2209 if (flags & (CSUM_IP_TCP | CSUM_IP_UDP)) { 2210 m_copydata(m, l3off, sizeof ip, (caddr_t)&ip); 2211 l4off = l3off + (ip.ip_hl << 2) + data; 2212 if (__predict_false(l4off > URE_L4_OFFSET_MAX)) 2213 return (1); 2214 2215 reg |= URE_TXPKT_IPV4_CS; 2216 if (flags & CSUM_IP_TCP) 2217 reg |= URE_TXPKT_TCP_CS; 2218 else if (flags & CSUM_IP_UDP) 2219 reg |= URE_TXPKT_UDP_CS; 2220 reg |= l4off << URE_L4_OFFSET_SHIFT; 2221 } 2222 #ifdef INET6 2223 else if (flags & (CSUM_IP6_TCP | CSUM_IP6_UDP)) { 2224 l4off = l3off + data; 2225 if (__predict_false(l4off > URE_L4_OFFSET_MAX)) 2226 return (1); 2227 2228 reg |= URE_TXPKT_IPV6_CS; 2229 if (flags & CSUM_IP6_TCP) 2230 reg |= URE_TXPKT_TCP_CS; 2231 else if (flags & CSUM_IP6_UDP) 2232 reg |= URE_TXPKT_UDP_CS; 2233 reg |= l4off << URE_L4_OFFSET_SHIFT; 2234 } 2235 #endif 2236 *regout = reg; 2237 return 0; 2238 } 2239