1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 1998 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Lennart Augustsson (lennart@augustsson.net) at 8 * Carlstedt Research & Technology. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _OHCI_H_ 40 #define _OHCI_H_ 41 42 #define OHCI_MAX_DEVICES USB_MAX_DEVICES 43 44 /* PCI config registers */ 45 #define PCI_CBMEM 0x10 /* configuration base memory */ 46 #define PCI_INTERFACE_OHCI 0x10 47 48 /* OHCI registers */ 49 #define OHCI_REVISION 0x00 /* OHCI revision */ 50 #define OHCI_REV_LO(rev) ((rev) & 0xf) 51 #define OHCI_REV_HI(rev) (((rev)>>4) & 0xf) 52 #define OHCI_REV_LEGACY(rev) ((rev) & 0x100) 53 #define OHCI_CONTROL 0x04 54 #define OHCI_CBSR_MASK 0x00000003 /* Control/Bulk Service Ratio */ 55 #define OHCI_RATIO_1_1 0x00000000 56 #define OHCI_RATIO_1_2 0x00000001 57 #define OHCI_RATIO_1_3 0x00000002 58 #define OHCI_RATIO_1_4 0x00000003 59 #define OHCI_PLE 0x00000004 /* Periodic List Enable */ 60 #define OHCI_IE 0x00000008 /* Isochronous Enable */ 61 #define OHCI_CLE 0x00000010 /* Control List Enable */ 62 #define OHCI_BLE 0x00000020 /* Bulk List Enable */ 63 #define OHCI_HCFS_MASK 0x000000c0 /* HostControllerFunctionalStat 64 * e */ 65 #define OHCI_HCFS_RESET 0x00000000 66 #define OHCI_HCFS_RESUME 0x00000040 67 #define OHCI_HCFS_OPERATIONAL 0x00000080 68 #define OHCI_HCFS_SUSPEND 0x000000c0 69 #define OHCI_IR 0x00000100 /* Interrupt Routing */ 70 #define OHCI_RWC 0x00000200 /* Remote Wakeup Connected */ 71 #define OHCI_RWE 0x00000400 /* Remote Wakeup Enabled */ 72 #define OHCI_COMMAND_STATUS 0x08 73 #define OHCI_HCR 0x00000001 /* Host Controller Reset */ 74 #define OHCI_CLF 0x00000002 /* Control List Filled */ 75 #define OHCI_BLF 0x00000004 /* Bulk List Filled */ 76 #define OHCI_OCR 0x00000008 /* Ownership Change Request */ 77 #define OHCI_SOC_MASK 0x00030000 /* Scheduling Overrun Count */ 78 #define OHCI_INTERRUPT_STATUS 0x0c 79 #define OHCI_SO 0x00000001 /* Scheduling Overrun */ 80 #define OHCI_WDH 0x00000002 /* Writeback Done Head */ 81 #define OHCI_SF 0x00000004 /* Start of Frame */ 82 #define OHCI_RD 0x00000008 /* Resume Detected */ 83 #define OHCI_UE 0x00000010 /* Unrecoverable Error */ 84 #define OHCI_FNO 0x00000020 /* Frame Number Overflow */ 85 #define OHCI_RHSC 0x00000040 /* Root Hub Status Change */ 86 #define OHCI_OC 0x40000000 /* Ownership Change */ 87 #define OHCI_MIE 0x80000000 /* Master Interrupt Enable */ 88 #define OHCI_INTERRUPT_ENABLE 0x10 89 #define OHCI_INTERRUPT_DISABLE 0x14 90 #define OHCI_HCCA 0x18 91 #define OHCI_PERIOD_CURRENT_ED 0x1c 92 #define OHCI_CONTROL_HEAD_ED 0x20 93 #define OHCI_CONTROL_CURRENT_ED 0x24 94 #define OHCI_BULK_HEAD_ED 0x28 95 #define OHCI_BULK_CURRENT_ED 0x2c 96 #define OHCI_DONE_HEAD 0x30 97 #define OHCI_FM_INTERVAL 0x34 98 #define OHCI_GET_IVAL(s) ((s) & 0x3fff) 99 #define OHCI_GET_FSMPS(s) (((s) >> 16) & 0x7fff) 100 #define OHCI_FIT 0x80000000 101 #define OHCI_FM_REMAINING 0x38 102 #define OHCI_FM_NUMBER 0x3c 103 #define OHCI_PERIODIC_START 0x40 104 #define OHCI_LS_THRESHOLD 0x44 105 #define OHCI_RH_DESCRIPTOR_A 0x48 106 #define OHCI_GET_NDP(s) ((s) & 0xff) 107 #define OHCI_PSM 0x0100 /* Power Switching Mode */ 108 #define OHCI_NPS 0x0200 /* No Power Switching */ 109 #define OHCI_DT 0x0400 /* Device Type */ 110 #define OHCI_OCPM 0x0800 /* Overcurrent Protection Mode */ 111 #define OHCI_NOCP 0x1000 /* No Overcurrent Protection */ 112 #define OHCI_GET_POTPGT(s) ((s) >> 24) 113 #define OHCI_RH_DESCRIPTOR_B 0x4c 114 #define OHCI_RH_STATUS 0x50 115 #define OHCI_LPS 0x00000001 /* Local Power Status */ 116 #define OHCI_OCI 0x00000002 /* OverCurrent Indicator */ 117 #define OHCI_DRWE 0x00008000 /* Device Remote Wakeup Enable */ 118 #define OHCI_LPSC 0x00010000 /* Local Power Status Change */ 119 #define OHCI_CCIC 0x00020000 /* OverCurrent Indicator 120 * Change */ 121 #define OHCI_CRWE 0x80000000 /* Clear Remote Wakeup Enable */ 122 #define OHCI_RH_PORT_STATUS(n) (0x50 + ((n)*4)) /* 1 based indexing */ 123 124 #define OHCI_LES (OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE) 125 #define OHCI_ALL_INTRS (OHCI_SO | OHCI_WDH | OHCI_SF | \ 126 OHCI_RD | OHCI_UE | OHCI_FNO | \ 127 OHCI_RHSC | OHCI_OC) 128 #define OHCI_NORMAL_INTRS (OHCI_WDH | OHCI_RD | OHCI_UE | OHCI_RHSC) 129 130 #define OHCI_FSMPS(i) (((i-210)*6/7) << 16) 131 #define OHCI_PERIODIC(i) ((i)*9/10) 132 133 #define OHCI_NO_INTRS 32 134 #define OHCI_HCCA_SIZE 256 135 136 /* Structures alignment (bytes) */ 137 #define OHCI_HCCA_ALIGN 256 138 #define OHCI_ED_ALIGN 16 139 #define OHCI_TD_ALIGN 16 140 #define OHCI_ITD_ALIGN 32 141 142 #define OHCI_PAGE_SIZE 0x1000 143 #define OHCI_PAGE(x) ((x) &~ 0xfff) 144 #define OHCI_PAGE_OFFSET(x) ((x) & 0xfff) 145 #define OHCI_PAGE_MASK(x) ((x) & 0xfff) 146 147 #if ((USB_PAGE_SIZE < OHCI_ED_ALIGN) || (OHCI_ED_ALIGN == 0) || \ 148 (USB_PAGE_SIZE < OHCI_TD_ALIGN) || (OHCI_TD_ALIGN == 0) || \ 149 (USB_PAGE_SIZE < OHCI_ITD_ALIGN) || (OHCI_ITD_ALIGN == 0) || \ 150 (USB_PAGE_SIZE < OHCI_PAGE_SIZE) || (OHCI_PAGE_SIZE == 0)) 151 #error "Invalid USB page size!" 152 #endif 153 154 #define OHCI_VIRTUAL_FRAMELIST_COUNT 128/* dummy */ 155 156 #if (OHCI_VIRTUAL_FRAMELIST_COUNT < USB_MAX_FS_ISOC_FRAMES_PER_XFER) 157 #error "maximum number of full-speed isochronous frames is higher than supported!" 158 #endif 159 160 struct ohci_hcca { 161 volatile uint32_t hcca_interrupt_table[OHCI_NO_INTRS]; 162 volatile uint32_t hcca_frame_number; 163 volatile uint32_t hcca_done_head; 164 #define OHCI_DONE_INTRS 1 165 } __aligned(OHCI_HCCA_ALIGN); 166 167 typedef struct ohci_hcca ohci_hcca_t; 168 169 struct ohci_ed { 170 volatile uint32_t ed_flags; 171 #define OHCI_ED_GET_FA(s) ((s) & 0x7f) 172 #define OHCI_ED_ADDRMASK 0x0000007f 173 #define OHCI_ED_SET_FA(s) (s) 174 #define OHCI_ED_GET_EN(s) (((s) >> 7) & 0xf) 175 #define OHCI_ED_SET_EN(s) ((s) << 7) 176 #define OHCI_ED_DIR_MASK 0x00001800 177 #define OHCI_ED_DIR_TD 0x00000000 178 #define OHCI_ED_DIR_OUT 0x00000800 179 #define OHCI_ED_DIR_IN 0x00001000 180 #define OHCI_ED_SPEED 0x00002000 181 #define OHCI_ED_SKIP 0x00004000 182 #define OHCI_ED_FORMAT_GEN 0x00000000 183 #define OHCI_ED_FORMAT_ISO 0x00008000 184 #define OHCI_ED_GET_MAXP(s) (((s) >> 16) & 0x07ff) 185 #define OHCI_ED_SET_MAXP(s) ((s) << 16) 186 #define OHCI_ED_MAXPMASK (0x7ff << 16) 187 volatile uint32_t ed_tailp; 188 volatile uint32_t ed_headp; 189 #define OHCI_HALTED 0x00000001 190 #define OHCI_TOGGLECARRY 0x00000002 191 #define OHCI_HEADMASK 0xfffffffc 192 volatile uint32_t ed_next; 193 /* 194 * Extra information needed: 195 */ 196 struct ohci_ed *next; 197 struct ohci_ed *prev; 198 struct ohci_ed *obj_next; 199 struct usb2_page_cache *page_cache; 200 uint32_t ed_self; 201 } __aligned(OHCI_ED_ALIGN); 202 203 typedef struct ohci_ed ohci_ed_t; 204 205 struct ohci_td { 206 volatile uint32_t td_flags; 207 #define OHCI_TD_R 0x00040000 /* Buffer Rounding */ 208 #define OHCI_TD_DP_MASK 0x00180000 /* Direction / PID */ 209 #define OHCI_TD_SETUP 0x00000000 210 #define OHCI_TD_OUT 0x00080000 211 #define OHCI_TD_IN 0x00100000 212 #define OHCI_TD_GET_DI(x) (((x) >> 21) & 7) /* Delay Interrupt */ 213 #define OHCI_TD_SET_DI(x) ((x) << 21) 214 #define OHCI_TD_NOINTR 0x00e00000 215 #define OHCI_TD_INTR_MASK 0x00e00000 216 #define OHCI_TD_TOGGLE_CARRY 0x00000000 217 #define OHCI_TD_TOGGLE_0 0x02000000 218 #define OHCI_TD_TOGGLE_1 0x03000000 219 #define OHCI_TD_TOGGLE_MASK 0x03000000 220 #define OHCI_TD_GET_EC(x) (((x) >> 26) & 3) /* Error Count */ 221 #define OHCI_TD_GET_CC(x) ((x) >> 28) /* Condition Code */ 222 #define OHCI_TD_SET_CC(x) ((x) << 28) 223 #define OHCI_TD_NOCC 0xf0000000 224 volatile uint32_t td_cbp; /* Current Buffer Pointer */ 225 volatile uint32_t td_next; /* Next TD */ 226 #define OHCI_TD_NEXT_END 0 227 volatile uint32_t td_be; /* Buffer End */ 228 /* 229 * Extra information needed: 230 */ 231 struct ohci_td *obj_next; 232 struct ohci_td *alt_next; 233 struct usb2_page_cache *page_cache; 234 uint32_t td_self; 235 uint16_t len; 236 } __aligned(OHCI_TD_ALIGN); 237 238 typedef struct ohci_td ohci_td_t; 239 240 struct ohci_itd { 241 volatile uint32_t itd_flags; 242 #define OHCI_ITD_GET_SF(x) ((x) & 0x0000ffff) 243 #define OHCI_ITD_SET_SF(x) ((x) & 0xffff) 244 #define OHCI_ITD_GET_DI(x) (((x) >> 21) & 7) /* Delay Interrupt */ 245 #define OHCI_ITD_SET_DI(x) ((x) << 21) 246 #define OHCI_ITD_NOINTR 0x00e00000 247 #define OHCI_ITD_GET_FC(x) ((((x) >> 24) & 7)+1) /* Frame Count */ 248 #define OHCI_ITD_SET_FC(x) (((x)-1) << 24) 249 #define OHCI_ITD_GET_CC(x) ((x) >> 28) /* Condition Code */ 250 #define OHCI_ITD_NOCC 0xf0000000 251 #define OHCI_ITD_NOFFSET 8 252 volatile uint32_t itd_bp0; /* Buffer Page 0 */ 253 volatile uint32_t itd_next; /* Next ITD */ 254 volatile uint32_t itd_be; /* Buffer End */ 255 volatile uint16_t itd_offset[OHCI_ITD_NOFFSET]; /* Buffer offsets and 256 * Status */ 257 #define OHCI_ITD_PAGE_SELECT 0x00001000 258 #define OHCI_ITD_MK_OFFS(len) (0xe000 | ((len) & 0x1fff)) 259 #define OHCI_ITD_PSW_LENGTH(x) ((x) & 0xfff) /* Transfer length */ 260 #define OHCI_ITD_PSW_GET_CC(x) ((x) >> 12) /* Condition Code */ 261 /* 262 * Extra information needed: 263 */ 264 struct ohci_itd *obj_next; 265 struct usb2_page_cache *page_cache; 266 uint32_t itd_self; 267 uint8_t frames; 268 } __aligned(OHCI_ITD_ALIGN); 269 270 typedef struct ohci_itd ohci_itd_t; 271 272 #define OHCI_CC_NO_ERROR 0 273 #define OHCI_CC_CRC 1 274 #define OHCI_CC_BIT_STUFFING 2 275 #define OHCI_CC_DATA_TOGGLE_MISMATCH 3 276 #define OHCI_CC_STALL 4 277 #define OHCI_CC_DEVICE_NOT_RESPONDING 5 278 #define OHCI_CC_PID_CHECK_FAILURE 6 279 #define OHCI_CC_UNEXPECTED_PID 7 280 #define OHCI_CC_DATA_OVERRUN 8 281 #define OHCI_CC_DATA_UNDERRUN 9 282 #define OHCI_CC_BUFFER_OVERRUN 12 283 #define OHCI_CC_BUFFER_UNDERRUN 13 284 #define OHCI_CC_NOT_ACCESSED 15 285 286 /* Some delay needed when changing certain registers. */ 287 #define OHCI_ENABLE_POWER_DELAY 5 288 #define OHCI_READ_DESC_DELAY 5 289 290 #define OHCI_NO_EDS (2*OHCI_NO_INTRS) 291 292 struct ohci_hw_softc { 293 struct usb2_page_cache hcca_pc; 294 struct usb2_page_cache ctrl_start_pc; 295 struct usb2_page_cache bulk_start_pc; 296 struct usb2_page_cache isoc_start_pc; 297 struct usb2_page_cache intr_start_pc[OHCI_NO_EDS]; 298 299 struct usb2_page hcca_pg; 300 struct usb2_page ctrl_start_pg; 301 struct usb2_page bulk_start_pg; 302 struct usb2_page isoc_start_pg; 303 struct usb2_page intr_start_pg[OHCI_NO_EDS]; 304 }; 305 306 struct ohci_config_desc { 307 struct usb2_config_descriptor confd; 308 struct usb2_interface_descriptor ifcd; 309 struct usb2_endpoint_descriptor endpd; 310 } __packed; 311 312 union ohci_hub_desc { 313 struct usb2_status stat; 314 struct usb2_port_status ps; 315 struct usb2_device_descriptor devd; 316 struct usb2_hub_descriptor hubd; 317 uint8_t temp[128]; 318 }; 319 320 typedef struct ohci_softc { 321 struct ohci_hw_softc sc_hw; 322 struct usb2_bus sc_bus; /* base device */ 323 struct usb2_callout sc_tmo_rhsc; 324 union ohci_hub_desc sc_hub_desc; 325 struct usb2_sw_transfer sc_root_ctrl; 326 struct usb2_sw_transfer sc_root_intr; 327 328 struct usb2_device *sc_devices[OHCI_MAX_DEVICES]; 329 struct resource *sc_io_res; 330 struct resource *sc_irq_res; 331 struct ohci_hcca *sc_hcca_p; 332 struct ohci_ed *sc_ctrl_p_last; 333 struct ohci_ed *sc_bulk_p_last; 334 struct ohci_ed *sc_isoc_p_last; 335 struct ohci_ed *sc_intr_p_last[OHCI_NO_EDS]; 336 void *sc_intr_hdl; 337 device_t sc_dev; 338 bus_size_t sc_io_size; 339 bus_space_tag_t sc_io_tag; 340 bus_space_handle_t sc_io_hdl; 341 342 uint32_t sc_eintrs; /* enabled interrupts */ 343 uint32_t sc_control; /* Preserved during suspend/standby */ 344 uint32_t sc_intre; 345 346 uint16_t sc_intr_stat[OHCI_NO_EDS]; 347 uint16_t sc_id_vendor; 348 349 uint8_t sc_noport; 350 uint8_t sc_addr; /* device address */ 351 uint8_t sc_conf; /* device configuration */ 352 uint8_t sc_hub_idata[32]; 353 354 char sc_vendor[16]; 355 356 } ohci_softc_t; 357 358 usb2_bus_mem_cb_t ohci_iterate_hw_softc; 359 360 usb2_error_t ohci_init(ohci_softc_t *sc); 361 void ohci_detach(struct ohci_softc *sc); 362 void ohci_suspend(ohci_softc_t *sc); 363 void ohci_resume(ohci_softc_t *sc); 364 void ohci_interrupt(ohci_softc_t *sc); 365 366 #endif /* _OHCI_H_ */ 367