1 /*- 2 * Copyright (c) 2025, Samsung Electronics Co., Ltd. 3 * Written by Jaeyoon Choi 4 * 5 * SPDX-License-Identifier: BSD-2-Clause 6 */ 7 #ifndef __UFSHCI_REG_H__ 8 #define __UFSHCI_REG_H__ 9 10 #include <sys/param.h> 11 #include <sys/endian.h> 12 13 /* UFSHCI 4.1, section 5.1 Register Map */ 14 struct ufshci_registers { 15 /* Host Capabilities (00h) */ 16 uint32_t cap; /* Host Controller Capabiities */ 17 uint32_t mcqcap; /* Multi-Circular Queue Capability Register */ 18 uint32_t ver; /* UFS Version */ 19 uint32_t ext_cap; /* Extended Controller Capabilities */ 20 uint32_t hcpid; /* Product ID */ 21 uint32_t hcmid; /* Manufacturer ID */ 22 uint32_t ahit; /* Auto-Hibernate Idle Timer */ 23 uint32_t reserved1; 24 /* Operation and Runtime (20h) */ 25 uint32_t is; /* Interrupt Status */ 26 uint32_t ie; /* Interrupt Enable */ 27 uint32_t reserved2; 28 uint32_t hcsext; /* Host Controller Status Extended */ 29 uint32_t hcs; /* Host Controller Status */ 30 uint32_t hce; /* Host Controller Enable */ 31 uint32_t uecpa; /* Host UIC Error Code PHY Adapter Layer */ 32 uint32_t uecdl; /* Host UIC Error Code Data Link Layer */ 33 uint32_t uecn; /* Host UIC Error Code Network Layer */ 34 uint32_t uect; /* Host UIC Error Code Transport Layer */ 35 uint32_t uecdme; /* Host UIC Error Code DME */ 36 uint32_t utriacr; /* Interrupt Aggregation Control */ 37 /* UTP Transfer (50h) */ 38 uint32_t utrlba; /* UTRL Base Address */ 39 uint32_t utrlbau; /* UTRL Base Address Upper 32-Bits */ 40 uint32_t utrldbr; /* UTRL DoorBell Register */ 41 uint32_t utrlclr; /* UTRL CLear Register */ 42 uint32_t utrlrsr; /* UTR Run-Stop Register */ 43 uint32_t utrlcnr; /* UTRL Completion Notification */ 44 uint64_t reserved3; 45 /* UTP Task Managemeng (70h) */ 46 uint32_t utmrlba; /* UTRL Base Address */ 47 uint32_t utmrlbau; /* UTMRL Base Address Upper 32-Bits */ 48 uint32_t utmrldbr; /* UTMRL DoorBell Register */ 49 uint32_t utmrlclr; /* UTMRL CLear Register */ 50 uint32_t utmrlrsr; /* UTM Run-Stop Register */ 51 uint8_t reserved4[12]; 52 /* UIC Command (90h) */ 53 uint32_t uiccmd; /* UIC Command Register */ 54 uint32_t ucmdarg1; /* UIC Command Argument 1 */ 55 uint32_t ucmdarg2; /* UIC Command Argument 2 */ 56 uint32_t ucmdarg3; /* UIC Command Argument 3 */ 57 uint8_t reserved5[16]; 58 /* UMA (B0h) */ 59 uint8_t reserved6[16]; /* Reserved for Unified Memory Extension */ 60 /* Vendor Specific (C0h) */ 61 uint8_t vendor[64]; /* Vendor Specific Registers */ 62 /* Crypto (100h) */ 63 uint32_t ccap; /* Crypto Capability */ 64 uint32_t reserved7[511]; 65 /* Config (300h) */ 66 uint32_t config; /* Global Configuration */ 67 uint8_t reserved9[124]; 68 /* MCQ Configuration (380h) */ 69 uint32_t mcqconfig; /* MCQ Config Register */ 70 /* Event Specific Interrupt Lower Base Address */ 71 uint32_t esilba; 72 /* Event Specific Interrupt Upper Base Address */ 73 uint32_t esiuba; 74 /* TODO: Need to define SQ/CQ registers */ 75 }; 76 77 /* Register field definitions */ 78 #define UFSHCI__REG__SHIFT (0) 79 #define UFSHCI__REG__MASK (0) 80 81 /* 82 * UFSHCI 4.1, section 5.2.1, Offset 00h: CAP 83 * Controller Capabilities 84 */ 85 #define UFSHCI_CAP_REG_NUTRS_SHIFT (0) 86 #define UFSHCI_CAP_REG_NUTRS_MASK (0xFF) 87 #define UFSHCI_CAP_REG_NORTT_SHIFT (8) 88 #define UFSHCI_CAP_REG_NORTT_MASK (0xFF) 89 #define UFSHCI_CAP_REG_NUTMRS_SHIFT (16) 90 #define UFSHCI_CAP_REG_NUTMRS_MASK (0x7) 91 #define UFSHCI_CAP_REG_EHSLUTRDS_SHIFT (22) 92 #define UFSHCI_CAP_REG_EHSLUTRDS_MASK (0x1) 93 #define UFSHCI_CAP_REG_AUTOH8_SHIFT (23) 94 #define UFSHCI_CAP_REG_AUTOH8_MASK (0x1) 95 #define UFSHCI_CAP_REG_64AS_SHIFT (24) 96 #define UFSHCI_CAP_REG_64AS_MASK (0x1) 97 #define UFSHCI_CAP_REG_OODDS_SHIFT (25) 98 #define UFSHCI_CAP_REG_OODDS_MASK (0x1) 99 #define UFSHCI_CAP_REG_UICDMETMS_SHIFT (26) 100 #define UFSHCI_CAP_REG_UICDMETMS_MASK (0x1) 101 #define UFSHCI_CAP_REG_CS_SHIFT (28) 102 #define UFSHCI_CAP_REG_CS_MASK (0x1) 103 #define UFSHCI_CAP_REG_LSDBS_SHIFT (29) 104 #define UFSHCI_CAP_REG_LSDBS_MASK (0x1) 105 #define UFSHCI_CAP_REG_MCQS_SHIFT (30) 106 #define UFSHCI_CAP_REG_MCQS_MASK (0x1) 107 #define UFSHCI_CAP_REG_EIS_SHIFT (31) 108 #define UFSHCI_CAP_REG_EIS_MASK (0x1) 109 110 /* 111 * UFSHCI 4.1, section 5.2.2, Offset 04h: MCQCAP 112 * Multi-Circular Queue Capability Register 113 */ 114 #define UFSHCI_MCQCAP_REG_MAXQ_SHIFT (0) 115 #define UFSHCI_MCQCAP_REG_MAXQ_MASK (0xFF) 116 #define UFSHCI_MCQCAP_REG_SP_SHIFT (8) 117 #define UFSHCI_MCQCAP_REG_SP_MASK (0x1) 118 #define UFSHCI_MCQCAP_REG_RRP_SHIFT (9) 119 #define UFSHCI_MCQCAP_REG_RRP_MASK (0x1) 120 #define UFSHCI_MCQCAP_REG_EIS_SHIFT (10) 121 #define UFSHCI_MCQCAP_REG_EIS_MASK (0x1) 122 #define UFSHCI_MCQCAP_REG_QCFGPTR_SHIFT (16) 123 #define UFSHCI_MCQCAP_REG_QCFGPTR_MASK (0xFF) 124 #define UFSHCI_MCQCAP_REG_MIAG_SHIFT (24) 125 #define UFSHCI_MCQCAP_REG_MIAG_MASK (0xFF) 126 127 /* 128 * UFSHCI 4.1, section 5.2.3, Offset 08h: VER 129 * UFS Version 130 */ 131 #define UFSHCI_VER_REG_VS_SHIFT (0) 132 #define UFSHCI_VER_REG_VS_MASK (0xF) 133 #define UFSHCI_VER_REG_MNR_SHIFT (4) 134 #define UFSHCI_VER_REG_MNR_MASK (0xF) 135 #define UFSHCI_VER_REG_MJR_SHIFT (8) 136 #define UFSHCI_VER_REG_MJR_MASK (0xFF) 137 138 /* 139 * UFSHCI 4.1, section 5.2.4, Offset 0Ch: EXT_CAP 140 * Extended Controller Capabilities 141 */ 142 #define UFSHCI_EXTCAP_REG_HOST_HINT_CACAHE_SIZE_SHIFT (0) 143 #define UFSHCI_EXTCAP_REG_HOST_HINT_CACAHE_SIZE_MASK (0xFFFF) 144 145 /* 146 * UFSHCI 4.1, section 5.2.5, Offset 10h: HCPID 147 * Host Controller Identification Descriptor – Product ID 148 */ 149 #define UFSHCI_HCPID_REG_PID_SHIFT (0) 150 #define UFSHCI_HCPID_REG_PID_MASK (0xFFFFFFFF) 151 152 /* 153 * UFSHCI 4.1, section 5.2.6, Offset 14h: HCMID 154 * Host Controller Identification Descriptor – Manufacturer ID 155 */ 156 #define UFSHCI_HCMID_REG_MIC_SHIFT (0) 157 #define UFSHCI_HCMID_REG_MIC_MASK (0xFFFF) 158 #define UFSHCI_HCMID_REG_BI_SHIFT (8) 159 #define UFSHCI_HCMID_REG_BI_MASK (0xFFFF) 160 161 /* 162 * UFSHCI 4.1, section 5.2.7, Offset 18h: AHIT 163 * Auto-Hibernate Idle Timer 164 */ 165 #define UFSHCI_AHIT_REG_AH8ITV_SHIFT (0) 166 #define UFSHCI_AHIT_REG_AH8ITV_MASK (0x3FF) 167 #define UFSHCI_AHIT_REG_TS_SHIFT (10) 168 #define UFSHCI_AHIT_REG_TS_MASK (0x7) 169 170 /* 171 * UFSHCI 4.1, section 5.3.1, Offset 20h: IS 172 * Interrupt Status 173 */ 174 #define UFSHCI_IS_REG_UTRCS_SHIFT (0) 175 #define UFSHCI_IS_REG_UTRCS_MASK (0x1) 176 #define UFSHCI_IS_REG_UDEPRI_SHIFT (1) 177 #define UFSHCI_IS_REG_UDEPRI_MASK (0x1) 178 #define UFSHCI_IS_REG_UE_SHIFT (2) 179 #define UFSHCI_IS_REG_UE_MASK (0x1) 180 #define UFSHCI_IS_REG_UTMS_SHIFT (3) 181 #define UFSHCI_IS_REG_UTMS_MASK (0x1) 182 #define UFSHCI_IS_REG_UPMS_SHIFT (4) 183 #define UFSHCI_IS_REG_UPMS_MASK (0x1) 184 #define UFSHCI_IS_REG_UHXS_SHIFT (5) 185 #define UFSHCI_IS_REG_UHXS_MASK (0x1) 186 #define UFSHCI_IS_REG_UHES_SHIFT (6) 187 #define UFSHCI_IS_REG_UHES_MASK (0x1) 188 #define UFSHCI_IS_REG_ULLS_SHIFT (7) 189 #define UFSHCI_IS_REG_ULLS_MASK (0x1) 190 #define UFSHCI_IS_REG_ULSS_SHIFT (8) 191 #define UFSHCI_IS_REG_ULSS_MASK (0x1) 192 #define UFSHCI_IS_REG_UTMRCS_SHIFT (9) 193 #define UFSHCI_IS_REG_UTMRCS_MASK (0x1) 194 #define UFSHCI_IS_REG_UCCS_SHIFT (10) 195 #define UFSHCI_IS_REG_UCCS_MASK (0x1) 196 #define UFSHCI_IS_REG_DFES_SHIFT (11) 197 #define UFSHCI_IS_REG_DFES_MASK (0x1) 198 #define UFSHCI_IS_REG_UTPES_SHIFT (12) 199 #define UFSHCI_IS_REG_UTPES_MASK (0x1) 200 #define UFSHCI_IS_REG_HCFES_SHIFT (16) 201 #define UFSHCI_IS_REG_HCFES_MASK (0x1) 202 #define UFSHCI_IS_REG_SBFES_SHIFT (17) 203 #define UFSHCI_IS_REG_SBFES_MASK (0x1) 204 #define UFSHCI_IS_REG_CEFES_SHIFT (18) 205 #define UFSHCI_IS_REG_CEFES_MASK (0x1) 206 #define UFSHCI_IS_REG_SQES_SHIFT (19) 207 #define UFSHCI_IS_REG_SQES_MASK (0x1) 208 #define UFSHCI_IS_REG_CQES_SHIFT (20) 209 #define UFSHCI_IS_REG_CQES_MASK (0x1) 210 #define UFSHCI_IS_REG_IAGES_SHIFT (21) 211 #define UFSHCI_IS_REG_IAGES_MASK (0x1) 212 213 /* 214 * UFSHCI 4.1, section 5.3.2, Offset 24h: IE 215 * Interrupt Enable 216 */ 217 #define UFSHCI_IE_REG_UTRCE_SHIFT (0) 218 #define UFSHCI_IE_REG_UTRCE_MASK (0x1) 219 #define UFSHCI_IE_REG_UDEPRIE_SHIFT (1) 220 #define UFSHCI_IE_REG_UDEPRIE_MASK (0x1) 221 #define UFSHCI_IE_REG_UEE_SHIFT (2) 222 #define UFSHCI_IE_REG_UEE_MASK (0x1) 223 #define UFSHCI_IE_REG_UTMSE_SHIFT (3) 224 #define UFSHCI_IE_REG_UTMSE_MASK (0x1) 225 #define UFSHCI_IE_REG_UPMSE_SHIFT (4) 226 #define UFSHCI_IE_REG_UPMSE_MASK (0x1) 227 #define UFSHCI_IE_REG_UHXSE_SHIFT (5) 228 #define UFSHCI_IE_REG_UHXSE_MASK (0x1) 229 #define UFSHCI_IE_REG_UHESE_SHIFT (6) 230 #define UFSHCI_IE_REG_UHESE_MASK (0x1) 231 #define UFSHCI_IE_REG_ULLSE_SHIFT (7) 232 #define UFSHCI_IE_REG_ULLSE_MASK (0x1) 233 #define UFSHCI_IE_REG_ULSSE_SHIFT (8) 234 #define UFSHCI_IE_REG_ULSSE_MASK (0x1) 235 #define UFSHCI_IE_REG_UTMRCE_SHIFT (9) 236 #define UFSHCI_IE_REG_UTMRCE_MASK (0x1) 237 #define UFSHCI_IE_REG_UCCE_SHIFT (10) 238 #define UFSHCI_IE_REG_UCCE_MASK (0x1) 239 #define UFSHCI_IE_REG_DFEE_SHIFT (11) 240 #define UFSHCI_IE_REG_DFEE_MASK (0x1) 241 #define UFSHCI_IE_REG_UTPEE_SHIFT (12) 242 #define UFSHCI_IE_REG_UTPEE_MASK (0x1) 243 #define UFSHCI_IE_REG_HCFEE_SHIFT (16) 244 #define UFSHCI_IE_REG_HCFEE_MASK (0x1) 245 #define UFSHCI_IE_REG_SBFEE_SHIFT (17) 246 #define UFSHCI_IE_REG_SBFEE_MASK (0x1) 247 #define UFSHCI_IE_REG_CEFEE_SHIFT (18) 248 #define UFSHCI_IE_REG_CEFEE_MASK (0x1) 249 #define UFSHCI_IE_REG_SQEE_SHIFT (19) 250 #define UFSHCI_IE_REG_SQEE_MASK (0x1) 251 #define UFSHCI_IE_REG_CQEE_SHIFT (20) 252 #define UFSHCI_IE_REG_CQEE_MASK (0x1) 253 #define UFSHCI_IE_REG_IAGEE_SHIFT (21) 254 #define UFSHCI_IE_REG_IAGEE_MASK (0x1) 255 256 /* 257 * UFSHCI 4.1, section 5.3.3, Offset 2Ch: HCSEXT 258 * Host Controller Status Extended 259 */ 260 #define UFSHCI_HCSEXT_IIDUTPE_SHIFT (0) 261 #define UFSHCI_HCSEXT_IIDUTPE_MASK (0xF) 262 #define UFSHCI_HCSEXT_EXT_IIDUTPE_SHIFT (4) 263 #define UFSHCI_HCSEXT_EXT_IIDUTPE_MASK (0xF) 264 265 /* 266 * UFSHCI 4.1, section 5.3.4, Offset 30h: HCS 267 * Host Controller Status 268 */ 269 #define UFSHCI_HCS_REG_DP_SHIFT (0) 270 #define UFSHCI_HCS_REG_DP_MASK (0x1) 271 #define UFSHCI_HCS_REG_UTRLRDY_SHIFT (1) 272 #define UFSHCI_HCS_REG_UTRLRDY_MASK (0x1) 273 #define UFSHCI_HCS_REG_UTMRLRDY_SHIFT (2) 274 #define UFSHCI_HCS_REG_UTMRLRDY_MASK (0x1) 275 #define UFSHCI_HCS_REG_UCRDY_SHIFT (3) 276 #define UFSHCI_HCS_REG_UCRDY_MASK (0x1) 277 #define UFSHCI_HCS_REG_UPMCRS_SHIFT (7) 278 #define UFSHCI_HCS_REG_UPMCRS_MASK (0x7) 279 #define UFSHCI_HCS_REG_UTPEC_SHIFT (12) 280 #define UFSHCI_HCS_REG_UTPEC_MASK (0xF) 281 #define UFSHCI_HCS_REG_TTAGUTPE_SHIFT (16) 282 #define UFSHCI_HCS_REG_TTAGUTPE_MASK (0xFF) 283 #define UFSHCI_HCS_REG_TLUNUTPE_SHIFT (24) 284 #define UFSHCI_HCS_REG_TLUNUTPE_MASK (0xFF) 285 286 /* 287 * UFSHCI 4.1, section 5.3.5, Offset 34h: HCE 288 * Host Controller Enable 289 */ 290 #define UFSHCI_HCE_REG_HCE_SHIFT (0) 291 #define UFSHCI_HCE_REG_HCE_MASK (0x1) 292 #define UFSHCI_HCE_REG_CGE_SHIFT (1) 293 #define UFSHCI_HCE_REG_CGE_MASK (0x1) 294 295 /* 296 * UFSHCI 4.1, section 5.3.6, Offset 38h: UECPA 297 * Host UIC Error Code PHY Adapter Layer 298 */ 299 #define UFSHCI_UECPA_REG_EC_SHIFT (0) 300 #define UFSHCI_UECPA_REG_EC_MASK (0xF) 301 #define UFSHCI_UECPA_REG_ERR_SHIFT (31) 302 #define UFSHCI_UECPA_REG_ERR_MASK (0x1) 303 304 /* 305 * UFSHCI 4.1, section 5.3.7, Offset 3Ch: UECDL 306 * Host UIC Error Code Data Link Layer 307 */ 308 #define UFSHCI_UECDL_REG_EC_SHIFT (0) 309 #define UFSHCI_UECDL_REG_EC_MASK (0xFFFF) 310 #define UFSHCI_UECDL_REG_ERR_SHIFT (31) 311 #define UFSHCI_UECDL_REG_ERR_MASK (0x1) 312 313 /* 314 * UFSHCI 4.1, section 5.3.8, Offset 40h: UECN 315 * Host UIC Error Code Network Layer 316 */ 317 #define UFSHCI_UECN_REG_EC_SHIFT (0) 318 #define UFSHCI_UECN_REG_EC_MASK (0x7) 319 #define UFSHCI_UECN_REG_ERR_SHIFT (31) 320 #define UFSHCI_UECN_REG_ERR_MASK (0x1) 321 322 /* 323 * UFSHCI 4.1, section 5.3.9, Offset 44h: UECT 324 * Host UIC Error Code Transport Layer 325 */ 326 #define UFSHCI_UECT_REG_EC_SHIFT (0) 327 #define UFSHCI_UECT_REG_EC_MASK (0x7F) 328 #define UFSHCI_UECT_REG_ERR_SHIFT (31) 329 #define UFSHCI_UECT_REG_ERR_MASK (0x1) 330 331 /* 332 * UFSHCI 4.1, section 5.3.10, Offset 48h: UECDME 333 * Host UIC Error Code 334 */ 335 #define UFSHCI_UECDME_REG_EC_SHIFT (0) 336 #define UFSHCI_UECDME_REG_EC_MASK (0xF) 337 #define UFSHCI_UECDME_REG_ERR_SHIFT (31) 338 #define UFSHCI_UECDME_REG_ERR_MASK (0x1) 339 340 /* 341 * UFSHCI 4.1, section 5.4.1, Offset 50h: UTRLBA 342 * UTP Transfer Request List Base Address 343 */ 344 #define UFSHCI_UTRLBA_REG_UTRLBA_SHIFT (0) 345 #define UFSHCI_UTRLBA_REG_UTRLBA_MASK (0xFFFFFFFF) 346 347 /* 348 * UFSHCI 4.1, section 5.4.2, Offset 54h: UTRLBAU 349 * UTP Transfer Request List Base Address Upper 32-bits 350 */ 351 #define UFSHCI_UTRLBAU_REG_UTRLBAU_SHIFT (0) 352 #define UFSHCI_UTRLBAU_REG_UTRLBAU_MASK (0xFFFFFFFF) 353 354 /* 355 * UFSHCI 4.1, section 5.4.3, Offset 58h: UTRLDBR 356 * UTP Transfer Request List Door Bell Register 357 */ 358 #define UFSHCI_UTRLDBR_REG_UTRLDBR_SHIFT (0) 359 #define UFSHCI_UTRLDBR_REG_UTRLDBR_MASK (0xFFFFFFFF) 360 361 /* 362 * UFSHCI 4.1, section 5.4.4, Offset 5Ch: UTRLCLR 363 * UTP Transfer Request List Clear Register 364 */ 365 #define UFSHCI_UTRLCLR_REG_UTRLCLR_SHIFT (0) 366 #define UFSHCI_UTRLCLR_REG_UTRLCLR_MASK (0xFFFFFFFF) 367 368 /* 369 * UFSHCI 4.1, section 5.4.5, Offset 60h: UTRLRSR 370 * UTP Transfer Request List Run Stop Register 371 */ 372 #define UFSHCI_UTRLRSR_REG_UTRLRSR_SHIFT (0) 373 #define UFSHCI_UTRLRSR_REG_UTRLRSR_MASK (0x1) 374 375 /* 376 * UFSHCI 4.1, section 5.4.6, Offset 64h: UTRLCNR 377 * UTP Transfer Request List Completion Notification Register 378 */ 379 #define UFSHCI_UTRLCNR_REG_UTRLCNR_SHIFT (0) 380 #define UFSHCI_UTRLCNR_REG_UTRLCNR_MASK (0xFFFFFFFF) 381 382 /* 383 * UFSHCI 4.1, section 5.5.1, Offset 70h: UTMRLBA 384 * UTP Task Management Request List Base Address 385 */ 386 #define UFSHCI_UTMRLBA_REG_UTMRLBA_SHIFT (0) 387 #define UFSHCI_UTMRLBA_REG_UTMRLBA_MASK (0xFFFFFFFF) 388 389 /* 390 * UFSHCI 4.1, section 5.5.2, Offset 74h: UTMRLBAU 391 * UTP Task Management Request List Base Address Upper 32-bits 392 */ 393 #define UFSHCI_UTMRLBAU_REG_UTMRLBAU_SHIFT (0) 394 #define UFSHCI_UTMRLBAU_REG_UTMRLBAU_MASK (0xFFFFFFFF) 395 396 /* 397 * UFSHCI 4.1, section 5.5.3, Offset 78h: UTMRLDBR 398 * UTP Task Management Request List Door Bell Register 399 */ 400 #define UFSHCI_UTMRLDBR_REG_UTMRLDBR_SHIFT (0) 401 #define UFSHCI_UTMRLDBR_REG_UTMRLDBR_MASK (0xFF) 402 403 /* 404 * UFSHCI 4.1, section 5.5.4, Offset 7Ch: UTMRLCLR 405 * UTP Task Management Request List CLear Register 406 */ 407 #define UFSHCI_UTMRLCLR_REG_UTMRLCLR_SHIFT (0) 408 #define UFSHCI_UTMRLCLR_REG_UTMRLCLR_MASK (0xFF) 409 410 /* 411 * UFSHCI 4.1, section 5.5.5, Offset 80h: UTMRLRSR 412 * UTP Task Management Request List Run Stop Register 413 */ 414 #define UFSHCI_UTMRLRSR_REG_UTMRLRSR_SHIFT (0) 415 #define UFSHCI_UTMRLRSR_REG_UTMRLRSR_MASK (0xFF) 416 417 /* 418 * UFSHCI 4.1, section 5.6.1 419 * Offset 90h: UICCMD – UIC Command 420 */ 421 #define UFSHCI_UICCMD_REG_CMDOP_SHIFT (0) 422 #define UFSHCI_UICCMD_REG_CMDOP_MASK (0xFF) 423 424 /* 425 * UFSHCI 4.1, section 5.6.2 426 * Offset 94h: UICCMDARG1 – UIC Command Argument 1 427 */ 428 #define UFSHCI_UICCMDARG1_REG_ARG1_SHIFT (0) 429 #define UFSHCI_UICCMDARG1_REG_ARG1_MASK (0xFFFFFFFF) 430 #define UFSHCI_UICCMDARG1_REG_GEN_SELECTOR_INDEX_SHIFT (0) 431 #define UFSHCI_UICCMDARG1_REG_GEN_SELECTOR_INDEX_MASK (0xFFFF) 432 #define UFSHCI_UICCMDARG1_REG_MIB_ATTR_SHIFT (16) 433 #define UFSHCI_UICCMDARG1_REG_MIB_ATTR_MASK (0xFFFF) 434 435 /* 436 * UFSHCI 4.1, section 5.6.3 437 * Offset 98h: UICCMDARG2 – UIC Command Argument 2 438 */ 439 #define UFSHCI_UICCMDARG2_REG_ARG2_SHIFT (0) 440 #define UFSHCI_UICCMDARG2_REG_ARG2_MASK (0xFFFFFFFF) 441 #define UFSHCI_UICCMDARG2_REG_ERROR_CODE_SHIFT (0) 442 #define UFSHCI_UICCMDARG2_REG_ERROR_CODE_MASK (0xFF) 443 #define UFSHCI_UICCMDARG2_REG_ATTR_SET_TYPE_SHIFT (16) 444 #define UFSHCI_UICCMDARG2_REG_ATTR_SET_TYPE_MASK (0xFF) 445 446 /* 447 * UFSHCI 4.1, section 5.6.4 448 * Offset 9Ch: UICCMDARG3 – UIC Command Argument 3 449 */ 450 #define UFSHCI_UICCMDARG3_REG_ARG3_SHIFT (0) 451 #define UFSHCI_UICCMDARG3_REG_ARG3_MASK (0xFFFFFFFF) 452 453 /* Helper macro to combine *_MASK and *_SHIFT defines */ 454 #define UFSHCIM(name) (name##_MASK << name##_SHIFT) 455 456 /* Helper macro to extract value from x */ 457 #define UFSHCIV(name, x) (((x) >> name##_SHIFT) & name##_MASK) 458 459 /* Helper macro to construct a field value */ 460 #define UFSHCIF(name, x) (((x)&name##_MASK) << name##_SHIFT) 461 462 #define UFSHCI_DUMP_REG(ctrlr, member) \ 463 do { \ 464 uint32_t _val = ufshci_mmio_read_4(ctrlr, member); \ 465 ufshci_printf(ctrlr, " %-15s (0x%03lx) : 0x%08x\n", #member, \ 466 ufshci_mmio_offsetof(member), _val); \ 467 } while (0) 468 469 #endif /* __UFSHCI_REG_H__ */ 470