1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2012 Semihalf. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_acpi.h" 30 #include "opt_platform.h" 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/bus.h> 39 40 #include <machine/bus.h> 41 #include <machine/machdep.h> 42 43 #include <dev/uart/uart.h> 44 #include <dev/uart/uart_cpu.h> 45 #ifdef FDT 46 #include <dev/uart/uart_cpu_fdt.h> 47 #include <dev/ofw/ofw_bus.h> 48 #endif 49 #include <dev/uart/uart_bus.h> 50 #include "uart_if.h" 51 52 #ifdef DEV_ACPI 53 #include <dev/uart/uart_cpu_acpi.h> 54 #include <contrib/dev/acpica/include/acpi.h> 55 #include <contrib/dev/acpica/include/accommon.h> 56 #include <contrib/dev/acpica/include/actables.h> 57 #endif 58 59 #include <sys/kdb.h> 60 61 #ifdef __aarch64__ 62 #define IS_FDT (arm64_bus_method == ARM64_BUS_FDT) 63 #elif defined(FDT) 64 #define IS_FDT 1 65 #else 66 #error Unsupported configuration 67 #endif 68 69 /* PL011 UART registers and masks*/ 70 #define UART_DR 0x00 /* Data register */ 71 #define DR_FE (1 << 8) /* Framing error */ 72 #define DR_PE (1 << 9) /* Parity error */ 73 #define DR_BE (1 << 10) /* Break error */ 74 #define DR_OE (1 << 11) /* Overrun error */ 75 76 #define UART_FR 0x06 /* Flag register */ 77 #define FR_RXFE (1 << 4) /* Receive FIFO/reg empty */ 78 #define FR_TXFF (1 << 5) /* Transmit FIFO/reg full */ 79 #define FR_RXFF (1 << 6) /* Receive FIFO/reg full */ 80 #define FR_TXFE (1 << 7) /* Transmit FIFO/reg empty */ 81 82 #define UART_IBRD 0x09 /* Integer baud rate register */ 83 #define IBRD_BDIVINT 0xffff /* Significant part of int. divisor value */ 84 85 #define UART_FBRD 0x0a /* Fractional baud rate register */ 86 #define FBRD_BDIVFRAC 0x3f /* Significant part of frac. divisor value */ 87 88 #define UART_LCR_H 0x0b /* Line control register */ 89 #define LCR_H_WLEN8 (0x3 << 5) 90 #define LCR_H_WLEN7 (0x2 << 5) 91 #define LCR_H_WLEN6 (0x1 << 5) 92 #define LCR_H_FEN (1 << 4) /* FIFO mode enable */ 93 #define LCR_H_STP2 (1 << 3) /* 2 stop frames at the end */ 94 #define LCR_H_EPS (1 << 2) /* Even parity select */ 95 #define LCR_H_PEN (1 << 1) /* Parity enable */ 96 97 #define UART_CR 0x0c /* Control register */ 98 #define CR_RXE (1 << 9) /* Receive enable */ 99 #define CR_TXE (1 << 8) /* Transmit enable */ 100 #define CR_UARTEN (1 << 0) /* UART enable */ 101 102 #define UART_IFLS 0x0d /* FIFO level select register */ 103 #define IFLS_RX_SHIFT 3 /* RX level in bits [5:3] */ 104 #define IFLS_TX_SHIFT 0 /* TX level in bits [2:0] */ 105 #define IFLS_MASK 0x07 /* RX/TX level is 3 bits */ 106 #define IFLS_LVL_1_8th 0 /* Interrupt at 1/8 full */ 107 #define IFLS_LVL_2_8th 1 /* Interrupt at 1/4 full */ 108 #define IFLS_LVL_4_8th 2 /* Interrupt at 1/2 full */ 109 #define IFLS_LVL_6_8th 3 /* Interrupt at 3/4 full */ 110 #define IFLS_LVL_7_8th 4 /* Interrupt at 7/8 full */ 111 112 #define UART_IMSC 0x0e /* Interrupt mask set/clear register */ 113 #define IMSC_MASK_ALL 0x7ff /* Mask all interrupts */ 114 115 #define UART_RIS 0x0f /* Raw interrupt status register */ 116 #define UART_RXREADY (1 << 4) /* RX buffer full */ 117 #define UART_TXEMPTY (1 << 5) /* TX buffer empty */ 118 #define RIS_RTIM (1 << 6) /* Receive timeout */ 119 #define RIS_FE (1 << 7) /* Framing error interrupt status */ 120 #define RIS_PE (1 << 8) /* Parity error interrupt status */ 121 #define RIS_BE (1 << 9) /* Break error interrupt status */ 122 #define RIS_OE (1 << 10) /* Overrun interrupt status */ 123 124 #define UART_MIS 0x10 /* Masked interrupt status register */ 125 #define UART_ICR 0x11 /* Interrupt clear register */ 126 127 #define UART_PIDREG_0 0x3f8 /* Peripheral ID register 0 */ 128 #define UART_PIDREG_1 0x3f9 /* Peripheral ID register 1 */ 129 #define UART_PIDREG_2 0x3fa /* Peripheral ID register 2 */ 130 #define UART_PIDREG_3 0x3fb /* Peripheral ID register 3 */ 131 132 /* 133 * The hardware FIFOs are 16 bytes each on rev 2 and earlier hardware, 32 bytes 134 * on rev 3 and later. We configure them to interrupt when 3/4 full/empty. For 135 * RX we set the size to the full hardware capacity so that the uart core 136 * allocates enough buffer space to hold a complete fifo full of incoming data. 137 * For TX, we need to limit the size to the capacity we know will be available 138 * when the interrupt occurs; uart_core will feed exactly that many bytes to 139 * uart_pl011_bus_transmit() which must consume them all. 140 */ 141 #define FIFO_RX_SIZE_R2 16 142 #define FIFO_TX_SIZE_R2 12 143 #define FIFO_RX_SIZE_R3 32 144 #define FIFO_TX_SIZE_R3 24 145 #define FIFO_IFLS_BITS ((IFLS_LVL_6_8th << IFLS_RX_SHIFT) | (IFLS_LVL_2_8th)) 146 147 /* 148 * FIXME: actual register size is SoC-dependent, we need to handle it 149 */ 150 #define __uart_getreg(bas, reg) \ 151 bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg)) 152 #define __uart_setreg(bas, reg, value) \ 153 bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value) 154 155 /* 156 * Low-level UART interface. 157 */ 158 static int uart_pl011_probe(struct uart_bas *bas); 159 static void uart_pl011_init(struct uart_bas *bas, int, int, int, int); 160 static void uart_pl011_term(struct uart_bas *bas); 161 static void uart_pl011_putc(struct uart_bas *bas, int); 162 static int uart_pl011_rxready(struct uart_bas *bas); 163 static int uart_pl011_getc(struct uart_bas *bas, struct mtx *); 164 165 static struct uart_ops uart_pl011_ops = { 166 .probe = uart_pl011_probe, 167 .init = uart_pl011_init, 168 .term = uart_pl011_term, 169 .putc = uart_pl011_putc, 170 .rxready = uart_pl011_rxready, 171 .getc = uart_pl011_getc, 172 }; 173 174 static int 175 uart_pl011_probe(struct uart_bas *bas) 176 { 177 178 return (0); 179 } 180 181 static void 182 uart_pl011_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 183 int parity) 184 { 185 uint32_t ctrl, line; 186 uint32_t baud; 187 188 /* 189 * Zero all settings to make sure 190 * UART is disabled and not configured 191 */ 192 ctrl = line = 0x0; 193 __uart_setreg(bas, UART_CR, ctrl); 194 195 /* As we know UART is disabled we may setup the line */ 196 switch (databits) { 197 case 7: 198 line |= LCR_H_WLEN7; 199 break; 200 case 6: 201 line |= LCR_H_WLEN6; 202 break; 203 case 8: 204 default: 205 line |= LCR_H_WLEN8; 206 break; 207 } 208 209 if (stopbits == 2) 210 line |= LCR_H_STP2; 211 else 212 line &= ~LCR_H_STP2; 213 214 if (parity) 215 line |= LCR_H_PEN; 216 else 217 line &= ~LCR_H_PEN; 218 line |= LCR_H_FEN; 219 220 /* Configure the rest */ 221 ctrl |= (CR_RXE | CR_TXE | CR_UARTEN); 222 223 if (bas->rclk != 0 && baudrate != 0) { 224 baud = bas->rclk * 4 / baudrate; 225 __uart_setreg(bas, UART_IBRD, ((uint32_t)(baud >> 6)) & IBRD_BDIVINT); 226 __uart_setreg(bas, UART_FBRD, (uint32_t)(baud & 0x3F) & FBRD_BDIVFRAC); 227 } 228 229 /* Add config. to line before reenabling UART */ 230 __uart_setreg(bas, UART_LCR_H, (__uart_getreg(bas, UART_LCR_H) & 231 ~0xff) | line); 232 233 /* Set rx and tx fifo levels. */ 234 __uart_setreg(bas, UART_IFLS, FIFO_IFLS_BITS); 235 236 __uart_setreg(bas, UART_CR, ctrl); 237 } 238 239 static void 240 uart_pl011_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 241 int parity) 242 { 243 /* Mask all interrupts */ 244 __uart_setreg(bas, UART_IMSC, __uart_getreg(bas, UART_IMSC) & 245 ~IMSC_MASK_ALL); 246 247 uart_pl011_param(bas, baudrate, databits, stopbits, parity); 248 } 249 250 static void 251 uart_pl011_term(struct uart_bas *bas) 252 { 253 } 254 255 static void 256 uart_pl011_putc(struct uart_bas *bas, int c) 257 { 258 259 /* Wait when TX FIFO full. Push character otherwise. */ 260 while (__uart_getreg(bas, UART_FR) & FR_TXFF) 261 ; 262 __uart_setreg(bas, UART_DR, c & 0xff); 263 } 264 265 static int 266 uart_pl011_rxready(struct uart_bas *bas) 267 { 268 269 return !(__uart_getreg(bas, UART_FR) & FR_RXFE); 270 } 271 272 static int 273 uart_pl011_getc(struct uart_bas *bas, struct mtx *hwmtx) 274 { 275 int c; 276 277 while (!uart_pl011_rxready(bas)) 278 ; 279 c = __uart_getreg(bas, UART_DR) & 0xff; 280 281 return (c); 282 } 283 284 /* 285 * High-level UART interface. 286 */ 287 struct uart_pl011_softc { 288 struct uart_softc base; 289 uint16_t imsc; /* Interrupt mask */ 290 }; 291 292 static int uart_pl011_bus_attach(struct uart_softc *); 293 static int uart_pl011_bus_detach(struct uart_softc *); 294 static int uart_pl011_bus_flush(struct uart_softc *, int); 295 static int uart_pl011_bus_getsig(struct uart_softc *); 296 static int uart_pl011_bus_ioctl(struct uart_softc *, int, intptr_t); 297 static int uart_pl011_bus_ipend(struct uart_softc *); 298 static int uart_pl011_bus_param(struct uart_softc *, int, int, int, int); 299 static int uart_pl011_bus_probe(struct uart_softc *); 300 static int uart_pl011_bus_receive(struct uart_softc *); 301 static int uart_pl011_bus_setsig(struct uart_softc *, int); 302 static int uart_pl011_bus_transmit(struct uart_softc *); 303 static void uart_pl011_bus_grab(struct uart_softc *); 304 static void uart_pl011_bus_ungrab(struct uart_softc *); 305 306 static kobj_method_t uart_pl011_methods[] = { 307 KOBJMETHOD(uart_attach, uart_pl011_bus_attach), 308 KOBJMETHOD(uart_detach, uart_pl011_bus_detach), 309 KOBJMETHOD(uart_flush, uart_pl011_bus_flush), 310 KOBJMETHOD(uart_getsig, uart_pl011_bus_getsig), 311 KOBJMETHOD(uart_ioctl, uart_pl011_bus_ioctl), 312 KOBJMETHOD(uart_ipend, uart_pl011_bus_ipend), 313 KOBJMETHOD(uart_param, uart_pl011_bus_param), 314 KOBJMETHOD(uart_probe, uart_pl011_bus_probe), 315 KOBJMETHOD(uart_receive, uart_pl011_bus_receive), 316 KOBJMETHOD(uart_setsig, uart_pl011_bus_setsig), 317 KOBJMETHOD(uart_transmit, uart_pl011_bus_transmit), 318 KOBJMETHOD(uart_grab, uart_pl011_bus_grab), 319 KOBJMETHOD(uart_ungrab, uart_pl011_bus_ungrab), 320 321 { 0, 0 } 322 }; 323 324 static struct uart_class uart_pl011_class = { 325 "uart_pl011", 326 uart_pl011_methods, 327 sizeof(struct uart_pl011_softc), 328 .uc_ops = &uart_pl011_ops, 329 .uc_range = 0x48, 330 .uc_rclk = 0, 331 .uc_rshift = 2 332 }; 333 334 335 #ifdef FDT 336 static struct ofw_compat_data fdt_compat_data[] = { 337 {"arm,pl011", (uintptr_t)&uart_pl011_class}, 338 {NULL, (uintptr_t)NULL}, 339 }; 340 UART_FDT_CLASS_AND_DEVICE(fdt_compat_data); 341 #endif 342 343 #ifdef DEV_ACPI 344 static struct acpi_uart_compat_data acpi_compat_data[] = { 345 {"ARMH0011", &uart_pl011_class, ACPI_DBG2_ARM_PL011, 2, 0, 0, 0, "uart plo11"}, 346 {"ARMH0011", &uart_pl011_class, ACPI_DBG2_ARM_SBSA_GENERIC, 2, 0, 0, 0, "uart plo11"}, 347 {NULL, NULL, 0, 0, 0, 0, 0, NULL}, 348 }; 349 UART_ACPI_CLASS_AND_DEVICE(acpi_compat_data); 350 #endif 351 352 static int 353 uart_pl011_bus_attach(struct uart_softc *sc) 354 { 355 struct uart_pl011_softc *psc; 356 struct uart_bas *bas; 357 358 psc = (struct uart_pl011_softc *)sc; 359 bas = &sc->sc_bas; 360 361 /* Enable interrupts */ 362 psc->imsc = (UART_RXREADY | RIS_RTIM | UART_TXEMPTY); 363 __uart_setreg(bas, UART_IMSC, psc->imsc); 364 365 /* Clear interrupts */ 366 __uart_setreg(bas, UART_ICR, IMSC_MASK_ALL); 367 368 return (0); 369 } 370 371 static int 372 uart_pl011_bus_detach(struct uart_softc *sc) 373 { 374 375 return (0); 376 } 377 378 static int 379 uart_pl011_bus_flush(struct uart_softc *sc, int what) 380 { 381 382 return (0); 383 } 384 385 static int 386 uart_pl011_bus_getsig(struct uart_softc *sc) 387 { 388 389 return (0); 390 } 391 392 static int 393 uart_pl011_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 394 { 395 int error; 396 397 error = 0; 398 uart_lock(sc->sc_hwmtx); 399 switch (request) { 400 case UART_IOCTL_BREAK: 401 break; 402 case UART_IOCTL_BAUD: 403 *(int*)data = 115200; 404 break; 405 default: 406 error = EINVAL; 407 break; 408 } 409 uart_unlock(sc->sc_hwmtx); 410 411 return (error); 412 } 413 414 static int 415 uart_pl011_bus_ipend(struct uart_softc *sc) 416 { 417 struct uart_pl011_softc *psc; 418 struct uart_bas *bas; 419 uint32_t ints; 420 int ipend; 421 422 psc = (struct uart_pl011_softc *)sc; 423 bas = &sc->sc_bas; 424 425 uart_lock(sc->sc_hwmtx); 426 ints = __uart_getreg(bas, UART_MIS); 427 ipend = 0; 428 429 if (ints & (UART_RXREADY | RIS_RTIM)) 430 ipend |= SER_INT_RXREADY; 431 if (ints & RIS_BE) 432 ipend |= SER_INT_BREAK; 433 if (ints & RIS_OE) 434 ipend |= SER_INT_OVERRUN; 435 if (ints & UART_TXEMPTY) { 436 if (sc->sc_txbusy) 437 ipend |= SER_INT_TXIDLE; 438 439 /* Disable TX interrupt */ 440 __uart_setreg(bas, UART_IMSC, psc->imsc & ~UART_TXEMPTY); 441 } 442 443 uart_unlock(sc->sc_hwmtx); 444 445 return (ipend); 446 } 447 448 static int 449 uart_pl011_bus_param(struct uart_softc *sc, int baudrate, int databits, 450 int stopbits, int parity) 451 { 452 453 uart_lock(sc->sc_hwmtx); 454 uart_pl011_param(&sc->sc_bas, baudrate, databits, stopbits, parity); 455 uart_unlock(sc->sc_hwmtx); 456 457 return (0); 458 } 459 460 #ifdef FDT 461 static int 462 uart_pl011_bus_hwrev_fdt(struct uart_softc *sc) 463 { 464 pcell_t node; 465 uint32_t periphid; 466 467 /* 468 * The FIFO sizes vary depending on hardware; rev 2 and below have 16 469 * byte FIFOs, rev 3 and up are 32 byte. The hardware rev is in the 470 * primecell periphid register, but we get a bit of drama, as always, 471 * with the bcm2835 (rpi), which claims to be rev 3, but has 16 byte 472 * FIFOs. We check for both the old freebsd-historic and the proper 473 * bindings-defined compatible strings for bcm2835, and also check the 474 * workaround the linux drivers use for rpi3, which is to override the 475 * primecell periphid register value with a property. 476 */ 477 if (ofw_bus_is_compatible(sc->sc_dev, "brcm,bcm2835-pl011") || 478 ofw_bus_is_compatible(sc->sc_dev, "broadcom,bcm2835-uart")) { 479 return (2); 480 } else { 481 node = ofw_bus_get_node(sc->sc_dev); 482 if (OF_getencprop(node, "arm,primecell-periphid", &periphid, 483 sizeof(periphid)) > 0) { 484 return ((periphid >> 20) & 0x0f); 485 } 486 } 487 488 return (-1); 489 } 490 #endif 491 492 static int 493 uart_pl011_bus_probe(struct uart_softc *sc) 494 { 495 int hwrev; 496 497 hwrev = -1; 498 #ifdef FDT 499 if (IS_FDT) 500 hwrev = uart_pl011_bus_hwrev_fdt(sc); 501 #endif 502 if (hwrev < 0) 503 hwrev = __uart_getreg(&sc->sc_bas, UART_PIDREG_2) >> 4; 504 505 if (hwrev <= 2) { 506 sc->sc_rxfifosz = FIFO_RX_SIZE_R2; 507 sc->sc_txfifosz = FIFO_TX_SIZE_R2; 508 } else { 509 sc->sc_rxfifosz = FIFO_RX_SIZE_R3; 510 sc->sc_txfifosz = FIFO_TX_SIZE_R3; 511 } 512 513 device_set_desc(sc->sc_dev, "PrimeCell UART (PL011)"); 514 515 return (0); 516 } 517 518 static int 519 uart_pl011_bus_receive(struct uart_softc *sc) 520 { 521 struct uart_bas *bas; 522 uint32_t ints, xc; 523 int rx; 524 525 bas = &sc->sc_bas; 526 uart_lock(sc->sc_hwmtx); 527 528 for (;;) { 529 ints = __uart_getreg(bas, UART_FR); 530 if (ints & FR_RXFE) 531 break; 532 if (uart_rx_full(sc)) { 533 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 534 break; 535 } 536 537 xc = __uart_getreg(bas, UART_DR); 538 rx = xc & 0xff; 539 540 if (xc & DR_FE) 541 rx |= UART_STAT_FRAMERR; 542 if (xc & DR_PE) 543 rx |= UART_STAT_PARERR; 544 545 uart_rx_put(sc, rx); 546 } 547 548 uart_unlock(sc->sc_hwmtx); 549 550 return (0); 551 } 552 553 static int 554 uart_pl011_bus_setsig(struct uart_softc *sc, int sig) 555 { 556 557 return (0); 558 } 559 560 static int 561 uart_pl011_bus_transmit(struct uart_softc *sc) 562 { 563 struct uart_pl011_softc *psc; 564 struct uart_bas *bas; 565 int i; 566 567 psc = (struct uart_pl011_softc *)sc; 568 bas = &sc->sc_bas; 569 uart_lock(sc->sc_hwmtx); 570 571 for (i = 0; i < sc->sc_txdatasz; i++) { 572 __uart_setreg(bas, UART_DR, sc->sc_txbuf[i]); 573 uart_barrier(bas); 574 } 575 576 /* Mark busy and enable TX interrupt */ 577 sc->sc_txbusy = 1; 578 __uart_setreg(bas, UART_IMSC, psc->imsc); 579 580 uart_unlock(sc->sc_hwmtx); 581 582 return (0); 583 } 584 585 static void 586 uart_pl011_bus_grab(struct uart_softc *sc) 587 { 588 struct uart_pl011_softc *psc; 589 struct uart_bas *bas; 590 591 psc = (struct uart_pl011_softc *)sc; 592 bas = &sc->sc_bas; 593 594 /* Disable interrupts on switch to polling */ 595 uart_lock(sc->sc_hwmtx); 596 __uart_setreg(bas, UART_IMSC, psc->imsc & ~IMSC_MASK_ALL); 597 uart_unlock(sc->sc_hwmtx); 598 } 599 600 static void 601 uart_pl011_bus_ungrab(struct uart_softc *sc) 602 { 603 struct uart_pl011_softc *psc; 604 struct uart_bas *bas; 605 606 psc = (struct uart_pl011_softc *)sc; 607 bas = &sc->sc_bas; 608 609 /* Switch to using interrupts while not grabbed */ 610 uart_lock(sc->sc_hwmtx); 611 __uart_setreg(bas, UART_IMSC, psc->imsc); 612 uart_unlock(sc->sc_hwmtx); 613 } 614