1 /*- 2 * Copyright (c) 2012 Semihalf. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include "opt_acpi.h" 28 #include "opt_platform.h" 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/bus.h> 37 #include <machine/bus.h> 38 39 #include <dev/uart/uart.h> 40 #include <dev/uart/uart_cpu.h> 41 #ifdef FDT 42 #include <dev/uart/uart_cpu_fdt.h> 43 #endif 44 #include <dev/uart/uart_bus.h> 45 #include "uart_if.h" 46 47 #ifdef DEV_ACPI 48 #include <dev/uart/uart_cpu_acpi.h> 49 #include <contrib/dev/acpica/include/acpi.h> 50 #include <contrib/dev/acpica/include/accommon.h> 51 #include <contrib/dev/acpica/include/actables.h> 52 #endif 53 54 #include <sys/kdb.h> 55 56 /* PL011 UART registers and masks*/ 57 #define UART_DR 0x00 /* Data register */ 58 #define DR_FE (1 << 8) /* Framing error */ 59 #define DR_PE (1 << 9) /* Parity error */ 60 #define DR_BE (1 << 10) /* Break error */ 61 #define DR_OE (1 << 11) /* Overrun error */ 62 63 #define UART_FR 0x06 /* Flag register */ 64 #define FR_RXFE (1 << 4) /* Receive FIFO/reg empty */ 65 #define FR_TXFF (1 << 5) /* Transmit FIFO/reg full */ 66 #define FR_RXFF (1 << 6) /* Receive FIFO/reg full */ 67 #define FR_TXFE (1 << 7) /* Transmit FIFO/reg empty */ 68 69 #define UART_IBRD 0x09 /* Integer baud rate register */ 70 #define IBRD_BDIVINT 0xffff /* Significant part of int. divisor value */ 71 72 #define UART_FBRD 0x0a /* Fractional baud rate register */ 73 #define FBRD_BDIVFRAC 0x3f /* Significant part of frac. divisor value */ 74 75 #define UART_LCR_H 0x0b /* Line control register */ 76 #define LCR_H_WLEN8 (0x3 << 5) 77 #define LCR_H_WLEN7 (0x2 << 5) 78 #define LCR_H_WLEN6 (0x1 << 5) 79 #define LCR_H_FEN (1 << 4) /* FIFO mode enable */ 80 #define LCR_H_STP2 (1 << 3) /* 2 stop frames at the end */ 81 #define LCR_H_EPS (1 << 2) /* Even parity select */ 82 #define LCR_H_PEN (1 << 1) /* Parity enable */ 83 84 #define UART_CR 0x0c /* Control register */ 85 #define CR_RXE (1 << 9) /* Receive enable */ 86 #define CR_TXE (1 << 8) /* Transmit enable */ 87 #define CR_UARTEN (1 << 0) /* UART enable */ 88 89 #define UART_IFLS 0x0d /* FIFO level select register */ 90 #define IFLS_RX_SHIFT 3 /* RX level in bits [5:3] */ 91 #define IFLS_TX_SHIFT 0 /* TX level in bits [2:0] */ 92 #define IFLS_MASK 0x07 /* RX/TX level is 3 bits */ 93 #define IFLS_LVL_1_8th 0 /* Interrupt at 1/8 full */ 94 #define IFLS_LVL_2_8th 1 /* Interrupt at 1/4 full */ 95 #define IFLS_LVL_4_8th 2 /* Interrupt at 1/2 full */ 96 #define IFLS_LVL_6_8th 3 /* Interrupt at 3/4 full */ 97 #define IFLS_LVL_7_8th 4 /* Interrupt at 7/8 full */ 98 99 #define UART_IMSC 0x0e /* Interrupt mask set/clear register */ 100 #define IMSC_MASK_ALL 0x7ff /* Mask all interrupts */ 101 102 #define UART_RIS 0x0f /* Raw interrupt status register */ 103 #define UART_RXREADY (1 << 4) /* RX buffer full */ 104 #define UART_TXEMPTY (1 << 5) /* TX buffer empty */ 105 #define RIS_RTIM (1 << 6) /* Receive timeout */ 106 #define RIS_FE (1 << 7) /* Framing error interrupt status */ 107 #define RIS_PE (1 << 8) /* Parity error interrupt status */ 108 #define RIS_BE (1 << 9) /* Break error interrupt status */ 109 #define RIS_OE (1 << 10) /* Overrun interrupt status */ 110 111 #define UART_MIS 0x10 /* Masked interrupt status register */ 112 #define UART_ICR 0x11 /* Interrupt clear register */ 113 114 #define UART_PIDREG_0 0x3f8 /* Peripheral ID register 0 */ 115 #define UART_PIDREG_1 0x3f9 /* Peripheral ID register 1 */ 116 #define UART_PIDREG_2 0x3fa /* Peripheral ID register 2 */ 117 #define UART_PIDREG_3 0x3fb /* Peripheral ID register 3 */ 118 119 /* 120 * The hardware FIFOs are 16 bytes each on rev 2 and earlier hardware, 32 bytes 121 * on rev 3 and later. We configure them to interrupt when 3/4 full/empty. For 122 * RX we set the size to the full hardware capacity so that the uart core 123 * allocates enough buffer space to hold a complete fifo full of incoming data. 124 * For TX, we need to limit the size to the capacity we know will be available 125 * when the interrupt occurs; uart_core will feed exactly that many bytes to 126 * uart_pl011_bus_transmit() which must consume them all. 127 */ 128 #define FIFO_RX_SIZE_R2 16 129 #define FIFO_TX_SIZE_R2 12 130 #define FIFO_RX_SIZE_R3 32 131 #define FIFO_TX_SIZE_R3 24 132 #define FIFO_IFLS_BITS ((IFLS_LVL_6_8th << IFLS_RX_SHIFT) | (IFLS_LVL_2_8th)) 133 134 /* 135 * FIXME: actual register size is SoC-dependent, we need to handle it 136 */ 137 #define __uart_getreg(bas, reg) \ 138 bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg)) 139 #define __uart_setreg(bas, reg, value) \ 140 bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value) 141 142 /* 143 * Low-level UART interface. 144 */ 145 static int uart_pl011_probe(struct uart_bas *bas); 146 static void uart_pl011_init(struct uart_bas *bas, int, int, int, int); 147 static void uart_pl011_term(struct uart_bas *bas); 148 static void uart_pl011_putc(struct uart_bas *bas, int); 149 static int uart_pl011_rxready(struct uart_bas *bas); 150 static int uart_pl011_getc(struct uart_bas *bas, struct mtx *); 151 152 static struct uart_ops uart_pl011_ops = { 153 .probe = uart_pl011_probe, 154 .init = uart_pl011_init, 155 .term = uart_pl011_term, 156 .putc = uart_pl011_putc, 157 .rxready = uart_pl011_rxready, 158 .getc = uart_pl011_getc, 159 }; 160 161 static int 162 uart_pl011_probe(struct uart_bas *bas) 163 { 164 165 return (0); 166 } 167 168 static void 169 uart_pl011_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 170 int parity) 171 { 172 uint32_t ctrl, line; 173 uint32_t baud; 174 175 /* 176 * Zero all settings to make sure 177 * UART is disabled and not configured 178 */ 179 ctrl = line = 0x0; 180 __uart_setreg(bas, UART_CR, ctrl); 181 182 /* As we know UART is disabled we may setup the line */ 183 switch (databits) { 184 case 7: 185 line |= LCR_H_WLEN7; 186 break; 187 case 6: 188 line |= LCR_H_WLEN6; 189 break; 190 case 8: 191 default: 192 line |= LCR_H_WLEN8; 193 break; 194 } 195 196 if (stopbits == 2) 197 line |= LCR_H_STP2; 198 else 199 line &= ~LCR_H_STP2; 200 201 if (parity) 202 line |= LCR_H_PEN; 203 else 204 line &= ~LCR_H_PEN; 205 line |= LCR_H_FEN; 206 207 /* Configure the rest */ 208 ctrl |= (CR_RXE | CR_TXE | CR_UARTEN); 209 210 if (bas->rclk != 0 && baudrate != 0) { 211 baud = bas->rclk * 4 / baudrate; 212 __uart_setreg(bas, UART_IBRD, ((uint32_t)(baud >> 6)) & IBRD_BDIVINT); 213 __uart_setreg(bas, UART_FBRD, (uint32_t)(baud & 0x3F) & FBRD_BDIVFRAC); 214 } 215 216 /* Add config. to line before reenabling UART */ 217 __uart_setreg(bas, UART_LCR_H, (__uart_getreg(bas, UART_LCR_H) & 218 ~0xff) | line); 219 220 /* Set rx and tx fifo levels. */ 221 __uart_setreg(bas, UART_IFLS, FIFO_IFLS_BITS); 222 223 __uart_setreg(bas, UART_CR, ctrl); 224 } 225 226 static void 227 uart_pl011_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 228 int parity) 229 { 230 /* Mask all interrupts */ 231 __uart_setreg(bas, UART_IMSC, __uart_getreg(bas, UART_IMSC) & 232 ~IMSC_MASK_ALL); 233 234 uart_pl011_param(bas, baudrate, databits, stopbits, parity); 235 } 236 237 static void 238 uart_pl011_term(struct uart_bas *bas) 239 { 240 } 241 242 static void 243 uart_pl011_putc(struct uart_bas *bas, int c) 244 { 245 246 /* Wait when TX FIFO full. Push character otherwise. */ 247 while (__uart_getreg(bas, UART_FR) & FR_TXFF) 248 ; 249 __uart_setreg(bas, UART_DR, c & 0xff); 250 } 251 252 static int 253 uart_pl011_rxready(struct uart_bas *bas) 254 { 255 256 return !(__uart_getreg(bas, UART_FR) & FR_RXFE); 257 } 258 259 static int 260 uart_pl011_getc(struct uart_bas *bas, struct mtx *hwmtx) 261 { 262 int c; 263 264 while (!uart_pl011_rxready(bas)) 265 ; 266 c = __uart_getreg(bas, UART_DR) & 0xff; 267 268 return (c); 269 } 270 271 /* 272 * High-level UART interface. 273 */ 274 struct uart_pl011_softc { 275 struct uart_softc base; 276 uint16_t imsc; /* Interrupt mask */ 277 }; 278 279 static int uart_pl011_bus_attach(struct uart_softc *); 280 static int uart_pl011_bus_detach(struct uart_softc *); 281 static int uart_pl011_bus_flush(struct uart_softc *, int); 282 static int uart_pl011_bus_getsig(struct uart_softc *); 283 static int uart_pl011_bus_ioctl(struct uart_softc *, int, intptr_t); 284 static int uart_pl011_bus_ipend(struct uart_softc *); 285 static int uart_pl011_bus_param(struct uart_softc *, int, int, int, int); 286 static int uart_pl011_bus_probe(struct uart_softc *); 287 static int uart_pl011_bus_receive(struct uart_softc *); 288 static int uart_pl011_bus_setsig(struct uart_softc *, int); 289 static int uart_pl011_bus_transmit(struct uart_softc *); 290 static void uart_pl011_bus_grab(struct uart_softc *); 291 static void uart_pl011_bus_ungrab(struct uart_softc *); 292 293 static kobj_method_t uart_pl011_methods[] = { 294 KOBJMETHOD(uart_attach, uart_pl011_bus_attach), 295 KOBJMETHOD(uart_detach, uart_pl011_bus_detach), 296 KOBJMETHOD(uart_flush, uart_pl011_bus_flush), 297 KOBJMETHOD(uart_getsig, uart_pl011_bus_getsig), 298 KOBJMETHOD(uart_ioctl, uart_pl011_bus_ioctl), 299 KOBJMETHOD(uart_ipend, uart_pl011_bus_ipend), 300 KOBJMETHOD(uart_param, uart_pl011_bus_param), 301 KOBJMETHOD(uart_probe, uart_pl011_bus_probe), 302 KOBJMETHOD(uart_receive, uart_pl011_bus_receive), 303 KOBJMETHOD(uart_setsig, uart_pl011_bus_setsig), 304 KOBJMETHOD(uart_transmit, uart_pl011_bus_transmit), 305 KOBJMETHOD(uart_grab, uart_pl011_bus_grab), 306 KOBJMETHOD(uart_ungrab, uart_pl011_bus_ungrab), 307 308 { 0, 0 } 309 }; 310 311 static struct uart_class uart_pl011_class = { 312 "uart_pl011", 313 uart_pl011_methods, 314 sizeof(struct uart_pl011_softc), 315 .uc_ops = &uart_pl011_ops, 316 .uc_range = 0x48, 317 .uc_rclk = 0, 318 .uc_rshift = 2 319 }; 320 321 322 #ifdef FDT 323 static struct ofw_compat_data compat_data[] = { 324 {"arm,pl011", (uintptr_t)&uart_pl011_class}, 325 {NULL, (uintptr_t)NULL}, 326 }; 327 UART_FDT_CLASS_AND_DEVICE(compat_data); 328 #endif 329 330 #ifdef DEV_ACPI 331 static struct acpi_uart_compat_data acpi_compat_data[] = { 332 {"ARMH0011", &uart_pl011_class, ACPI_DBG2_ARM_PL011}, 333 {NULL, NULL, 0}, 334 }; 335 UART_ACPI_CLASS_AND_DEVICE(acpi_compat_data); 336 #endif 337 338 static int 339 uart_pl011_bus_attach(struct uart_softc *sc) 340 { 341 struct uart_pl011_softc *psc; 342 struct uart_bas *bas; 343 344 psc = (struct uart_pl011_softc *)sc; 345 bas = &sc->sc_bas; 346 347 /* Enable interrupts */ 348 psc->imsc = (UART_RXREADY | RIS_RTIM | UART_TXEMPTY); 349 __uart_setreg(bas, UART_IMSC, psc->imsc); 350 351 /* Clear interrupts */ 352 __uart_setreg(bas, UART_ICR, IMSC_MASK_ALL); 353 354 return (0); 355 } 356 357 static int 358 uart_pl011_bus_detach(struct uart_softc *sc) 359 { 360 361 return (0); 362 } 363 364 static int 365 uart_pl011_bus_flush(struct uart_softc *sc, int what) 366 { 367 368 return (0); 369 } 370 371 static int 372 uart_pl011_bus_getsig(struct uart_softc *sc) 373 { 374 375 return (0); 376 } 377 378 static int 379 uart_pl011_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 380 { 381 struct uart_bas *bas; 382 int error; 383 384 bas = &sc->sc_bas; 385 error = 0; 386 uart_lock(sc->sc_hwmtx); 387 switch (request) { 388 case UART_IOCTL_BREAK: 389 break; 390 case UART_IOCTL_BAUD: 391 *(int*)data = 115200; 392 break; 393 default: 394 error = EINVAL; 395 break; 396 } 397 uart_unlock(sc->sc_hwmtx); 398 399 return (error); 400 } 401 402 static int 403 uart_pl011_bus_ipend(struct uart_softc *sc) 404 { 405 struct uart_pl011_softc *psc; 406 struct uart_bas *bas; 407 uint32_t ints; 408 int ipend; 409 410 psc = (struct uart_pl011_softc *)sc; 411 bas = &sc->sc_bas; 412 413 uart_lock(sc->sc_hwmtx); 414 ints = __uart_getreg(bas, UART_MIS); 415 ipend = 0; 416 417 if (ints & (UART_RXREADY | RIS_RTIM)) 418 ipend |= SER_INT_RXREADY; 419 if (ints & RIS_BE) 420 ipend |= SER_INT_BREAK; 421 if (ints & RIS_OE) 422 ipend |= SER_INT_OVERRUN; 423 if (ints & UART_TXEMPTY) { 424 if (sc->sc_txbusy) 425 ipend |= SER_INT_TXIDLE; 426 427 /* Disable TX interrupt */ 428 __uart_setreg(bas, UART_IMSC, psc->imsc & ~UART_TXEMPTY); 429 } 430 431 uart_unlock(sc->sc_hwmtx); 432 433 return (ipend); 434 } 435 436 static int 437 uart_pl011_bus_param(struct uart_softc *sc, int baudrate, int databits, 438 int stopbits, int parity) 439 { 440 441 uart_lock(sc->sc_hwmtx); 442 uart_pl011_param(&sc->sc_bas, baudrate, databits, stopbits, parity); 443 uart_unlock(sc->sc_hwmtx); 444 445 return (0); 446 } 447 448 static int 449 uart_pl011_bus_probe(struct uart_softc *sc) 450 { 451 uint8_t hwrev; 452 bool is_bcm2835; 453 454 device_set_desc(sc->sc_dev, "PrimeCell UART (PL011)"); 455 456 /* 457 * The FIFO sizes vary depending on hardware; rev 2 and below have 16 458 * byte FIFOs, rev 3 and up are 32 byte. We get a bit of drama, as 459 * always, with the bcm2835 (rpi), which claims to be rev 3, but has 16 460 * byte FIFOs. We check for both the old freebsd-historic and the 461 * proper bindings-defined compatible strings for bcm2835. 462 */ 463 #ifdef FDT 464 is_bcm2835 = ofw_bus_is_compatible(sc->sc_dev, "brcm,bcm2835-pl011") || 465 ofw_bus_is_compatible(sc->sc_dev, "broadcom,bcm2835-uart"); 466 #else 467 is_bcm2835 = false; 468 #endif 469 hwrev = __uart_getreg(&sc->sc_bas, UART_PIDREG_2) >> 4; 470 if (hwrev <= 2 || is_bcm2835) { 471 sc->sc_rxfifosz = FIFO_RX_SIZE_R2; 472 sc->sc_txfifosz = FIFO_TX_SIZE_R2; 473 } else { 474 sc->sc_rxfifosz = FIFO_RX_SIZE_R3; 475 sc->sc_txfifosz = FIFO_TX_SIZE_R3; 476 } 477 478 return (0); 479 } 480 481 static int 482 uart_pl011_bus_receive(struct uart_softc *sc) 483 { 484 struct uart_bas *bas; 485 uint32_t ints, xc; 486 int rx; 487 488 bas = &sc->sc_bas; 489 uart_lock(sc->sc_hwmtx); 490 491 for (;;) { 492 ints = __uart_getreg(bas, UART_FR); 493 if (ints & FR_RXFE) 494 break; 495 if (uart_rx_full(sc)) { 496 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 497 break; 498 } 499 500 xc = __uart_getreg(bas, UART_DR); 501 rx = xc & 0xff; 502 503 if (xc & DR_FE) 504 rx |= UART_STAT_FRAMERR; 505 if (xc & DR_PE) 506 rx |= UART_STAT_PARERR; 507 508 uart_rx_put(sc, rx); 509 } 510 511 uart_unlock(sc->sc_hwmtx); 512 513 return (0); 514 } 515 516 static int 517 uart_pl011_bus_setsig(struct uart_softc *sc, int sig) 518 { 519 520 return (0); 521 } 522 523 static int 524 uart_pl011_bus_transmit(struct uart_softc *sc) 525 { 526 struct uart_pl011_softc *psc; 527 struct uart_bas *bas; 528 int i; 529 530 psc = (struct uart_pl011_softc *)sc; 531 bas = &sc->sc_bas; 532 uart_lock(sc->sc_hwmtx); 533 534 for (i = 0; i < sc->sc_txdatasz; i++) { 535 __uart_setreg(bas, UART_DR, sc->sc_txbuf[i]); 536 uart_barrier(bas); 537 } 538 539 /* Mark busy and enable TX interrupt */ 540 sc->sc_txbusy = 1; 541 __uart_setreg(bas, UART_IMSC, psc->imsc); 542 543 uart_unlock(sc->sc_hwmtx); 544 545 return (0); 546 } 547 548 static void 549 uart_pl011_bus_grab(struct uart_softc *sc) 550 { 551 struct uart_pl011_softc *psc; 552 struct uart_bas *bas; 553 554 psc = (struct uart_pl011_softc *)sc; 555 bas = &sc->sc_bas; 556 557 /* Disable interrupts on switch to polling */ 558 uart_lock(sc->sc_hwmtx); 559 __uart_setreg(bas, UART_IMSC, psc->imsc & ~IMSC_MASK_ALL); 560 uart_unlock(sc->sc_hwmtx); 561 } 562 563 static void 564 uart_pl011_bus_ungrab(struct uart_softc *sc) 565 { 566 struct uart_pl011_softc *psc; 567 struct uart_bas *bas; 568 569 psc = (struct uart_pl011_softc *)sc; 570 bas = &sc->sc_bas; 571 572 /* Switch to using interrupts while not grabbed */ 573 uart_lock(sc->sc_hwmtx); 574 __uart_setreg(bas, UART_IMSC, psc->imsc); 575 uart_unlock(sc->sc_hwmtx); 576 } 577