1 /*- 2 * Copyright (c) 2012 Semihalf. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/bus.h> 34 #include <machine/bus.h> 35 36 #include <dev/uart/uart.h> 37 #include <dev/uart/uart_cpu.h> 38 #include <dev/uart/uart_cpu_fdt.h> 39 #include <dev/uart/uart_bus.h> 40 #include "uart_if.h" 41 42 #include <sys/kdb.h> 43 44 /* PL011 UART registers and masks*/ 45 #define UART_DR 0x00 /* Data register */ 46 #define DR_FE (1 << 8) /* Framing error */ 47 #define DR_PE (1 << 9) /* Parity error */ 48 #define DR_BE (1 << 10) /* Break error */ 49 #define DR_OE (1 << 11) /* Overrun error */ 50 51 #define UART_FR 0x06 /* Flag register */ 52 #define FR_TXFF (1 << 5) /* Transmit FIFO/reg full */ 53 #define FR_RXFF (1 << 6) /* Receive FIFO/reg full */ 54 #define FR_TXFE (1 << 7) /* Transmit FIFO/reg empty */ 55 56 #define UART_IBRD 0x09 /* Integer baud rate register */ 57 #define IBRD_BDIVINT 0xffff /* Significant part of int. divisor value */ 58 59 #define UART_FBRD 0x0a /* Fractional baud rate register */ 60 #define FBRD_BDIVFRAC 0x3f /* Significant part of frac. divisor value */ 61 62 #define UART_LCR_H 0x0b /* Line control register */ 63 #define LCR_H_WLEN8 (0x3 << 5) 64 #define LCR_H_WLEN7 (0x2 << 5) 65 #define LCR_H_WLEN6 (0x1 << 5) 66 #define LCR_H_FEN (1 << 4) /* FIFO mode enable */ 67 #define LCR_H_STP2 (1 << 3) /* 2 stop frames at the end */ 68 #define LCR_H_EPS (1 << 2) /* Even parity select */ 69 #define LCR_H_PEN (1 << 1) /* Parity enable */ 70 71 #define UART_CR 0x0c /* Control register */ 72 #define CR_RXE (1 << 9) /* Receive enable */ 73 #define CR_TXE (1 << 8) /* Transmit enable */ 74 #define CR_UARTEN (1 << 0) /* UART enable */ 75 76 #define UART_IMSC 0x0e /* Interrupt mask set/clear register */ 77 #define IMSC_MASK_ALL 0x7ff /* Mask all interrupts */ 78 79 #define UART_RIS 0x0f /* Raw interrupt status register */ 80 #define UART_RXREADY (1 << 4) /* RX buffer full */ 81 #define UART_TXEMPTY (1 << 5) /* TX buffer empty */ 82 #define RIS_RTIM (1 << 6) /* Receive timeout */ 83 #define RIS_FE (1 << 7) /* Framing error interrupt status */ 84 #define RIS_PE (1 << 8) /* Parity error interrupt status */ 85 #define RIS_BE (1 << 9) /* Break error interrupt status */ 86 #define RIS_OE (1 << 10) /* Overrun interrupt status */ 87 88 #define UART_MIS 0x10 /* Masked interrupt status register */ 89 #define UART_ICR 0x11 /* Interrupt clear register */ 90 91 /* 92 * FIXME: actual register size is SoC-dependent, we need to handle it 93 */ 94 #define __uart_getreg(bas, reg) \ 95 bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg)) 96 #define __uart_setreg(bas, reg, value) \ 97 bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value) 98 99 /* 100 * Low-level UART interface. 101 */ 102 static int uart_pl011_probe(struct uart_bas *bas); 103 static void uart_pl011_init(struct uart_bas *bas, int, int, int, int); 104 static void uart_pl011_term(struct uart_bas *bas); 105 static void uart_pl011_putc(struct uart_bas *bas, int); 106 static int uart_pl011_rxready(struct uart_bas *bas); 107 static int uart_pl011_getc(struct uart_bas *bas, struct mtx *); 108 109 static struct uart_ops uart_pl011_ops = { 110 .probe = uart_pl011_probe, 111 .init = uart_pl011_init, 112 .term = uart_pl011_term, 113 .putc = uart_pl011_putc, 114 .rxready = uart_pl011_rxready, 115 .getc = uart_pl011_getc, 116 }; 117 118 static int 119 uart_pl011_probe(struct uart_bas *bas) 120 { 121 122 return (0); 123 } 124 125 static void 126 uart_pl011_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 127 int parity) 128 { 129 uint32_t ctrl, line; 130 uint32_t baud; 131 132 /* 133 * Zero all settings to make sure 134 * UART is disabled and not configured 135 */ 136 ctrl = line = 0x0; 137 __uart_setreg(bas, UART_CR, ctrl); 138 139 /* As we know UART is disabled we may setup the line */ 140 switch (databits) { 141 case 7: 142 line |= LCR_H_WLEN7; 143 break; 144 case 6: 145 line |= LCR_H_WLEN6; 146 break; 147 case 8: 148 default: 149 line |= LCR_H_WLEN8; 150 break; 151 } 152 153 if (stopbits == 2) 154 line |= LCR_H_STP2; 155 else 156 line &= ~LCR_H_STP2; 157 158 if (parity) 159 line |= LCR_H_PEN; 160 else 161 line &= ~LCR_H_PEN; 162 163 /* Configure the rest */ 164 line &= ~LCR_H_FEN; 165 ctrl |= (CR_RXE | CR_TXE | CR_UARTEN); 166 167 if (bas->rclk != 0 && baudrate != 0) { 168 baud = bas->rclk * 4 / baudrate; 169 __uart_setreg(bas, UART_IBRD, ((uint32_t)(baud >> 6)) & IBRD_BDIVINT); 170 __uart_setreg(bas, UART_FBRD, (uint32_t)(baud & 0x3F) & FBRD_BDIVFRAC); 171 } 172 173 /* Add config. to line before reenabling UART */ 174 __uart_setreg(bas, UART_LCR_H, (__uart_getreg(bas, UART_LCR_H) & 175 ~0xff) | line); 176 177 __uart_setreg(bas, UART_CR, ctrl); 178 } 179 180 static void 181 uart_pl011_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 182 int parity) 183 { 184 /* Mask all interrupts */ 185 __uart_setreg(bas, UART_IMSC, __uart_getreg(bas, UART_IMSC) & 186 ~IMSC_MASK_ALL); 187 188 uart_pl011_param(bas, baudrate, databits, stopbits, parity); 189 } 190 191 static void 192 uart_pl011_term(struct uart_bas *bas) 193 { 194 } 195 196 static void 197 uart_pl011_putc(struct uart_bas *bas, int c) 198 { 199 200 /* Wait when TX FIFO full. Push character otherwise. */ 201 while (__uart_getreg(bas, UART_FR) & FR_TXFF) 202 ; 203 __uart_setreg(bas, UART_DR, c & 0xff); 204 } 205 206 static int 207 uart_pl011_rxready(struct uart_bas *bas) 208 { 209 210 return (__uart_getreg(bas, UART_FR) & FR_RXFF); 211 } 212 213 static int 214 uart_pl011_getc(struct uart_bas *bas, struct mtx *hwmtx) 215 { 216 int c; 217 218 while (!uart_pl011_rxready(bas)) 219 ; 220 c = __uart_getreg(bas, UART_DR) & 0xff; 221 222 return (c); 223 } 224 225 /* 226 * High-level UART interface. 227 */ 228 struct uart_pl011_softc { 229 struct uart_softc base; 230 uint8_t fcr; 231 uint8_t ier; 232 uint8_t mcr; 233 234 uint8_t ier_mask; 235 uint8_t ier_rxbits; 236 }; 237 238 static int uart_pl011_bus_attach(struct uart_softc *); 239 static int uart_pl011_bus_detach(struct uart_softc *); 240 static int uart_pl011_bus_flush(struct uart_softc *, int); 241 static int uart_pl011_bus_getsig(struct uart_softc *); 242 static int uart_pl011_bus_ioctl(struct uart_softc *, int, intptr_t); 243 static int uart_pl011_bus_ipend(struct uart_softc *); 244 static int uart_pl011_bus_param(struct uart_softc *, int, int, int, int); 245 static int uart_pl011_bus_probe(struct uart_softc *); 246 static int uart_pl011_bus_receive(struct uart_softc *); 247 static int uart_pl011_bus_setsig(struct uart_softc *, int); 248 static int uart_pl011_bus_transmit(struct uart_softc *); 249 static void uart_pl011_bus_grab(struct uart_softc *); 250 static void uart_pl011_bus_ungrab(struct uart_softc *); 251 252 static kobj_method_t uart_pl011_methods[] = { 253 KOBJMETHOD(uart_attach, uart_pl011_bus_attach), 254 KOBJMETHOD(uart_detach, uart_pl011_bus_detach), 255 KOBJMETHOD(uart_flush, uart_pl011_bus_flush), 256 KOBJMETHOD(uart_getsig, uart_pl011_bus_getsig), 257 KOBJMETHOD(uart_ioctl, uart_pl011_bus_ioctl), 258 KOBJMETHOD(uart_ipend, uart_pl011_bus_ipend), 259 KOBJMETHOD(uart_param, uart_pl011_bus_param), 260 KOBJMETHOD(uart_probe, uart_pl011_bus_probe), 261 KOBJMETHOD(uart_receive, uart_pl011_bus_receive), 262 KOBJMETHOD(uart_setsig, uart_pl011_bus_setsig), 263 KOBJMETHOD(uart_transmit, uart_pl011_bus_transmit), 264 KOBJMETHOD(uart_grab, uart_pl011_bus_grab), 265 KOBJMETHOD(uart_ungrab, uart_pl011_bus_ungrab), 266 267 { 0, 0 } 268 }; 269 270 static struct uart_class uart_pl011_class = { 271 "uart_pl011", 272 uart_pl011_methods, 273 sizeof(struct uart_pl011_softc), 274 .uc_ops = &uart_pl011_ops, 275 .uc_range = 0x48, 276 .uc_rclk = 0, 277 .uc_rshift = 2 278 }; 279 280 static struct ofw_compat_data compat_data[] = { 281 {"arm,pl011", (uintptr_t)&uart_pl011_class}, 282 {NULL, (uintptr_t)NULL}, 283 }; 284 UART_FDT_CLASS_AND_DEVICE(compat_data); 285 286 static int 287 uart_pl011_bus_attach(struct uart_softc *sc) 288 { 289 struct uart_bas *bas; 290 int reg; 291 292 bas = &sc->sc_bas; 293 294 /* Enable interrupts */ 295 reg = (UART_RXREADY | RIS_RTIM | UART_TXEMPTY); 296 __uart_setreg(bas, UART_IMSC, reg); 297 298 /* Clear interrupts */ 299 __uart_setreg(bas, UART_ICR, IMSC_MASK_ALL); 300 301 return (0); 302 } 303 304 static int 305 uart_pl011_bus_detach(struct uart_softc *sc) 306 { 307 308 return (0); 309 } 310 311 static int 312 uart_pl011_bus_flush(struct uart_softc *sc, int what) 313 { 314 315 return (0); 316 } 317 318 static int 319 uart_pl011_bus_getsig(struct uart_softc *sc) 320 { 321 322 return (0); 323 } 324 325 static int 326 uart_pl011_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 327 { 328 struct uart_bas *bas; 329 int error; 330 331 bas = &sc->sc_bas; 332 error = 0; 333 uart_lock(sc->sc_hwmtx); 334 switch (request) { 335 case UART_IOCTL_BREAK: 336 break; 337 case UART_IOCTL_BAUD: 338 *(int*)data = 115200; 339 break; 340 default: 341 error = EINVAL; 342 break; 343 } 344 uart_unlock(sc->sc_hwmtx); 345 346 return (error); 347 } 348 349 static int 350 uart_pl011_bus_ipend(struct uart_softc *sc) 351 { 352 struct uart_bas *bas; 353 uint32_t ints; 354 int ipend; 355 int reg; 356 357 bas = &sc->sc_bas; 358 uart_lock(sc->sc_hwmtx); 359 ints = __uart_getreg(bas, UART_MIS); 360 ipend = 0; 361 362 if (ints & (UART_RXREADY | RIS_RTIM)) 363 ipend |= SER_INT_RXREADY; 364 if (ints & RIS_BE) 365 ipend |= SER_INT_BREAK; 366 if (ints & RIS_OE) 367 ipend |= SER_INT_OVERRUN; 368 if (ints & UART_TXEMPTY) { 369 if (sc->sc_txbusy) 370 ipend |= SER_INT_TXIDLE; 371 372 /* Disable TX interrupt */ 373 reg = __uart_getreg(bas, UART_IMSC); 374 reg &= ~(UART_TXEMPTY); 375 __uart_setreg(bas, UART_IMSC, reg); 376 } 377 378 uart_unlock(sc->sc_hwmtx); 379 380 return (ipend); 381 } 382 383 static int 384 uart_pl011_bus_param(struct uart_softc *sc, int baudrate, int databits, 385 int stopbits, int parity) 386 { 387 388 uart_lock(sc->sc_hwmtx); 389 uart_pl011_param(&sc->sc_bas, baudrate, databits, stopbits, parity); 390 uart_unlock(sc->sc_hwmtx); 391 392 return (0); 393 } 394 395 static int 396 uart_pl011_bus_probe(struct uart_softc *sc) 397 { 398 399 device_set_desc(sc->sc_dev, "PrimeCell UART (PL011)"); 400 401 sc->sc_rxfifosz = 1; 402 sc->sc_txfifosz = 1; 403 404 return (0); 405 } 406 407 static int 408 uart_pl011_bus_receive(struct uart_softc *sc) 409 { 410 struct uart_bas *bas; 411 uint32_t ints, xc; 412 int rx; 413 414 bas = &sc->sc_bas; 415 uart_lock(sc->sc_hwmtx); 416 417 ints = __uart_getreg(bas, UART_MIS); 418 while (ints & (UART_RXREADY | RIS_RTIM)) { 419 if (uart_rx_full(sc)) { 420 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 421 break; 422 } 423 xc = __uart_getreg(bas, UART_DR); 424 rx = xc & 0xff; 425 426 if (xc & DR_FE) 427 rx |= UART_STAT_FRAMERR; 428 if (xc & DR_PE) 429 rx |= UART_STAT_PARERR; 430 431 __uart_setreg(bas, UART_ICR, (UART_RXREADY | RIS_RTIM)); 432 433 uart_rx_put(sc, rx); 434 ints = __uart_getreg(bas, UART_MIS); 435 } 436 437 uart_unlock(sc->sc_hwmtx); 438 439 return (0); 440 } 441 442 static int 443 uart_pl011_bus_setsig(struct uart_softc *sc, int sig) 444 { 445 446 return (0); 447 } 448 449 static int 450 uart_pl011_bus_transmit(struct uart_softc *sc) 451 { 452 struct uart_bas *bas; 453 int reg; 454 int i; 455 456 bas = &sc->sc_bas; 457 uart_lock(sc->sc_hwmtx); 458 459 for (i = 0; i < sc->sc_txdatasz; i++) { 460 __uart_setreg(bas, UART_DR, sc->sc_txbuf[i]); 461 uart_barrier(bas); 462 } 463 464 /* If not empty wait until it is */ 465 if ((__uart_getreg(bas, UART_FR) & FR_TXFE) != FR_TXFE) { 466 sc->sc_txbusy = 1; 467 468 /* Enable TX interrupt */ 469 reg = __uart_getreg(bas, UART_IMSC); 470 reg |= (UART_TXEMPTY); 471 __uart_setreg(bas, UART_IMSC, reg); 472 } 473 474 uart_unlock(sc->sc_hwmtx); 475 476 /* No interrupt expected, schedule the next fifo write */ 477 if (!sc->sc_txbusy) 478 uart_sched_softih(sc, SER_INT_TXIDLE); 479 480 return (0); 481 } 482 483 static void 484 uart_pl011_bus_grab(struct uart_softc *sc) 485 { 486 struct uart_bas *bas; 487 488 bas = &sc->sc_bas; 489 uart_lock(sc->sc_hwmtx); 490 __uart_setreg(bas, UART_IMSC, /* Switch to RX polling while grabbed */ 491 ~UART_RXREADY & __uart_getreg(bas, UART_IMSC)); 492 uart_unlock(sc->sc_hwmtx); 493 } 494 495 static void 496 uart_pl011_bus_ungrab(struct uart_softc *sc) 497 { 498 struct uart_bas *bas; 499 500 bas = &sc->sc_bas; 501 uart_lock(sc->sc_hwmtx); 502 __uart_setreg(bas, UART_IMSC, /* Switch to RX interrupts while not grabbed */ 503 UART_RXREADY | __uart_getreg(bas, UART_IMSC)); 504 uart_unlock(sc->sc_hwmtx); 505 } 506