1 /*- 2 * Copyright (c) 2012 Semihalf. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include "opt_acpi.h" 28 #include "opt_platform.h" 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/bus.h> 37 #include <machine/bus.h> 38 39 #include <dev/uart/uart.h> 40 #include <dev/uart/uart_cpu.h> 41 #ifdef DEV_ACPI 42 #include <dev/uart/uart_cpu_acpi.h> 43 #endif 44 #ifdef FDT 45 #include <dev/uart/uart_cpu_fdt.h> 46 #endif 47 #include <dev/uart/uart_bus.h> 48 #include "uart_if.h" 49 50 #include <sys/kdb.h> 51 52 /* PL011 UART registers and masks*/ 53 #define UART_DR 0x00 /* Data register */ 54 #define DR_FE (1 << 8) /* Framing error */ 55 #define DR_PE (1 << 9) /* Parity error */ 56 #define DR_BE (1 << 10) /* Break error */ 57 #define DR_OE (1 << 11) /* Overrun error */ 58 59 #define UART_FR 0x06 /* Flag register */ 60 #define FR_TXFF (1 << 5) /* Transmit FIFO/reg full */ 61 #define FR_RXFF (1 << 6) /* Receive FIFO/reg full */ 62 #define FR_TXFE (1 << 7) /* Transmit FIFO/reg empty */ 63 64 #define UART_IBRD 0x09 /* Integer baud rate register */ 65 #define IBRD_BDIVINT 0xffff /* Significant part of int. divisor value */ 66 67 #define UART_FBRD 0x0a /* Fractional baud rate register */ 68 #define FBRD_BDIVFRAC 0x3f /* Significant part of frac. divisor value */ 69 70 #define UART_LCR_H 0x0b /* Line control register */ 71 #define LCR_H_WLEN8 (0x3 << 5) 72 #define LCR_H_WLEN7 (0x2 << 5) 73 #define LCR_H_WLEN6 (0x1 << 5) 74 #define LCR_H_FEN (1 << 4) /* FIFO mode enable */ 75 #define LCR_H_STP2 (1 << 3) /* 2 stop frames at the end */ 76 #define LCR_H_EPS (1 << 2) /* Even parity select */ 77 #define LCR_H_PEN (1 << 1) /* Parity enable */ 78 79 #define UART_CR 0x0c /* Control register */ 80 #define CR_RXE (1 << 9) /* Receive enable */ 81 #define CR_TXE (1 << 8) /* Transmit enable */ 82 #define CR_UARTEN (1 << 0) /* UART enable */ 83 84 #define UART_IMSC 0x0e /* Interrupt mask set/clear register */ 85 #define IMSC_MASK_ALL 0x7ff /* Mask all interrupts */ 86 87 #define UART_RIS 0x0f /* Raw interrupt status register */ 88 #define UART_RXREADY (1 << 4) /* RX buffer full */ 89 #define UART_TXEMPTY (1 << 5) /* TX buffer empty */ 90 #define RIS_RTIM (1 << 6) /* Receive timeout */ 91 #define RIS_FE (1 << 7) /* Framing error interrupt status */ 92 #define RIS_PE (1 << 8) /* Parity error interrupt status */ 93 #define RIS_BE (1 << 9) /* Break error interrupt status */ 94 #define RIS_OE (1 << 10) /* Overrun interrupt status */ 95 96 #define UART_MIS 0x10 /* Masked interrupt status register */ 97 #define UART_ICR 0x11 /* Interrupt clear register */ 98 99 /* 100 * FIXME: actual register size is SoC-dependent, we need to handle it 101 */ 102 #define __uart_getreg(bas, reg) \ 103 bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg)) 104 #define __uart_setreg(bas, reg, value) \ 105 bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value) 106 107 /* 108 * Low-level UART interface. 109 */ 110 static int uart_pl011_probe(struct uart_bas *bas); 111 static void uart_pl011_init(struct uart_bas *bas, int, int, int, int); 112 static void uart_pl011_term(struct uart_bas *bas); 113 static void uart_pl011_putc(struct uart_bas *bas, int); 114 static int uart_pl011_rxready(struct uart_bas *bas); 115 static int uart_pl011_getc(struct uart_bas *bas, struct mtx *); 116 117 static struct uart_ops uart_pl011_ops = { 118 .probe = uart_pl011_probe, 119 .init = uart_pl011_init, 120 .term = uart_pl011_term, 121 .putc = uart_pl011_putc, 122 .rxready = uart_pl011_rxready, 123 .getc = uart_pl011_getc, 124 }; 125 126 static int 127 uart_pl011_probe(struct uart_bas *bas) 128 { 129 130 return (0); 131 } 132 133 static void 134 uart_pl011_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 135 int parity) 136 { 137 uint32_t ctrl, line; 138 uint32_t baud; 139 140 /* 141 * Zero all settings to make sure 142 * UART is disabled and not configured 143 */ 144 ctrl = line = 0x0; 145 __uart_setreg(bas, UART_CR, ctrl); 146 147 /* As we know UART is disabled we may setup the line */ 148 switch (databits) { 149 case 7: 150 line |= LCR_H_WLEN7; 151 break; 152 case 6: 153 line |= LCR_H_WLEN6; 154 break; 155 case 8: 156 default: 157 line |= LCR_H_WLEN8; 158 break; 159 } 160 161 if (stopbits == 2) 162 line |= LCR_H_STP2; 163 else 164 line &= ~LCR_H_STP2; 165 166 if (parity) 167 line |= LCR_H_PEN; 168 else 169 line &= ~LCR_H_PEN; 170 171 /* Configure the rest */ 172 line &= ~LCR_H_FEN; 173 ctrl |= (CR_RXE | CR_TXE | CR_UARTEN); 174 175 if (bas->rclk != 0 && baudrate != 0) { 176 baud = bas->rclk * 4 / baudrate; 177 __uart_setreg(bas, UART_IBRD, ((uint32_t)(baud >> 6)) & IBRD_BDIVINT); 178 __uart_setreg(bas, UART_FBRD, (uint32_t)(baud & 0x3F) & FBRD_BDIVFRAC); 179 } 180 181 /* Add config. to line before reenabling UART */ 182 __uart_setreg(bas, UART_LCR_H, (__uart_getreg(bas, UART_LCR_H) & 183 ~0xff) | line); 184 185 __uart_setreg(bas, UART_CR, ctrl); 186 } 187 188 static void 189 uart_pl011_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 190 int parity) 191 { 192 /* Mask all interrupts */ 193 __uart_setreg(bas, UART_IMSC, __uart_getreg(bas, UART_IMSC) & 194 ~IMSC_MASK_ALL); 195 196 uart_pl011_param(bas, baudrate, databits, stopbits, parity); 197 } 198 199 static void 200 uart_pl011_term(struct uart_bas *bas) 201 { 202 } 203 204 static void 205 uart_pl011_putc(struct uart_bas *bas, int c) 206 { 207 208 /* Wait when TX FIFO full. Push character otherwise. */ 209 while (__uart_getreg(bas, UART_FR) & FR_TXFF) 210 ; 211 __uart_setreg(bas, UART_DR, c & 0xff); 212 } 213 214 static int 215 uart_pl011_rxready(struct uart_bas *bas) 216 { 217 218 return (__uart_getreg(bas, UART_FR) & FR_RXFF); 219 } 220 221 static int 222 uart_pl011_getc(struct uart_bas *bas, struct mtx *hwmtx) 223 { 224 int c; 225 226 while (!uart_pl011_rxready(bas)) 227 ; 228 c = __uart_getreg(bas, UART_DR) & 0xff; 229 230 return (c); 231 } 232 233 /* 234 * High-level UART interface. 235 */ 236 struct uart_pl011_softc { 237 struct uart_softc base; 238 uint8_t fcr; 239 uint8_t ier; 240 uint8_t mcr; 241 242 uint8_t ier_mask; 243 uint8_t ier_rxbits; 244 }; 245 246 static int uart_pl011_bus_attach(struct uart_softc *); 247 static int uart_pl011_bus_detach(struct uart_softc *); 248 static int uart_pl011_bus_flush(struct uart_softc *, int); 249 static int uart_pl011_bus_getsig(struct uart_softc *); 250 static int uart_pl011_bus_ioctl(struct uart_softc *, int, intptr_t); 251 static int uart_pl011_bus_ipend(struct uart_softc *); 252 static int uart_pl011_bus_param(struct uart_softc *, int, int, int, int); 253 static int uart_pl011_bus_probe(struct uart_softc *); 254 static int uart_pl011_bus_receive(struct uart_softc *); 255 static int uart_pl011_bus_setsig(struct uart_softc *, int); 256 static int uart_pl011_bus_transmit(struct uart_softc *); 257 static void uart_pl011_bus_grab(struct uart_softc *); 258 static void uart_pl011_bus_ungrab(struct uart_softc *); 259 260 static kobj_method_t uart_pl011_methods[] = { 261 KOBJMETHOD(uart_attach, uart_pl011_bus_attach), 262 KOBJMETHOD(uart_detach, uart_pl011_bus_detach), 263 KOBJMETHOD(uart_flush, uart_pl011_bus_flush), 264 KOBJMETHOD(uart_getsig, uart_pl011_bus_getsig), 265 KOBJMETHOD(uart_ioctl, uart_pl011_bus_ioctl), 266 KOBJMETHOD(uart_ipend, uart_pl011_bus_ipend), 267 KOBJMETHOD(uart_param, uart_pl011_bus_param), 268 KOBJMETHOD(uart_probe, uart_pl011_bus_probe), 269 KOBJMETHOD(uart_receive, uart_pl011_bus_receive), 270 KOBJMETHOD(uart_setsig, uart_pl011_bus_setsig), 271 KOBJMETHOD(uart_transmit, uart_pl011_bus_transmit), 272 KOBJMETHOD(uart_grab, uart_pl011_bus_grab), 273 KOBJMETHOD(uart_ungrab, uart_pl011_bus_ungrab), 274 275 { 0, 0 } 276 }; 277 278 static struct uart_class uart_pl011_class = { 279 "uart_pl011", 280 uart_pl011_methods, 281 sizeof(struct uart_pl011_softc), 282 .uc_ops = &uart_pl011_ops, 283 .uc_range = 0x48, 284 .uc_rclk = 0, 285 .uc_rshift = 2 286 }; 287 288 289 #ifdef FDT 290 static struct ofw_compat_data compat_data[] = { 291 {"arm,pl011", (uintptr_t)&uart_pl011_class}, 292 {NULL, (uintptr_t)NULL}, 293 }; 294 UART_FDT_CLASS_AND_DEVICE(compat_data); 295 #endif 296 297 #ifdef DEV_ACPI 298 static struct acpi_uart_compat_data acpi_compat_data[] = { 299 {"ARMH0011", &uart_pl011_class}, 300 {NULL, NULL}, 301 }; 302 UART_ACPI_CLASS_AND_DEVICE(acpi_compat_data); 303 #endif 304 305 static int 306 uart_pl011_bus_attach(struct uart_softc *sc) 307 { 308 struct uart_bas *bas; 309 int reg; 310 311 bas = &sc->sc_bas; 312 313 /* Enable interrupts */ 314 reg = (UART_RXREADY | RIS_RTIM | UART_TXEMPTY); 315 __uart_setreg(bas, UART_IMSC, reg); 316 317 /* Clear interrupts */ 318 __uart_setreg(bas, UART_ICR, IMSC_MASK_ALL); 319 320 return (0); 321 } 322 323 static int 324 uart_pl011_bus_detach(struct uart_softc *sc) 325 { 326 327 return (0); 328 } 329 330 static int 331 uart_pl011_bus_flush(struct uart_softc *sc, int what) 332 { 333 334 return (0); 335 } 336 337 static int 338 uart_pl011_bus_getsig(struct uart_softc *sc) 339 { 340 341 return (0); 342 } 343 344 static int 345 uart_pl011_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 346 { 347 struct uart_bas *bas; 348 int error; 349 350 bas = &sc->sc_bas; 351 error = 0; 352 uart_lock(sc->sc_hwmtx); 353 switch (request) { 354 case UART_IOCTL_BREAK: 355 break; 356 case UART_IOCTL_BAUD: 357 *(int*)data = 115200; 358 break; 359 default: 360 error = EINVAL; 361 break; 362 } 363 uart_unlock(sc->sc_hwmtx); 364 365 return (error); 366 } 367 368 static int 369 uart_pl011_bus_ipend(struct uart_softc *sc) 370 { 371 struct uart_bas *bas; 372 uint32_t ints; 373 int ipend; 374 int reg; 375 376 bas = &sc->sc_bas; 377 uart_lock(sc->sc_hwmtx); 378 ints = __uart_getreg(bas, UART_MIS); 379 ipend = 0; 380 381 if (ints & (UART_RXREADY | RIS_RTIM)) 382 ipend |= SER_INT_RXREADY; 383 if (ints & RIS_BE) 384 ipend |= SER_INT_BREAK; 385 if (ints & RIS_OE) 386 ipend |= SER_INT_OVERRUN; 387 if (ints & UART_TXEMPTY) { 388 if (sc->sc_txbusy) 389 ipend |= SER_INT_TXIDLE; 390 391 /* Disable TX interrupt */ 392 reg = __uart_getreg(bas, UART_IMSC); 393 reg &= ~(UART_TXEMPTY); 394 __uart_setreg(bas, UART_IMSC, reg); 395 } 396 397 uart_unlock(sc->sc_hwmtx); 398 399 return (ipend); 400 } 401 402 static int 403 uart_pl011_bus_param(struct uart_softc *sc, int baudrate, int databits, 404 int stopbits, int parity) 405 { 406 407 uart_lock(sc->sc_hwmtx); 408 uart_pl011_param(&sc->sc_bas, baudrate, databits, stopbits, parity); 409 uart_unlock(sc->sc_hwmtx); 410 411 return (0); 412 } 413 414 static int 415 uart_pl011_bus_probe(struct uart_softc *sc) 416 { 417 418 device_set_desc(sc->sc_dev, "PrimeCell UART (PL011)"); 419 420 sc->sc_rxfifosz = 1; 421 sc->sc_txfifosz = 1; 422 423 return (0); 424 } 425 426 static int 427 uart_pl011_bus_receive(struct uart_softc *sc) 428 { 429 struct uart_bas *bas; 430 uint32_t ints, xc; 431 int rx; 432 433 bas = &sc->sc_bas; 434 uart_lock(sc->sc_hwmtx); 435 436 ints = __uart_getreg(bas, UART_MIS); 437 while (ints & (UART_RXREADY | RIS_RTIM)) { 438 if (uart_rx_full(sc)) { 439 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 440 break; 441 } 442 xc = __uart_getreg(bas, UART_DR); 443 rx = xc & 0xff; 444 445 if (xc & DR_FE) 446 rx |= UART_STAT_FRAMERR; 447 if (xc & DR_PE) 448 rx |= UART_STAT_PARERR; 449 450 __uart_setreg(bas, UART_ICR, (UART_RXREADY | RIS_RTIM)); 451 452 uart_rx_put(sc, rx); 453 ints = __uart_getreg(bas, UART_MIS); 454 } 455 456 uart_unlock(sc->sc_hwmtx); 457 458 return (0); 459 } 460 461 static int 462 uart_pl011_bus_setsig(struct uart_softc *sc, int sig) 463 { 464 465 return (0); 466 } 467 468 static int 469 uart_pl011_bus_transmit(struct uart_softc *sc) 470 { 471 struct uart_bas *bas; 472 int reg; 473 int i; 474 475 bas = &sc->sc_bas; 476 uart_lock(sc->sc_hwmtx); 477 478 for (i = 0; i < sc->sc_txdatasz; i++) { 479 __uart_setreg(bas, UART_DR, sc->sc_txbuf[i]); 480 uart_barrier(bas); 481 } 482 483 /* If not empty wait until it is */ 484 if ((__uart_getreg(bas, UART_FR) & FR_TXFE) != FR_TXFE) { 485 sc->sc_txbusy = 1; 486 487 /* Enable TX interrupt */ 488 reg = __uart_getreg(bas, UART_IMSC); 489 reg |= (UART_TXEMPTY); 490 __uart_setreg(bas, UART_IMSC, reg); 491 } 492 493 uart_unlock(sc->sc_hwmtx); 494 495 /* No interrupt expected, schedule the next fifo write */ 496 if (!sc->sc_txbusy) 497 uart_sched_softih(sc, SER_INT_TXIDLE); 498 499 return (0); 500 } 501 502 static void 503 uart_pl011_bus_grab(struct uart_softc *sc) 504 { 505 struct uart_bas *bas; 506 507 bas = &sc->sc_bas; 508 uart_lock(sc->sc_hwmtx); 509 __uart_setreg(bas, UART_IMSC, /* Switch to RX polling while grabbed */ 510 ~UART_RXREADY & __uart_getreg(bas, UART_IMSC)); 511 uart_unlock(sc->sc_hwmtx); 512 } 513 514 static void 515 uart_pl011_bus_ungrab(struct uart_softc *sc) 516 { 517 struct uart_bas *bas; 518 519 bas = &sc->sc_bas; 520 uart_lock(sc->sc_hwmtx); 521 __uart_setreg(bas, UART_IMSC, /* Switch to RX interrupts while not grabbed */ 522 UART_RXREADY | __uart_getreg(bas, UART_IMSC)); 523 uart_unlock(sc->sc_hwmtx); 524 } 525