1 /*- 2 * Copyright (c) 2012 Semihalf. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include "opt_acpi.h" 28 #include "opt_platform.h" 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/bus.h> 37 #include <machine/bus.h> 38 39 #include <dev/uart/uart.h> 40 #include <dev/uart/uart_cpu.h> 41 #ifdef FDT 42 #include <dev/uart/uart_cpu_fdt.h> 43 #endif 44 #include <dev/uart/uart_bus.h> 45 #include "uart_if.h" 46 47 #ifdef DEV_ACPI 48 #include <dev/uart/uart_cpu_acpi.h> 49 #include <contrib/dev/acpica/include/acpi.h> 50 #include <contrib/dev/acpica/include/accommon.h> 51 #include <contrib/dev/acpica/include/actables.h> 52 #endif 53 54 #include <sys/kdb.h> 55 56 /* PL011 UART registers and masks*/ 57 #define UART_DR 0x00 /* Data register */ 58 #define DR_FE (1 << 8) /* Framing error */ 59 #define DR_PE (1 << 9) /* Parity error */ 60 #define DR_BE (1 << 10) /* Break error */ 61 #define DR_OE (1 << 11) /* Overrun error */ 62 63 #define UART_FR 0x06 /* Flag register */ 64 #define FR_TXFF (1 << 5) /* Transmit FIFO/reg full */ 65 #define FR_RXFF (1 << 6) /* Receive FIFO/reg full */ 66 #define FR_TXFE (1 << 7) /* Transmit FIFO/reg empty */ 67 68 #define UART_IBRD 0x09 /* Integer baud rate register */ 69 #define IBRD_BDIVINT 0xffff /* Significant part of int. divisor value */ 70 71 #define UART_FBRD 0x0a /* Fractional baud rate register */ 72 #define FBRD_BDIVFRAC 0x3f /* Significant part of frac. divisor value */ 73 74 #define UART_LCR_H 0x0b /* Line control register */ 75 #define LCR_H_WLEN8 (0x3 << 5) 76 #define LCR_H_WLEN7 (0x2 << 5) 77 #define LCR_H_WLEN6 (0x1 << 5) 78 #define LCR_H_FEN (1 << 4) /* FIFO mode enable */ 79 #define LCR_H_STP2 (1 << 3) /* 2 stop frames at the end */ 80 #define LCR_H_EPS (1 << 2) /* Even parity select */ 81 #define LCR_H_PEN (1 << 1) /* Parity enable */ 82 83 #define UART_CR 0x0c /* Control register */ 84 #define CR_RXE (1 << 9) /* Receive enable */ 85 #define CR_TXE (1 << 8) /* Transmit enable */ 86 #define CR_UARTEN (1 << 0) /* UART enable */ 87 88 #define UART_IMSC 0x0e /* Interrupt mask set/clear register */ 89 #define IMSC_MASK_ALL 0x7ff /* Mask all interrupts */ 90 91 #define UART_RIS 0x0f /* Raw interrupt status register */ 92 #define UART_RXREADY (1 << 4) /* RX buffer full */ 93 #define UART_TXEMPTY (1 << 5) /* TX buffer empty */ 94 #define RIS_RTIM (1 << 6) /* Receive timeout */ 95 #define RIS_FE (1 << 7) /* Framing error interrupt status */ 96 #define RIS_PE (1 << 8) /* Parity error interrupt status */ 97 #define RIS_BE (1 << 9) /* Break error interrupt status */ 98 #define RIS_OE (1 << 10) /* Overrun interrupt status */ 99 100 #define UART_MIS 0x10 /* Masked interrupt status register */ 101 #define UART_ICR 0x11 /* Interrupt clear register */ 102 103 /* 104 * FIXME: actual register size is SoC-dependent, we need to handle it 105 */ 106 #define __uart_getreg(bas, reg) \ 107 bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg)) 108 #define __uart_setreg(bas, reg, value) \ 109 bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value) 110 111 /* 112 * Low-level UART interface. 113 */ 114 static int uart_pl011_probe(struct uart_bas *bas); 115 static void uart_pl011_init(struct uart_bas *bas, int, int, int, int); 116 static void uart_pl011_term(struct uart_bas *bas); 117 static void uart_pl011_putc(struct uart_bas *bas, int); 118 static int uart_pl011_rxready(struct uart_bas *bas); 119 static int uart_pl011_getc(struct uart_bas *bas, struct mtx *); 120 121 static struct uart_ops uart_pl011_ops = { 122 .probe = uart_pl011_probe, 123 .init = uart_pl011_init, 124 .term = uart_pl011_term, 125 .putc = uart_pl011_putc, 126 .rxready = uart_pl011_rxready, 127 .getc = uart_pl011_getc, 128 }; 129 130 static int 131 uart_pl011_probe(struct uart_bas *bas) 132 { 133 134 return (0); 135 } 136 137 static void 138 uart_pl011_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 139 int parity) 140 { 141 uint32_t ctrl, line; 142 uint32_t baud; 143 144 /* 145 * Zero all settings to make sure 146 * UART is disabled and not configured 147 */ 148 ctrl = line = 0x0; 149 __uart_setreg(bas, UART_CR, ctrl); 150 151 /* As we know UART is disabled we may setup the line */ 152 switch (databits) { 153 case 7: 154 line |= LCR_H_WLEN7; 155 break; 156 case 6: 157 line |= LCR_H_WLEN6; 158 break; 159 case 8: 160 default: 161 line |= LCR_H_WLEN8; 162 break; 163 } 164 165 if (stopbits == 2) 166 line |= LCR_H_STP2; 167 else 168 line &= ~LCR_H_STP2; 169 170 if (parity) 171 line |= LCR_H_PEN; 172 else 173 line &= ~LCR_H_PEN; 174 175 /* Configure the rest */ 176 line &= ~LCR_H_FEN; 177 ctrl |= (CR_RXE | CR_TXE | CR_UARTEN); 178 179 if (bas->rclk != 0 && baudrate != 0) { 180 baud = bas->rclk * 4 / baudrate; 181 __uart_setreg(bas, UART_IBRD, ((uint32_t)(baud >> 6)) & IBRD_BDIVINT); 182 __uart_setreg(bas, UART_FBRD, (uint32_t)(baud & 0x3F) & FBRD_BDIVFRAC); 183 } 184 185 /* Add config. to line before reenabling UART */ 186 __uart_setreg(bas, UART_LCR_H, (__uart_getreg(bas, UART_LCR_H) & 187 ~0xff) | line); 188 189 __uart_setreg(bas, UART_CR, ctrl); 190 } 191 192 static void 193 uart_pl011_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 194 int parity) 195 { 196 /* Mask all interrupts */ 197 __uart_setreg(bas, UART_IMSC, __uart_getreg(bas, UART_IMSC) & 198 ~IMSC_MASK_ALL); 199 200 uart_pl011_param(bas, baudrate, databits, stopbits, parity); 201 } 202 203 static void 204 uart_pl011_term(struct uart_bas *bas) 205 { 206 } 207 208 static void 209 uart_pl011_putc(struct uart_bas *bas, int c) 210 { 211 212 /* Wait when TX FIFO full. Push character otherwise. */ 213 while (__uart_getreg(bas, UART_FR) & FR_TXFF) 214 ; 215 __uart_setreg(bas, UART_DR, c & 0xff); 216 } 217 218 static int 219 uart_pl011_rxready(struct uart_bas *bas) 220 { 221 222 return (__uart_getreg(bas, UART_FR) & FR_RXFF); 223 } 224 225 static int 226 uart_pl011_getc(struct uart_bas *bas, struct mtx *hwmtx) 227 { 228 int c; 229 230 while (!uart_pl011_rxready(bas)) 231 ; 232 c = __uart_getreg(bas, UART_DR) & 0xff; 233 234 return (c); 235 } 236 237 /* 238 * High-level UART interface. 239 */ 240 struct uart_pl011_softc { 241 struct uart_softc base; 242 uint8_t fcr; 243 uint8_t ier; 244 uint8_t mcr; 245 246 uint8_t ier_mask; 247 uint8_t ier_rxbits; 248 }; 249 250 static int uart_pl011_bus_attach(struct uart_softc *); 251 static int uart_pl011_bus_detach(struct uart_softc *); 252 static int uart_pl011_bus_flush(struct uart_softc *, int); 253 static int uart_pl011_bus_getsig(struct uart_softc *); 254 static int uart_pl011_bus_ioctl(struct uart_softc *, int, intptr_t); 255 static int uart_pl011_bus_ipend(struct uart_softc *); 256 static int uart_pl011_bus_param(struct uart_softc *, int, int, int, int); 257 static int uart_pl011_bus_probe(struct uart_softc *); 258 static int uart_pl011_bus_receive(struct uart_softc *); 259 static int uart_pl011_bus_setsig(struct uart_softc *, int); 260 static int uart_pl011_bus_transmit(struct uart_softc *); 261 static void uart_pl011_bus_grab(struct uart_softc *); 262 static void uart_pl011_bus_ungrab(struct uart_softc *); 263 264 static kobj_method_t uart_pl011_methods[] = { 265 KOBJMETHOD(uart_attach, uart_pl011_bus_attach), 266 KOBJMETHOD(uart_detach, uart_pl011_bus_detach), 267 KOBJMETHOD(uart_flush, uart_pl011_bus_flush), 268 KOBJMETHOD(uart_getsig, uart_pl011_bus_getsig), 269 KOBJMETHOD(uart_ioctl, uart_pl011_bus_ioctl), 270 KOBJMETHOD(uart_ipend, uart_pl011_bus_ipend), 271 KOBJMETHOD(uart_param, uart_pl011_bus_param), 272 KOBJMETHOD(uart_probe, uart_pl011_bus_probe), 273 KOBJMETHOD(uart_receive, uart_pl011_bus_receive), 274 KOBJMETHOD(uart_setsig, uart_pl011_bus_setsig), 275 KOBJMETHOD(uart_transmit, uart_pl011_bus_transmit), 276 KOBJMETHOD(uart_grab, uart_pl011_bus_grab), 277 KOBJMETHOD(uart_ungrab, uart_pl011_bus_ungrab), 278 279 { 0, 0 } 280 }; 281 282 static struct uart_class uart_pl011_class = { 283 "uart_pl011", 284 uart_pl011_methods, 285 sizeof(struct uart_pl011_softc), 286 .uc_ops = &uart_pl011_ops, 287 .uc_range = 0x48, 288 .uc_rclk = 0, 289 .uc_rshift = 2 290 }; 291 292 293 #ifdef FDT 294 static struct ofw_compat_data compat_data[] = { 295 {"arm,pl011", (uintptr_t)&uart_pl011_class}, 296 {NULL, (uintptr_t)NULL}, 297 }; 298 UART_FDT_CLASS_AND_DEVICE(compat_data); 299 #endif 300 301 #ifdef DEV_ACPI 302 static struct acpi_uart_compat_data acpi_compat_data[] = { 303 {"ARMH0011", &uart_pl011_class, ACPI_DBG2_ARM_PL011}, 304 {NULL, NULL, 0}, 305 }; 306 UART_ACPI_CLASS_AND_DEVICE(acpi_compat_data); 307 #endif 308 309 static int 310 uart_pl011_bus_attach(struct uart_softc *sc) 311 { 312 struct uart_bas *bas; 313 int reg; 314 315 bas = &sc->sc_bas; 316 317 /* Enable interrupts */ 318 reg = (UART_RXREADY | RIS_RTIM | UART_TXEMPTY); 319 __uart_setreg(bas, UART_IMSC, reg); 320 321 /* Clear interrupts */ 322 __uart_setreg(bas, UART_ICR, IMSC_MASK_ALL); 323 324 return (0); 325 } 326 327 static int 328 uart_pl011_bus_detach(struct uart_softc *sc) 329 { 330 331 return (0); 332 } 333 334 static int 335 uart_pl011_bus_flush(struct uart_softc *sc, int what) 336 { 337 338 return (0); 339 } 340 341 static int 342 uart_pl011_bus_getsig(struct uart_softc *sc) 343 { 344 345 return (0); 346 } 347 348 static int 349 uart_pl011_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 350 { 351 struct uart_bas *bas; 352 int error; 353 354 bas = &sc->sc_bas; 355 error = 0; 356 uart_lock(sc->sc_hwmtx); 357 switch (request) { 358 case UART_IOCTL_BREAK: 359 break; 360 case UART_IOCTL_BAUD: 361 *(int*)data = 115200; 362 break; 363 default: 364 error = EINVAL; 365 break; 366 } 367 uart_unlock(sc->sc_hwmtx); 368 369 return (error); 370 } 371 372 static int 373 uart_pl011_bus_ipend(struct uart_softc *sc) 374 { 375 struct uart_bas *bas; 376 uint32_t ints; 377 int ipend; 378 int reg; 379 380 bas = &sc->sc_bas; 381 uart_lock(sc->sc_hwmtx); 382 ints = __uart_getreg(bas, UART_MIS); 383 ipend = 0; 384 385 if (ints & (UART_RXREADY | RIS_RTIM)) 386 ipend |= SER_INT_RXREADY; 387 if (ints & RIS_BE) 388 ipend |= SER_INT_BREAK; 389 if (ints & RIS_OE) 390 ipend |= SER_INT_OVERRUN; 391 if (ints & UART_TXEMPTY) { 392 if (sc->sc_txbusy) 393 ipend |= SER_INT_TXIDLE; 394 395 /* Disable TX interrupt */ 396 reg = __uart_getreg(bas, UART_IMSC); 397 reg &= ~(UART_TXEMPTY); 398 __uart_setreg(bas, UART_IMSC, reg); 399 } 400 401 uart_unlock(sc->sc_hwmtx); 402 403 return (ipend); 404 } 405 406 static int 407 uart_pl011_bus_param(struct uart_softc *sc, int baudrate, int databits, 408 int stopbits, int parity) 409 { 410 411 uart_lock(sc->sc_hwmtx); 412 uart_pl011_param(&sc->sc_bas, baudrate, databits, stopbits, parity); 413 uart_unlock(sc->sc_hwmtx); 414 415 return (0); 416 } 417 418 static int 419 uart_pl011_bus_probe(struct uart_softc *sc) 420 { 421 422 device_set_desc(sc->sc_dev, "PrimeCell UART (PL011)"); 423 424 sc->sc_rxfifosz = 1; 425 sc->sc_txfifosz = 1; 426 427 return (0); 428 } 429 430 static int 431 uart_pl011_bus_receive(struct uart_softc *sc) 432 { 433 struct uart_bas *bas; 434 uint32_t ints, xc; 435 int rx; 436 437 bas = &sc->sc_bas; 438 uart_lock(sc->sc_hwmtx); 439 440 ints = __uart_getreg(bas, UART_MIS); 441 while (ints & (UART_RXREADY | RIS_RTIM)) { 442 if (uart_rx_full(sc)) { 443 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 444 break; 445 } 446 447 __uart_setreg(bas, UART_ICR, (UART_RXREADY | RIS_RTIM)); 448 xc = __uart_getreg(bas, UART_DR); 449 rx = xc & 0xff; 450 451 if (xc & DR_FE) 452 rx |= UART_STAT_FRAMERR; 453 if (xc & DR_PE) 454 rx |= UART_STAT_PARERR; 455 456 uart_rx_put(sc, rx); 457 ints = __uart_getreg(bas, UART_MIS); 458 } 459 460 uart_unlock(sc->sc_hwmtx); 461 462 return (0); 463 } 464 465 static int 466 uart_pl011_bus_setsig(struct uart_softc *sc, int sig) 467 { 468 469 return (0); 470 } 471 472 static int 473 uart_pl011_bus_transmit(struct uart_softc *sc) 474 { 475 struct uart_bas *bas; 476 int reg; 477 int i; 478 479 bas = &sc->sc_bas; 480 uart_lock(sc->sc_hwmtx); 481 482 for (i = 0; i < sc->sc_txdatasz; i++) { 483 __uart_setreg(bas, UART_DR, sc->sc_txbuf[i]); 484 uart_barrier(bas); 485 } 486 487 /* If not empty wait until it is */ 488 if ((__uart_getreg(bas, UART_FR) & FR_TXFE) != FR_TXFE) { 489 sc->sc_txbusy = 1; 490 491 /* Enable TX interrupt */ 492 reg = __uart_getreg(bas, UART_IMSC); 493 reg |= (UART_TXEMPTY); 494 __uart_setreg(bas, UART_IMSC, reg); 495 } 496 497 uart_unlock(sc->sc_hwmtx); 498 499 /* No interrupt expected, schedule the next fifo write */ 500 if (!sc->sc_txbusy) 501 uart_sched_softih(sc, SER_INT_TXIDLE); 502 503 return (0); 504 } 505 506 static void 507 uart_pl011_bus_grab(struct uart_softc *sc) 508 { 509 struct uart_bas *bas; 510 511 bas = &sc->sc_bas; 512 uart_lock(sc->sc_hwmtx); 513 __uart_setreg(bas, UART_IMSC, /* Switch to RX polling while grabbed */ 514 ~UART_RXREADY & __uart_getreg(bas, UART_IMSC)); 515 uart_unlock(sc->sc_hwmtx); 516 } 517 518 static void 519 uart_pl011_bus_ungrab(struct uart_softc *sc) 520 { 521 struct uart_bas *bas; 522 523 bas = &sc->sc_bas; 524 uart_lock(sc->sc_hwmtx); 525 __uart_setreg(bas, UART_IMSC, /* Switch to RX interrupts while not grabbed */ 526 UART_RXREADY | __uart_getreg(bas, UART_IMSC)); 527 uart_unlock(sc->sc_hwmtx); 528 } 529