1 /*- 2 * Copyright (c) 2012 Semihalf. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include "opt_acpi.h" 28 #include "opt_platform.h" 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/bus.h> 37 #include <machine/bus.h> 38 39 #include <dev/uart/uart.h> 40 #include <dev/uart/uart_cpu.h> 41 #ifdef FDT 42 #include <dev/uart/uart_cpu_fdt.h> 43 #endif 44 #include <dev/uart/uart_bus.h> 45 #include "uart_if.h" 46 47 #ifdef DEV_ACPI 48 #include <dev/uart/uart_cpu_acpi.h> 49 #include <contrib/dev/acpica/include/acpi.h> 50 #include <contrib/dev/acpica/include/accommon.h> 51 #include <contrib/dev/acpica/include/actables.h> 52 #endif 53 54 #include <sys/kdb.h> 55 56 /* PL011 UART registers and masks*/ 57 #define UART_DR 0x00 /* Data register */ 58 #define DR_FE (1 << 8) /* Framing error */ 59 #define DR_PE (1 << 9) /* Parity error */ 60 #define DR_BE (1 << 10) /* Break error */ 61 #define DR_OE (1 << 11) /* Overrun error */ 62 63 #define UART_FR 0x06 /* Flag register */ 64 #define FR_RXFE (1 << 4) /* Receive FIFO/reg empty */ 65 #define FR_TXFF (1 << 5) /* Transmit FIFO/reg full */ 66 #define FR_RXFF (1 << 6) /* Receive FIFO/reg full */ 67 #define FR_TXFE (1 << 7) /* Transmit FIFO/reg empty */ 68 69 #define UART_IBRD 0x09 /* Integer baud rate register */ 70 #define IBRD_BDIVINT 0xffff /* Significant part of int. divisor value */ 71 72 #define UART_FBRD 0x0a /* Fractional baud rate register */ 73 #define FBRD_BDIVFRAC 0x3f /* Significant part of frac. divisor value */ 74 75 #define UART_LCR_H 0x0b /* Line control register */ 76 #define LCR_H_WLEN8 (0x3 << 5) 77 #define LCR_H_WLEN7 (0x2 << 5) 78 #define LCR_H_WLEN6 (0x1 << 5) 79 #define LCR_H_FEN (1 << 4) /* FIFO mode enable */ 80 #define LCR_H_STP2 (1 << 3) /* 2 stop frames at the end */ 81 #define LCR_H_EPS (1 << 2) /* Even parity select */ 82 #define LCR_H_PEN (1 << 1) /* Parity enable */ 83 84 #define UART_CR 0x0c /* Control register */ 85 #define CR_RXE (1 << 9) /* Receive enable */ 86 #define CR_TXE (1 << 8) /* Transmit enable */ 87 #define CR_UARTEN (1 << 0) /* UART enable */ 88 89 #define UART_IMSC 0x0e /* Interrupt mask set/clear register */ 90 #define IMSC_MASK_ALL 0x7ff /* Mask all interrupts */ 91 92 #define UART_RIS 0x0f /* Raw interrupt status register */ 93 #define UART_RXREADY (1 << 4) /* RX buffer full */ 94 #define UART_TXEMPTY (1 << 5) /* TX buffer empty */ 95 #define RIS_RTIM (1 << 6) /* Receive timeout */ 96 #define RIS_FE (1 << 7) /* Framing error interrupt status */ 97 #define RIS_PE (1 << 8) /* Parity error interrupt status */ 98 #define RIS_BE (1 << 9) /* Break error interrupt status */ 99 #define RIS_OE (1 << 10) /* Overrun interrupt status */ 100 101 #define UART_MIS 0x10 /* Masked interrupt status register */ 102 #define UART_ICR 0x11 /* Interrupt clear register */ 103 104 /* 105 * FIXME: actual register size is SoC-dependent, we need to handle it 106 */ 107 #define __uart_getreg(bas, reg) \ 108 bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg)) 109 #define __uart_setreg(bas, reg, value) \ 110 bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value) 111 112 /* 113 * Low-level UART interface. 114 */ 115 static int uart_pl011_probe(struct uart_bas *bas); 116 static void uart_pl011_init(struct uart_bas *bas, int, int, int, int); 117 static void uart_pl011_term(struct uart_bas *bas); 118 static void uart_pl011_putc(struct uart_bas *bas, int); 119 static int uart_pl011_rxready(struct uart_bas *bas); 120 static int uart_pl011_getc(struct uart_bas *bas, struct mtx *); 121 122 static struct uart_ops uart_pl011_ops = { 123 .probe = uart_pl011_probe, 124 .init = uart_pl011_init, 125 .term = uart_pl011_term, 126 .putc = uart_pl011_putc, 127 .rxready = uart_pl011_rxready, 128 .getc = uart_pl011_getc, 129 }; 130 131 static int 132 uart_pl011_probe(struct uart_bas *bas) 133 { 134 135 return (0); 136 } 137 138 static void 139 uart_pl011_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 140 int parity) 141 { 142 uint32_t ctrl, line; 143 uint32_t baud; 144 145 /* 146 * Zero all settings to make sure 147 * UART is disabled and not configured 148 */ 149 ctrl = line = 0x0; 150 __uart_setreg(bas, UART_CR, ctrl); 151 152 /* As we know UART is disabled we may setup the line */ 153 switch (databits) { 154 case 7: 155 line |= LCR_H_WLEN7; 156 break; 157 case 6: 158 line |= LCR_H_WLEN6; 159 break; 160 case 8: 161 default: 162 line |= LCR_H_WLEN8; 163 break; 164 } 165 166 if (stopbits == 2) 167 line |= LCR_H_STP2; 168 else 169 line &= ~LCR_H_STP2; 170 171 if (parity) 172 line |= LCR_H_PEN; 173 else 174 line &= ~LCR_H_PEN; 175 line |= LCR_H_FEN; 176 177 /* Configure the rest */ 178 ctrl |= (CR_RXE | CR_TXE | CR_UARTEN); 179 180 if (bas->rclk != 0 && baudrate != 0) { 181 baud = bas->rclk * 4 / baudrate; 182 __uart_setreg(bas, UART_IBRD, ((uint32_t)(baud >> 6)) & IBRD_BDIVINT); 183 __uart_setreg(bas, UART_FBRD, (uint32_t)(baud & 0x3F) & FBRD_BDIVFRAC); 184 } 185 186 /* Add config. to line before reenabling UART */ 187 __uart_setreg(bas, UART_LCR_H, (__uart_getreg(bas, UART_LCR_H) & 188 ~0xff) | line); 189 190 __uart_setreg(bas, UART_CR, ctrl); 191 } 192 193 static void 194 uart_pl011_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 195 int parity) 196 { 197 /* Mask all interrupts */ 198 __uart_setreg(bas, UART_IMSC, __uart_getreg(bas, UART_IMSC) & 199 ~IMSC_MASK_ALL); 200 201 uart_pl011_param(bas, baudrate, databits, stopbits, parity); 202 } 203 204 static void 205 uart_pl011_term(struct uart_bas *bas) 206 { 207 } 208 209 static void 210 uart_pl011_putc(struct uart_bas *bas, int c) 211 { 212 213 /* Wait when TX FIFO full. Push character otherwise. */ 214 while (__uart_getreg(bas, UART_FR) & FR_TXFF) 215 ; 216 __uart_setreg(bas, UART_DR, c & 0xff); 217 } 218 219 static int 220 uart_pl011_rxready(struct uart_bas *bas) 221 { 222 223 return !(__uart_getreg(bas, UART_FR) & FR_RXFE); 224 } 225 226 static int 227 uart_pl011_getc(struct uart_bas *bas, struct mtx *hwmtx) 228 { 229 int c; 230 231 while (!uart_pl011_rxready(bas)) 232 ; 233 c = __uart_getreg(bas, UART_DR) & 0xff; 234 235 return (c); 236 } 237 238 /* 239 * High-level UART interface. 240 */ 241 struct uart_pl011_softc { 242 struct uart_softc base; 243 uint16_t imsc; /* Interrupt mask */ 244 }; 245 246 static int uart_pl011_bus_attach(struct uart_softc *); 247 static int uart_pl011_bus_detach(struct uart_softc *); 248 static int uart_pl011_bus_flush(struct uart_softc *, int); 249 static int uart_pl011_bus_getsig(struct uart_softc *); 250 static int uart_pl011_bus_ioctl(struct uart_softc *, int, intptr_t); 251 static int uart_pl011_bus_ipend(struct uart_softc *); 252 static int uart_pl011_bus_param(struct uart_softc *, int, int, int, int); 253 static int uart_pl011_bus_probe(struct uart_softc *); 254 static int uart_pl011_bus_receive(struct uart_softc *); 255 static int uart_pl011_bus_setsig(struct uart_softc *, int); 256 static int uart_pl011_bus_transmit(struct uart_softc *); 257 static void uart_pl011_bus_grab(struct uart_softc *); 258 static void uart_pl011_bus_ungrab(struct uart_softc *); 259 260 static kobj_method_t uart_pl011_methods[] = { 261 KOBJMETHOD(uart_attach, uart_pl011_bus_attach), 262 KOBJMETHOD(uart_detach, uart_pl011_bus_detach), 263 KOBJMETHOD(uart_flush, uart_pl011_bus_flush), 264 KOBJMETHOD(uart_getsig, uart_pl011_bus_getsig), 265 KOBJMETHOD(uart_ioctl, uart_pl011_bus_ioctl), 266 KOBJMETHOD(uart_ipend, uart_pl011_bus_ipend), 267 KOBJMETHOD(uart_param, uart_pl011_bus_param), 268 KOBJMETHOD(uart_probe, uart_pl011_bus_probe), 269 KOBJMETHOD(uart_receive, uart_pl011_bus_receive), 270 KOBJMETHOD(uart_setsig, uart_pl011_bus_setsig), 271 KOBJMETHOD(uart_transmit, uart_pl011_bus_transmit), 272 KOBJMETHOD(uart_grab, uart_pl011_bus_grab), 273 KOBJMETHOD(uart_ungrab, uart_pl011_bus_ungrab), 274 275 { 0, 0 } 276 }; 277 278 static struct uart_class uart_pl011_class = { 279 "uart_pl011", 280 uart_pl011_methods, 281 sizeof(struct uart_pl011_softc), 282 .uc_ops = &uart_pl011_ops, 283 .uc_range = 0x48, 284 .uc_rclk = 0, 285 .uc_rshift = 2 286 }; 287 288 289 #ifdef FDT 290 static struct ofw_compat_data compat_data[] = { 291 {"arm,pl011", (uintptr_t)&uart_pl011_class}, 292 {NULL, (uintptr_t)NULL}, 293 }; 294 UART_FDT_CLASS_AND_DEVICE(compat_data); 295 #endif 296 297 #ifdef DEV_ACPI 298 static struct acpi_uart_compat_data acpi_compat_data[] = { 299 {"ARMH0011", &uart_pl011_class, ACPI_DBG2_ARM_PL011}, 300 {NULL, NULL, 0}, 301 }; 302 UART_ACPI_CLASS_AND_DEVICE(acpi_compat_data); 303 #endif 304 305 static int 306 uart_pl011_bus_attach(struct uart_softc *sc) 307 { 308 struct uart_pl011_softc *psc; 309 struct uart_bas *bas; 310 311 psc = (struct uart_pl011_softc *)sc; 312 bas = &sc->sc_bas; 313 314 /* Enable interrupts */ 315 psc->imsc = (UART_RXREADY | RIS_RTIM | UART_TXEMPTY); 316 __uart_setreg(bas, UART_IMSC, psc->imsc); 317 318 /* Clear interrupts */ 319 __uart_setreg(bas, UART_ICR, IMSC_MASK_ALL); 320 321 return (0); 322 } 323 324 static int 325 uart_pl011_bus_detach(struct uart_softc *sc) 326 { 327 328 return (0); 329 } 330 331 static int 332 uart_pl011_bus_flush(struct uart_softc *sc, int what) 333 { 334 335 return (0); 336 } 337 338 static int 339 uart_pl011_bus_getsig(struct uart_softc *sc) 340 { 341 342 return (0); 343 } 344 345 static int 346 uart_pl011_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 347 { 348 struct uart_bas *bas; 349 int error; 350 351 bas = &sc->sc_bas; 352 error = 0; 353 uart_lock(sc->sc_hwmtx); 354 switch (request) { 355 case UART_IOCTL_BREAK: 356 break; 357 case UART_IOCTL_BAUD: 358 *(int*)data = 115200; 359 break; 360 default: 361 error = EINVAL; 362 break; 363 } 364 uart_unlock(sc->sc_hwmtx); 365 366 return (error); 367 } 368 369 static int 370 uart_pl011_bus_ipend(struct uart_softc *sc) 371 { 372 struct uart_pl011_softc *psc; 373 struct uart_bas *bas; 374 uint32_t ints; 375 int ipend; 376 377 psc = (struct uart_pl011_softc *)sc; 378 bas = &sc->sc_bas; 379 380 uart_lock(sc->sc_hwmtx); 381 ints = __uart_getreg(bas, UART_MIS); 382 ipend = 0; 383 384 if (ints & (UART_RXREADY | RIS_RTIM)) 385 ipend |= SER_INT_RXREADY; 386 if (ints & RIS_BE) 387 ipend |= SER_INT_BREAK; 388 if (ints & RIS_OE) 389 ipend |= SER_INT_OVERRUN; 390 if (ints & UART_TXEMPTY) { 391 if (sc->sc_txbusy) 392 ipend |= SER_INT_TXIDLE; 393 394 /* Disable TX interrupt */ 395 __uart_setreg(bas, UART_IMSC, psc->imsc & ~UART_TXEMPTY); 396 } 397 398 uart_unlock(sc->sc_hwmtx); 399 400 return (ipend); 401 } 402 403 static int 404 uart_pl011_bus_param(struct uart_softc *sc, int baudrate, int databits, 405 int stopbits, int parity) 406 { 407 408 uart_lock(sc->sc_hwmtx); 409 uart_pl011_param(&sc->sc_bas, baudrate, databits, stopbits, parity); 410 uart_unlock(sc->sc_hwmtx); 411 412 return (0); 413 } 414 415 static int 416 uart_pl011_bus_probe(struct uart_softc *sc) 417 { 418 419 device_set_desc(sc->sc_dev, "PrimeCell UART (PL011)"); 420 421 sc->sc_rxfifosz = 16; 422 sc->sc_txfifosz = 16; 423 424 return (0); 425 } 426 427 static int 428 uart_pl011_bus_receive(struct uart_softc *sc) 429 { 430 struct uart_bas *bas; 431 uint32_t ints, xc; 432 int rx; 433 434 bas = &sc->sc_bas; 435 uart_lock(sc->sc_hwmtx); 436 437 ints = __uart_getreg(bas, UART_MIS); 438 while (ints & (UART_RXREADY | RIS_RTIM)) { 439 if (uart_rx_full(sc)) { 440 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 441 break; 442 } 443 444 xc = __uart_getreg(bas, UART_DR); 445 rx = xc & 0xff; 446 447 if (xc & DR_FE) 448 rx |= UART_STAT_FRAMERR; 449 if (xc & DR_PE) 450 rx |= UART_STAT_PARERR; 451 452 uart_rx_put(sc, rx); 453 ints = __uart_getreg(bas, UART_MIS); 454 } 455 456 uart_unlock(sc->sc_hwmtx); 457 458 return (0); 459 } 460 461 static int 462 uart_pl011_bus_setsig(struct uart_softc *sc, int sig) 463 { 464 465 return (0); 466 } 467 468 static int 469 uart_pl011_bus_transmit(struct uart_softc *sc) 470 { 471 struct uart_pl011_softc *psc; 472 struct uart_bas *bas; 473 int i; 474 475 psc = (struct uart_pl011_softc *)sc; 476 bas = &sc->sc_bas; 477 uart_lock(sc->sc_hwmtx); 478 479 for (i = 0; i < sc->sc_txdatasz; i++) { 480 __uart_setreg(bas, UART_DR, sc->sc_txbuf[i]); 481 uart_barrier(bas); 482 } 483 484 /* Mark busy and enable TX interrupt */ 485 sc->sc_txbusy = 1; 486 __uart_setreg(bas, UART_IMSC, psc->imsc); 487 488 uart_unlock(sc->sc_hwmtx); 489 490 return (0); 491 } 492 493 static void 494 uart_pl011_bus_grab(struct uart_softc *sc) 495 { 496 struct uart_pl011_softc *psc; 497 struct uart_bas *bas; 498 499 psc = (struct uart_pl011_softc *)sc; 500 bas = &sc->sc_bas; 501 502 /* Disable interrupts on switch to polling */ 503 uart_lock(sc->sc_hwmtx); 504 __uart_setreg(bas, UART_IMSC, psc->imsc & ~IMSC_MASK_ALL); 505 uart_unlock(sc->sc_hwmtx); 506 } 507 508 static void 509 uart_pl011_bus_ungrab(struct uart_softc *sc) 510 { 511 struct uart_pl011_softc *psc; 512 struct uart_bas *bas; 513 514 psc = (struct uart_pl011_softc *)sc; 515 bas = &sc->sc_bas; 516 517 /* Switch to using interrupts while not grabbed */ 518 uart_lock(sc->sc_hwmtx); 519 __uart_setreg(bas, UART_IMSC, psc->imsc); 520 uart_unlock(sc->sc_hwmtx); 521 } 522