1 /*- 2 * Copyright (c) 2012 Semihalf. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include "opt_acpi.h" 28 #include "opt_platform.h" 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/bus.h> 37 #include <machine/bus.h> 38 39 #include <dev/uart/uart.h> 40 #include <dev/uart/uart_cpu.h> 41 #ifdef FDT 42 #include <dev/uart/uart_cpu_fdt.h> 43 #include <dev/ofw/ofw_bus.h> 44 #endif 45 #include <dev/uart/uart_bus.h> 46 #include "uart_if.h" 47 48 #ifdef DEV_ACPI 49 #include <dev/uart/uart_cpu_acpi.h> 50 #include <contrib/dev/acpica/include/acpi.h> 51 #include <contrib/dev/acpica/include/accommon.h> 52 #include <contrib/dev/acpica/include/actables.h> 53 #endif 54 55 #include <sys/kdb.h> 56 57 /* PL011 UART registers and masks*/ 58 #define UART_DR 0x00 /* Data register */ 59 #define DR_FE (1 << 8) /* Framing error */ 60 #define DR_PE (1 << 9) /* Parity error */ 61 #define DR_BE (1 << 10) /* Break error */ 62 #define DR_OE (1 << 11) /* Overrun error */ 63 64 #define UART_FR 0x06 /* Flag register */ 65 #define FR_RXFE (1 << 4) /* Receive FIFO/reg empty */ 66 #define FR_TXFF (1 << 5) /* Transmit FIFO/reg full */ 67 #define FR_RXFF (1 << 6) /* Receive FIFO/reg full */ 68 #define FR_TXFE (1 << 7) /* Transmit FIFO/reg empty */ 69 70 #define UART_IBRD 0x09 /* Integer baud rate register */ 71 #define IBRD_BDIVINT 0xffff /* Significant part of int. divisor value */ 72 73 #define UART_FBRD 0x0a /* Fractional baud rate register */ 74 #define FBRD_BDIVFRAC 0x3f /* Significant part of frac. divisor value */ 75 76 #define UART_LCR_H 0x0b /* Line control register */ 77 #define LCR_H_WLEN8 (0x3 << 5) 78 #define LCR_H_WLEN7 (0x2 << 5) 79 #define LCR_H_WLEN6 (0x1 << 5) 80 #define LCR_H_FEN (1 << 4) /* FIFO mode enable */ 81 #define LCR_H_STP2 (1 << 3) /* 2 stop frames at the end */ 82 #define LCR_H_EPS (1 << 2) /* Even parity select */ 83 #define LCR_H_PEN (1 << 1) /* Parity enable */ 84 85 #define UART_CR 0x0c /* Control register */ 86 #define CR_RXE (1 << 9) /* Receive enable */ 87 #define CR_TXE (1 << 8) /* Transmit enable */ 88 #define CR_UARTEN (1 << 0) /* UART enable */ 89 90 #define UART_IFLS 0x0d /* FIFO level select register */ 91 #define IFLS_RX_SHIFT 3 /* RX level in bits [5:3] */ 92 #define IFLS_TX_SHIFT 0 /* TX level in bits [2:0] */ 93 #define IFLS_MASK 0x07 /* RX/TX level is 3 bits */ 94 #define IFLS_LVL_1_8th 0 /* Interrupt at 1/8 full */ 95 #define IFLS_LVL_2_8th 1 /* Interrupt at 1/4 full */ 96 #define IFLS_LVL_4_8th 2 /* Interrupt at 1/2 full */ 97 #define IFLS_LVL_6_8th 3 /* Interrupt at 3/4 full */ 98 #define IFLS_LVL_7_8th 4 /* Interrupt at 7/8 full */ 99 100 #define UART_IMSC 0x0e /* Interrupt mask set/clear register */ 101 #define IMSC_MASK_ALL 0x7ff /* Mask all interrupts */ 102 103 #define UART_RIS 0x0f /* Raw interrupt status register */ 104 #define UART_RXREADY (1 << 4) /* RX buffer full */ 105 #define UART_TXEMPTY (1 << 5) /* TX buffer empty */ 106 #define RIS_RTIM (1 << 6) /* Receive timeout */ 107 #define RIS_FE (1 << 7) /* Framing error interrupt status */ 108 #define RIS_PE (1 << 8) /* Parity error interrupt status */ 109 #define RIS_BE (1 << 9) /* Break error interrupt status */ 110 #define RIS_OE (1 << 10) /* Overrun interrupt status */ 111 112 #define UART_MIS 0x10 /* Masked interrupt status register */ 113 #define UART_ICR 0x11 /* Interrupt clear register */ 114 115 #define UART_PIDREG_0 0x3f8 /* Peripheral ID register 0 */ 116 #define UART_PIDREG_1 0x3f9 /* Peripheral ID register 1 */ 117 #define UART_PIDREG_2 0x3fa /* Peripheral ID register 2 */ 118 #define UART_PIDREG_3 0x3fb /* Peripheral ID register 3 */ 119 120 /* 121 * The hardware FIFOs are 16 bytes each on rev 2 and earlier hardware, 32 bytes 122 * on rev 3 and later. We configure them to interrupt when 3/4 full/empty. For 123 * RX we set the size to the full hardware capacity so that the uart core 124 * allocates enough buffer space to hold a complete fifo full of incoming data. 125 * For TX, we need to limit the size to the capacity we know will be available 126 * when the interrupt occurs; uart_core will feed exactly that many bytes to 127 * uart_pl011_bus_transmit() which must consume them all. 128 */ 129 #define FIFO_RX_SIZE_R2 16 130 #define FIFO_TX_SIZE_R2 12 131 #define FIFO_RX_SIZE_R3 32 132 #define FIFO_TX_SIZE_R3 24 133 #define FIFO_IFLS_BITS ((IFLS_LVL_6_8th << IFLS_RX_SHIFT) | (IFLS_LVL_2_8th)) 134 135 /* 136 * FIXME: actual register size is SoC-dependent, we need to handle it 137 */ 138 #define __uart_getreg(bas, reg) \ 139 bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg)) 140 #define __uart_setreg(bas, reg, value) \ 141 bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value) 142 143 /* 144 * Low-level UART interface. 145 */ 146 static int uart_pl011_probe(struct uart_bas *bas); 147 static void uart_pl011_init(struct uart_bas *bas, int, int, int, int); 148 static void uart_pl011_term(struct uart_bas *bas); 149 static void uart_pl011_putc(struct uart_bas *bas, int); 150 static int uart_pl011_rxready(struct uart_bas *bas); 151 static int uart_pl011_getc(struct uart_bas *bas, struct mtx *); 152 153 static struct uart_ops uart_pl011_ops = { 154 .probe = uart_pl011_probe, 155 .init = uart_pl011_init, 156 .term = uart_pl011_term, 157 .putc = uart_pl011_putc, 158 .rxready = uart_pl011_rxready, 159 .getc = uart_pl011_getc, 160 }; 161 162 static int 163 uart_pl011_probe(struct uart_bas *bas) 164 { 165 166 return (0); 167 } 168 169 static void 170 uart_pl011_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 171 int parity) 172 { 173 uint32_t ctrl, line; 174 uint32_t baud; 175 176 /* 177 * Zero all settings to make sure 178 * UART is disabled and not configured 179 */ 180 ctrl = line = 0x0; 181 __uart_setreg(bas, UART_CR, ctrl); 182 183 /* As we know UART is disabled we may setup the line */ 184 switch (databits) { 185 case 7: 186 line |= LCR_H_WLEN7; 187 break; 188 case 6: 189 line |= LCR_H_WLEN6; 190 break; 191 case 8: 192 default: 193 line |= LCR_H_WLEN8; 194 break; 195 } 196 197 if (stopbits == 2) 198 line |= LCR_H_STP2; 199 else 200 line &= ~LCR_H_STP2; 201 202 if (parity) 203 line |= LCR_H_PEN; 204 else 205 line &= ~LCR_H_PEN; 206 line |= LCR_H_FEN; 207 208 /* Configure the rest */ 209 ctrl |= (CR_RXE | CR_TXE | CR_UARTEN); 210 211 if (bas->rclk != 0 && baudrate != 0) { 212 baud = bas->rclk * 4 / baudrate; 213 __uart_setreg(bas, UART_IBRD, ((uint32_t)(baud >> 6)) & IBRD_BDIVINT); 214 __uart_setreg(bas, UART_FBRD, (uint32_t)(baud & 0x3F) & FBRD_BDIVFRAC); 215 } 216 217 /* Add config. to line before reenabling UART */ 218 __uart_setreg(bas, UART_LCR_H, (__uart_getreg(bas, UART_LCR_H) & 219 ~0xff) | line); 220 221 /* Set rx and tx fifo levels. */ 222 __uart_setreg(bas, UART_IFLS, FIFO_IFLS_BITS); 223 224 __uart_setreg(bas, UART_CR, ctrl); 225 } 226 227 static void 228 uart_pl011_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 229 int parity) 230 { 231 /* Mask all interrupts */ 232 __uart_setreg(bas, UART_IMSC, __uart_getreg(bas, UART_IMSC) & 233 ~IMSC_MASK_ALL); 234 235 uart_pl011_param(bas, baudrate, databits, stopbits, parity); 236 } 237 238 static void 239 uart_pl011_term(struct uart_bas *bas) 240 { 241 } 242 243 static void 244 uart_pl011_putc(struct uart_bas *bas, int c) 245 { 246 247 /* Wait when TX FIFO full. Push character otherwise. */ 248 while (__uart_getreg(bas, UART_FR) & FR_TXFF) 249 ; 250 __uart_setreg(bas, UART_DR, c & 0xff); 251 } 252 253 static int 254 uart_pl011_rxready(struct uart_bas *bas) 255 { 256 257 return !(__uart_getreg(bas, UART_FR) & FR_RXFE); 258 } 259 260 static int 261 uart_pl011_getc(struct uart_bas *bas, struct mtx *hwmtx) 262 { 263 int c; 264 265 while (!uart_pl011_rxready(bas)) 266 ; 267 c = __uart_getreg(bas, UART_DR) & 0xff; 268 269 return (c); 270 } 271 272 /* 273 * High-level UART interface. 274 */ 275 struct uart_pl011_softc { 276 struct uart_softc base; 277 uint16_t imsc; /* Interrupt mask */ 278 }; 279 280 static int uart_pl011_bus_attach(struct uart_softc *); 281 static int uart_pl011_bus_detach(struct uart_softc *); 282 static int uart_pl011_bus_flush(struct uart_softc *, int); 283 static int uart_pl011_bus_getsig(struct uart_softc *); 284 static int uart_pl011_bus_ioctl(struct uart_softc *, int, intptr_t); 285 static int uart_pl011_bus_ipend(struct uart_softc *); 286 static int uart_pl011_bus_param(struct uart_softc *, int, int, int, int); 287 static int uart_pl011_bus_probe(struct uart_softc *); 288 static int uart_pl011_bus_receive(struct uart_softc *); 289 static int uart_pl011_bus_setsig(struct uart_softc *, int); 290 static int uart_pl011_bus_transmit(struct uart_softc *); 291 static void uart_pl011_bus_grab(struct uart_softc *); 292 static void uart_pl011_bus_ungrab(struct uart_softc *); 293 294 static kobj_method_t uart_pl011_methods[] = { 295 KOBJMETHOD(uart_attach, uart_pl011_bus_attach), 296 KOBJMETHOD(uart_detach, uart_pl011_bus_detach), 297 KOBJMETHOD(uart_flush, uart_pl011_bus_flush), 298 KOBJMETHOD(uart_getsig, uart_pl011_bus_getsig), 299 KOBJMETHOD(uart_ioctl, uart_pl011_bus_ioctl), 300 KOBJMETHOD(uart_ipend, uart_pl011_bus_ipend), 301 KOBJMETHOD(uart_param, uart_pl011_bus_param), 302 KOBJMETHOD(uart_probe, uart_pl011_bus_probe), 303 KOBJMETHOD(uart_receive, uart_pl011_bus_receive), 304 KOBJMETHOD(uart_setsig, uart_pl011_bus_setsig), 305 KOBJMETHOD(uart_transmit, uart_pl011_bus_transmit), 306 KOBJMETHOD(uart_grab, uart_pl011_bus_grab), 307 KOBJMETHOD(uart_ungrab, uart_pl011_bus_ungrab), 308 309 { 0, 0 } 310 }; 311 312 static struct uart_class uart_pl011_class = { 313 "uart_pl011", 314 uart_pl011_methods, 315 sizeof(struct uart_pl011_softc), 316 .uc_ops = &uart_pl011_ops, 317 .uc_range = 0x48, 318 .uc_rclk = 0, 319 .uc_rshift = 2 320 }; 321 322 323 #ifdef FDT 324 static struct ofw_compat_data compat_data[] = { 325 {"arm,pl011", (uintptr_t)&uart_pl011_class}, 326 {NULL, (uintptr_t)NULL}, 327 }; 328 UART_FDT_CLASS_AND_DEVICE(compat_data); 329 #endif 330 331 #ifdef DEV_ACPI 332 static struct acpi_uart_compat_data acpi_compat_data[] = { 333 {"ARMH0011", &uart_pl011_class, ACPI_DBG2_ARM_PL011}, 334 {NULL, NULL, 0}, 335 }; 336 UART_ACPI_CLASS_AND_DEVICE(acpi_compat_data); 337 #endif 338 339 static int 340 uart_pl011_bus_attach(struct uart_softc *sc) 341 { 342 struct uart_pl011_softc *psc; 343 struct uart_bas *bas; 344 345 psc = (struct uart_pl011_softc *)sc; 346 bas = &sc->sc_bas; 347 348 /* Enable interrupts */ 349 psc->imsc = (UART_RXREADY | RIS_RTIM | UART_TXEMPTY); 350 __uart_setreg(bas, UART_IMSC, psc->imsc); 351 352 /* Clear interrupts */ 353 __uart_setreg(bas, UART_ICR, IMSC_MASK_ALL); 354 355 return (0); 356 } 357 358 static int 359 uart_pl011_bus_detach(struct uart_softc *sc) 360 { 361 362 return (0); 363 } 364 365 static int 366 uart_pl011_bus_flush(struct uart_softc *sc, int what) 367 { 368 369 return (0); 370 } 371 372 static int 373 uart_pl011_bus_getsig(struct uart_softc *sc) 374 { 375 376 return (0); 377 } 378 379 static int 380 uart_pl011_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 381 { 382 struct uart_bas *bas; 383 int error; 384 385 bas = &sc->sc_bas; 386 error = 0; 387 uart_lock(sc->sc_hwmtx); 388 switch (request) { 389 case UART_IOCTL_BREAK: 390 break; 391 case UART_IOCTL_BAUD: 392 *(int*)data = 115200; 393 break; 394 default: 395 error = EINVAL; 396 break; 397 } 398 uart_unlock(sc->sc_hwmtx); 399 400 return (error); 401 } 402 403 static int 404 uart_pl011_bus_ipend(struct uart_softc *sc) 405 { 406 struct uart_pl011_softc *psc; 407 struct uart_bas *bas; 408 uint32_t ints; 409 int ipend; 410 411 psc = (struct uart_pl011_softc *)sc; 412 bas = &sc->sc_bas; 413 414 uart_lock(sc->sc_hwmtx); 415 ints = __uart_getreg(bas, UART_MIS); 416 ipend = 0; 417 418 if (ints & (UART_RXREADY | RIS_RTIM)) 419 ipend |= SER_INT_RXREADY; 420 if (ints & RIS_BE) 421 ipend |= SER_INT_BREAK; 422 if (ints & RIS_OE) 423 ipend |= SER_INT_OVERRUN; 424 if (ints & UART_TXEMPTY) { 425 if (sc->sc_txbusy) 426 ipend |= SER_INT_TXIDLE; 427 428 /* Disable TX interrupt */ 429 __uart_setreg(bas, UART_IMSC, psc->imsc & ~UART_TXEMPTY); 430 } 431 432 uart_unlock(sc->sc_hwmtx); 433 434 return (ipend); 435 } 436 437 static int 438 uart_pl011_bus_param(struct uart_softc *sc, int baudrate, int databits, 439 int stopbits, int parity) 440 { 441 442 uart_lock(sc->sc_hwmtx); 443 uart_pl011_param(&sc->sc_bas, baudrate, databits, stopbits, parity); 444 uart_unlock(sc->sc_hwmtx); 445 446 return (0); 447 } 448 449 static int 450 uart_pl011_bus_probe(struct uart_softc *sc) 451 { 452 uint8_t hwrev; 453 #ifdef FDT 454 pcell_t node; 455 uint32_t periphid; 456 457 /* 458 * The FIFO sizes vary depending on hardware; rev 2 and below have 16 459 * byte FIFOs, rev 3 and up are 32 byte. The hardware rev is in the 460 * primecell periphid register, but we get a bit of drama, as always, 461 * with the bcm2835 (rpi), which claims to be rev 3, but has 16 byte 462 * FIFOs. We check for both the old freebsd-historic and the proper 463 * bindings-defined compatible strings for bcm2835, and also check the 464 * workaround the linux drivers use for rpi3, which is to override the 465 * primecell periphid register value with a property. 466 */ 467 if (ofw_bus_is_compatible(sc->sc_dev, "brcm,bcm2835-pl011") || 468 ofw_bus_is_compatible(sc->sc_dev, "broadcom,bcm2835-uart")) { 469 hwrev = 2; 470 } else { 471 node = ofw_bus_get_node(sc->sc_dev); 472 if (OF_getencprop(node, "arm,primecell-periphid", &periphid, 473 sizeof(periphid)) > 0) { 474 hwrev = (periphid >> 20) & 0x0f; 475 } else { 476 hwrev = __uart_getreg(&sc->sc_bas, UART_PIDREG_2) >> 4; 477 } 478 } 479 #else 480 hwrev = __uart_getreg(&sc->sc_bas, UART_PIDREG_2) >> 4; 481 #endif 482 if (hwrev <= 2) { 483 sc->sc_rxfifosz = FIFO_RX_SIZE_R2; 484 sc->sc_txfifosz = FIFO_TX_SIZE_R2; 485 } else { 486 sc->sc_rxfifosz = FIFO_RX_SIZE_R3; 487 sc->sc_txfifosz = FIFO_TX_SIZE_R3; 488 } 489 490 device_set_desc(sc->sc_dev, "PrimeCell UART (PL011)"); 491 492 return (0); 493 } 494 495 static int 496 uart_pl011_bus_receive(struct uart_softc *sc) 497 { 498 struct uart_bas *bas; 499 uint32_t ints, xc; 500 int rx; 501 502 bas = &sc->sc_bas; 503 uart_lock(sc->sc_hwmtx); 504 505 for (;;) { 506 ints = __uart_getreg(bas, UART_FR); 507 if (ints & FR_RXFE) 508 break; 509 if (uart_rx_full(sc)) { 510 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 511 break; 512 } 513 514 xc = __uart_getreg(bas, UART_DR); 515 rx = xc & 0xff; 516 517 if (xc & DR_FE) 518 rx |= UART_STAT_FRAMERR; 519 if (xc & DR_PE) 520 rx |= UART_STAT_PARERR; 521 522 uart_rx_put(sc, rx); 523 } 524 525 uart_unlock(sc->sc_hwmtx); 526 527 return (0); 528 } 529 530 static int 531 uart_pl011_bus_setsig(struct uart_softc *sc, int sig) 532 { 533 534 return (0); 535 } 536 537 static int 538 uart_pl011_bus_transmit(struct uart_softc *sc) 539 { 540 struct uart_pl011_softc *psc; 541 struct uart_bas *bas; 542 int i; 543 544 psc = (struct uart_pl011_softc *)sc; 545 bas = &sc->sc_bas; 546 uart_lock(sc->sc_hwmtx); 547 548 for (i = 0; i < sc->sc_txdatasz; i++) { 549 __uart_setreg(bas, UART_DR, sc->sc_txbuf[i]); 550 uart_barrier(bas); 551 } 552 553 /* Mark busy and enable TX interrupt */ 554 sc->sc_txbusy = 1; 555 __uart_setreg(bas, UART_IMSC, psc->imsc); 556 557 uart_unlock(sc->sc_hwmtx); 558 559 return (0); 560 } 561 562 static void 563 uart_pl011_bus_grab(struct uart_softc *sc) 564 { 565 struct uart_pl011_softc *psc; 566 struct uart_bas *bas; 567 568 psc = (struct uart_pl011_softc *)sc; 569 bas = &sc->sc_bas; 570 571 /* Disable interrupts on switch to polling */ 572 uart_lock(sc->sc_hwmtx); 573 __uart_setreg(bas, UART_IMSC, psc->imsc & ~IMSC_MASK_ALL); 574 uart_unlock(sc->sc_hwmtx); 575 } 576 577 static void 578 uart_pl011_bus_ungrab(struct uart_softc *sc) 579 { 580 struct uart_pl011_softc *psc; 581 struct uart_bas *bas; 582 583 psc = (struct uart_pl011_softc *)sc; 584 bas = &sc->sc_bas; 585 586 /* Switch to using interrupts while not grabbed */ 587 uart_lock(sc->sc_hwmtx); 588 __uart_setreg(bas, UART_IMSC, psc->imsc); 589 uart_unlock(sc->sc_hwmtx); 590 } 591