1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2012 Semihalf. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_acpi.h" 30 #include "opt_platform.h" 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/bus.h> 36 37 #include <machine/bus.h> 38 #include <machine/machdep.h> 39 40 #include <dev/uart/uart.h> 41 #include <dev/uart/uart_cpu.h> 42 #ifdef FDT 43 #include <dev/uart/uart_cpu_fdt.h> 44 #include <dev/ofw/ofw_bus.h> 45 #endif 46 #include <dev/uart/uart_bus.h> 47 #include "uart_if.h" 48 49 #ifdef DEV_ACPI 50 #include <dev/uart/uart_cpu_acpi.h> 51 #include <contrib/dev/acpica/include/acpi.h> 52 #include <contrib/dev/acpica/include/accommon.h> 53 #include <contrib/dev/acpica/include/actables.h> 54 #endif 55 56 #include <sys/kdb.h> 57 58 #ifdef __aarch64__ 59 #define IS_FDT (arm64_bus_method == ARM64_BUS_FDT) 60 #elif defined(FDT) 61 #define IS_FDT 1 62 #else 63 #error Unsupported configuration 64 #endif 65 66 /* PL011 UART registers and masks*/ 67 #define UART_DR 0x00 /* Data register */ 68 #define DR_FE (1 << 8) /* Framing error */ 69 #define DR_PE (1 << 9) /* Parity error */ 70 #define DR_BE (1 << 10) /* Break error */ 71 #define DR_OE (1 << 11) /* Overrun error */ 72 73 #define UART_FR 0x06 /* Flag register */ 74 #define FR_RXFE (1 << 4) /* Receive FIFO/reg empty */ 75 #define FR_TXFF (1 << 5) /* Transmit FIFO/reg full */ 76 #define FR_RXFF (1 << 6) /* Receive FIFO/reg full */ 77 #define FR_TXFE (1 << 7) /* Transmit FIFO/reg empty */ 78 79 #define UART_IBRD 0x09 /* Integer baud rate register */ 80 #define IBRD_BDIVINT 0xffff /* Significant part of int. divisor value */ 81 82 #define UART_FBRD 0x0a /* Fractional baud rate register */ 83 #define FBRD_BDIVFRAC 0x3f /* Significant part of frac. divisor value */ 84 85 #define UART_LCR_H 0x0b /* Line control register */ 86 #define LCR_H_WLEN8 (0x3 << 5) 87 #define LCR_H_WLEN7 (0x2 << 5) 88 #define LCR_H_WLEN6 (0x1 << 5) 89 #define LCR_H_FEN (1 << 4) /* FIFO mode enable */ 90 #define LCR_H_STP2 (1 << 3) /* 2 stop frames at the end */ 91 #define LCR_H_EPS (1 << 2) /* Even parity select */ 92 #define LCR_H_PEN (1 << 1) /* Parity enable */ 93 94 #define UART_CR 0x0c /* Control register */ 95 #define CR_RXE (1 << 9) /* Receive enable */ 96 #define CR_TXE (1 << 8) /* Transmit enable */ 97 #define CR_UARTEN (1 << 0) /* UART enable */ 98 99 #define UART_IFLS 0x0d /* FIFO level select register */ 100 #define IFLS_RX_SHIFT 3 /* RX level in bits [5:3] */ 101 #define IFLS_TX_SHIFT 0 /* TX level in bits [2:0] */ 102 #define IFLS_MASK 0x07 /* RX/TX level is 3 bits */ 103 #define IFLS_LVL_1_8th 0 /* Interrupt at 1/8 full */ 104 #define IFLS_LVL_2_8th 1 /* Interrupt at 1/4 full */ 105 #define IFLS_LVL_4_8th 2 /* Interrupt at 1/2 full */ 106 #define IFLS_LVL_6_8th 3 /* Interrupt at 3/4 full */ 107 #define IFLS_LVL_7_8th 4 /* Interrupt at 7/8 full */ 108 109 #define UART_IMSC 0x0e /* Interrupt mask set/clear register */ 110 #define IMSC_MASK_ALL 0x7ff /* Mask all interrupts */ 111 112 #define UART_RIS 0x0f /* Raw interrupt status register */ 113 #define UART_RXREADY (1 << 4) /* RX buffer full */ 114 #define UART_TXEMPTY (1 << 5) /* TX buffer empty */ 115 #define RIS_RTIM (1 << 6) /* Receive timeout */ 116 #define RIS_FE (1 << 7) /* Framing error interrupt status */ 117 #define RIS_PE (1 << 8) /* Parity error interrupt status */ 118 #define RIS_BE (1 << 9) /* Break error interrupt status */ 119 #define RIS_OE (1 << 10) /* Overrun interrupt status */ 120 121 #define UART_MIS 0x10 /* Masked interrupt status register */ 122 #define UART_ICR 0x11 /* Interrupt clear register */ 123 124 #define UART_PIDREG_0 0x3f8 /* Peripheral ID register 0 */ 125 #define UART_PIDREG_1 0x3f9 /* Peripheral ID register 1 */ 126 #define UART_PIDREG_2 0x3fa /* Peripheral ID register 2 */ 127 #define UART_PIDREG_3 0x3fb /* Peripheral ID register 3 */ 128 129 /* 130 * The hardware FIFOs are 16 bytes each on rev 2 and earlier hardware, 32 bytes 131 * on rev 3 and later. We configure them to interrupt when 3/4 full/empty. For 132 * RX we set the size to the full hardware capacity so that the uart core 133 * allocates enough buffer space to hold a complete fifo full of incoming data. 134 * For TX, we need to limit the size to the capacity we know will be available 135 * when the interrupt occurs; uart_core will feed exactly that many bytes to 136 * uart_pl011_bus_transmit() which must consume them all. 137 */ 138 #define FIFO_RX_SIZE_R2 16 139 #define FIFO_TX_SIZE_R2 12 140 #define FIFO_RX_SIZE_R3 32 141 #define FIFO_TX_SIZE_R3 24 142 #define FIFO_IFLS_BITS ((IFLS_LVL_6_8th << IFLS_RX_SHIFT) | (IFLS_LVL_2_8th)) 143 144 /* 145 * FIXME: actual register size is SoC-dependent, we need to handle it 146 */ 147 #define __uart_getreg(bas, reg) \ 148 bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg)) 149 #define __uart_setreg(bas, reg, value) \ 150 bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value) 151 152 /* 153 * Low-level UART interface. 154 */ 155 static int uart_pl011_probe(struct uart_bas *bas); 156 static void uart_pl011_init(struct uart_bas *bas, int, int, int, int); 157 static void uart_pl011_term(struct uart_bas *bas); 158 static void uart_pl011_putc(struct uart_bas *bas, int); 159 static int uart_pl011_rxready(struct uart_bas *bas); 160 static int uart_pl011_getc(struct uart_bas *bas, struct mtx *); 161 162 static struct uart_ops uart_pl011_ops = { 163 .probe = uart_pl011_probe, 164 .init = uart_pl011_init, 165 .term = uart_pl011_term, 166 .putc = uart_pl011_putc, 167 .rxready = uart_pl011_rxready, 168 .getc = uart_pl011_getc, 169 }; 170 171 static int 172 uart_pl011_probe(struct uart_bas *bas) 173 { 174 175 return (0); 176 } 177 178 static void 179 uart_pl011_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 180 int parity) 181 { 182 uint32_t ctrl, line; 183 uint32_t baud; 184 185 /* 186 * Zero all settings to make sure 187 * UART is disabled and not configured 188 */ 189 ctrl = line = 0x0; 190 __uart_setreg(bas, UART_CR, ctrl); 191 192 /* As we know UART is disabled we may setup the line */ 193 switch (databits) { 194 case 7: 195 line |= LCR_H_WLEN7; 196 break; 197 case 6: 198 line |= LCR_H_WLEN6; 199 break; 200 case 8: 201 default: 202 line |= LCR_H_WLEN8; 203 break; 204 } 205 206 if (stopbits == 2) 207 line |= LCR_H_STP2; 208 else 209 line &= ~LCR_H_STP2; 210 211 if (parity) 212 line |= LCR_H_PEN; 213 else 214 line &= ~LCR_H_PEN; 215 line |= LCR_H_FEN; 216 217 /* Configure the rest */ 218 ctrl |= (CR_RXE | CR_TXE | CR_UARTEN); 219 220 if (bas->rclk != 0 && baudrate != 0) { 221 baud = bas->rclk * 4 / baudrate; 222 __uart_setreg(bas, UART_IBRD, ((uint32_t)(baud >> 6)) & IBRD_BDIVINT); 223 __uart_setreg(bas, UART_FBRD, (uint32_t)(baud & 0x3F) & FBRD_BDIVFRAC); 224 } 225 226 /* Add config. to line before reenabling UART */ 227 __uart_setreg(bas, UART_LCR_H, (__uart_getreg(bas, UART_LCR_H) & 228 ~0xff) | line); 229 230 /* Set rx and tx fifo levels. */ 231 __uart_setreg(bas, UART_IFLS, FIFO_IFLS_BITS); 232 233 __uart_setreg(bas, UART_CR, ctrl); 234 } 235 236 static void 237 uart_pl011_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 238 int parity) 239 { 240 /* Mask all interrupts */ 241 __uart_setreg(bas, UART_IMSC, __uart_getreg(bas, UART_IMSC) & 242 ~IMSC_MASK_ALL); 243 244 uart_pl011_param(bas, baudrate, databits, stopbits, parity); 245 } 246 247 static void 248 uart_pl011_term(struct uart_bas *bas) 249 { 250 } 251 252 static void 253 uart_pl011_putc(struct uart_bas *bas, int c) 254 { 255 256 /* Wait when TX FIFO full. Push character otherwise. */ 257 while (__uart_getreg(bas, UART_FR) & FR_TXFF) 258 ; 259 __uart_setreg(bas, UART_DR, c & 0xff); 260 } 261 262 static int 263 uart_pl011_rxready(struct uart_bas *bas) 264 { 265 266 return !(__uart_getreg(bas, UART_FR) & FR_RXFE); 267 } 268 269 static int 270 uart_pl011_getc(struct uart_bas *bas, struct mtx *hwmtx) 271 { 272 int c; 273 274 while (!uart_pl011_rxready(bas)) 275 ; 276 c = __uart_getreg(bas, UART_DR) & 0xff; 277 278 return (c); 279 } 280 281 /* 282 * High-level UART interface. 283 */ 284 struct uart_pl011_softc { 285 struct uart_softc base; 286 uint16_t imsc; /* Interrupt mask */ 287 }; 288 289 static int uart_pl011_bus_attach(struct uart_softc *); 290 static int uart_pl011_bus_detach(struct uart_softc *); 291 static int uart_pl011_bus_flush(struct uart_softc *, int); 292 static int uart_pl011_bus_getsig(struct uart_softc *); 293 static int uart_pl011_bus_ioctl(struct uart_softc *, int, intptr_t); 294 static int uart_pl011_bus_ipend(struct uart_softc *); 295 static int uart_pl011_bus_param(struct uart_softc *, int, int, int, int); 296 static int uart_pl011_bus_probe(struct uart_softc *); 297 static int uart_pl011_bus_receive(struct uart_softc *); 298 static int uart_pl011_bus_setsig(struct uart_softc *, int); 299 static int uart_pl011_bus_transmit(struct uart_softc *); 300 static void uart_pl011_bus_grab(struct uart_softc *); 301 static void uart_pl011_bus_ungrab(struct uart_softc *); 302 303 static kobj_method_t uart_pl011_methods[] = { 304 KOBJMETHOD(uart_attach, uart_pl011_bus_attach), 305 KOBJMETHOD(uart_detach, uart_pl011_bus_detach), 306 KOBJMETHOD(uart_flush, uart_pl011_bus_flush), 307 KOBJMETHOD(uart_getsig, uart_pl011_bus_getsig), 308 KOBJMETHOD(uart_ioctl, uart_pl011_bus_ioctl), 309 KOBJMETHOD(uart_ipend, uart_pl011_bus_ipend), 310 KOBJMETHOD(uart_param, uart_pl011_bus_param), 311 KOBJMETHOD(uart_probe, uart_pl011_bus_probe), 312 KOBJMETHOD(uart_receive, uart_pl011_bus_receive), 313 KOBJMETHOD(uart_setsig, uart_pl011_bus_setsig), 314 KOBJMETHOD(uart_transmit, uart_pl011_bus_transmit), 315 KOBJMETHOD(uart_grab, uart_pl011_bus_grab), 316 KOBJMETHOD(uart_ungrab, uart_pl011_bus_ungrab), 317 { 0, 0 } 318 }; 319 320 static struct uart_class uart_pl011_class = { 321 "uart_pl011", 322 uart_pl011_methods, 323 sizeof(struct uart_pl011_softc), 324 .uc_ops = &uart_pl011_ops, 325 .uc_range = 0x48, 326 .uc_rclk = 0, 327 .uc_rshift = 2 328 }; 329 330 #ifdef FDT 331 static struct ofw_compat_data fdt_compat_data[] = { 332 {"arm,pl011", (uintptr_t)&uart_pl011_class}, 333 {NULL, (uintptr_t)NULL}, 334 }; 335 UART_FDT_CLASS_AND_DEVICE(fdt_compat_data); 336 #endif 337 338 #ifdef DEV_ACPI 339 static struct acpi_uart_compat_data acpi_compat_data[] = { 340 {"ARMH0011", &uart_pl011_class, ACPI_DBG2_ARM_PL011, 2, 0, 0, UART_F_IGNORE_SPCR_REGSHFT, "uart pl011"}, 341 {"ARMHB000", &uart_pl011_class, ACPI_DBG2_ARM_SBSA_GENERIC, 2, 0, 0, UART_F_IGNORE_SPCR_REGSHFT, "uart pl011"}, 342 {"ARMHB000", &uart_pl011_class, ACPI_DBG2_ARM_SBSA_32BIT, 2, 0, 0, UART_F_IGNORE_SPCR_REGSHFT, "uart pl011"}, 343 {NULL, NULL, 0, 0, 0, 0, 0, NULL}, 344 }; 345 UART_ACPI_CLASS_AND_DEVICE(acpi_compat_data); 346 #endif 347 348 static int 349 uart_pl011_bus_attach(struct uart_softc *sc) 350 { 351 struct uart_pl011_softc *psc; 352 struct uart_bas *bas; 353 354 psc = (struct uart_pl011_softc *)sc; 355 bas = &sc->sc_bas; 356 357 /* Enable interrupts */ 358 psc->imsc = (UART_RXREADY | RIS_RTIM | UART_TXEMPTY); 359 __uart_setreg(bas, UART_IMSC, psc->imsc); 360 361 /* Clear interrupts */ 362 __uart_setreg(bas, UART_ICR, IMSC_MASK_ALL); 363 364 return (0); 365 } 366 367 static int 368 uart_pl011_bus_detach(struct uart_softc *sc) 369 { 370 371 return (0); 372 } 373 374 static int 375 uart_pl011_bus_flush(struct uart_softc *sc, int what) 376 { 377 378 return (0); 379 } 380 381 static int 382 uart_pl011_bus_getsig(struct uart_softc *sc) 383 { 384 385 return (0); 386 } 387 388 static int 389 uart_pl011_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 390 { 391 int error; 392 393 error = 0; 394 uart_lock(sc->sc_hwmtx); 395 switch (request) { 396 case UART_IOCTL_BREAK: 397 break; 398 case UART_IOCTL_BAUD: 399 *(int*)data = 115200; 400 break; 401 default: 402 error = EINVAL; 403 break; 404 } 405 uart_unlock(sc->sc_hwmtx); 406 407 return (error); 408 } 409 410 static int 411 uart_pl011_bus_ipend(struct uart_softc *sc) 412 { 413 struct uart_pl011_softc *psc; 414 struct uart_bas *bas; 415 uint32_t ints; 416 int ipend; 417 418 psc = (struct uart_pl011_softc *)sc; 419 bas = &sc->sc_bas; 420 421 uart_lock(sc->sc_hwmtx); 422 ints = __uart_getreg(bas, UART_MIS); 423 ipend = 0; 424 425 if (ints & (UART_RXREADY | RIS_RTIM)) 426 ipend |= SER_INT_RXREADY; 427 if (ints & RIS_BE) 428 ipend |= SER_INT_BREAK; 429 if (ints & RIS_OE) 430 ipend |= SER_INT_OVERRUN; 431 if (ints & UART_TXEMPTY) { 432 if (sc->sc_txbusy) 433 ipend |= SER_INT_TXIDLE; 434 435 /* Disable TX interrupt */ 436 __uart_setreg(bas, UART_IMSC, psc->imsc & ~UART_TXEMPTY); 437 } 438 439 uart_unlock(sc->sc_hwmtx); 440 441 return (ipend); 442 } 443 444 static int 445 uart_pl011_bus_param(struct uart_softc *sc, int baudrate, int databits, 446 int stopbits, int parity) 447 { 448 449 uart_lock(sc->sc_hwmtx); 450 uart_pl011_param(&sc->sc_bas, baudrate, databits, stopbits, parity); 451 uart_unlock(sc->sc_hwmtx); 452 453 return (0); 454 } 455 456 #ifdef FDT 457 static int 458 uart_pl011_bus_hwrev_fdt(struct uart_softc *sc) 459 { 460 pcell_t node; 461 uint32_t periphid; 462 463 /* 464 * The FIFO sizes vary depending on hardware; rev 2 and below have 16 465 * byte FIFOs, rev 3 and up are 32 byte. The hardware rev is in the 466 * primecell periphid register, but we get a bit of drama, as always, 467 * with the bcm2835 (rpi), which claims to be rev 3, but has 16 byte 468 * FIFOs. We check for both the old freebsd-historic and the proper 469 * bindings-defined compatible strings for bcm2835, and also check the 470 * workaround the linux drivers use for rpi3, which is to override the 471 * primecell periphid register value with a property. 472 */ 473 if (ofw_bus_is_compatible(sc->sc_dev, "brcm,bcm2835-pl011") || 474 ofw_bus_is_compatible(sc->sc_dev, "broadcom,bcm2835-uart")) { 475 return (2); 476 } else { 477 node = ofw_bus_get_node(sc->sc_dev); 478 if (OF_getencprop(node, "arm,primecell-periphid", &periphid, 479 sizeof(periphid)) > 0) { 480 return ((periphid >> 20) & 0x0f); 481 } 482 } 483 484 return (-1); 485 } 486 #endif 487 488 static int 489 uart_pl011_bus_probe(struct uart_softc *sc) 490 { 491 int hwrev; 492 493 hwrev = -1; 494 #ifdef FDT 495 if (IS_FDT) 496 hwrev = uart_pl011_bus_hwrev_fdt(sc); 497 #endif 498 if (hwrev < 0) 499 hwrev = __uart_getreg(&sc->sc_bas, UART_PIDREG_2) >> 4; 500 501 if (hwrev <= 2) { 502 sc->sc_rxfifosz = FIFO_RX_SIZE_R2; 503 sc->sc_txfifosz = FIFO_TX_SIZE_R2; 504 } else { 505 sc->sc_rxfifosz = FIFO_RX_SIZE_R3; 506 sc->sc_txfifosz = FIFO_TX_SIZE_R3; 507 } 508 509 device_set_desc(sc->sc_dev, "PrimeCell UART (PL011)"); 510 511 return (0); 512 } 513 514 static int 515 uart_pl011_bus_receive(struct uart_softc *sc) 516 { 517 struct uart_bas *bas; 518 uint32_t ints, xc; 519 int rx; 520 521 bas = &sc->sc_bas; 522 uart_lock(sc->sc_hwmtx); 523 524 for (;;) { 525 ints = __uart_getreg(bas, UART_FR); 526 if (ints & FR_RXFE) 527 break; 528 if (uart_rx_full(sc)) { 529 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 530 break; 531 } 532 533 xc = __uart_getreg(bas, UART_DR); 534 rx = xc & 0xff; 535 536 if (xc & DR_FE) 537 rx |= UART_STAT_FRAMERR; 538 if (xc & DR_PE) 539 rx |= UART_STAT_PARERR; 540 541 uart_rx_put(sc, rx); 542 } 543 544 uart_unlock(sc->sc_hwmtx); 545 546 return (0); 547 } 548 549 static int 550 uart_pl011_bus_setsig(struct uart_softc *sc, int sig) 551 { 552 553 return (0); 554 } 555 556 static int 557 uart_pl011_bus_transmit(struct uart_softc *sc) 558 { 559 struct uart_pl011_softc *psc; 560 struct uart_bas *bas; 561 int i; 562 563 psc = (struct uart_pl011_softc *)sc; 564 bas = &sc->sc_bas; 565 uart_lock(sc->sc_hwmtx); 566 567 for (i = 0; i < sc->sc_txdatasz; i++) { 568 __uart_setreg(bas, UART_DR, sc->sc_txbuf[i]); 569 uart_barrier(bas); 570 } 571 572 /* Mark busy and enable TX interrupt */ 573 sc->sc_txbusy = 1; 574 __uart_setreg(bas, UART_IMSC, psc->imsc); 575 576 uart_unlock(sc->sc_hwmtx); 577 578 return (0); 579 } 580 581 static void 582 uart_pl011_bus_grab(struct uart_softc *sc) 583 { 584 struct uart_pl011_softc *psc; 585 struct uart_bas *bas; 586 587 psc = (struct uart_pl011_softc *)sc; 588 bas = &sc->sc_bas; 589 590 /* Disable interrupts on switch to polling */ 591 uart_lock(sc->sc_hwmtx); 592 __uart_setreg(bas, UART_IMSC, psc->imsc & ~IMSC_MASK_ALL); 593 uart_unlock(sc->sc_hwmtx); 594 } 595 596 static void 597 uart_pl011_bus_ungrab(struct uart_softc *sc) 598 { 599 struct uart_pl011_softc *psc; 600 struct uart_bas *bas; 601 602 psc = (struct uart_pl011_softc *)sc; 603 bas = &sc->sc_bas; 604 605 /* Switch to using interrupts while not grabbed */ 606 uart_lock(sc->sc_hwmtx); 607 __uart_setreg(bas, UART_IMSC, psc->imsc); 608 uart_unlock(sc->sc_hwmtx); 609 } 610