1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2012 Semihalf. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_acpi.h" 30 #include "opt_platform.h" 31 32 #include <sys/cdefs.h> 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/bus.h> 37 38 #include <machine/bus.h> 39 #include <machine/machdep.h> 40 41 #include <dev/uart/uart.h> 42 #include <dev/uart/uart_cpu.h> 43 #ifdef FDT 44 #include <dev/uart/uart_cpu_fdt.h> 45 #include <dev/ofw/ofw_bus.h> 46 #endif 47 #include <dev/uart/uart_bus.h> 48 #include "uart_if.h" 49 50 #ifdef DEV_ACPI 51 #include <dev/uart/uart_cpu_acpi.h> 52 #include <contrib/dev/acpica/include/acpi.h> 53 #include <contrib/dev/acpica/include/accommon.h> 54 #include <contrib/dev/acpica/include/actables.h> 55 #endif 56 57 #include <sys/kdb.h> 58 59 #ifdef __aarch64__ 60 #define IS_FDT (arm64_bus_method == ARM64_BUS_FDT) 61 #elif defined(FDT) 62 #define IS_FDT 1 63 #else 64 #error Unsupported configuration 65 #endif 66 67 /* PL011 UART registers and masks*/ 68 #define UART_DR 0x00 /* Data register */ 69 #define DR_FE (1 << 8) /* Framing error */ 70 #define DR_PE (1 << 9) /* Parity error */ 71 #define DR_BE (1 << 10) /* Break error */ 72 #define DR_OE (1 << 11) /* Overrun error */ 73 74 #define UART_FR 0x06 /* Flag register */ 75 #define FR_RXFE (1 << 4) /* Receive FIFO/reg empty */ 76 #define FR_TXFF (1 << 5) /* Transmit FIFO/reg full */ 77 #define FR_RXFF (1 << 6) /* Receive FIFO/reg full */ 78 #define FR_TXFE (1 << 7) /* Transmit FIFO/reg empty */ 79 80 #define UART_IBRD 0x09 /* Integer baud rate register */ 81 #define IBRD_BDIVINT 0xffff /* Significant part of int. divisor value */ 82 83 #define UART_FBRD 0x0a /* Fractional baud rate register */ 84 #define FBRD_BDIVFRAC 0x3f /* Significant part of frac. divisor value */ 85 86 #define UART_LCR_H 0x0b /* Line control register */ 87 #define LCR_H_WLEN8 (0x3 << 5) 88 #define LCR_H_WLEN7 (0x2 << 5) 89 #define LCR_H_WLEN6 (0x1 << 5) 90 #define LCR_H_FEN (1 << 4) /* FIFO mode enable */ 91 #define LCR_H_STP2 (1 << 3) /* 2 stop frames at the end */ 92 #define LCR_H_EPS (1 << 2) /* Even parity select */ 93 #define LCR_H_PEN (1 << 1) /* Parity enable */ 94 95 #define UART_CR 0x0c /* Control register */ 96 #define CR_RXE (1 << 9) /* Receive enable */ 97 #define CR_TXE (1 << 8) /* Transmit enable */ 98 #define CR_UARTEN (1 << 0) /* UART enable */ 99 100 #define UART_IFLS 0x0d /* FIFO level select register */ 101 #define IFLS_RX_SHIFT 3 /* RX level in bits [5:3] */ 102 #define IFLS_TX_SHIFT 0 /* TX level in bits [2:0] */ 103 #define IFLS_MASK 0x07 /* RX/TX level is 3 bits */ 104 #define IFLS_LVL_1_8th 0 /* Interrupt at 1/8 full */ 105 #define IFLS_LVL_2_8th 1 /* Interrupt at 1/4 full */ 106 #define IFLS_LVL_4_8th 2 /* Interrupt at 1/2 full */ 107 #define IFLS_LVL_6_8th 3 /* Interrupt at 3/4 full */ 108 #define IFLS_LVL_7_8th 4 /* Interrupt at 7/8 full */ 109 110 #define UART_IMSC 0x0e /* Interrupt mask set/clear register */ 111 #define IMSC_MASK_ALL 0x7ff /* Mask all interrupts */ 112 113 #define UART_RIS 0x0f /* Raw interrupt status register */ 114 #define UART_RXREADY (1 << 4) /* RX buffer full */ 115 #define UART_TXEMPTY (1 << 5) /* TX buffer empty */ 116 #define RIS_RTIM (1 << 6) /* Receive timeout */ 117 #define RIS_FE (1 << 7) /* Framing error interrupt status */ 118 #define RIS_PE (1 << 8) /* Parity error interrupt status */ 119 #define RIS_BE (1 << 9) /* Break error interrupt status */ 120 #define RIS_OE (1 << 10) /* Overrun interrupt status */ 121 122 #define UART_MIS 0x10 /* Masked interrupt status register */ 123 #define UART_ICR 0x11 /* Interrupt clear register */ 124 125 #define UART_PIDREG_0 0x3f8 /* Peripheral ID register 0 */ 126 #define UART_PIDREG_1 0x3f9 /* Peripheral ID register 1 */ 127 #define UART_PIDREG_2 0x3fa /* Peripheral ID register 2 */ 128 #define UART_PIDREG_3 0x3fb /* Peripheral ID register 3 */ 129 130 /* 131 * The hardware FIFOs are 16 bytes each on rev 2 and earlier hardware, 32 bytes 132 * on rev 3 and later. We configure them to interrupt when 3/4 full/empty. For 133 * RX we set the size to the full hardware capacity so that the uart core 134 * allocates enough buffer space to hold a complete fifo full of incoming data. 135 * For TX, we need to limit the size to the capacity we know will be available 136 * when the interrupt occurs; uart_core will feed exactly that many bytes to 137 * uart_pl011_bus_transmit() which must consume them all. 138 */ 139 #define FIFO_RX_SIZE_R2 16 140 #define FIFO_TX_SIZE_R2 12 141 #define FIFO_RX_SIZE_R3 32 142 #define FIFO_TX_SIZE_R3 24 143 #define FIFO_IFLS_BITS ((IFLS_LVL_6_8th << IFLS_RX_SHIFT) | (IFLS_LVL_2_8th)) 144 145 /* 146 * FIXME: actual register size is SoC-dependent, we need to handle it 147 */ 148 #define __uart_getreg(bas, reg) \ 149 bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg)) 150 #define __uart_setreg(bas, reg, value) \ 151 bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value) 152 153 /* 154 * Low-level UART interface. 155 */ 156 static int uart_pl011_probe(struct uart_bas *bas); 157 static void uart_pl011_init(struct uart_bas *bas, int, int, int, int); 158 static void uart_pl011_term(struct uart_bas *bas); 159 static void uart_pl011_putc(struct uart_bas *bas, int); 160 static int uart_pl011_rxready(struct uart_bas *bas); 161 static int uart_pl011_getc(struct uart_bas *bas, struct mtx *); 162 163 static struct uart_ops uart_pl011_ops = { 164 .probe = uart_pl011_probe, 165 .init = uart_pl011_init, 166 .term = uart_pl011_term, 167 .putc = uart_pl011_putc, 168 .rxready = uart_pl011_rxready, 169 .getc = uart_pl011_getc, 170 }; 171 172 static int 173 uart_pl011_probe(struct uart_bas *bas) 174 { 175 176 return (0); 177 } 178 179 static void 180 uart_pl011_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 181 int parity) 182 { 183 uint32_t ctrl, line; 184 uint32_t baud; 185 186 /* 187 * Zero all settings to make sure 188 * UART is disabled and not configured 189 */ 190 ctrl = line = 0x0; 191 __uart_setreg(bas, UART_CR, ctrl); 192 193 /* As we know UART is disabled we may setup the line */ 194 switch (databits) { 195 case 7: 196 line |= LCR_H_WLEN7; 197 break; 198 case 6: 199 line |= LCR_H_WLEN6; 200 break; 201 case 8: 202 default: 203 line |= LCR_H_WLEN8; 204 break; 205 } 206 207 if (stopbits == 2) 208 line |= LCR_H_STP2; 209 else 210 line &= ~LCR_H_STP2; 211 212 if (parity) 213 line |= LCR_H_PEN; 214 else 215 line &= ~LCR_H_PEN; 216 line |= LCR_H_FEN; 217 218 /* Configure the rest */ 219 ctrl |= (CR_RXE | CR_TXE | CR_UARTEN); 220 221 if (bas->rclk != 0 && baudrate != 0) { 222 baud = bas->rclk * 4 / baudrate; 223 __uart_setreg(bas, UART_IBRD, ((uint32_t)(baud >> 6)) & IBRD_BDIVINT); 224 __uart_setreg(bas, UART_FBRD, (uint32_t)(baud & 0x3F) & FBRD_BDIVFRAC); 225 } 226 227 /* Add config. to line before reenabling UART */ 228 __uart_setreg(bas, UART_LCR_H, (__uart_getreg(bas, UART_LCR_H) & 229 ~0xff) | line); 230 231 /* Set rx and tx fifo levels. */ 232 __uart_setreg(bas, UART_IFLS, FIFO_IFLS_BITS); 233 234 __uart_setreg(bas, UART_CR, ctrl); 235 } 236 237 static void 238 uart_pl011_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 239 int parity) 240 { 241 /* Mask all interrupts */ 242 __uart_setreg(bas, UART_IMSC, __uart_getreg(bas, UART_IMSC) & 243 ~IMSC_MASK_ALL); 244 245 uart_pl011_param(bas, baudrate, databits, stopbits, parity); 246 } 247 248 static void 249 uart_pl011_term(struct uart_bas *bas) 250 { 251 } 252 253 static void 254 uart_pl011_putc(struct uart_bas *bas, int c) 255 { 256 257 /* Wait when TX FIFO full. Push character otherwise. */ 258 while (__uart_getreg(bas, UART_FR) & FR_TXFF) 259 ; 260 __uart_setreg(bas, UART_DR, c & 0xff); 261 } 262 263 static int 264 uart_pl011_rxready(struct uart_bas *bas) 265 { 266 267 return !(__uart_getreg(bas, UART_FR) & FR_RXFE); 268 } 269 270 static int 271 uart_pl011_getc(struct uart_bas *bas, struct mtx *hwmtx) 272 { 273 int c; 274 275 while (!uart_pl011_rxready(bas)) 276 ; 277 c = __uart_getreg(bas, UART_DR) & 0xff; 278 279 return (c); 280 } 281 282 /* 283 * High-level UART interface. 284 */ 285 struct uart_pl011_softc { 286 struct uart_softc base; 287 uint16_t imsc; /* Interrupt mask */ 288 }; 289 290 static int uart_pl011_bus_attach(struct uart_softc *); 291 static int uart_pl011_bus_detach(struct uart_softc *); 292 static int uart_pl011_bus_flush(struct uart_softc *, int); 293 static int uart_pl011_bus_getsig(struct uart_softc *); 294 static int uart_pl011_bus_ioctl(struct uart_softc *, int, intptr_t); 295 static int uart_pl011_bus_ipend(struct uart_softc *); 296 static int uart_pl011_bus_param(struct uart_softc *, int, int, int, int); 297 static int uart_pl011_bus_probe(struct uart_softc *); 298 static int uart_pl011_bus_receive(struct uart_softc *); 299 static int uart_pl011_bus_setsig(struct uart_softc *, int); 300 static int uart_pl011_bus_transmit(struct uart_softc *); 301 static void uart_pl011_bus_grab(struct uart_softc *); 302 static void uart_pl011_bus_ungrab(struct uart_softc *); 303 304 static kobj_method_t uart_pl011_methods[] = { 305 KOBJMETHOD(uart_attach, uart_pl011_bus_attach), 306 KOBJMETHOD(uart_detach, uart_pl011_bus_detach), 307 KOBJMETHOD(uart_flush, uart_pl011_bus_flush), 308 KOBJMETHOD(uart_getsig, uart_pl011_bus_getsig), 309 KOBJMETHOD(uart_ioctl, uart_pl011_bus_ioctl), 310 KOBJMETHOD(uart_ipend, uart_pl011_bus_ipend), 311 KOBJMETHOD(uart_param, uart_pl011_bus_param), 312 KOBJMETHOD(uart_probe, uart_pl011_bus_probe), 313 KOBJMETHOD(uart_receive, uart_pl011_bus_receive), 314 KOBJMETHOD(uart_setsig, uart_pl011_bus_setsig), 315 KOBJMETHOD(uart_transmit, uart_pl011_bus_transmit), 316 KOBJMETHOD(uart_grab, uart_pl011_bus_grab), 317 KOBJMETHOD(uart_ungrab, uart_pl011_bus_ungrab), 318 { 0, 0 } 319 }; 320 321 static struct uart_class uart_pl011_class = { 322 "uart_pl011", 323 uart_pl011_methods, 324 sizeof(struct uart_pl011_softc), 325 .uc_ops = &uart_pl011_ops, 326 .uc_range = 0x48, 327 .uc_rclk = 0, 328 .uc_rshift = 2 329 }; 330 331 #ifdef FDT 332 static struct ofw_compat_data fdt_compat_data[] = { 333 {"arm,pl011", (uintptr_t)&uart_pl011_class}, 334 {NULL, (uintptr_t)NULL}, 335 }; 336 UART_FDT_CLASS_AND_DEVICE(fdt_compat_data); 337 #endif 338 339 #ifdef DEV_ACPI 340 static struct acpi_uart_compat_data acpi_compat_data[] = { 341 {"ARMH0011", &uart_pl011_class, ACPI_DBG2_ARM_PL011, 2, 0, 0, UART_F_IGNORE_SPCR_REGSHFT, "uart pl011"}, 342 {"ARMHB000", &uart_pl011_class, ACPI_DBG2_ARM_SBSA_GENERIC, 2, 0, 0, UART_F_IGNORE_SPCR_REGSHFT, "uart pl011"}, 343 {"ARMHB000", &uart_pl011_class, ACPI_DBG2_ARM_SBSA_32BIT, 2, 0, 0, UART_F_IGNORE_SPCR_REGSHFT, "uart pl011"}, 344 {NULL, NULL, 0, 0, 0, 0, 0, NULL}, 345 }; 346 UART_ACPI_CLASS_AND_DEVICE(acpi_compat_data); 347 #endif 348 349 static int 350 uart_pl011_bus_attach(struct uart_softc *sc) 351 { 352 struct uart_pl011_softc *psc; 353 struct uart_bas *bas; 354 355 psc = (struct uart_pl011_softc *)sc; 356 bas = &sc->sc_bas; 357 358 /* Enable interrupts */ 359 psc->imsc = (UART_RXREADY | RIS_RTIM | UART_TXEMPTY); 360 __uart_setreg(bas, UART_IMSC, psc->imsc); 361 362 /* Clear interrupts */ 363 __uart_setreg(bas, UART_ICR, IMSC_MASK_ALL); 364 365 return (0); 366 } 367 368 static int 369 uart_pl011_bus_detach(struct uart_softc *sc) 370 { 371 372 return (0); 373 } 374 375 static int 376 uart_pl011_bus_flush(struct uart_softc *sc, int what) 377 { 378 379 return (0); 380 } 381 382 static int 383 uart_pl011_bus_getsig(struct uart_softc *sc) 384 { 385 386 return (0); 387 } 388 389 static int 390 uart_pl011_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 391 { 392 int error; 393 394 error = 0; 395 uart_lock(sc->sc_hwmtx); 396 switch (request) { 397 case UART_IOCTL_BREAK: 398 break; 399 case UART_IOCTL_BAUD: 400 *(int*)data = 115200; 401 break; 402 default: 403 error = EINVAL; 404 break; 405 } 406 uart_unlock(sc->sc_hwmtx); 407 408 return (error); 409 } 410 411 static int 412 uart_pl011_bus_ipend(struct uart_softc *sc) 413 { 414 struct uart_pl011_softc *psc; 415 struct uart_bas *bas; 416 uint32_t ints; 417 int ipend; 418 419 psc = (struct uart_pl011_softc *)sc; 420 bas = &sc->sc_bas; 421 422 uart_lock(sc->sc_hwmtx); 423 ints = __uart_getreg(bas, UART_MIS); 424 ipend = 0; 425 426 if (ints & (UART_RXREADY | RIS_RTIM)) 427 ipend |= SER_INT_RXREADY; 428 if (ints & RIS_BE) 429 ipend |= SER_INT_BREAK; 430 if (ints & RIS_OE) 431 ipend |= SER_INT_OVERRUN; 432 if (ints & UART_TXEMPTY) { 433 if (sc->sc_txbusy) 434 ipend |= SER_INT_TXIDLE; 435 436 /* Disable TX interrupt */ 437 __uart_setreg(bas, UART_IMSC, psc->imsc & ~UART_TXEMPTY); 438 } 439 440 uart_unlock(sc->sc_hwmtx); 441 442 return (ipend); 443 } 444 445 static int 446 uart_pl011_bus_param(struct uart_softc *sc, int baudrate, int databits, 447 int stopbits, int parity) 448 { 449 450 uart_lock(sc->sc_hwmtx); 451 uart_pl011_param(&sc->sc_bas, baudrate, databits, stopbits, parity); 452 uart_unlock(sc->sc_hwmtx); 453 454 return (0); 455 } 456 457 #ifdef FDT 458 static int 459 uart_pl011_bus_hwrev_fdt(struct uart_softc *sc) 460 { 461 pcell_t node; 462 uint32_t periphid; 463 464 /* 465 * The FIFO sizes vary depending on hardware; rev 2 and below have 16 466 * byte FIFOs, rev 3 and up are 32 byte. The hardware rev is in the 467 * primecell periphid register, but we get a bit of drama, as always, 468 * with the bcm2835 (rpi), which claims to be rev 3, but has 16 byte 469 * FIFOs. We check for both the old freebsd-historic and the proper 470 * bindings-defined compatible strings for bcm2835, and also check the 471 * workaround the linux drivers use for rpi3, which is to override the 472 * primecell periphid register value with a property. 473 */ 474 if (ofw_bus_is_compatible(sc->sc_dev, "brcm,bcm2835-pl011") || 475 ofw_bus_is_compatible(sc->sc_dev, "broadcom,bcm2835-uart")) { 476 return (2); 477 } else { 478 node = ofw_bus_get_node(sc->sc_dev); 479 if (OF_getencprop(node, "arm,primecell-periphid", &periphid, 480 sizeof(periphid)) > 0) { 481 return ((periphid >> 20) & 0x0f); 482 } 483 } 484 485 return (-1); 486 } 487 #endif 488 489 static int 490 uart_pl011_bus_probe(struct uart_softc *sc) 491 { 492 int hwrev; 493 494 hwrev = -1; 495 #ifdef FDT 496 if (IS_FDT) 497 hwrev = uart_pl011_bus_hwrev_fdt(sc); 498 #endif 499 if (hwrev < 0) 500 hwrev = __uart_getreg(&sc->sc_bas, UART_PIDREG_2) >> 4; 501 502 if (hwrev <= 2) { 503 sc->sc_rxfifosz = FIFO_RX_SIZE_R2; 504 sc->sc_txfifosz = FIFO_TX_SIZE_R2; 505 } else { 506 sc->sc_rxfifosz = FIFO_RX_SIZE_R3; 507 sc->sc_txfifosz = FIFO_TX_SIZE_R3; 508 } 509 510 device_set_desc(sc->sc_dev, "PrimeCell UART (PL011)"); 511 512 return (0); 513 } 514 515 static int 516 uart_pl011_bus_receive(struct uart_softc *sc) 517 { 518 struct uart_bas *bas; 519 uint32_t ints, xc; 520 int rx; 521 522 bas = &sc->sc_bas; 523 uart_lock(sc->sc_hwmtx); 524 525 for (;;) { 526 ints = __uart_getreg(bas, UART_FR); 527 if (ints & FR_RXFE) 528 break; 529 if (uart_rx_full(sc)) { 530 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 531 break; 532 } 533 534 xc = __uart_getreg(bas, UART_DR); 535 rx = xc & 0xff; 536 537 if (xc & DR_FE) 538 rx |= UART_STAT_FRAMERR; 539 if (xc & DR_PE) 540 rx |= UART_STAT_PARERR; 541 542 uart_rx_put(sc, rx); 543 } 544 545 uart_unlock(sc->sc_hwmtx); 546 547 return (0); 548 } 549 550 static int 551 uart_pl011_bus_setsig(struct uart_softc *sc, int sig) 552 { 553 554 return (0); 555 } 556 557 static int 558 uart_pl011_bus_transmit(struct uart_softc *sc) 559 { 560 struct uart_pl011_softc *psc; 561 struct uart_bas *bas; 562 int i; 563 564 psc = (struct uart_pl011_softc *)sc; 565 bas = &sc->sc_bas; 566 uart_lock(sc->sc_hwmtx); 567 568 for (i = 0; i < sc->sc_txdatasz; i++) { 569 __uart_setreg(bas, UART_DR, sc->sc_txbuf[i]); 570 uart_barrier(bas); 571 } 572 573 /* Mark busy and enable TX interrupt */ 574 sc->sc_txbusy = 1; 575 __uart_setreg(bas, UART_IMSC, psc->imsc); 576 577 uart_unlock(sc->sc_hwmtx); 578 579 return (0); 580 } 581 582 static void 583 uart_pl011_bus_grab(struct uart_softc *sc) 584 { 585 struct uart_pl011_softc *psc; 586 struct uart_bas *bas; 587 588 psc = (struct uart_pl011_softc *)sc; 589 bas = &sc->sc_bas; 590 591 /* Disable interrupts on switch to polling */ 592 uart_lock(sc->sc_hwmtx); 593 __uart_setreg(bas, UART_IMSC, psc->imsc & ~IMSC_MASK_ALL); 594 uart_unlock(sc->sc_hwmtx); 595 } 596 597 static void 598 uart_pl011_bus_ungrab(struct uart_softc *sc) 599 { 600 struct uart_pl011_softc *psc; 601 struct uart_bas *bas; 602 603 psc = (struct uart_pl011_softc *)sc; 604 bas = &sc->sc_bas; 605 606 /* Switch to using interrupts while not grabbed */ 607 uart_lock(sc->sc_hwmtx); 608 __uart_setreg(bas, UART_IMSC, psc->imsc); 609 uart_unlock(sc->sc_hwmtx); 610 } 611