1 /*- 2 * Device driver optimized for the Symbios/LSI 53C896/53C895A/53C1010 3 * PCI-SCSI controllers. 4 * 5 * Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr> 6 * 7 * This driver also supports the following Symbios/LSI PCI-SCSI chips: 8 * 53C810A, 53C825A, 53C860, 53C875, 53C876, 53C885, 53C895, 9 * 53C810, 53C815, 53C825 and the 53C1510D is 53C8XX mode. 10 * 11 * 12 * This driver for FreeBSD-CAM is derived from the Linux sym53c8xx driver. 13 * Copyright (C) 1998-1999 Gerard Roudier 14 * 15 * The sym53c8xx driver is derived from the ncr53c8xx driver that had been 16 * a port of the FreeBSD ncr driver to Linux-1.2.13. 17 * 18 * The original ncr driver has been written for 386bsd and FreeBSD by 19 * Wolfgang Stanglmeier <wolf@cologne.de> 20 * Stefan Esser <se@mi.Uni-Koeln.de> 21 * Copyright (C) 1994 Wolfgang Stanglmeier 22 * 23 * The initialisation code, and part of the code that addresses 24 * FreeBSD-CAM services is based on the aic7xxx driver for FreeBSD-CAM 25 * written by Justin T. Gibbs. 26 * 27 * Other major contributions: 28 * 29 * NVRAM detection and reading. 30 * Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk> 31 * 32 *----------------------------------------------------------------------------- 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 3. The name of the author may not be used to endorse or promote products 43 * derived from this software without specific prior written permission. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 49 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 __FBSDID("$FreeBSD$"); 60 61 #define SYM_DRIVER_NAME "sym-1.6.5-20000902" 62 63 /* #define SYM_DEBUG_GENERIC_SUPPORT */ 64 /* #define CAM_NEW_TRAN_CODE */ 65 66 #include <sys/param.h> 67 68 /* 69 * Driver configuration options. 70 */ 71 #include "opt_sym.h" 72 #include <dev/sym/sym_conf.h> 73 74 75 #include <sys/systm.h> 76 #include <sys/malloc.h> 77 #include <sys/endian.h> 78 #include <sys/kernel.h> 79 #include <sys/lock.h> 80 #include <sys/mutex.h> 81 #include <sys/module.h> 82 #include <sys/bus.h> 83 84 #include <sys/proc.h> 85 86 #include <dev/pci/pcireg.h> 87 #include <dev/pci/pcivar.h> 88 89 #include <machine/bus.h> 90 #include <machine/resource.h> 91 #include <sys/rman.h> 92 93 #include <cam/cam.h> 94 #include <cam/cam_ccb.h> 95 #include <cam/cam_sim.h> 96 #include <cam/cam_xpt_sim.h> 97 #include <cam/cam_debug.h> 98 99 #include <cam/scsi/scsi_all.h> 100 #include <cam/scsi/scsi_message.h> 101 102 #include <vm/vm.h> 103 #include <vm/vm_param.h> 104 #include <vm/pmap.h> 105 106 /* Short and quite clear integer types */ 107 typedef int8_t s8; 108 typedef int16_t s16; 109 typedef int32_t s32; 110 typedef u_int8_t u8; 111 typedef u_int16_t u16; 112 typedef u_int32_t u32; 113 114 /* 115 * From 'cam.error_recovery_diffs.20010313.context' patch. 116 */ 117 #ifdef CAM_NEW_TRAN_CODE 118 #define FreeBSD_New_Tran_Settings 119 #endif /* CAM_NEW_TRAN_CODE */ 120 121 /* 122 * Driver definitions. 123 */ 124 #include <dev/sym/sym_defs.h> 125 #include <dev/sym/sym_fw.h> 126 127 /* 128 * IA32 architecture does not reorder STORES and prevents 129 * LOADS from passing STORES. It is called `program order' 130 * by Intel and allows device drivers to deal with memory 131 * ordering by only ensuring that the code is not reordered 132 * by the compiler when ordering is required. 133 * Other architectures implement a weaker ordering that 134 * requires memory barriers (and also IO barriers when they 135 * make sense) to be used. 136 */ 137 138 #if defined __i386__ || defined __amd64__ 139 #define MEMORY_BARRIER() do { ; } while(0) 140 #elif defined __powerpc__ 141 #define MEMORY_BARRIER() __asm__ volatile("eieio; sync" : : : "memory") 142 #elif defined __ia64__ 143 #define MEMORY_BARRIER() __asm__ volatile("mf.a; mf" : : : "memory") 144 #elif defined __sparc64__ 145 #define MEMORY_BARRIER() __asm__ volatile("membar #Sync" : : : "memory") 146 #else 147 #error "Not supported platform" 148 #endif 149 150 /* 151 * A la VMS/CAM-3 queue management. 152 */ 153 154 typedef struct sym_quehead { 155 struct sym_quehead *flink; /* Forward pointer */ 156 struct sym_quehead *blink; /* Backward pointer */ 157 } SYM_QUEHEAD; 158 159 #define sym_que_init(ptr) do { \ 160 (ptr)->flink = (ptr); (ptr)->blink = (ptr); \ 161 } while (0) 162 163 static __inline struct sym_quehead *sym_que_first(struct sym_quehead *head) 164 { 165 return (head->flink == head) ? 0 : head->flink; 166 } 167 168 static __inline struct sym_quehead *sym_que_last(struct sym_quehead *head) 169 { 170 return (head->blink == head) ? 0 : head->blink; 171 } 172 173 static __inline void __sym_que_add(struct sym_quehead * new, 174 struct sym_quehead * blink, 175 struct sym_quehead * flink) 176 { 177 flink->blink = new; 178 new->flink = flink; 179 new->blink = blink; 180 blink->flink = new; 181 } 182 183 static __inline void __sym_que_del(struct sym_quehead * blink, 184 struct sym_quehead * flink) 185 { 186 flink->blink = blink; 187 blink->flink = flink; 188 } 189 190 static __inline int sym_que_empty(struct sym_quehead *head) 191 { 192 return head->flink == head; 193 } 194 195 static __inline void sym_que_splice(struct sym_quehead *list, 196 struct sym_quehead *head) 197 { 198 struct sym_quehead *first = list->flink; 199 200 if (first != list) { 201 struct sym_quehead *last = list->blink; 202 struct sym_quehead *at = head->flink; 203 204 first->blink = head; 205 head->flink = first; 206 207 last->flink = at; 208 at->blink = last; 209 } 210 } 211 212 #define sym_que_entry(ptr, type, member) \ 213 ((type *)((char *)(ptr)-(unsigned int)(&((type *)0)->member))) 214 215 216 #define sym_insque(new, pos) __sym_que_add(new, pos, (pos)->flink) 217 218 #define sym_remque(el) __sym_que_del((el)->blink, (el)->flink) 219 220 #define sym_insque_head(new, head) __sym_que_add(new, head, (head)->flink) 221 222 static __inline struct sym_quehead *sym_remque_head(struct sym_quehead *head) 223 { 224 struct sym_quehead *elem = head->flink; 225 226 if (elem != head) 227 __sym_que_del(head, elem->flink); 228 else 229 elem = 0; 230 return elem; 231 } 232 233 #define sym_insque_tail(new, head) __sym_que_add(new, (head)->blink, head) 234 235 static __inline struct sym_quehead *sym_remque_tail(struct sym_quehead *head) 236 { 237 struct sym_quehead *elem = head->blink; 238 239 if (elem != head) 240 __sym_que_del(elem->blink, head); 241 else 242 elem = 0; 243 return elem; 244 } 245 246 /* 247 * This one may be useful. 248 */ 249 #define FOR_EACH_QUEUED_ELEMENT(head, qp) \ 250 for (qp = (head)->flink; qp != (head); qp = qp->flink) 251 /* 252 * FreeBSD does not offer our kind of queue in the CAM CCB. 253 * So, we have to cast. 254 */ 255 #define sym_qptr(p) ((struct sym_quehead *) (p)) 256 257 /* 258 * Simple bitmap operations. 259 */ 260 #define sym_set_bit(p, n) (((u32 *)(p))[(n)>>5] |= (1<<((n)&0x1f))) 261 #define sym_clr_bit(p, n) (((u32 *)(p))[(n)>>5] &= ~(1<<((n)&0x1f))) 262 #define sym_is_bit(p, n) (((u32 *)(p))[(n)>>5] & (1<<((n)&0x1f))) 263 264 /* 265 * Number of tasks per device we want to handle. 266 */ 267 #if SYM_CONF_MAX_TAG_ORDER > 8 268 #error "more than 256 tags per logical unit not allowed." 269 #endif 270 #define SYM_CONF_MAX_TASK (1<<SYM_CONF_MAX_TAG_ORDER) 271 272 /* 273 * Donnot use more tasks that we can handle. 274 */ 275 #ifndef SYM_CONF_MAX_TAG 276 #define SYM_CONF_MAX_TAG SYM_CONF_MAX_TASK 277 #endif 278 #if SYM_CONF_MAX_TAG > SYM_CONF_MAX_TASK 279 #undef SYM_CONF_MAX_TAG 280 #define SYM_CONF_MAX_TAG SYM_CONF_MAX_TASK 281 #endif 282 283 /* 284 * This one means 'NO TAG for this job' 285 */ 286 #define NO_TAG (256) 287 288 /* 289 * Number of SCSI targets. 290 */ 291 #if SYM_CONF_MAX_TARGET > 16 292 #error "more than 16 targets not allowed." 293 #endif 294 295 /* 296 * Number of logical units per target. 297 */ 298 #if SYM_CONF_MAX_LUN > 64 299 #error "more than 64 logical units per target not allowed." 300 #endif 301 302 /* 303 * Asynchronous pre-scaler (ns). Shall be 40 for 304 * the SCSI timings to be compliant. 305 */ 306 #define SYM_CONF_MIN_ASYNC (40) 307 308 /* 309 * Number of entries in the START and DONE queues. 310 * 311 * We limit to 1 PAGE in order to succeed allocation of 312 * these queues. Each entry is 8 bytes long (2 DWORDS). 313 */ 314 #ifdef SYM_CONF_MAX_START 315 #define SYM_CONF_MAX_QUEUE (SYM_CONF_MAX_START+2) 316 #else 317 #define SYM_CONF_MAX_QUEUE (7*SYM_CONF_MAX_TASK+2) 318 #define SYM_CONF_MAX_START (SYM_CONF_MAX_QUEUE-2) 319 #endif 320 321 #if SYM_CONF_MAX_QUEUE > PAGE_SIZE/8 322 #undef SYM_CONF_MAX_QUEUE 323 #define SYM_CONF_MAX_QUEUE PAGE_SIZE/8 324 #undef SYM_CONF_MAX_START 325 #define SYM_CONF_MAX_START (SYM_CONF_MAX_QUEUE-2) 326 #endif 327 328 /* 329 * For this one, we want a short name :-) 330 */ 331 #define MAX_QUEUE SYM_CONF_MAX_QUEUE 332 333 /* 334 * Active debugging tags and verbosity. 335 */ 336 #define DEBUG_ALLOC (0x0001) 337 #define DEBUG_PHASE (0x0002) 338 #define DEBUG_POLL (0x0004) 339 #define DEBUG_QUEUE (0x0008) 340 #define DEBUG_RESULT (0x0010) 341 #define DEBUG_SCATTER (0x0020) 342 #define DEBUG_SCRIPT (0x0040) 343 #define DEBUG_TINY (0x0080) 344 #define DEBUG_TIMING (0x0100) 345 #define DEBUG_NEGO (0x0200) 346 #define DEBUG_TAGS (0x0400) 347 #define DEBUG_POINTER (0x0800) 348 349 #if 0 350 static int sym_debug = 0; 351 #define DEBUG_FLAGS sym_debug 352 #else 353 /* #define DEBUG_FLAGS (0x0631) */ 354 #define DEBUG_FLAGS (0x0000) 355 356 #endif 357 #define sym_verbose (np->verbose) 358 359 /* 360 * Insert a delay in micro-seconds and milli-seconds. 361 */ 362 static void UDELAY(int us) { DELAY(us); } 363 static void MDELAY(int ms) { while (ms--) UDELAY(1000); } 364 365 /* 366 * Simple power of two buddy-like allocator. 367 * 368 * This simple code is not intended to be fast, but to 369 * provide power of 2 aligned memory allocations. 370 * Since the SCRIPTS processor only supplies 8 bit arithmetic, 371 * this allocator allows simple and fast address calculations 372 * from the SCRIPTS code. In addition, cache line alignment 373 * is guaranteed for power of 2 cache line size. 374 * 375 * This allocator has been developped for the Linux sym53c8xx 376 * driver, since this O/S does not provide naturally aligned 377 * allocations. 378 * It has the advantage of allowing the driver to use private 379 * pages of memory that will be useful if we ever need to deal 380 * with IO MMUs for PCI. 381 */ 382 383 #define MEMO_SHIFT 4 /* 16 bytes minimum memory chunk */ 384 #ifndef __amd64__ 385 #define MEMO_PAGE_ORDER 0 /* 1 PAGE maximum */ 386 #else 387 #define MEMO_PAGE_ORDER 1 /* 2 PAGEs maximum on amd64 */ 388 #endif 389 #if 0 390 #define MEMO_FREE_UNUSED /* Free unused pages immediately */ 391 #endif 392 #define MEMO_WARN 1 393 #define MEMO_CLUSTER_SHIFT (PAGE_SHIFT+MEMO_PAGE_ORDER) 394 #define MEMO_CLUSTER_SIZE (1UL << MEMO_CLUSTER_SHIFT) 395 #define MEMO_CLUSTER_MASK (MEMO_CLUSTER_SIZE-1) 396 397 #ifndef __amd64__ 398 #define get_pages() malloc(MEMO_CLUSTER_SIZE, M_DEVBUF, M_NOWAIT) 399 #define free_pages(p) free((p), M_DEVBUF) 400 #else 401 #define get_pages() contigmalloc(MEMO_CLUSTER_SIZE, M_DEVBUF, \ 402 0, 0, 1LL << 32, PAGE_SIZE, 1LL << 32) 403 #define free_pages(p) contigfree((p), MEMO_CLUSTER_SIZE, M_DEVBUF) 404 #endif 405 406 typedef u_long m_addr_t; /* Enough bits to bit-hack addresses */ 407 408 typedef struct m_link { /* Link between free memory chunks */ 409 struct m_link *next; 410 } m_link_s; 411 412 typedef struct m_vtob { /* Virtual to Bus address translation */ 413 struct m_vtob *next; 414 bus_dmamap_t dmamap; /* Map for this chunk */ 415 m_addr_t vaddr; /* Virtual address */ 416 m_addr_t baddr; /* Bus physical address */ 417 } m_vtob_s; 418 /* Hash this stuff a bit to speed up translations */ 419 #define VTOB_HASH_SHIFT 5 420 #define VTOB_HASH_SIZE (1UL << VTOB_HASH_SHIFT) 421 #define VTOB_HASH_MASK (VTOB_HASH_SIZE-1) 422 #define VTOB_HASH_CODE(m) \ 423 ((((m_addr_t) (m)) >> MEMO_CLUSTER_SHIFT) & VTOB_HASH_MASK) 424 425 typedef struct m_pool { /* Memory pool of a given kind */ 426 bus_dma_tag_t dev_dmat; /* Identifies the pool */ 427 bus_dma_tag_t dmat; /* Tag for our fixed allocations */ 428 m_addr_t (*getp)(struct m_pool *); 429 #ifdef MEMO_FREE_UNUSED 430 void (*freep)(struct m_pool *, m_addr_t); 431 #endif 432 #define M_GETP() mp->getp(mp) 433 #define M_FREEP(p) mp->freep(mp, p) 434 int nump; 435 m_vtob_s *(vtob[VTOB_HASH_SIZE]); 436 struct m_pool *next; 437 struct m_link h[MEMO_CLUSTER_SHIFT - MEMO_SHIFT + 1]; 438 } m_pool_s; 439 440 static void *___sym_malloc(m_pool_s *mp, int size) 441 { 442 int i = 0; 443 int s = (1 << MEMO_SHIFT); 444 int j; 445 m_addr_t a; 446 m_link_s *h = mp->h; 447 448 if (size > MEMO_CLUSTER_SIZE) 449 return 0; 450 451 while (size > s) { 452 s <<= 1; 453 ++i; 454 } 455 456 j = i; 457 while (!h[j].next) { 458 if (s == MEMO_CLUSTER_SIZE) { 459 h[j].next = (m_link_s *) M_GETP(); 460 if (h[j].next) 461 h[j].next->next = 0; 462 break; 463 } 464 ++j; 465 s <<= 1; 466 } 467 a = (m_addr_t) h[j].next; 468 if (a) { 469 h[j].next = h[j].next->next; 470 while (j > i) { 471 j -= 1; 472 s >>= 1; 473 h[j].next = (m_link_s *) (a+s); 474 h[j].next->next = 0; 475 } 476 } 477 #ifdef DEBUG 478 printf("___sym_malloc(%d) = %p\n", size, (void *) a); 479 #endif 480 return (void *) a; 481 } 482 483 static void ___sym_mfree(m_pool_s *mp, void *ptr, int size) 484 { 485 int i = 0; 486 int s = (1 << MEMO_SHIFT); 487 m_link_s *q; 488 m_addr_t a, b; 489 m_link_s *h = mp->h; 490 491 #ifdef DEBUG 492 printf("___sym_mfree(%p, %d)\n", ptr, size); 493 #endif 494 495 if (size > MEMO_CLUSTER_SIZE) 496 return; 497 498 while (size > s) { 499 s <<= 1; 500 ++i; 501 } 502 503 a = (m_addr_t) ptr; 504 505 while (1) { 506 #ifdef MEMO_FREE_UNUSED 507 if (s == MEMO_CLUSTER_SIZE) { 508 M_FREEP(a); 509 break; 510 } 511 #endif 512 b = a ^ s; 513 q = &h[i]; 514 while (q->next && q->next != (m_link_s *) b) { 515 q = q->next; 516 } 517 if (!q->next) { 518 ((m_link_s *) a)->next = h[i].next; 519 h[i].next = (m_link_s *) a; 520 break; 521 } 522 q->next = q->next->next; 523 a = a & b; 524 s <<= 1; 525 ++i; 526 } 527 } 528 529 static void *__sym_calloc2(m_pool_s *mp, int size, char *name, int uflags) 530 { 531 void *p; 532 533 p = ___sym_malloc(mp, size); 534 535 if (DEBUG_FLAGS & DEBUG_ALLOC) 536 printf ("new %-10s[%4d] @%p.\n", name, size, p); 537 538 if (p) 539 bzero(p, size); 540 else if (uflags & MEMO_WARN) 541 printf ("__sym_calloc2: failed to allocate %s[%d]\n", name, size); 542 543 return p; 544 } 545 546 #define __sym_calloc(mp, s, n) __sym_calloc2(mp, s, n, MEMO_WARN) 547 548 static void __sym_mfree(m_pool_s *mp, void *ptr, int size, char *name) 549 { 550 if (DEBUG_FLAGS & DEBUG_ALLOC) 551 printf ("freeing %-10s[%4d] @%p.\n", name, size, ptr); 552 553 ___sym_mfree(mp, ptr, size); 554 555 } 556 557 /* 558 * Default memory pool we donnot need to involve in DMA. 559 */ 560 /* 561 * With the `bus dma abstraction', we use a separate pool for 562 * memory we donnot need to involve in DMA. 563 */ 564 static m_addr_t ___mp0_getp(m_pool_s *mp) 565 { 566 m_addr_t m = (m_addr_t) get_pages(); 567 if (m) 568 ++mp->nump; 569 return m; 570 } 571 572 #ifdef MEMO_FREE_UNUSED 573 static void ___mp0_freep(m_pool_s *mp, m_addr_t m) 574 { 575 free_pages(m); 576 --mp->nump; 577 } 578 #endif 579 580 #ifdef MEMO_FREE_UNUSED 581 static m_pool_s mp0 = {0, 0, ___mp0_getp, ___mp0_freep}; 582 #else 583 static m_pool_s mp0 = {0, 0, ___mp0_getp}; 584 #endif 585 586 587 /* 588 * Actual memory allocation routine for non-DMAed memory. 589 */ 590 static void *sym_calloc(int size, char *name) 591 { 592 void *m; 593 /* Lock */ 594 m = __sym_calloc(&mp0, size, name); 595 /* Unlock */ 596 return m; 597 } 598 599 /* 600 * Actual memory allocation routine for non-DMAed memory. 601 */ 602 static void sym_mfree(void *ptr, int size, char *name) 603 { 604 /* Lock */ 605 __sym_mfree(&mp0, ptr, size, name); 606 /* Unlock */ 607 } 608 609 /* 610 * DMAable pools. 611 */ 612 /* 613 * With `bus dma abstraction', we use a separate pool per parent 614 * BUS handle. A reverse table (hashed) is maintained for virtual 615 * to BUS address translation. 616 */ 617 static void getbaddrcb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 618 { 619 bus_addr_t *baddr; 620 baddr = (bus_addr_t *)arg; 621 *baddr = segs->ds_addr; 622 } 623 624 static m_addr_t ___dma_getp(m_pool_s *mp) 625 { 626 m_vtob_s *vbp; 627 void *vaddr = 0; 628 bus_addr_t baddr = 0; 629 630 vbp = __sym_calloc(&mp0, sizeof(*vbp), "VTOB"); 631 if (!vbp) 632 goto out_err; 633 634 if (bus_dmamem_alloc(mp->dmat, &vaddr, 635 BUS_DMA_NOWAIT, &vbp->dmamap)) 636 goto out_err; 637 bus_dmamap_load(mp->dmat, vbp->dmamap, vaddr, 638 MEMO_CLUSTER_SIZE, getbaddrcb, &baddr, 0); 639 if (baddr) { 640 int hc = VTOB_HASH_CODE(vaddr); 641 vbp->vaddr = (m_addr_t) vaddr; 642 vbp->baddr = (m_addr_t) baddr; 643 vbp->next = mp->vtob[hc]; 644 mp->vtob[hc] = vbp; 645 ++mp->nump; 646 return (m_addr_t) vaddr; 647 } 648 out_err: 649 if (baddr) 650 bus_dmamap_unload(mp->dmat, vbp->dmamap); 651 if (vaddr) 652 bus_dmamem_free(mp->dmat, vaddr, vbp->dmamap); 653 if (vbp) { 654 if (vbp->dmamap) 655 bus_dmamap_destroy(mp->dmat, vbp->dmamap); 656 __sym_mfree(&mp0, vbp, sizeof(*vbp), "VTOB"); 657 } 658 return 0; 659 } 660 661 #ifdef MEMO_FREE_UNUSED 662 static void ___dma_freep(m_pool_s *mp, m_addr_t m) 663 { 664 m_vtob_s **vbpp, *vbp; 665 int hc = VTOB_HASH_CODE(m); 666 667 vbpp = &mp->vtob[hc]; 668 while (*vbpp && (*vbpp)->vaddr != m) 669 vbpp = &(*vbpp)->next; 670 if (*vbpp) { 671 vbp = *vbpp; 672 *vbpp = (*vbpp)->next; 673 bus_dmamap_unload(mp->dmat, vbp->dmamap); 674 bus_dmamem_free(mp->dmat, (void *) vbp->vaddr, vbp->dmamap); 675 bus_dmamap_destroy(mp->dmat, vbp->dmamap); 676 __sym_mfree(&mp0, vbp, sizeof(*vbp), "VTOB"); 677 --mp->nump; 678 } 679 } 680 #endif 681 682 static __inline m_pool_s *___get_dma_pool(bus_dma_tag_t dev_dmat) 683 { 684 m_pool_s *mp; 685 for (mp = mp0.next; mp && mp->dev_dmat != dev_dmat; mp = mp->next); 686 return mp; 687 } 688 689 static m_pool_s *___cre_dma_pool(bus_dma_tag_t dev_dmat) 690 { 691 m_pool_s *mp = 0; 692 693 mp = __sym_calloc(&mp0, sizeof(*mp), "MPOOL"); 694 if (mp) { 695 mp->dev_dmat = dev_dmat; 696 if (!bus_dma_tag_create(dev_dmat, 1, MEMO_CLUSTER_SIZE, 697 BUS_SPACE_MAXADDR_32BIT, 698 BUS_SPACE_MAXADDR_32BIT, 699 NULL, NULL, MEMO_CLUSTER_SIZE, 1, 700 MEMO_CLUSTER_SIZE, 0, 701 busdma_lock_mutex, &Giant, &mp->dmat)) { 702 mp->getp = ___dma_getp; 703 #ifdef MEMO_FREE_UNUSED 704 mp->freep = ___dma_freep; 705 #endif 706 mp->next = mp0.next; 707 mp0.next = mp; 708 return mp; 709 } 710 } 711 if (mp) 712 __sym_mfree(&mp0, mp, sizeof(*mp), "MPOOL"); 713 return 0; 714 } 715 716 #ifdef MEMO_FREE_UNUSED 717 static void ___del_dma_pool(m_pool_s *p) 718 { 719 struct m_pool **pp = &mp0.next; 720 721 while (*pp && *pp != p) 722 pp = &(*pp)->next; 723 if (*pp) { 724 *pp = (*pp)->next; 725 bus_dma_tag_destroy(p->dmat); 726 __sym_mfree(&mp0, p, sizeof(*p), "MPOOL"); 727 } 728 } 729 #endif 730 731 static void *__sym_calloc_dma(bus_dma_tag_t dev_dmat, int size, char *name) 732 { 733 struct m_pool *mp; 734 void *m = 0; 735 736 /* Lock */ 737 mp = ___get_dma_pool(dev_dmat); 738 if (!mp) 739 mp = ___cre_dma_pool(dev_dmat); 740 if (mp) 741 m = __sym_calloc(mp, size, name); 742 #ifdef MEMO_FREE_UNUSED 743 if (mp && !mp->nump) 744 ___del_dma_pool(mp); 745 #endif 746 /* Unlock */ 747 748 return m; 749 } 750 751 static void 752 __sym_mfree_dma(bus_dma_tag_t dev_dmat, void *m, int size, char *name) 753 { 754 struct m_pool *mp; 755 756 /* Lock */ 757 mp = ___get_dma_pool(dev_dmat); 758 if (mp) 759 __sym_mfree(mp, m, size, name); 760 #ifdef MEMO_FREE_UNUSED 761 if (mp && !mp->nump) 762 ___del_dma_pool(mp); 763 #endif 764 /* Unlock */ 765 } 766 767 static m_addr_t __vtobus(bus_dma_tag_t dev_dmat, void *m) 768 { 769 m_pool_s *mp; 770 int hc = VTOB_HASH_CODE(m); 771 m_vtob_s *vp = 0; 772 m_addr_t a = ((m_addr_t) m) & ~MEMO_CLUSTER_MASK; 773 774 /* Lock */ 775 mp = ___get_dma_pool(dev_dmat); 776 if (mp) { 777 vp = mp->vtob[hc]; 778 while (vp && (m_addr_t) vp->vaddr != a) 779 vp = vp->next; 780 } 781 /* Unlock */ 782 if (!vp) 783 panic("sym: VTOBUS FAILED!\n"); 784 return vp ? vp->baddr + (((m_addr_t) m) - a) : 0; 785 } 786 787 788 /* 789 * Verbs for DMAable memory handling. 790 * The _uvptv_ macro avoids a nasty warning about pointer to volatile 791 * being discarded. 792 */ 793 #define _uvptv_(p) ((void *)((vm_offset_t)(p))) 794 #define _sym_calloc_dma(np, s, n) __sym_calloc_dma(np->bus_dmat, s, n) 795 #define _sym_mfree_dma(np, p, s, n) \ 796 __sym_mfree_dma(np->bus_dmat, _uvptv_(p), s, n) 797 #define sym_calloc_dma(s, n) _sym_calloc_dma(np, s, n) 798 #define sym_mfree_dma(p, s, n) _sym_mfree_dma(np, p, s, n) 799 #define _vtobus(np, p) __vtobus(np->bus_dmat, _uvptv_(p)) 800 #define vtobus(p) _vtobus(np, p) 801 802 803 /* 804 * Print a buffer in hexadecimal format. 805 */ 806 static void sym_printb_hex (u_char *p, int n) 807 { 808 while (n-- > 0) 809 printf (" %x", *p++); 810 } 811 812 /* 813 * Same with a label at beginning and .\n at end. 814 */ 815 static void sym_printl_hex (char *label, u_char *p, int n) 816 { 817 printf ("%s", label); 818 sym_printb_hex (p, n); 819 printf (".\n"); 820 } 821 822 /* 823 * Return a string for SCSI BUS mode. 824 */ 825 static char *sym_scsi_bus_mode(int mode) 826 { 827 switch(mode) { 828 case SMODE_HVD: return "HVD"; 829 case SMODE_SE: return "SE"; 830 case SMODE_LVD: return "LVD"; 831 } 832 return "??"; 833 } 834 835 /* 836 * Some poor and bogus sync table that refers to Tekram NVRAM layout. 837 */ 838 #ifdef SYM_CONF_NVRAM_SUPPORT 839 static u_char Tekram_sync[16] = 840 {25,31,37,43, 50,62,75,125, 12,15,18,21, 6,7,9,10}; 841 #endif 842 843 /* 844 * Union of supported NVRAM formats. 845 */ 846 struct sym_nvram { 847 int type; 848 #define SYM_SYMBIOS_NVRAM (1) 849 #define SYM_TEKRAM_NVRAM (2) 850 #ifdef SYM_CONF_NVRAM_SUPPORT 851 union { 852 Symbios_nvram Symbios; 853 Tekram_nvram Tekram; 854 } data; 855 #endif 856 }; 857 858 /* 859 * This one is hopefully useless, but actually useful. :-) 860 */ 861 #ifndef assert 862 #define assert(expression) { \ 863 if (!(expression)) { \ 864 (void)panic( \ 865 "assertion \"%s\" failed: file \"%s\", line %d\n", \ 866 #expression, \ 867 __FILE__, __LINE__); \ 868 } \ 869 } 870 #endif 871 872 /* 873 * Some provision for a possible big endian mode supported by 874 * Symbios chips (never seen, by the way). 875 * For now, this stuff does not deserve any comments. :) 876 */ 877 878 #define sym_offb(o) (o) 879 #define sym_offw(o) (o) 880 881 /* 882 * Some provision for support for BIG ENDIAN CPU. 883 */ 884 885 #define cpu_to_scr(dw) htole32(dw) 886 #define scr_to_cpu(dw) le32toh(dw) 887 888 /* 889 * Access to the chip IO registers and on-chip RAM. 890 * We use the `bus space' interface under FreeBSD-4 and 891 * later kernel versions. 892 */ 893 894 895 #if defined(SYM_CONF_IOMAPPED) 896 897 #define INB_OFF(o) bus_space_read_1(np->io_tag, np->io_bsh, o) 898 #define INW_OFF(o) bus_space_read_2(np->io_tag, np->io_bsh, o) 899 #define INL_OFF(o) bus_space_read_4(np->io_tag, np->io_bsh, o) 900 901 #define OUTB_OFF(o, v) bus_space_write_1(np->io_tag, np->io_bsh, o, (v)) 902 #define OUTW_OFF(o, v) bus_space_write_2(np->io_tag, np->io_bsh, o, (v)) 903 #define OUTL_OFF(o, v) bus_space_write_4(np->io_tag, np->io_bsh, o, (v)) 904 905 #else /* Memory mapped IO */ 906 907 #define INB_OFF(o) bus_space_read_1(np->mmio_tag, np->mmio_bsh, o) 908 #define INW_OFF(o) bus_space_read_2(np->mmio_tag, np->mmio_bsh, o) 909 #define INL_OFF(o) bus_space_read_4(np->mmio_tag, np->mmio_bsh, o) 910 911 #define OUTB_OFF(o, v) bus_space_write_1(np->mmio_tag, np->mmio_bsh, o, (v)) 912 #define OUTW_OFF(o, v) bus_space_write_2(np->mmio_tag, np->mmio_bsh, o, (v)) 913 #define OUTL_OFF(o, v) bus_space_write_4(np->mmio_tag, np->mmio_bsh, o, (v)) 914 915 #endif /* SYM_CONF_IOMAPPED */ 916 917 #define OUTRAM_OFF(o, a, l) \ 918 bus_space_write_region_1(np->ram_tag, np->ram_bsh, o, (a), (l)) 919 920 921 /* 922 * Common definitions for both bus space and legacy IO methods. 923 */ 924 #define INB(r) INB_OFF(offsetof(struct sym_reg,r)) 925 #define INW(r) INW_OFF(offsetof(struct sym_reg,r)) 926 #define INL(r) INL_OFF(offsetof(struct sym_reg,r)) 927 928 #define OUTB(r, v) OUTB_OFF(offsetof(struct sym_reg,r), (v)) 929 #define OUTW(r, v) OUTW_OFF(offsetof(struct sym_reg,r), (v)) 930 #define OUTL(r, v) OUTL_OFF(offsetof(struct sym_reg,r), (v)) 931 932 #define OUTONB(r, m) OUTB(r, INB(r) | (m)) 933 #define OUTOFFB(r, m) OUTB(r, INB(r) & ~(m)) 934 #define OUTONW(r, m) OUTW(r, INW(r) | (m)) 935 #define OUTOFFW(r, m) OUTW(r, INW(r) & ~(m)) 936 #define OUTONL(r, m) OUTL(r, INL(r) | (m)) 937 #define OUTOFFL(r, m) OUTL(r, INL(r) & ~(m)) 938 939 /* 940 * We normally want the chip to have a consistent view 941 * of driver internal data structures when we restart it. 942 * Thus these macros. 943 */ 944 #define OUTL_DSP(v) \ 945 do { \ 946 MEMORY_BARRIER(); \ 947 OUTL (nc_dsp, (v)); \ 948 } while (0) 949 950 #define OUTONB_STD() \ 951 do { \ 952 MEMORY_BARRIER(); \ 953 OUTONB (nc_dcntl, (STD|NOCOM)); \ 954 } while (0) 955 956 /* 957 * Command control block states. 958 */ 959 #define HS_IDLE (0) 960 #define HS_BUSY (1) 961 #define HS_NEGOTIATE (2) /* sync/wide data transfer*/ 962 #define HS_DISCONNECT (3) /* Disconnected by target */ 963 #define HS_WAIT (4) /* waiting for resource */ 964 965 #define HS_DONEMASK (0x80) 966 #define HS_COMPLETE (4|HS_DONEMASK) 967 #define HS_SEL_TIMEOUT (5|HS_DONEMASK) /* Selection timeout */ 968 #define HS_UNEXPECTED (6|HS_DONEMASK) /* Unexpected disconnect */ 969 #define HS_COMP_ERR (7|HS_DONEMASK) /* Completed with error */ 970 971 /* 972 * Software Interrupt Codes 973 */ 974 #define SIR_BAD_SCSI_STATUS (1) 975 #define SIR_SEL_ATN_NO_MSG_OUT (2) 976 #define SIR_MSG_RECEIVED (3) 977 #define SIR_MSG_WEIRD (4) 978 #define SIR_NEGO_FAILED (5) 979 #define SIR_NEGO_PROTO (6) 980 #define SIR_SCRIPT_STOPPED (7) 981 #define SIR_REJECT_TO_SEND (8) 982 #define SIR_SWIDE_OVERRUN (9) 983 #define SIR_SODL_UNDERRUN (10) 984 #define SIR_RESEL_NO_MSG_IN (11) 985 #define SIR_RESEL_NO_IDENTIFY (12) 986 #define SIR_RESEL_BAD_LUN (13) 987 #define SIR_TARGET_SELECTED (14) 988 #define SIR_RESEL_BAD_I_T_L (15) 989 #define SIR_RESEL_BAD_I_T_L_Q (16) 990 #define SIR_ABORT_SENT (17) 991 #define SIR_RESEL_ABORTED (18) 992 #define SIR_MSG_OUT_DONE (19) 993 #define SIR_COMPLETE_ERROR (20) 994 #define SIR_DATA_OVERRUN (21) 995 #define SIR_BAD_PHASE (22) 996 #define SIR_MAX (22) 997 998 /* 999 * Extended error bit codes. 1000 * xerr_status field of struct sym_ccb. 1001 */ 1002 #define XE_EXTRA_DATA (1) /* unexpected data phase */ 1003 #define XE_BAD_PHASE (1<<1) /* illegal phase (4/5) */ 1004 #define XE_PARITY_ERR (1<<2) /* unrecovered SCSI parity error */ 1005 #define XE_SODL_UNRUN (1<<3) /* ODD transfer in DATA OUT phase */ 1006 #define XE_SWIDE_OVRUN (1<<4) /* ODD transfer in DATA IN phase */ 1007 1008 /* 1009 * Negotiation status. 1010 * nego_status field of struct sym_ccb. 1011 */ 1012 #define NS_SYNC (1) 1013 #define NS_WIDE (2) 1014 #define NS_PPR (3) 1015 1016 /* 1017 * A CCB hashed table is used to retrieve CCB address 1018 * from DSA value. 1019 */ 1020 #define CCB_HASH_SHIFT 8 1021 #define CCB_HASH_SIZE (1UL << CCB_HASH_SHIFT) 1022 #define CCB_HASH_MASK (CCB_HASH_SIZE-1) 1023 #define CCB_HASH_CODE(dsa) (((dsa) >> 9) & CCB_HASH_MASK) 1024 1025 /* 1026 * Device flags. 1027 */ 1028 #define SYM_DISC_ENABLED (1) 1029 #define SYM_TAGS_ENABLED (1<<1) 1030 #define SYM_SCAN_BOOT_DISABLED (1<<2) 1031 #define SYM_SCAN_LUNS_DISABLED (1<<3) 1032 1033 /* 1034 * Host adapter miscellaneous flags. 1035 */ 1036 #define SYM_AVOID_BUS_RESET (1) 1037 #define SYM_SCAN_TARGETS_HILO (1<<1) 1038 1039 /* 1040 * Device quirks. 1041 * Some devices, for example the CHEETAH 2 LVD, disconnects without 1042 * saving the DATA POINTER then reselects and terminates the IO. 1043 * On reselection, the automatic RESTORE DATA POINTER makes the 1044 * CURRENT DATA POINTER not point at the end of the IO. 1045 * This behaviour just breaks our calculation of the residual. 1046 * For now, we just force an AUTO SAVE on disconnection and will 1047 * fix that in a further driver version. 1048 */ 1049 #define SYM_QUIRK_AUTOSAVE 1 1050 1051 /* 1052 * Misc. 1053 */ 1054 #define SYM_SNOOP_TIMEOUT (10000000) 1055 #define SYM_PCI_IO PCIR_BAR(0) 1056 #define SYM_PCI_MMIO PCIR_BAR(1) 1057 #define SYM_PCI_RAM PCIR_BAR(2) 1058 #define SYM_PCI_RAM64 PCIR_BAR(3) 1059 1060 /* 1061 * Back-pointer from the CAM CCB to our data structures. 1062 */ 1063 #define sym_hcb_ptr spriv_ptr0 1064 /* #define sym_ccb_ptr spriv_ptr1 */ 1065 1066 /* 1067 * We mostly have to deal with pointers. 1068 * Thus these typedef's. 1069 */ 1070 typedef struct sym_tcb *tcb_p; 1071 typedef struct sym_lcb *lcb_p; 1072 typedef struct sym_ccb *ccb_p; 1073 typedef struct sym_hcb *hcb_p; 1074 1075 /* 1076 * Gather negotiable parameters value 1077 */ 1078 struct sym_trans { 1079 #ifdef FreeBSD_New_Tran_Settings 1080 u8 scsi_version; 1081 u8 spi_version; 1082 #endif 1083 u8 period; 1084 u8 offset; 1085 u8 width; 1086 u8 options; /* PPR options */ 1087 }; 1088 1089 struct sym_tinfo { 1090 struct sym_trans current; 1091 struct sym_trans goal; 1092 struct sym_trans user; 1093 }; 1094 1095 #define BUS_8_BIT MSG_EXT_WDTR_BUS_8_BIT 1096 #define BUS_16_BIT MSG_EXT_WDTR_BUS_16_BIT 1097 1098 /* 1099 * Global TCB HEADER. 1100 * 1101 * Due to lack of indirect addressing on earlier NCR chips, 1102 * this substructure is copied from the TCB to a global 1103 * address after selection. 1104 * For SYMBIOS chips that support LOAD/STORE this copy is 1105 * not needed and thus not performed. 1106 */ 1107 struct sym_tcbh { 1108 /* 1109 * Scripts bus addresses of LUN table accessed from scripts. 1110 * LUN #0 is a special case, since multi-lun devices are rare, 1111 * and we we want to speed-up the general case and not waste 1112 * resources. 1113 */ 1114 u32 luntbl_sa; /* bus address of this table */ 1115 u32 lun0_sa; /* bus address of LCB #0 */ 1116 /* 1117 * Actual SYNC/WIDE IO registers value for this target. 1118 * 'sval', 'wval' and 'uval' are read from SCRIPTS and 1119 * so have alignment constraints. 1120 */ 1121 /*0*/ u_char uval; /* -> SCNTL4 register */ 1122 /*1*/ u_char sval; /* -> SXFER io register */ 1123 /*2*/ u_char filler1; 1124 /*3*/ u_char wval; /* -> SCNTL3 io register */ 1125 }; 1126 1127 /* 1128 * Target Control Block 1129 */ 1130 struct sym_tcb { 1131 /* 1132 * TCB header. 1133 * Assumed at offset 0. 1134 */ 1135 /*0*/ struct sym_tcbh head; 1136 1137 /* 1138 * LUN table used by the SCRIPTS processor. 1139 * An array of bus addresses is used on reselection. 1140 */ 1141 u32 *luntbl; /* LCBs bus address table */ 1142 1143 /* 1144 * LUN table used by the C code. 1145 */ 1146 lcb_p lun0p; /* LCB of LUN #0 (usual case) */ 1147 #if SYM_CONF_MAX_LUN > 1 1148 lcb_p *lunmp; /* Other LCBs [1..MAX_LUN] */ 1149 #endif 1150 1151 /* 1152 * Bitmap that tells about LUNs that succeeded at least 1153 * 1 IO and therefore assumed to be a real device. 1154 * Avoid useless allocation of the LCB structure. 1155 */ 1156 u32 lun_map[(SYM_CONF_MAX_LUN+31)/32]; 1157 1158 /* 1159 * Bitmap that tells about LUNs that haven't yet an LCB 1160 * allocated (not discovered or LCB allocation failed). 1161 */ 1162 u32 busy0_map[(SYM_CONF_MAX_LUN+31)/32]; 1163 1164 /* 1165 * Transfer capabilities (SIP) 1166 */ 1167 struct sym_tinfo tinfo; 1168 1169 /* 1170 * Keep track of the CCB used for the negotiation in order 1171 * to ensure that only 1 negotiation is queued at a time. 1172 */ 1173 ccb_p nego_cp; /* CCB used for the nego */ 1174 1175 /* 1176 * Set when we want to reset the device. 1177 */ 1178 u_char to_reset; 1179 1180 /* 1181 * Other user settable limits and options. 1182 * These limits are read from the NVRAM if present. 1183 */ 1184 u_char usrflags; 1185 u_short usrtags; 1186 }; 1187 1188 /* 1189 * Global LCB HEADER. 1190 * 1191 * Due to lack of indirect addressing on earlier NCR chips, 1192 * this substructure is copied from the LCB to a global 1193 * address after selection. 1194 * For SYMBIOS chips that support LOAD/STORE this copy is 1195 * not needed and thus not performed. 1196 */ 1197 struct sym_lcbh { 1198 /* 1199 * SCRIPTS address jumped by SCRIPTS on reselection. 1200 * For not probed logical units, this address points to 1201 * SCRIPTS that deal with bad LU handling (must be at 1202 * offset zero of the LCB for that reason). 1203 */ 1204 /*0*/ u32 resel_sa; 1205 1206 /* 1207 * Task (bus address of a CCB) read from SCRIPTS that points 1208 * to the unique ITL nexus allowed to be disconnected. 1209 */ 1210 u32 itl_task_sa; 1211 1212 /* 1213 * Task table bus address (read from SCRIPTS). 1214 */ 1215 u32 itlq_tbl_sa; 1216 }; 1217 1218 /* 1219 * Logical Unit Control Block 1220 */ 1221 struct sym_lcb { 1222 /* 1223 * TCB header. 1224 * Assumed at offset 0. 1225 */ 1226 /*0*/ struct sym_lcbh head; 1227 1228 /* 1229 * Task table read from SCRIPTS that contains pointers to 1230 * ITLQ nexuses. The bus address read from SCRIPTS is 1231 * inside the header. 1232 */ 1233 u32 *itlq_tbl; /* Kernel virtual address */ 1234 1235 /* 1236 * Busy CCBs management. 1237 */ 1238 u_short busy_itlq; /* Number of busy tagged CCBs */ 1239 u_short busy_itl; /* Number of busy untagged CCBs */ 1240 1241 /* 1242 * Circular tag allocation buffer. 1243 */ 1244 u_short ia_tag; /* Tag allocation index */ 1245 u_short if_tag; /* Tag release index */ 1246 u_char *cb_tags; /* Circular tags buffer */ 1247 1248 /* 1249 * Set when we want to clear all tasks. 1250 */ 1251 u_char to_clear; 1252 1253 /* 1254 * Capabilities. 1255 */ 1256 u_char user_flags; 1257 u_char current_flags; 1258 }; 1259 1260 /* 1261 * Action from SCRIPTS on a task. 1262 * Is part of the CCB, but is also used separately to plug 1263 * error handling action to perform from SCRIPTS. 1264 */ 1265 struct sym_actscr { 1266 u32 start; /* Jumped by SCRIPTS after selection */ 1267 u32 restart; /* Jumped by SCRIPTS on relection */ 1268 }; 1269 1270 /* 1271 * Phase mismatch context. 1272 * 1273 * It is part of the CCB and is used as parameters for the 1274 * DATA pointer. We need two contexts to handle correctly the 1275 * SAVED DATA POINTER. 1276 */ 1277 struct sym_pmc { 1278 struct sym_tblmove sg; /* Updated interrupted SG block */ 1279 u32 ret; /* SCRIPT return address */ 1280 }; 1281 1282 /* 1283 * LUN control block lookup. 1284 * We use a direct pointer for LUN #0, and a table of 1285 * pointers which is only allocated for devices that support 1286 * LUN(s) > 0. 1287 */ 1288 #if SYM_CONF_MAX_LUN <= 1 1289 #define sym_lp(np, tp, lun) (!lun) ? (tp)->lun0p : 0 1290 #else 1291 #define sym_lp(np, tp, lun) \ 1292 (!lun) ? (tp)->lun0p : (tp)->lunmp ? (tp)->lunmp[(lun)] : 0 1293 #endif 1294 1295 /* 1296 * Status are used by the host and the script processor. 1297 * 1298 * The last four bytes (status[4]) are copied to the 1299 * scratchb register (declared as scr0..scr3) just after the 1300 * select/reselect, and copied back just after disconnecting. 1301 * Inside the script the XX_REG are used. 1302 */ 1303 1304 /* 1305 * Last four bytes (script) 1306 */ 1307 #define QU_REG scr0 1308 #define HS_REG scr1 1309 #define HS_PRT nc_scr1 1310 #define SS_REG scr2 1311 #define SS_PRT nc_scr2 1312 #define HF_REG scr3 1313 #define HF_PRT nc_scr3 1314 1315 /* 1316 * Last four bytes (host) 1317 */ 1318 #define actualquirks phys.head.status[0] 1319 #define host_status phys.head.status[1] 1320 #define ssss_status phys.head.status[2] 1321 #define host_flags phys.head.status[3] 1322 1323 /* 1324 * Host flags 1325 */ 1326 #define HF_IN_PM0 1u 1327 #define HF_IN_PM1 (1u<<1) 1328 #define HF_ACT_PM (1u<<2) 1329 #define HF_DP_SAVED (1u<<3) 1330 #define HF_SENSE (1u<<4) 1331 #define HF_EXT_ERR (1u<<5) 1332 #define HF_DATA_IN (1u<<6) 1333 #ifdef SYM_CONF_IARB_SUPPORT 1334 #define HF_HINT_IARB (1u<<7) 1335 #endif 1336 1337 /* 1338 * Global CCB HEADER. 1339 * 1340 * Due to lack of indirect addressing on earlier NCR chips, 1341 * this substructure is copied from the ccb to a global 1342 * address after selection (or reselection) and copied back 1343 * before disconnect. 1344 * For SYMBIOS chips that support LOAD/STORE this copy is 1345 * not needed and thus not performed. 1346 */ 1347 1348 struct sym_ccbh { 1349 /* 1350 * Start and restart SCRIPTS addresses (must be at 0). 1351 */ 1352 /*0*/ struct sym_actscr go; 1353 1354 /* 1355 * SCRIPTS jump address that deal with data pointers. 1356 * 'savep' points to the position in the script responsible 1357 * for the actual transfer of data. 1358 * It's written on reception of a SAVE_DATA_POINTER message. 1359 */ 1360 u32 savep; /* Jump address to saved data pointer */ 1361 u32 lastp; /* SCRIPTS address at end of data */ 1362 u32 goalp; /* Not accessed for now from SCRIPTS */ 1363 1364 /* 1365 * Status fields. 1366 */ 1367 u8 status[4]; 1368 }; 1369 1370 /* 1371 * Data Structure Block 1372 * 1373 * During execution of a ccb by the script processor, the 1374 * DSA (data structure address) register points to this 1375 * substructure of the ccb. 1376 */ 1377 struct sym_dsb { 1378 /* 1379 * CCB header. 1380 * Also assumed at offset 0 of the sym_ccb structure. 1381 */ 1382 /*0*/ struct sym_ccbh head; 1383 1384 /* 1385 * Phase mismatch contexts. 1386 * We need two to handle correctly the SAVED DATA POINTER. 1387 * MUST BOTH BE AT OFFSET < 256, due to using 8 bit arithmetic 1388 * for address calculation from SCRIPTS. 1389 */ 1390 struct sym_pmc pm0; 1391 struct sym_pmc pm1; 1392 1393 /* 1394 * Table data for Script 1395 */ 1396 struct sym_tblsel select; 1397 struct sym_tblmove smsg; 1398 struct sym_tblmove smsg_ext; 1399 struct sym_tblmove cmd; 1400 struct sym_tblmove sense; 1401 struct sym_tblmove wresid; 1402 struct sym_tblmove data [SYM_CONF_MAX_SG]; 1403 }; 1404 1405 /* 1406 * Our Command Control Block 1407 */ 1408 struct sym_ccb { 1409 /* 1410 * This is the data structure which is pointed by the DSA 1411 * register when it is executed by the script processor. 1412 * It must be the first entry. 1413 */ 1414 struct sym_dsb phys; 1415 1416 /* 1417 * Pointer to CAM ccb and related stuff. 1418 */ 1419 union ccb *cam_ccb; /* CAM scsiio ccb */ 1420 u8 cdb_buf[16]; /* Copy of CDB */ 1421 u8 *sns_bbuf; /* Bounce buffer for sense data */ 1422 #define SYM_SNS_BBUF_LEN sizeof(struct scsi_sense_data) 1423 int data_len; /* Total data length */ 1424 int segments; /* Number of SG segments */ 1425 1426 /* 1427 * Miscellaneous status'. 1428 */ 1429 u_char nego_status; /* Negotiation status */ 1430 u_char xerr_status; /* Extended error flags */ 1431 u32 extra_bytes; /* Extraneous bytes transferred */ 1432 1433 /* 1434 * Message areas. 1435 * We prepare a message to be sent after selection. 1436 * We may use a second one if the command is rescheduled 1437 * due to CHECK_CONDITION or COMMAND TERMINATED. 1438 * Contents are IDENTIFY and SIMPLE_TAG. 1439 * While negotiating sync or wide transfer, 1440 * a SDTR or WDTR message is appended. 1441 */ 1442 u_char scsi_smsg [12]; 1443 u_char scsi_smsg2[12]; 1444 1445 /* 1446 * Auto request sense related fields. 1447 */ 1448 u_char sensecmd[6]; /* Request Sense command */ 1449 u_char sv_scsi_status; /* Saved SCSI status */ 1450 u_char sv_xerr_status; /* Saved extended status */ 1451 int sv_resid; /* Saved residual */ 1452 1453 /* 1454 * Map for the DMA of user data. 1455 */ 1456 void *arg; /* Argument for some callback */ 1457 bus_dmamap_t dmamap; /* DMA map for user data */ 1458 u_char dmamapped; 1459 #define SYM_DMA_NONE 0 1460 #define SYM_DMA_READ 1 1461 #define SYM_DMA_WRITE 2 1462 /* 1463 * Other fields. 1464 */ 1465 u32 ccb_ba; /* BUS address of this CCB */ 1466 u_short tag; /* Tag for this transfer */ 1467 /* NO_TAG means no tag */ 1468 u_char target; 1469 u_char lun; 1470 ccb_p link_ccbh; /* Host adapter CCB hash chain */ 1471 SYM_QUEHEAD 1472 link_ccbq; /* Link to free/busy CCB queue */ 1473 u32 startp; /* Initial data pointer */ 1474 int ext_sg; /* Extreme data pointer, used */ 1475 int ext_ofs; /* to calculate the residual. */ 1476 u_char to_abort; /* Want this IO to be aborted */ 1477 }; 1478 1479 #define CCB_BA(cp,lbl) (cp->ccb_ba + offsetof(struct sym_ccb, lbl)) 1480 1481 /* 1482 * Host Control Block 1483 */ 1484 struct sym_hcb { 1485 /* 1486 * Global headers. 1487 * Due to poorness of addressing capabilities, earlier 1488 * chips (810, 815, 825) copy part of the data structures 1489 * (CCB, TCB and LCB) in fixed areas. 1490 */ 1491 #ifdef SYM_CONF_GENERIC_SUPPORT 1492 struct sym_ccbh ccb_head; 1493 struct sym_tcbh tcb_head; 1494 struct sym_lcbh lcb_head; 1495 #endif 1496 /* 1497 * Idle task and invalid task actions and 1498 * their bus addresses. 1499 */ 1500 struct sym_actscr idletask, notask, bad_itl, bad_itlq; 1501 vm_offset_t idletask_ba, notask_ba, bad_itl_ba, bad_itlq_ba; 1502 1503 /* 1504 * Dummy lun table to protect us against target 1505 * returning bad lun number on reselection. 1506 */ 1507 u32 *badluntbl; /* Table physical address */ 1508 u32 badlun_sa; /* SCRIPT handler BUS address */ 1509 1510 /* 1511 * Bus address of this host control block. 1512 */ 1513 u32 hcb_ba; 1514 1515 /* 1516 * Bit 32-63 of the on-chip RAM bus address in LE format. 1517 * The START_RAM64 script loads the MMRS and MMWS from this 1518 * field. 1519 */ 1520 u32 scr_ram_seg; 1521 1522 /* 1523 * Chip and controller indentification. 1524 */ 1525 device_t device; 1526 int unit; 1527 char inst_name[8]; 1528 1529 /* 1530 * Initial value of some IO register bits. 1531 * These values are assumed to have been set by BIOS, and may 1532 * be used to probe adapter implementation differences. 1533 */ 1534 u_char sv_scntl0, sv_scntl3, sv_dmode, sv_dcntl, sv_ctest3, sv_ctest4, 1535 sv_ctest5, sv_gpcntl, sv_stest2, sv_stest4, sv_scntl4, 1536 sv_stest1; 1537 1538 /* 1539 * Actual initial value of IO register bits used by the 1540 * driver. They are loaded at initialisation according to 1541 * features that are to be enabled/disabled. 1542 */ 1543 u_char rv_scntl0, rv_scntl3, rv_dmode, rv_dcntl, rv_ctest3, rv_ctest4, 1544 rv_ctest5, rv_stest2, rv_ccntl0, rv_ccntl1, rv_scntl4; 1545 1546 /* 1547 * Target data. 1548 */ 1549 struct sym_tcb target[SYM_CONF_MAX_TARGET]; 1550 1551 /* 1552 * Target control block bus address array used by the SCRIPT 1553 * on reselection. 1554 */ 1555 u32 *targtbl; 1556 u32 targtbl_ba; 1557 1558 /* 1559 * CAM SIM information for this instance. 1560 */ 1561 struct cam_sim *sim; 1562 struct cam_path *path; 1563 1564 /* 1565 * Allocated hardware resources. 1566 */ 1567 struct resource *irq_res; 1568 struct resource *io_res; 1569 struct resource *mmio_res; 1570 struct resource *ram_res; 1571 int ram_id; 1572 void *intr; 1573 1574 /* 1575 * Bus stuff. 1576 * 1577 * My understanding of PCI is that all agents must share the 1578 * same addressing range and model. 1579 * But some hardware architecture guys provide complex and 1580 * brain-deaded stuff that makes shit. 1581 * This driver only support PCI compliant implementations and 1582 * deals with part of the BUS stuff complexity only to fit O/S 1583 * requirements. 1584 */ 1585 bus_space_handle_t io_bsh; 1586 bus_space_tag_t io_tag; 1587 bus_space_handle_t mmio_bsh; 1588 bus_space_tag_t mmio_tag; 1589 bus_space_handle_t ram_bsh; 1590 bus_space_tag_t ram_tag; 1591 1592 /* 1593 * DMA stuff. 1594 */ 1595 bus_dma_tag_t bus_dmat; /* DMA tag from parent BUS */ 1596 bus_dma_tag_t data_dmat; /* DMA tag for user data */ 1597 /* 1598 * Virtual and physical bus addresses of the chip. 1599 */ 1600 vm_offset_t mmio_va; /* MMIO kernel virtual address */ 1601 vm_offset_t mmio_pa; /* MMIO CPU physical address */ 1602 vm_offset_t mmio_ba; /* MMIO BUS address */ 1603 int mmio_ws; /* MMIO Window size */ 1604 1605 vm_offset_t ram_va; /* RAM kernel virtual address */ 1606 vm_offset_t ram_pa; /* RAM CPU physical address */ 1607 vm_offset_t ram_ba; /* RAM BUS address */ 1608 int ram_ws; /* RAM window size */ 1609 u32 io_port; /* IO port address */ 1610 1611 /* 1612 * SCRIPTS virtual and physical bus addresses. 1613 * 'script' is loaded in the on-chip RAM if present. 1614 * 'scripth' stays in main memory for all chips except the 1615 * 53C895A, 53C896 and 53C1010 that provide 8K on-chip RAM. 1616 */ 1617 u_char *scripta0; /* Copies of script and scripth */ 1618 u_char *scriptb0; /* Copies of script and scripth */ 1619 vm_offset_t scripta_ba; /* Actual script and scripth */ 1620 vm_offset_t scriptb_ba; /* bus addresses. */ 1621 vm_offset_t scriptb0_ba; 1622 u_short scripta_sz; /* Actual size of script A */ 1623 u_short scriptb_sz; /* Actual size of script B */ 1624 1625 /* 1626 * Bus addresses, setup and patch methods for 1627 * the selected firmware. 1628 */ 1629 struct sym_fwa_ba fwa_bas; /* Useful SCRIPTA bus addresses */ 1630 struct sym_fwb_ba fwb_bas; /* Useful SCRIPTB bus addresses */ 1631 void (*fw_setup)(hcb_p np, struct sym_fw *fw); 1632 void (*fw_patch)(hcb_p np); 1633 char *fw_name; 1634 1635 /* 1636 * General controller parameters and configuration. 1637 */ 1638 u_short device_id; /* PCI device id */ 1639 u_char revision_id; /* PCI device revision id */ 1640 u_int features; /* Chip features map */ 1641 u_char myaddr; /* SCSI id of the adapter */ 1642 u_char maxburst; /* log base 2 of dwords burst */ 1643 u_char maxwide; /* Maximum transfer width */ 1644 u_char minsync; /* Min sync period factor (ST) */ 1645 u_char maxsync; /* Max sync period factor (ST) */ 1646 u_char maxoffs; /* Max scsi offset (ST) */ 1647 u_char minsync_dt; /* Min sync period factor (DT) */ 1648 u_char maxsync_dt; /* Max sync period factor (DT) */ 1649 u_char maxoffs_dt; /* Max scsi offset (DT) */ 1650 u_char multiplier; /* Clock multiplier (1,2,4) */ 1651 u_char clock_divn; /* Number of clock divisors */ 1652 u32 clock_khz; /* SCSI clock frequency in KHz */ 1653 u32 pciclk_khz; /* Estimated PCI clock in KHz */ 1654 /* 1655 * Start queue management. 1656 * It is filled up by the host processor and accessed by the 1657 * SCRIPTS processor in order to start SCSI commands. 1658 */ 1659 volatile /* Prevent code optimizations */ 1660 u32 *squeue; /* Start queue virtual address */ 1661 u32 squeue_ba; /* Start queue BUS address */ 1662 u_short squeueput; /* Next free slot of the queue */ 1663 u_short actccbs; /* Number of allocated CCBs */ 1664 1665 /* 1666 * Command completion queue. 1667 * It is the same size as the start queue to avoid overflow. 1668 */ 1669 u_short dqueueget; /* Next position to scan */ 1670 volatile /* Prevent code optimizations */ 1671 u32 *dqueue; /* Completion (done) queue */ 1672 u32 dqueue_ba; /* Done queue BUS address */ 1673 1674 /* 1675 * Miscellaneous buffers accessed by the scripts-processor. 1676 * They shall be DWORD aligned, because they may be read or 1677 * written with a script command. 1678 */ 1679 u_char msgout[8]; /* Buffer for MESSAGE OUT */ 1680 u_char msgin [8]; /* Buffer for MESSAGE IN */ 1681 u32 lastmsg; /* Last SCSI message sent */ 1682 u_char scratch; /* Scratch for SCSI receive */ 1683 1684 /* 1685 * Miscellaneous configuration and status parameters. 1686 */ 1687 u_char usrflags; /* Miscellaneous user flags */ 1688 u_char scsi_mode; /* Current SCSI BUS mode */ 1689 u_char verbose; /* Verbosity for this controller*/ 1690 u32 cache; /* Used for cache test at init. */ 1691 1692 /* 1693 * CCB lists and queue. 1694 */ 1695 ccb_p ccbh[CCB_HASH_SIZE]; /* CCB hashed by DSA value */ 1696 SYM_QUEHEAD free_ccbq; /* Queue of available CCBs */ 1697 SYM_QUEHEAD busy_ccbq; /* Queue of busy CCBs */ 1698 1699 /* 1700 * During error handling and/or recovery, 1701 * active CCBs that are to be completed with 1702 * error or requeued are moved from the busy_ccbq 1703 * to the comp_ccbq prior to completion. 1704 */ 1705 SYM_QUEHEAD comp_ccbq; 1706 1707 /* 1708 * CAM CCB pending queue. 1709 */ 1710 SYM_QUEHEAD cam_ccbq; 1711 1712 /* 1713 * IMMEDIATE ARBITRATION (IARB) control. 1714 * 1715 * We keep track in 'last_cp' of the last CCB that has been 1716 * queued to the SCRIPTS processor and clear 'last_cp' when 1717 * this CCB completes. If last_cp is not zero at the moment 1718 * we queue a new CCB, we set a flag in 'last_cp' that is 1719 * used by the SCRIPTS as a hint for setting IARB. 1720 * We donnot set more than 'iarb_max' consecutive hints for 1721 * IARB in order to leave devices a chance to reselect. 1722 * By the way, any non zero value of 'iarb_max' is unfair. :) 1723 */ 1724 #ifdef SYM_CONF_IARB_SUPPORT 1725 u_short iarb_max; /* Max. # consecutive IARB hints*/ 1726 u_short iarb_count; /* Actual # of these hints */ 1727 ccb_p last_cp; 1728 #endif 1729 1730 /* 1731 * Command abort handling. 1732 * We need to synchronize tightly with the SCRIPTS 1733 * processor in order to handle things correctly. 1734 */ 1735 u_char abrt_msg[4]; /* Message to send buffer */ 1736 struct sym_tblmove abrt_tbl; /* Table for the MOV of it */ 1737 struct sym_tblsel abrt_sel; /* Sync params for selection */ 1738 u_char istat_sem; /* Tells the chip to stop (SEM) */ 1739 }; 1740 1741 #define HCB_BA(np, lbl) (np->hcb_ba + offsetof(struct sym_hcb, lbl)) 1742 1743 /* 1744 * Return the name of the controller. 1745 */ 1746 static __inline char *sym_name(hcb_p np) 1747 { 1748 return np->inst_name; 1749 } 1750 1751 /*--------------------------------------------------------------------------*/ 1752 /*------------------------------ FIRMWARES ---------------------------------*/ 1753 /*--------------------------------------------------------------------------*/ 1754 1755 /* 1756 * This stuff will be moved to a separate source file when 1757 * the driver will be broken into several source modules. 1758 */ 1759 1760 /* 1761 * Macros used for all firmwares. 1762 */ 1763 #define SYM_GEN_A(s, label) ((short) offsetof(s, label)), 1764 #define SYM_GEN_B(s, label) ((short) offsetof(s, label)), 1765 #define PADDR_A(label) SYM_GEN_PADDR_A(struct SYM_FWA_SCR, label) 1766 #define PADDR_B(label) SYM_GEN_PADDR_B(struct SYM_FWB_SCR, label) 1767 1768 1769 #ifdef SYM_CONF_GENERIC_SUPPORT 1770 /* 1771 * Allocate firmware #1 script area. 1772 */ 1773 #define SYM_FWA_SCR sym_fw1a_scr 1774 #define SYM_FWB_SCR sym_fw1b_scr 1775 #include <dev/sym/sym_fw1.h> 1776 struct sym_fwa_ofs sym_fw1a_ofs = { 1777 SYM_GEN_FW_A(struct SYM_FWA_SCR) 1778 }; 1779 struct sym_fwb_ofs sym_fw1b_ofs = { 1780 SYM_GEN_FW_B(struct SYM_FWB_SCR) 1781 }; 1782 #undef SYM_FWA_SCR 1783 #undef SYM_FWB_SCR 1784 #endif /* SYM_CONF_GENERIC_SUPPORT */ 1785 1786 /* 1787 * Allocate firmware #2 script area. 1788 */ 1789 #define SYM_FWA_SCR sym_fw2a_scr 1790 #define SYM_FWB_SCR sym_fw2b_scr 1791 #include <dev/sym/sym_fw2.h> 1792 struct sym_fwa_ofs sym_fw2a_ofs = { 1793 SYM_GEN_FW_A(struct SYM_FWA_SCR) 1794 }; 1795 struct sym_fwb_ofs sym_fw2b_ofs = { 1796 SYM_GEN_FW_B(struct SYM_FWB_SCR) 1797 SYM_GEN_B(struct SYM_FWB_SCR, start64) 1798 SYM_GEN_B(struct SYM_FWB_SCR, pm_handle) 1799 }; 1800 #undef SYM_FWA_SCR 1801 #undef SYM_FWB_SCR 1802 1803 #undef SYM_GEN_A 1804 #undef SYM_GEN_B 1805 #undef PADDR_A 1806 #undef PADDR_B 1807 1808 #ifdef SYM_CONF_GENERIC_SUPPORT 1809 /* 1810 * Patch routine for firmware #1. 1811 */ 1812 static void 1813 sym_fw1_patch(hcb_p np) 1814 { 1815 struct sym_fw1a_scr *scripta0; 1816 struct sym_fw1b_scr *scriptb0; 1817 1818 scripta0 = (struct sym_fw1a_scr *) np->scripta0; 1819 scriptb0 = (struct sym_fw1b_scr *) np->scriptb0; 1820 1821 /* 1822 * Remove LED support if not needed. 1823 */ 1824 if (!(np->features & FE_LED0)) { 1825 scripta0->idle[0] = cpu_to_scr(SCR_NO_OP); 1826 scripta0->reselected[0] = cpu_to_scr(SCR_NO_OP); 1827 scripta0->start[0] = cpu_to_scr(SCR_NO_OP); 1828 } 1829 1830 #ifdef SYM_CONF_IARB_SUPPORT 1831 /* 1832 * If user does not want to use IMMEDIATE ARBITRATION 1833 * when we are reselected while attempting to arbitrate, 1834 * patch the SCRIPTS accordingly with a SCRIPT NO_OP. 1835 */ 1836 if (!SYM_CONF_SET_IARB_ON_ARB_LOST) 1837 scripta0->ungetjob[0] = cpu_to_scr(SCR_NO_OP); 1838 #endif 1839 /* 1840 * Patch some data in SCRIPTS. 1841 * - start and done queue initial bus address. 1842 * - target bus address table bus address. 1843 */ 1844 scriptb0->startpos[0] = cpu_to_scr(np->squeue_ba); 1845 scriptb0->done_pos[0] = cpu_to_scr(np->dqueue_ba); 1846 scriptb0->targtbl[0] = cpu_to_scr(np->targtbl_ba); 1847 } 1848 #endif /* SYM_CONF_GENERIC_SUPPORT */ 1849 1850 /* 1851 * Patch routine for firmware #2. 1852 */ 1853 static void 1854 sym_fw2_patch(hcb_p np) 1855 { 1856 struct sym_fw2a_scr *scripta0; 1857 struct sym_fw2b_scr *scriptb0; 1858 1859 scripta0 = (struct sym_fw2a_scr *) np->scripta0; 1860 scriptb0 = (struct sym_fw2b_scr *) np->scriptb0; 1861 1862 /* 1863 * Remove LED support if not needed. 1864 */ 1865 if (!(np->features & FE_LED0)) { 1866 scripta0->idle[0] = cpu_to_scr(SCR_NO_OP); 1867 scripta0->reselected[0] = cpu_to_scr(SCR_NO_OP); 1868 scripta0->start[0] = cpu_to_scr(SCR_NO_OP); 1869 } 1870 1871 #ifdef SYM_CONF_IARB_SUPPORT 1872 /* 1873 * If user does not want to use IMMEDIATE ARBITRATION 1874 * when we are reselected while attempting to arbitrate, 1875 * patch the SCRIPTS accordingly with a SCRIPT NO_OP. 1876 */ 1877 if (!SYM_CONF_SET_IARB_ON_ARB_LOST) 1878 scripta0->ungetjob[0] = cpu_to_scr(SCR_NO_OP); 1879 #endif 1880 /* 1881 * Patch some variable in SCRIPTS. 1882 * - start and done queue initial bus address. 1883 * - target bus address table bus address. 1884 */ 1885 scriptb0->startpos[0] = cpu_to_scr(np->squeue_ba); 1886 scriptb0->done_pos[0] = cpu_to_scr(np->dqueue_ba); 1887 scriptb0->targtbl[0] = cpu_to_scr(np->targtbl_ba); 1888 1889 /* 1890 * Remove the load of SCNTL4 on reselection if not a C10. 1891 */ 1892 if (!(np->features & FE_C10)) { 1893 scripta0->resel_scntl4[0] = cpu_to_scr(SCR_NO_OP); 1894 scripta0->resel_scntl4[1] = cpu_to_scr(0); 1895 } 1896 1897 /* 1898 * Remove a couple of work-arounds specific to C1010 if 1899 * they are not desirable. See `sym_fw2.h' for more details. 1900 */ 1901 if (!(np->device_id == PCI_ID_LSI53C1010_2 && 1902 np->revision_id < 0x1 && 1903 np->pciclk_khz < 60000)) { 1904 scripta0->datao_phase[0] = cpu_to_scr(SCR_NO_OP); 1905 scripta0->datao_phase[1] = cpu_to_scr(0); 1906 } 1907 if (!(np->device_id == PCI_ID_LSI53C1010 && 1908 /* np->revision_id < 0xff */ 1)) { 1909 scripta0->sel_done[0] = cpu_to_scr(SCR_NO_OP); 1910 scripta0->sel_done[1] = cpu_to_scr(0); 1911 } 1912 1913 /* 1914 * Patch some other variables in SCRIPTS. 1915 * These ones are loaded by the SCRIPTS processor. 1916 */ 1917 scriptb0->pm0_data_addr[0] = 1918 cpu_to_scr(np->scripta_ba + 1919 offsetof(struct sym_fw2a_scr, pm0_data)); 1920 scriptb0->pm1_data_addr[0] = 1921 cpu_to_scr(np->scripta_ba + 1922 offsetof(struct sym_fw2a_scr, pm1_data)); 1923 } 1924 1925 /* 1926 * Fill the data area in scripts. 1927 * To be done for all firmwares. 1928 */ 1929 static void 1930 sym_fw_fill_data (u32 *in, u32 *out) 1931 { 1932 int i; 1933 1934 for (i = 0; i < SYM_CONF_MAX_SG; i++) { 1935 *in++ = SCR_CHMOV_TBL ^ SCR_DATA_IN; 1936 *in++ = offsetof (struct sym_dsb, data[i]); 1937 *out++ = SCR_CHMOV_TBL ^ SCR_DATA_OUT; 1938 *out++ = offsetof (struct sym_dsb, data[i]); 1939 } 1940 } 1941 1942 /* 1943 * Setup useful script bus addresses. 1944 * To be done for all firmwares. 1945 */ 1946 static void 1947 sym_fw_setup_bus_addresses(hcb_p np, struct sym_fw *fw) 1948 { 1949 u32 *pa; 1950 u_short *po; 1951 int i; 1952 1953 /* 1954 * Build the bus address table for script A 1955 * from the script A offset table. 1956 */ 1957 po = (u_short *) fw->a_ofs; 1958 pa = (u32 *) &np->fwa_bas; 1959 for (i = 0 ; i < sizeof(np->fwa_bas)/sizeof(u32) ; i++) 1960 pa[i] = np->scripta_ba + po[i]; 1961 1962 /* 1963 * Same for script B. 1964 */ 1965 po = (u_short *) fw->b_ofs; 1966 pa = (u32 *) &np->fwb_bas; 1967 for (i = 0 ; i < sizeof(np->fwb_bas)/sizeof(u32) ; i++) 1968 pa[i] = np->scriptb_ba + po[i]; 1969 } 1970 1971 #ifdef SYM_CONF_GENERIC_SUPPORT 1972 /* 1973 * Setup routine for firmware #1. 1974 */ 1975 static void 1976 sym_fw1_setup(hcb_p np, struct sym_fw *fw) 1977 { 1978 struct sym_fw1a_scr *scripta0; 1979 struct sym_fw1b_scr *scriptb0; 1980 1981 scripta0 = (struct sym_fw1a_scr *) np->scripta0; 1982 scriptb0 = (struct sym_fw1b_scr *) np->scriptb0; 1983 1984 /* 1985 * Fill variable parts in scripts. 1986 */ 1987 sym_fw_fill_data(scripta0->data_in, scripta0->data_out); 1988 1989 /* 1990 * Setup bus addresses used from the C code.. 1991 */ 1992 sym_fw_setup_bus_addresses(np, fw); 1993 } 1994 #endif /* SYM_CONF_GENERIC_SUPPORT */ 1995 1996 /* 1997 * Setup routine for firmware #2. 1998 */ 1999 static void 2000 sym_fw2_setup(hcb_p np, struct sym_fw *fw) 2001 { 2002 struct sym_fw2a_scr *scripta0; 2003 struct sym_fw2b_scr *scriptb0; 2004 2005 scripta0 = (struct sym_fw2a_scr *) np->scripta0; 2006 scriptb0 = (struct sym_fw2b_scr *) np->scriptb0; 2007 2008 /* 2009 * Fill variable parts in scripts. 2010 */ 2011 sym_fw_fill_data(scripta0->data_in, scripta0->data_out); 2012 2013 /* 2014 * Setup bus addresses used from the C code.. 2015 */ 2016 sym_fw_setup_bus_addresses(np, fw); 2017 } 2018 2019 /* 2020 * Allocate firmware descriptors. 2021 */ 2022 #ifdef SYM_CONF_GENERIC_SUPPORT 2023 static struct sym_fw sym_fw1 = SYM_FW_ENTRY(sym_fw1, "NCR-generic"); 2024 #endif /* SYM_CONF_GENERIC_SUPPORT */ 2025 static struct sym_fw sym_fw2 = SYM_FW_ENTRY(sym_fw2, "LOAD/STORE-based"); 2026 2027 /* 2028 * Find the most appropriate firmware for a chip. 2029 */ 2030 static struct sym_fw * 2031 sym_find_firmware(struct sym_pci_chip *chip) 2032 { 2033 if (chip->features & FE_LDSTR) 2034 return &sym_fw2; 2035 #ifdef SYM_CONF_GENERIC_SUPPORT 2036 else if (!(chip->features & (FE_PFEN|FE_NOPM|FE_DAC))) 2037 return &sym_fw1; 2038 #endif 2039 else 2040 return 0; 2041 } 2042 2043 /* 2044 * Bind a script to physical addresses. 2045 */ 2046 static void sym_fw_bind_script (hcb_p np, u32 *start, int len) 2047 { 2048 u32 opcode, new, old, tmp1, tmp2; 2049 u32 *end, *cur; 2050 int relocs; 2051 2052 cur = start; 2053 end = start + len/4; 2054 2055 while (cur < end) { 2056 2057 opcode = *cur; 2058 2059 /* 2060 * If we forget to change the length 2061 * in scripts, a field will be 2062 * padded with 0. This is an illegal 2063 * command. 2064 */ 2065 if (opcode == 0) { 2066 printf ("%s: ERROR0 IN SCRIPT at %d.\n", 2067 sym_name(np), (int) (cur-start)); 2068 MDELAY (10000); 2069 ++cur; 2070 continue; 2071 }; 2072 2073 /* 2074 * We use the bogus value 0xf00ff00f ;-) 2075 * to reserve data area in SCRIPTS. 2076 */ 2077 if (opcode == SCR_DATA_ZERO) { 2078 *cur++ = 0; 2079 continue; 2080 } 2081 2082 if (DEBUG_FLAGS & DEBUG_SCRIPT) 2083 printf ("%d: <%x>\n", (int) (cur-start), 2084 (unsigned)opcode); 2085 2086 /* 2087 * We don't have to decode ALL commands 2088 */ 2089 switch (opcode >> 28) { 2090 case 0xf: 2091 /* 2092 * LOAD / STORE DSA relative, don't relocate. 2093 */ 2094 relocs = 0; 2095 break; 2096 case 0xe: 2097 /* 2098 * LOAD / STORE absolute. 2099 */ 2100 relocs = 1; 2101 break; 2102 case 0xc: 2103 /* 2104 * COPY has TWO arguments. 2105 */ 2106 relocs = 2; 2107 tmp1 = cur[1]; 2108 tmp2 = cur[2]; 2109 if ((tmp1 ^ tmp2) & 3) { 2110 printf ("%s: ERROR1 IN SCRIPT at %d.\n", 2111 sym_name(np), (int) (cur-start)); 2112 MDELAY (10000); 2113 } 2114 /* 2115 * If PREFETCH feature not enabled, remove 2116 * the NO FLUSH bit if present. 2117 */ 2118 if ((opcode & SCR_NO_FLUSH) && 2119 !(np->features & FE_PFEN)) { 2120 opcode = (opcode & ~SCR_NO_FLUSH); 2121 } 2122 break; 2123 case 0x0: 2124 /* 2125 * MOVE/CHMOV (absolute address) 2126 */ 2127 if (!(np->features & FE_WIDE)) 2128 opcode = (opcode | OPC_MOVE); 2129 relocs = 1; 2130 break; 2131 case 0x1: 2132 /* 2133 * MOVE/CHMOV (table indirect) 2134 */ 2135 if (!(np->features & FE_WIDE)) 2136 opcode = (opcode | OPC_MOVE); 2137 relocs = 0; 2138 break; 2139 case 0x8: 2140 /* 2141 * JUMP / CALL 2142 * dont't relocate if relative :-) 2143 */ 2144 if (opcode & 0x00800000) 2145 relocs = 0; 2146 else if ((opcode & 0xf8400000) == 0x80400000)/*JUMP64*/ 2147 relocs = 2; 2148 else 2149 relocs = 1; 2150 break; 2151 case 0x4: 2152 case 0x5: 2153 case 0x6: 2154 case 0x7: 2155 relocs = 1; 2156 break; 2157 default: 2158 relocs = 0; 2159 break; 2160 }; 2161 2162 /* 2163 * Scriptify:) the opcode. 2164 */ 2165 *cur++ = cpu_to_scr(opcode); 2166 2167 /* 2168 * If no relocation, assume 1 argument 2169 * and just scriptize:) it. 2170 */ 2171 if (!relocs) { 2172 *cur = cpu_to_scr(*cur); 2173 ++cur; 2174 continue; 2175 } 2176 2177 /* 2178 * Otherwise performs all needed relocations. 2179 */ 2180 while (relocs--) { 2181 old = *cur; 2182 2183 switch (old & RELOC_MASK) { 2184 case RELOC_REGISTER: 2185 new = (old & ~RELOC_MASK) + np->mmio_ba; 2186 break; 2187 case RELOC_LABEL_A: 2188 new = (old & ~RELOC_MASK) + np->scripta_ba; 2189 break; 2190 case RELOC_LABEL_B: 2191 new = (old & ~RELOC_MASK) + np->scriptb_ba; 2192 break; 2193 case RELOC_SOFTC: 2194 new = (old & ~RELOC_MASK) + np->hcb_ba; 2195 break; 2196 case 0: 2197 /* 2198 * Don't relocate a 0 address. 2199 * They are mostly used for patched or 2200 * script self-modified areas. 2201 */ 2202 if (old == 0) { 2203 new = old; 2204 break; 2205 } 2206 /* fall through */ 2207 default: 2208 new = 0; 2209 panic("sym_fw_bind_script: " 2210 "weird relocation %x\n", old); 2211 break; 2212 } 2213 2214 *cur++ = cpu_to_scr(new); 2215 } 2216 }; 2217 } 2218 2219 /*--------------------------------------------------------------------------*/ 2220 /*--------------------------- END OF FIRMARES -----------------------------*/ 2221 /*--------------------------------------------------------------------------*/ 2222 2223 /* 2224 * Function prototypes. 2225 */ 2226 static void sym_save_initial_setting (hcb_p np); 2227 static int sym_prepare_setting (hcb_p np, struct sym_nvram *nvram); 2228 static int sym_prepare_nego (hcb_p np, ccb_p cp, int nego, u_char *msgptr); 2229 static void sym_put_start_queue (hcb_p np, ccb_p cp); 2230 static void sym_chip_reset (hcb_p np); 2231 static void sym_soft_reset (hcb_p np); 2232 static void sym_start_reset (hcb_p np); 2233 static int sym_reset_scsi_bus (hcb_p np, int enab_int); 2234 static int sym_wakeup_done (hcb_p np); 2235 static void sym_flush_busy_queue (hcb_p np, int cam_status); 2236 static void sym_flush_comp_queue (hcb_p np, int cam_status); 2237 static void sym_init (hcb_p np, int reason); 2238 static int sym_getsync(hcb_p np, u_char dt, u_char sfac, u_char *divp, 2239 u_char *fakp); 2240 static void sym_setsync (hcb_p np, ccb_p cp, u_char ofs, u_char per, 2241 u_char div, u_char fak); 2242 static void sym_setwide (hcb_p np, ccb_p cp, u_char wide); 2243 static void sym_setpprot(hcb_p np, ccb_p cp, u_char dt, u_char ofs, 2244 u_char per, u_char wide, u_char div, u_char fak); 2245 static void sym_settrans(hcb_p np, ccb_p cp, u_char dt, u_char ofs, 2246 u_char per, u_char wide, u_char div, u_char fak); 2247 static void sym_log_hard_error (hcb_p np, u_short sist, u_char dstat); 2248 static void sym_intr (void *arg); 2249 static void sym_poll (struct cam_sim *sim); 2250 static void sym_recover_scsi_int (hcb_p np, u_char hsts); 2251 static void sym_int_sto (hcb_p np); 2252 static void sym_int_udc (hcb_p np); 2253 static void sym_int_sbmc (hcb_p np); 2254 static void sym_int_par (hcb_p np, u_short sist); 2255 static void sym_int_ma (hcb_p np); 2256 static int sym_dequeue_from_squeue(hcb_p np, int i, int target, int lun, 2257 int task); 2258 static void sym_sir_bad_scsi_status (hcb_p np, int num, ccb_p cp); 2259 static int sym_clear_tasks (hcb_p np, int status, int targ, int lun, int task); 2260 static void sym_sir_task_recovery (hcb_p np, int num); 2261 static int sym_evaluate_dp (hcb_p np, ccb_p cp, u32 scr, int *ofs); 2262 static void sym_modify_dp (hcb_p np, tcb_p tp, ccb_p cp, int ofs); 2263 static int sym_compute_residual (hcb_p np, ccb_p cp); 2264 static int sym_show_msg (u_char * msg); 2265 static void sym_print_msg (ccb_p cp, char *label, u_char *msg); 2266 static void sym_sync_nego (hcb_p np, tcb_p tp, ccb_p cp); 2267 static void sym_ppr_nego (hcb_p np, tcb_p tp, ccb_p cp); 2268 static void sym_wide_nego (hcb_p np, tcb_p tp, ccb_p cp); 2269 static void sym_nego_default (hcb_p np, tcb_p tp, ccb_p cp); 2270 static void sym_nego_rejected (hcb_p np, tcb_p tp, ccb_p cp); 2271 static void sym_int_sir (hcb_p np); 2272 static void sym_free_ccb (hcb_p np, ccb_p cp); 2273 static ccb_p sym_get_ccb (hcb_p np, u_char tn, u_char ln, u_char tag_order); 2274 static ccb_p sym_alloc_ccb (hcb_p np); 2275 static ccb_p sym_ccb_from_dsa (hcb_p np, u32 dsa); 2276 static lcb_p sym_alloc_lcb (hcb_p np, u_char tn, u_char ln); 2277 static void sym_alloc_lcb_tags (hcb_p np, u_char tn, u_char ln); 2278 static int sym_snooptest (hcb_p np); 2279 static void sym_selectclock(hcb_p np, u_char scntl3); 2280 static void sym_getclock (hcb_p np, int mult); 2281 static int sym_getpciclock (hcb_p np); 2282 static void sym_complete_ok (hcb_p np, ccb_p cp); 2283 static void sym_complete_error (hcb_p np, ccb_p cp); 2284 static void sym_timeout (void *arg); 2285 static int sym_abort_scsiio (hcb_p np, union ccb *ccb, int timed_out); 2286 static void sym_reset_dev (hcb_p np, union ccb *ccb); 2287 static void sym_action (struct cam_sim *sim, union ccb *ccb); 2288 static void sym_action1 (struct cam_sim *sim, union ccb *ccb); 2289 static int sym_setup_cdb (hcb_p np, struct ccb_scsiio *csio, ccb_p cp); 2290 static void sym_setup_data_and_start (hcb_p np, struct ccb_scsiio *csio, 2291 ccb_p cp); 2292 static int sym_fast_scatter_sg_physical(hcb_p np, ccb_p cp, 2293 bus_dma_segment_t *psegs, int nsegs); 2294 static int sym_scatter_sg_physical (hcb_p np, ccb_p cp, 2295 bus_dma_segment_t *psegs, int nsegs); 2296 static void sym_action2 (struct cam_sim *sim, union ccb *ccb); 2297 static void sym_update_trans (hcb_p np, tcb_p tp, struct sym_trans *tip, 2298 struct ccb_trans_settings *cts); 2299 static void sym_update_dflags(hcb_p np, u_char *flags, 2300 struct ccb_trans_settings *cts); 2301 2302 static struct sym_pci_chip *sym_find_pci_chip (device_t dev); 2303 static int sym_pci_probe (device_t dev); 2304 static int sym_pci_attach (device_t dev); 2305 2306 static void sym_pci_free (hcb_p np); 2307 static int sym_cam_attach (hcb_p np); 2308 static void sym_cam_free (hcb_p np); 2309 2310 static void sym_nvram_setup_host (hcb_p np, struct sym_nvram *nvram); 2311 static void sym_nvram_setup_target (hcb_p np, int targ, struct sym_nvram *nvp); 2312 static int sym_read_nvram (hcb_p np, struct sym_nvram *nvp); 2313 2314 /* 2315 * Print something which allows to retrieve the controler type, 2316 * unit, target, lun concerned by a kernel message. 2317 */ 2318 static void PRINT_TARGET (hcb_p np, int target) 2319 { 2320 printf ("%s:%d:", sym_name(np), target); 2321 } 2322 2323 static void PRINT_LUN(hcb_p np, int target, int lun) 2324 { 2325 printf ("%s:%d:%d:", sym_name(np), target, lun); 2326 } 2327 2328 static void PRINT_ADDR (ccb_p cp) 2329 { 2330 if (cp && cp->cam_ccb) 2331 xpt_print_path(cp->cam_ccb->ccb_h.path); 2332 } 2333 2334 /* 2335 * Take into account this ccb in the freeze count. 2336 */ 2337 static void sym_freeze_cam_ccb(union ccb *ccb) 2338 { 2339 if (!(ccb->ccb_h.flags & CAM_DEV_QFRZDIS)) { 2340 if (!(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 2341 ccb->ccb_h.status |= CAM_DEV_QFRZN; 2342 xpt_freeze_devq(ccb->ccb_h.path, 1); 2343 } 2344 } 2345 } 2346 2347 /* 2348 * Set the status field of a CAM CCB. 2349 */ 2350 static __inline void sym_set_cam_status(union ccb *ccb, cam_status status) 2351 { 2352 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2353 ccb->ccb_h.status |= status; 2354 } 2355 2356 /* 2357 * Get the status field of a CAM CCB. 2358 */ 2359 static __inline int sym_get_cam_status(union ccb *ccb) 2360 { 2361 return ccb->ccb_h.status & CAM_STATUS_MASK; 2362 } 2363 2364 /* 2365 * Enqueue a CAM CCB. 2366 */ 2367 static void sym_enqueue_cam_ccb(hcb_p np, union ccb *ccb) 2368 { 2369 assert(!(ccb->ccb_h.status & CAM_SIM_QUEUED)); 2370 ccb->ccb_h.status = CAM_REQ_INPROG; 2371 2372 ccb->ccb_h.timeout_ch = timeout(sym_timeout, (caddr_t) ccb, 2373 ccb->ccb_h.timeout*hz/1000); 2374 ccb->ccb_h.status |= CAM_SIM_QUEUED; 2375 ccb->ccb_h.sym_hcb_ptr = np; 2376 2377 sym_insque_tail(sym_qptr(&ccb->ccb_h.sim_links), &np->cam_ccbq); 2378 } 2379 2380 /* 2381 * Complete a pending CAM CCB. 2382 */ 2383 static void sym_xpt_done(hcb_p np, union ccb *ccb) 2384 { 2385 if (ccb->ccb_h.status & CAM_SIM_QUEUED) { 2386 untimeout(sym_timeout, (caddr_t) ccb, ccb->ccb_h.timeout_ch); 2387 sym_remque(sym_qptr(&ccb->ccb_h.sim_links)); 2388 ccb->ccb_h.status &= ~CAM_SIM_QUEUED; 2389 ccb->ccb_h.sym_hcb_ptr = 0; 2390 } 2391 if (ccb->ccb_h.flags & CAM_DEV_QFREEZE) 2392 sym_freeze_cam_ccb(ccb); 2393 xpt_done(ccb); 2394 } 2395 2396 static void sym_xpt_done2(hcb_p np, union ccb *ccb, int cam_status) 2397 { 2398 sym_set_cam_status(ccb, cam_status); 2399 sym_xpt_done(np, ccb); 2400 } 2401 2402 /* 2403 * SYMBIOS chip clock divisor table. 2404 * 2405 * Divisors are multiplied by 10,000,000 in order to make 2406 * calculations more simple. 2407 */ 2408 #define _5M 5000000 2409 static u32 div_10M[] = {2*_5M, 3*_5M, 4*_5M, 6*_5M, 8*_5M, 12*_5M, 16*_5M}; 2410 2411 /* 2412 * SYMBIOS chips allow burst lengths of 2, 4, 8, 16, 32, 64, 2413 * 128 transfers. All chips support at least 16 transfers 2414 * bursts. The 825A, 875 and 895 chips support bursts of up 2415 * to 128 transfers and the 895A and 896 support bursts of up 2416 * to 64 transfers. All other chips support up to 16 2417 * transfers bursts. 2418 * 2419 * For PCI 32 bit data transfers each transfer is a DWORD. 2420 * It is a QUADWORD (8 bytes) for PCI 64 bit data transfers. 2421 * 2422 * We use log base 2 (burst length) as internal code, with 2423 * value 0 meaning "burst disabled". 2424 */ 2425 2426 /* 2427 * Burst length from burst code. 2428 */ 2429 #define burst_length(bc) (!(bc))? 0 : 1 << (bc) 2430 2431 /* 2432 * Burst code from io register bits. 2433 */ 2434 #define burst_code(dmode, ctest4, ctest5) \ 2435 (ctest4) & 0x80? 0 : (((dmode) & 0xc0) >> 6) + ((ctest5) & 0x04) + 1 2436 2437 /* 2438 * Set initial io register bits from burst code. 2439 */ 2440 static __inline void sym_init_burst(hcb_p np, u_char bc) 2441 { 2442 np->rv_ctest4 &= ~0x80; 2443 np->rv_dmode &= ~(0x3 << 6); 2444 np->rv_ctest5 &= ~0x4; 2445 2446 if (!bc) { 2447 np->rv_ctest4 |= 0x80; 2448 } 2449 else { 2450 --bc; 2451 np->rv_dmode |= ((bc & 0x3) << 6); 2452 np->rv_ctest5 |= (bc & 0x4); 2453 } 2454 } 2455 2456 2457 /* 2458 * Print out the list of targets that have some flag disabled by user. 2459 */ 2460 static void sym_print_targets_flag(hcb_p np, int mask, char *msg) 2461 { 2462 int cnt; 2463 int i; 2464 2465 for (cnt = 0, i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) { 2466 if (i == np->myaddr) 2467 continue; 2468 if (np->target[i].usrflags & mask) { 2469 if (!cnt++) 2470 printf("%s: %s disabled for targets", 2471 sym_name(np), msg); 2472 printf(" %d", i); 2473 } 2474 } 2475 if (cnt) 2476 printf(".\n"); 2477 } 2478 2479 /* 2480 * Save initial settings of some IO registers. 2481 * Assumed to have been set by BIOS. 2482 * We cannot reset the chip prior to reading the 2483 * IO registers, since informations will be lost. 2484 * Since the SCRIPTS processor may be running, this 2485 * is not safe on paper, but it seems to work quite 2486 * well. :) 2487 */ 2488 static void sym_save_initial_setting (hcb_p np) 2489 { 2490 np->sv_scntl0 = INB(nc_scntl0) & 0x0a; 2491 np->sv_scntl3 = INB(nc_scntl3) & 0x07; 2492 np->sv_dmode = INB(nc_dmode) & 0xce; 2493 np->sv_dcntl = INB(nc_dcntl) & 0xa8; 2494 np->sv_ctest3 = INB(nc_ctest3) & 0x01; 2495 np->sv_ctest4 = INB(nc_ctest4) & 0x80; 2496 np->sv_gpcntl = INB(nc_gpcntl); 2497 np->sv_stest1 = INB(nc_stest1); 2498 np->sv_stest2 = INB(nc_stest2) & 0x20; 2499 np->sv_stest4 = INB(nc_stest4); 2500 if (np->features & FE_C10) { /* Always large DMA fifo + ultra3 */ 2501 np->sv_scntl4 = INB(nc_scntl4); 2502 np->sv_ctest5 = INB(nc_ctest5) & 0x04; 2503 } 2504 else 2505 np->sv_ctest5 = INB(nc_ctest5) & 0x24; 2506 } 2507 2508 /* 2509 * Prepare io register values used by sym_init() according 2510 * to selected and supported features. 2511 */ 2512 static int sym_prepare_setting(hcb_p np, struct sym_nvram *nvram) 2513 { 2514 u_char burst_max; 2515 u32 period; 2516 int i; 2517 2518 /* 2519 * Wide ? 2520 */ 2521 np->maxwide = (np->features & FE_WIDE)? 1 : 0; 2522 2523 /* 2524 * Get the frequency of the chip's clock. 2525 */ 2526 if (np->features & FE_QUAD) 2527 np->multiplier = 4; 2528 else if (np->features & FE_DBLR) 2529 np->multiplier = 2; 2530 else 2531 np->multiplier = 1; 2532 2533 np->clock_khz = (np->features & FE_CLK80)? 80000 : 40000; 2534 np->clock_khz *= np->multiplier; 2535 2536 if (np->clock_khz != 40000) 2537 sym_getclock(np, np->multiplier); 2538 2539 /* 2540 * Divisor to be used for async (timer pre-scaler). 2541 */ 2542 i = np->clock_divn - 1; 2543 while (--i >= 0) { 2544 if (10ul * SYM_CONF_MIN_ASYNC * np->clock_khz > div_10M[i]) { 2545 ++i; 2546 break; 2547 } 2548 } 2549 np->rv_scntl3 = i+1; 2550 2551 /* 2552 * The C1010 uses hardwired divisors for async. 2553 * So, we just throw away, the async. divisor.:-) 2554 */ 2555 if (np->features & FE_C10) 2556 np->rv_scntl3 = 0; 2557 2558 /* 2559 * Minimum synchronous period factor supported by the chip. 2560 * Btw, 'period' is in tenths of nanoseconds. 2561 */ 2562 period = (4 * div_10M[0] + np->clock_khz - 1) / np->clock_khz; 2563 if (period <= 250) np->minsync = 10; 2564 else if (period <= 303) np->minsync = 11; 2565 else if (period <= 500) np->minsync = 12; 2566 else np->minsync = (period + 40 - 1) / 40; 2567 2568 /* 2569 * Check against chip SCSI standard support (SCSI-2,ULTRA,ULTRA2). 2570 */ 2571 if (np->minsync < 25 && 2572 !(np->features & (FE_ULTRA|FE_ULTRA2|FE_ULTRA3))) 2573 np->minsync = 25; 2574 else if (np->minsync < 12 && 2575 !(np->features & (FE_ULTRA2|FE_ULTRA3))) 2576 np->minsync = 12; 2577 2578 /* 2579 * Maximum synchronous period factor supported by the chip. 2580 */ 2581 period = (11 * div_10M[np->clock_divn - 1]) / (4 * np->clock_khz); 2582 np->maxsync = period > 2540 ? 254 : period / 10; 2583 2584 /* 2585 * If chip is a C1010, guess the sync limits in DT mode. 2586 */ 2587 if ((np->features & (FE_C10|FE_ULTRA3)) == (FE_C10|FE_ULTRA3)) { 2588 if (np->clock_khz == 160000) { 2589 np->minsync_dt = 9; 2590 np->maxsync_dt = 50; 2591 np->maxoffs_dt = 62; 2592 } 2593 } 2594 2595 /* 2596 * 64 bit addressing (895A/896/1010) ? 2597 */ 2598 if (np->features & FE_DAC) 2599 #ifdef __LP64__ 2600 np->rv_ccntl1 |= (XTIMOD | EXTIBMV); 2601 #else 2602 np->rv_ccntl1 |= (DDAC); 2603 #endif 2604 2605 /* 2606 * Phase mismatch handled by SCRIPTS (895A/896/1010) ? 2607 */ 2608 if (np->features & FE_NOPM) 2609 np->rv_ccntl0 |= (ENPMJ); 2610 2611 /* 2612 * C1010 Errata. 2613 * In dual channel mode, contention occurs if internal cycles 2614 * are used. Disable internal cycles. 2615 */ 2616 if (np->device_id == PCI_ID_LSI53C1010 && 2617 np->revision_id < 0x2) 2618 np->rv_ccntl0 |= DILS; 2619 2620 /* 2621 * Select burst length (dwords) 2622 */ 2623 burst_max = SYM_SETUP_BURST_ORDER; 2624 if (burst_max == 255) 2625 burst_max = burst_code(np->sv_dmode, np->sv_ctest4, 2626 np->sv_ctest5); 2627 if (burst_max > 7) 2628 burst_max = 7; 2629 if (burst_max > np->maxburst) 2630 burst_max = np->maxburst; 2631 2632 /* 2633 * DEL 352 - 53C810 Rev x11 - Part Number 609-0392140 - ITEM 2. 2634 * This chip and the 860 Rev 1 may wrongly use PCI cache line 2635 * based transactions on LOAD/STORE instructions. So we have 2636 * to prevent these chips from using such PCI transactions in 2637 * this driver. The generic ncr driver that does not use 2638 * LOAD/STORE instructions does not need this work-around. 2639 */ 2640 if ((np->device_id == PCI_ID_SYM53C810 && 2641 np->revision_id >= 0x10 && np->revision_id <= 0x11) || 2642 (np->device_id == PCI_ID_SYM53C860 && 2643 np->revision_id <= 0x1)) 2644 np->features &= ~(FE_WRIE|FE_ERL|FE_ERMP); 2645 2646 /* 2647 * Select all supported special features. 2648 * If we are using on-board RAM for scripts, prefetch (PFEN) 2649 * does not help, but burst op fetch (BOF) does. 2650 * Disabling PFEN makes sure BOF will be used. 2651 */ 2652 if (np->features & FE_ERL) 2653 np->rv_dmode |= ERL; /* Enable Read Line */ 2654 if (np->features & FE_BOF) 2655 np->rv_dmode |= BOF; /* Burst Opcode Fetch */ 2656 if (np->features & FE_ERMP) 2657 np->rv_dmode |= ERMP; /* Enable Read Multiple */ 2658 #if 1 2659 if ((np->features & FE_PFEN) && !np->ram_ba) 2660 #else 2661 if (np->features & FE_PFEN) 2662 #endif 2663 np->rv_dcntl |= PFEN; /* Prefetch Enable */ 2664 if (np->features & FE_CLSE) 2665 np->rv_dcntl |= CLSE; /* Cache Line Size Enable */ 2666 if (np->features & FE_WRIE) 2667 np->rv_ctest3 |= WRIE; /* Write and Invalidate */ 2668 if (np->features & FE_DFS) 2669 np->rv_ctest5 |= DFS; /* Dma Fifo Size */ 2670 2671 /* 2672 * Select some other 2673 */ 2674 if (SYM_SETUP_PCI_PARITY) 2675 np->rv_ctest4 |= MPEE; /* Master parity checking */ 2676 if (SYM_SETUP_SCSI_PARITY) 2677 np->rv_scntl0 |= 0x0a; /* full arb., ena parity, par->ATN */ 2678 2679 /* 2680 * Get parity checking, host ID and verbose mode from NVRAM 2681 */ 2682 np->myaddr = 255; 2683 sym_nvram_setup_host (np, nvram); 2684 2685 /* 2686 * Get SCSI addr of host adapter (set by bios?). 2687 */ 2688 if (np->myaddr == 255) { 2689 np->myaddr = INB(nc_scid) & 0x07; 2690 if (!np->myaddr) 2691 np->myaddr = SYM_SETUP_HOST_ID; 2692 } 2693 2694 /* 2695 * Prepare initial io register bits for burst length 2696 */ 2697 sym_init_burst(np, burst_max); 2698 2699 /* 2700 * Set SCSI BUS mode. 2701 * - LVD capable chips (895/895A/896/1010) report the 2702 * current BUS mode through the STEST4 IO register. 2703 * - For previous generation chips (825/825A/875), 2704 * user has to tell us how to check against HVD, 2705 * since a 100% safe algorithm is not possible. 2706 */ 2707 np->scsi_mode = SMODE_SE; 2708 if (np->features & (FE_ULTRA2|FE_ULTRA3)) 2709 np->scsi_mode = (np->sv_stest4 & SMODE); 2710 else if (np->features & FE_DIFF) { 2711 if (SYM_SETUP_SCSI_DIFF == 1) { 2712 if (np->sv_scntl3) { 2713 if (np->sv_stest2 & 0x20) 2714 np->scsi_mode = SMODE_HVD; 2715 } 2716 else if (nvram->type == SYM_SYMBIOS_NVRAM) { 2717 if (!(INB(nc_gpreg) & 0x08)) 2718 np->scsi_mode = SMODE_HVD; 2719 } 2720 } 2721 else if (SYM_SETUP_SCSI_DIFF == 2) 2722 np->scsi_mode = SMODE_HVD; 2723 } 2724 if (np->scsi_mode == SMODE_HVD) 2725 np->rv_stest2 |= 0x20; 2726 2727 /* 2728 * Set LED support from SCRIPTS. 2729 * Ignore this feature for boards known to use a 2730 * specific GPIO wiring and for the 895A, 896 2731 * and 1010 that drive the LED directly. 2732 */ 2733 if ((SYM_SETUP_SCSI_LED || 2734 (nvram->type == SYM_SYMBIOS_NVRAM || 2735 (nvram->type == SYM_TEKRAM_NVRAM && 2736 np->device_id == PCI_ID_SYM53C895))) && 2737 !(np->features & FE_LEDC) && !(np->sv_gpcntl & 0x01)) 2738 np->features |= FE_LED0; 2739 2740 /* 2741 * Set irq mode. 2742 */ 2743 switch(SYM_SETUP_IRQ_MODE & 3) { 2744 case 2: 2745 np->rv_dcntl |= IRQM; 2746 break; 2747 case 1: 2748 np->rv_dcntl |= (np->sv_dcntl & IRQM); 2749 break; 2750 default: 2751 break; 2752 } 2753 2754 /* 2755 * Configure targets according to driver setup. 2756 * If NVRAM present get targets setup from NVRAM. 2757 */ 2758 for (i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) { 2759 tcb_p tp = &np->target[i]; 2760 2761 #ifdef FreeBSD_New_Tran_Settings 2762 tp->tinfo.user.scsi_version = tp->tinfo.current.scsi_version= 2; 2763 tp->tinfo.user.spi_version = tp->tinfo.current.spi_version = 2; 2764 #endif 2765 tp->tinfo.user.period = np->minsync; 2766 tp->tinfo.user.offset = np->maxoffs; 2767 tp->tinfo.user.width = np->maxwide ? BUS_16_BIT : BUS_8_BIT; 2768 tp->usrflags |= (SYM_DISC_ENABLED | SYM_TAGS_ENABLED); 2769 tp->usrtags = SYM_SETUP_MAX_TAG; 2770 2771 sym_nvram_setup_target (np, i, nvram); 2772 2773 /* 2774 * For now, guess PPR/DT support from the period 2775 * and BUS width. 2776 */ 2777 if (np->features & FE_ULTRA3) { 2778 if (tp->tinfo.user.period <= 9 && 2779 tp->tinfo.user.width == BUS_16_BIT) { 2780 tp->tinfo.user.options |= PPR_OPT_DT; 2781 tp->tinfo.user.offset = np->maxoffs_dt; 2782 #ifdef FreeBSD_New_Tran_Settings 2783 tp->tinfo.user.spi_version = 3; 2784 #endif 2785 } 2786 } 2787 2788 if (!tp->usrtags) 2789 tp->usrflags &= ~SYM_TAGS_ENABLED; 2790 } 2791 2792 /* 2793 * Let user know about the settings. 2794 */ 2795 i = nvram->type; 2796 printf("%s: %s NVRAM, ID %d, Fast-%d, %s, %s\n", sym_name(np), 2797 i == SYM_SYMBIOS_NVRAM ? "Symbios" : 2798 (i == SYM_TEKRAM_NVRAM ? "Tekram" : "No"), 2799 np->myaddr, 2800 (np->features & FE_ULTRA3) ? 80 : 2801 (np->features & FE_ULTRA2) ? 40 : 2802 (np->features & FE_ULTRA) ? 20 : 10, 2803 sym_scsi_bus_mode(np->scsi_mode), 2804 (np->rv_scntl0 & 0xa) ? "parity checking" : "NO parity"); 2805 /* 2806 * Tell him more on demand. 2807 */ 2808 if (sym_verbose) { 2809 printf("%s: %s IRQ line driver%s\n", 2810 sym_name(np), 2811 np->rv_dcntl & IRQM ? "totem pole" : "open drain", 2812 np->ram_ba ? ", using on-chip SRAM" : ""); 2813 printf("%s: using %s firmware.\n", sym_name(np), np->fw_name); 2814 if (np->features & FE_NOPM) 2815 printf("%s: handling phase mismatch from SCRIPTS.\n", 2816 sym_name(np)); 2817 } 2818 /* 2819 * And still more. 2820 */ 2821 if (sym_verbose > 1) { 2822 printf ("%s: initial SCNTL3/DMODE/DCNTL/CTEST3/4/5 = " 2823 "(hex) %02x/%02x/%02x/%02x/%02x/%02x\n", 2824 sym_name(np), np->sv_scntl3, np->sv_dmode, np->sv_dcntl, 2825 np->sv_ctest3, np->sv_ctest4, np->sv_ctest5); 2826 2827 printf ("%s: final SCNTL3/DMODE/DCNTL/CTEST3/4/5 = " 2828 "(hex) %02x/%02x/%02x/%02x/%02x/%02x\n", 2829 sym_name(np), np->rv_scntl3, np->rv_dmode, np->rv_dcntl, 2830 np->rv_ctest3, np->rv_ctest4, np->rv_ctest5); 2831 } 2832 /* 2833 * Let user be aware of targets that have some disable flags set. 2834 */ 2835 sym_print_targets_flag(np, SYM_SCAN_BOOT_DISABLED, "SCAN AT BOOT"); 2836 if (sym_verbose) 2837 sym_print_targets_flag(np, SYM_SCAN_LUNS_DISABLED, 2838 "SCAN FOR LUNS"); 2839 2840 return 0; 2841 } 2842 2843 /* 2844 * Prepare the next negotiation message if needed. 2845 * 2846 * Fill in the part of message buffer that contains the 2847 * negotiation and the nego_status field of the CCB. 2848 * Returns the size of the message in bytes. 2849 */ 2850 2851 static int sym_prepare_nego(hcb_p np, ccb_p cp, int nego, u_char *msgptr) 2852 { 2853 tcb_p tp = &np->target[cp->target]; 2854 int msglen = 0; 2855 2856 /* 2857 * Early C1010 chips need a work-around for DT 2858 * data transfer to work. 2859 */ 2860 if (!(np->features & FE_U3EN)) 2861 tp->tinfo.goal.options = 0; 2862 /* 2863 * negotiate using PPR ? 2864 */ 2865 if (tp->tinfo.goal.options & PPR_OPT_MASK) 2866 nego = NS_PPR; 2867 /* 2868 * negotiate wide transfers ? 2869 */ 2870 else if (tp->tinfo.current.width != tp->tinfo.goal.width) 2871 nego = NS_WIDE; 2872 /* 2873 * negotiate synchronous transfers? 2874 */ 2875 else if (tp->tinfo.current.period != tp->tinfo.goal.period || 2876 tp->tinfo.current.offset != tp->tinfo.goal.offset) 2877 nego = NS_SYNC; 2878 2879 switch (nego) { 2880 case NS_SYNC: 2881 msgptr[msglen++] = M_EXTENDED; 2882 msgptr[msglen++] = 3; 2883 msgptr[msglen++] = M_X_SYNC_REQ; 2884 msgptr[msglen++] = tp->tinfo.goal.period; 2885 msgptr[msglen++] = tp->tinfo.goal.offset; 2886 break; 2887 case NS_WIDE: 2888 msgptr[msglen++] = M_EXTENDED; 2889 msgptr[msglen++] = 2; 2890 msgptr[msglen++] = M_X_WIDE_REQ; 2891 msgptr[msglen++] = tp->tinfo.goal.width; 2892 break; 2893 case NS_PPR: 2894 msgptr[msglen++] = M_EXTENDED; 2895 msgptr[msglen++] = 6; 2896 msgptr[msglen++] = M_X_PPR_REQ; 2897 msgptr[msglen++] = tp->tinfo.goal.period; 2898 msgptr[msglen++] = 0; 2899 msgptr[msglen++] = tp->tinfo.goal.offset; 2900 msgptr[msglen++] = tp->tinfo.goal.width; 2901 msgptr[msglen++] = tp->tinfo.goal.options & PPR_OPT_DT; 2902 break; 2903 }; 2904 2905 cp->nego_status = nego; 2906 2907 if (nego) { 2908 tp->nego_cp = cp; /* Keep track a nego will be performed */ 2909 if (DEBUG_FLAGS & DEBUG_NEGO) { 2910 sym_print_msg(cp, nego == NS_SYNC ? "sync msgout" : 2911 nego == NS_WIDE ? "wide msgout" : 2912 "ppr msgout", msgptr); 2913 }; 2914 }; 2915 2916 return msglen; 2917 } 2918 2919 /* 2920 * Insert a job into the start queue. 2921 */ 2922 static void sym_put_start_queue(hcb_p np, ccb_p cp) 2923 { 2924 u_short qidx; 2925 2926 #ifdef SYM_CONF_IARB_SUPPORT 2927 /* 2928 * If the previously queued CCB is not yet done, 2929 * set the IARB hint. The SCRIPTS will go with IARB 2930 * for this job when starting the previous one. 2931 * We leave devices a chance to win arbitration by 2932 * not using more than 'iarb_max' consecutive 2933 * immediate arbitrations. 2934 */ 2935 if (np->last_cp && np->iarb_count < np->iarb_max) { 2936 np->last_cp->host_flags |= HF_HINT_IARB; 2937 ++np->iarb_count; 2938 } 2939 else 2940 np->iarb_count = 0; 2941 np->last_cp = cp; 2942 #endif 2943 2944 /* 2945 * Insert first the idle task and then our job. 2946 * The MB should ensure proper ordering. 2947 */ 2948 qidx = np->squeueput + 2; 2949 if (qidx >= MAX_QUEUE*2) qidx = 0; 2950 2951 np->squeue [qidx] = cpu_to_scr(np->idletask_ba); 2952 MEMORY_BARRIER(); 2953 np->squeue [np->squeueput] = cpu_to_scr(cp->ccb_ba); 2954 2955 np->squeueput = qidx; 2956 2957 if (DEBUG_FLAGS & DEBUG_QUEUE) 2958 printf ("%s: queuepos=%d.\n", sym_name (np), np->squeueput); 2959 2960 /* 2961 * Script processor may be waiting for reselect. 2962 * Wake it up. 2963 */ 2964 MEMORY_BARRIER(); 2965 OUTB (nc_istat, SIGP|np->istat_sem); 2966 } 2967 2968 2969 /* 2970 * Soft reset the chip. 2971 * 2972 * Raising SRST when the chip is running may cause 2973 * problems on dual function chips (see below). 2974 * On the other hand, LVD devices need some delay 2975 * to settle and report actual BUS mode in STEST4. 2976 */ 2977 static void sym_chip_reset (hcb_p np) 2978 { 2979 OUTB (nc_istat, SRST); 2980 UDELAY (10); 2981 OUTB (nc_istat, 0); 2982 UDELAY(2000); /* For BUS MODE to settle */ 2983 } 2984 2985 /* 2986 * Soft reset the chip. 2987 * 2988 * Some 896 and 876 chip revisions may hang-up if we set 2989 * the SRST (soft reset) bit at the wrong time when SCRIPTS 2990 * are running. 2991 * So, we need to abort the current operation prior to 2992 * soft resetting the chip. 2993 */ 2994 static void sym_soft_reset (hcb_p np) 2995 { 2996 u_char istat; 2997 int i; 2998 2999 OUTB (nc_istat, CABRT); 3000 for (i = 1000000 ; i ; --i) { 3001 istat = INB (nc_istat); 3002 if (istat & SIP) { 3003 INW (nc_sist); 3004 continue; 3005 } 3006 if (istat & DIP) { 3007 OUTB (nc_istat, 0); 3008 INB (nc_dstat); 3009 break; 3010 } 3011 } 3012 if (!i) 3013 printf("%s: unable to abort current chip operation.\n", 3014 sym_name(np)); 3015 sym_chip_reset (np); 3016 } 3017 3018 /* 3019 * Start reset process. 3020 * 3021 * The interrupt handler will reinitialize the chip. 3022 */ 3023 static void sym_start_reset(hcb_p np) 3024 { 3025 (void) sym_reset_scsi_bus(np, 1); 3026 } 3027 3028 static int sym_reset_scsi_bus(hcb_p np, int enab_int) 3029 { 3030 u32 term; 3031 int retv = 0; 3032 3033 sym_soft_reset(np); /* Soft reset the chip */ 3034 if (enab_int) 3035 OUTW (nc_sien, RST); 3036 /* 3037 * Enable Tolerant, reset IRQD if present and 3038 * properly set IRQ mode, prior to resetting the bus. 3039 */ 3040 OUTB (nc_stest3, TE); 3041 OUTB (nc_dcntl, (np->rv_dcntl & IRQM)); 3042 OUTB (nc_scntl1, CRST); 3043 UDELAY (200); 3044 3045 if (!SYM_SETUP_SCSI_BUS_CHECK) 3046 goto out; 3047 /* 3048 * Check for no terminators or SCSI bus shorts to ground. 3049 * Read SCSI data bus, data parity bits and control signals. 3050 * We are expecting RESET to be TRUE and other signals to be 3051 * FALSE. 3052 */ 3053 term = INB(nc_sstat0); 3054 term = ((term & 2) << 7) + ((term & 1) << 17); /* rst sdp0 */ 3055 term |= ((INB(nc_sstat2) & 0x01) << 26) | /* sdp1 */ 3056 ((INW(nc_sbdl) & 0xff) << 9) | /* d7-0 */ 3057 ((INW(nc_sbdl) & 0xff00) << 10) | /* d15-8 */ 3058 INB(nc_sbcl); /* req ack bsy sel atn msg cd io */ 3059 3060 if (!(np->features & FE_WIDE)) 3061 term &= 0x3ffff; 3062 3063 if (term != (2<<7)) { 3064 printf("%s: suspicious SCSI data while resetting the BUS.\n", 3065 sym_name(np)); 3066 printf("%s: %sdp0,d7-0,rst,req,ack,bsy,sel,atn,msg,c/d,i/o = " 3067 "0x%lx, expecting 0x%lx\n", 3068 sym_name(np), 3069 (np->features & FE_WIDE) ? "dp1,d15-8," : "", 3070 (u_long)term, (u_long)(2<<7)); 3071 if (SYM_SETUP_SCSI_BUS_CHECK == 1) 3072 retv = 1; 3073 } 3074 out: 3075 OUTB (nc_scntl1, 0); 3076 /* MDELAY(100); */ 3077 return retv; 3078 } 3079 3080 /* 3081 * The chip may have completed jobs. Look at the DONE QUEUE. 3082 * 3083 * On architectures that may reorder LOAD/STORE operations, 3084 * a memory barrier may be needed after the reading of the 3085 * so-called `flag' and prior to dealing with the data. 3086 */ 3087 static int sym_wakeup_done (hcb_p np) 3088 { 3089 ccb_p cp; 3090 int i, n; 3091 u32 dsa; 3092 3093 n = 0; 3094 i = np->dqueueget; 3095 while (1) { 3096 dsa = scr_to_cpu(np->dqueue[i]); 3097 if (!dsa) 3098 break; 3099 np->dqueue[i] = 0; 3100 if ((i = i+2) >= MAX_QUEUE*2) 3101 i = 0; 3102 3103 cp = sym_ccb_from_dsa(np, dsa); 3104 if (cp) { 3105 MEMORY_BARRIER(); 3106 sym_complete_ok (np, cp); 3107 ++n; 3108 } 3109 else 3110 printf ("%s: bad DSA (%x) in done queue.\n", 3111 sym_name(np), (u_int) dsa); 3112 } 3113 np->dqueueget = i; 3114 3115 return n; 3116 } 3117 3118 /* 3119 * Complete all active CCBs with error. 3120 * Used on CHIP/SCSI RESET. 3121 */ 3122 static void sym_flush_busy_queue (hcb_p np, int cam_status) 3123 { 3124 /* 3125 * Move all active CCBs to the COMP queue 3126 * and flush this queue. 3127 */ 3128 sym_que_splice(&np->busy_ccbq, &np->comp_ccbq); 3129 sym_que_init(&np->busy_ccbq); 3130 sym_flush_comp_queue(np, cam_status); 3131 } 3132 3133 /* 3134 * Start chip. 3135 * 3136 * 'reason' means: 3137 * 0: initialisation. 3138 * 1: SCSI BUS RESET delivered or received. 3139 * 2: SCSI BUS MODE changed. 3140 */ 3141 static void sym_init (hcb_p np, int reason) 3142 { 3143 int i; 3144 u32 phys; 3145 3146 /* 3147 * Reset chip if asked, otherwise just clear fifos. 3148 */ 3149 if (reason == 1) 3150 sym_soft_reset(np); 3151 else { 3152 OUTB (nc_stest3, TE|CSF); 3153 OUTONB (nc_ctest3, CLF); 3154 } 3155 3156 /* 3157 * Clear Start Queue 3158 */ 3159 phys = np->squeue_ba; 3160 for (i = 0; i < MAX_QUEUE*2; i += 2) { 3161 np->squeue[i] = cpu_to_scr(np->idletask_ba); 3162 np->squeue[i+1] = cpu_to_scr(phys + (i+2)*4); 3163 } 3164 np->squeue[MAX_QUEUE*2-1] = cpu_to_scr(phys); 3165 3166 /* 3167 * Start at first entry. 3168 */ 3169 np->squeueput = 0; 3170 3171 /* 3172 * Clear Done Queue 3173 */ 3174 phys = np->dqueue_ba; 3175 for (i = 0; i < MAX_QUEUE*2; i += 2) { 3176 np->dqueue[i] = 0; 3177 np->dqueue[i+1] = cpu_to_scr(phys + (i+2)*4); 3178 } 3179 np->dqueue[MAX_QUEUE*2-1] = cpu_to_scr(phys); 3180 3181 /* 3182 * Start at first entry. 3183 */ 3184 np->dqueueget = 0; 3185 3186 /* 3187 * Install patches in scripts. 3188 * This also let point to first position the start 3189 * and done queue pointers used from SCRIPTS. 3190 */ 3191 np->fw_patch(np); 3192 3193 /* 3194 * Wakeup all pending jobs. 3195 */ 3196 sym_flush_busy_queue(np, CAM_SCSI_BUS_RESET); 3197 3198 /* 3199 * Init chip. 3200 */ 3201 OUTB (nc_istat, 0x00 ); /* Remove Reset, abort */ 3202 UDELAY (2000); /* The 895 needs time for the bus mode to settle */ 3203 3204 OUTB (nc_scntl0, np->rv_scntl0 | 0xc0); 3205 /* full arb., ena parity, par->ATN */ 3206 OUTB (nc_scntl1, 0x00); /* odd parity, and remove CRST!! */ 3207 3208 sym_selectclock(np, np->rv_scntl3); /* Select SCSI clock */ 3209 3210 OUTB (nc_scid , RRE|np->myaddr); /* Adapter SCSI address */ 3211 OUTW (nc_respid, 1ul<<np->myaddr); /* Id to respond to */ 3212 OUTB (nc_istat , SIGP ); /* Signal Process */ 3213 OUTB (nc_dmode , np->rv_dmode); /* Burst length, dma mode */ 3214 OUTB (nc_ctest5, np->rv_ctest5); /* Large fifo + large burst */ 3215 3216 OUTB (nc_dcntl , NOCOM|np->rv_dcntl); /* Protect SFBR */ 3217 OUTB (nc_ctest3, np->rv_ctest3); /* Write and invalidate */ 3218 OUTB (nc_ctest4, np->rv_ctest4); /* Master parity checking */ 3219 3220 /* Extended Sreq/Sack filtering not supported on the C10 */ 3221 if (np->features & FE_C10) 3222 OUTB (nc_stest2, np->rv_stest2); 3223 else 3224 OUTB (nc_stest2, EXT|np->rv_stest2); 3225 3226 OUTB (nc_stest3, TE); /* TolerANT enable */ 3227 OUTB (nc_stime0, 0x0c); /* HTH disabled STO 0.25 sec */ 3228 3229 /* 3230 * For now, disable AIP generation on C1010-66. 3231 */ 3232 if (np->device_id == PCI_ID_LSI53C1010_2) 3233 OUTB (nc_aipcntl1, DISAIP); 3234 3235 /* 3236 * C10101 Errata. 3237 * Errant SGE's when in narrow. Write bits 4 & 5 of 3238 * STEST1 register to disable SGE. We probably should do 3239 * that from SCRIPTS for each selection/reselection, but 3240 * I just don't want. :) 3241 */ 3242 if (np->device_id == PCI_ID_LSI53C1010 && 3243 /* np->revision_id < 0xff */ 1) 3244 OUTB (nc_stest1, INB(nc_stest1) | 0x30); 3245 3246 /* 3247 * DEL 441 - 53C876 Rev 5 - Part Number 609-0392787/2788 - ITEM 2. 3248 * Disable overlapped arbitration for some dual function devices, 3249 * regardless revision id (kind of post-chip-design feature. ;-)) 3250 */ 3251 if (np->device_id == PCI_ID_SYM53C875) 3252 OUTB (nc_ctest0, (1<<5)); 3253 else if (np->device_id == PCI_ID_SYM53C896) 3254 np->rv_ccntl0 |= DPR; 3255 3256 /* 3257 * Write CCNTL0/CCNTL1 for chips capable of 64 bit addressing 3258 * and/or hardware phase mismatch, since only such chips 3259 * seem to support those IO registers. 3260 */ 3261 if (np->features & (FE_DAC|FE_NOPM)) { 3262 OUTB (nc_ccntl0, np->rv_ccntl0); 3263 OUTB (nc_ccntl1, np->rv_ccntl1); 3264 } 3265 3266 /* 3267 * If phase mismatch handled by scripts (895A/896/1010), 3268 * set PM jump addresses. 3269 */ 3270 if (np->features & FE_NOPM) { 3271 OUTL (nc_pmjad1, SCRIPTB_BA (np, pm_handle)); 3272 OUTL (nc_pmjad2, SCRIPTB_BA (np, pm_handle)); 3273 } 3274 3275 /* 3276 * Enable GPIO0 pin for writing if LED support from SCRIPTS. 3277 * Also set GPIO5 and clear GPIO6 if hardware LED control. 3278 */ 3279 if (np->features & FE_LED0) 3280 OUTB(nc_gpcntl, INB(nc_gpcntl) & ~0x01); 3281 else if (np->features & FE_LEDC) 3282 OUTB(nc_gpcntl, (INB(nc_gpcntl) & ~0x41) | 0x20); 3283 3284 /* 3285 * enable ints 3286 */ 3287 OUTW (nc_sien , STO|HTH|MA|SGE|UDC|RST|PAR); 3288 OUTB (nc_dien , MDPE|BF|SSI|SIR|IID); 3289 3290 /* 3291 * For 895/6 enable SBMC interrupt and save current SCSI bus mode. 3292 * Try to eat the spurious SBMC interrupt that may occur when 3293 * we reset the chip but not the SCSI BUS (at initialization). 3294 */ 3295 if (np->features & (FE_ULTRA2|FE_ULTRA3)) { 3296 OUTONW (nc_sien, SBMC); 3297 if (reason == 0) { 3298 MDELAY(100); 3299 INW (nc_sist); 3300 } 3301 np->scsi_mode = INB (nc_stest4) & SMODE; 3302 } 3303 3304 /* 3305 * Fill in target structure. 3306 * Reinitialize usrsync. 3307 * Reinitialize usrwide. 3308 * Prepare sync negotiation according to actual SCSI bus mode. 3309 */ 3310 for (i=0;i<SYM_CONF_MAX_TARGET;i++) { 3311 tcb_p tp = &np->target[i]; 3312 3313 tp->to_reset = 0; 3314 tp->head.sval = 0; 3315 tp->head.wval = np->rv_scntl3; 3316 tp->head.uval = 0; 3317 3318 tp->tinfo.current.period = 0; 3319 tp->tinfo.current.offset = 0; 3320 tp->tinfo.current.width = BUS_8_BIT; 3321 tp->tinfo.current.options = 0; 3322 } 3323 3324 /* 3325 * Download SCSI SCRIPTS to on-chip RAM if present, 3326 * and start script processor. 3327 */ 3328 if (np->ram_ba) { 3329 if (sym_verbose > 1) 3330 printf ("%s: Downloading SCSI SCRIPTS.\n", 3331 sym_name(np)); 3332 if (np->ram_ws == 8192) { 3333 OUTRAM_OFF(4096, np->scriptb0, np->scriptb_sz); 3334 OUTL (nc_mmws, np->scr_ram_seg); 3335 OUTL (nc_mmrs, np->scr_ram_seg); 3336 OUTL (nc_sfs, np->scr_ram_seg); 3337 phys = SCRIPTB_BA (np, start64); 3338 } 3339 else 3340 phys = SCRIPTA_BA (np, init); 3341 OUTRAM_OFF(0, np->scripta0, np->scripta_sz); 3342 } 3343 else 3344 phys = SCRIPTA_BA (np, init); 3345 3346 np->istat_sem = 0; 3347 3348 OUTL (nc_dsa, np->hcb_ba); 3349 OUTL_DSP (phys); 3350 3351 /* 3352 * Notify the XPT about the RESET condition. 3353 */ 3354 if (reason != 0) 3355 xpt_async(AC_BUS_RESET, np->path, NULL); 3356 } 3357 3358 /* 3359 * Get clock factor and sync divisor for a given 3360 * synchronous factor period. 3361 */ 3362 static int 3363 sym_getsync(hcb_p np, u_char dt, u_char sfac, u_char *divp, u_char *fakp) 3364 { 3365 u32 clk = np->clock_khz; /* SCSI clock frequency in kHz */ 3366 int div = np->clock_divn; /* Number of divisors supported */ 3367 u32 fak; /* Sync factor in sxfer */ 3368 u32 per; /* Period in tenths of ns */ 3369 u32 kpc; /* (per * clk) */ 3370 int ret; 3371 3372 /* 3373 * Compute the synchronous period in tenths of nano-seconds 3374 */ 3375 if (dt && sfac <= 9) per = 125; 3376 else if (sfac <= 10) per = 250; 3377 else if (sfac == 11) per = 303; 3378 else if (sfac == 12) per = 500; 3379 else per = 40 * sfac; 3380 ret = per; 3381 3382 kpc = per * clk; 3383 if (dt) 3384 kpc <<= 1; 3385 3386 /* 3387 * For earliest C10 revision 0, we cannot use extra 3388 * clocks for the setting of the SCSI clocking. 3389 * Note that this limits the lowest sync data transfer 3390 * to 5 Mega-transfers per second and may result in 3391 * using higher clock divisors. 3392 */ 3393 #if 1 3394 if ((np->features & (FE_C10|FE_U3EN)) == FE_C10) { 3395 /* 3396 * Look for the lowest clock divisor that allows an 3397 * output speed not faster than the period. 3398 */ 3399 while (div > 0) { 3400 --div; 3401 if (kpc > (div_10M[div] << 2)) { 3402 ++div; 3403 break; 3404 } 3405 } 3406 fak = 0; /* No extra clocks */ 3407 if (div == np->clock_divn) { /* Are we too fast ? */ 3408 ret = -1; 3409 } 3410 *divp = div; 3411 *fakp = fak; 3412 return ret; 3413 } 3414 #endif 3415 3416 /* 3417 * Look for the greatest clock divisor that allows an 3418 * input speed faster than the period. 3419 */ 3420 while (div-- > 0) 3421 if (kpc >= (div_10M[div] << 2)) break; 3422 3423 /* 3424 * Calculate the lowest clock factor that allows an output 3425 * speed not faster than the period, and the max output speed. 3426 * If fak >= 1 we will set both XCLKH_ST and XCLKH_DT. 3427 * If fak >= 2 we will also set XCLKS_ST and XCLKS_DT. 3428 */ 3429 if (dt) { 3430 fak = (kpc - 1) / (div_10M[div] << 1) + 1 - 2; 3431 /* ret = ((2+fak)*div_10M[div])/np->clock_khz; */ 3432 } 3433 else { 3434 fak = (kpc - 1) / div_10M[div] + 1 - 4; 3435 /* ret = ((4+fak)*div_10M[div])/np->clock_khz; */ 3436 } 3437 3438 /* 3439 * Check against our hardware limits, or bugs :). 3440 */ 3441 if (fak < 0) {fak = 0; ret = -1;} 3442 if (fak > 2) {fak = 2; ret = -1;} 3443 3444 /* 3445 * Compute and return sync parameters. 3446 */ 3447 *divp = div; 3448 *fakp = fak; 3449 3450 return ret; 3451 } 3452 3453 /* 3454 * Tell the SCSI layer about the new transfer parameters. 3455 */ 3456 static void 3457 sym_xpt_async_transfer_neg(hcb_p np, int target, u_int spi_valid) 3458 { 3459 struct ccb_trans_settings cts; 3460 struct cam_path *path; 3461 int sts; 3462 tcb_p tp = &np->target[target]; 3463 3464 sts = xpt_create_path(&path, NULL, cam_sim_path(np->sim), target, 3465 CAM_LUN_WILDCARD); 3466 if (sts != CAM_REQ_CMP) 3467 return; 3468 3469 bzero(&cts, sizeof(cts)); 3470 3471 #ifdef FreeBSD_New_Tran_Settings 3472 #define cts__scsi (cts.proto_specific.scsi) 3473 #define cts__spi (cts.xport_specific.spi) 3474 3475 cts.type = CTS_TYPE_CURRENT_SETTINGS; 3476 cts.protocol = PROTO_SCSI; 3477 cts.transport = XPORT_SPI; 3478 cts.protocol_version = tp->tinfo.current.scsi_version; 3479 cts.transport_version = tp->tinfo.current.spi_version; 3480 3481 cts__spi.valid = spi_valid; 3482 if (spi_valid & CTS_SPI_VALID_SYNC_RATE) 3483 cts__spi.sync_period = tp->tinfo.current.period; 3484 if (spi_valid & CTS_SPI_VALID_SYNC_OFFSET) 3485 cts__spi.sync_offset = tp->tinfo.current.offset; 3486 if (spi_valid & CTS_SPI_VALID_BUS_WIDTH) 3487 cts__spi.bus_width = tp->tinfo.current.width; 3488 if (spi_valid & CTS_SPI_VALID_PPR_OPTIONS) 3489 cts__spi.ppr_options = tp->tinfo.current.options; 3490 #undef cts__spi 3491 #undef cts__scsi 3492 #else 3493 cts.valid = spi_valid; 3494 if (spi_valid & CCB_TRANS_SYNC_RATE_VALID) 3495 cts.sync_period = tp->tinfo.current.period; 3496 if (spi_valid & CCB_TRANS_SYNC_OFFSET_VALID) 3497 cts.sync_offset = tp->tinfo.current.offset; 3498 if (spi_valid & CCB_TRANS_BUS_WIDTH_VALID) 3499 cts.bus_width = tp->tinfo.current.width; 3500 #endif 3501 xpt_setup_ccb(&cts.ccb_h, path, /*priority*/1); 3502 xpt_async(AC_TRANSFER_NEG, path, &cts); 3503 xpt_free_path(path); 3504 } 3505 3506 #ifdef FreeBSD_New_Tran_Settings 3507 #define SYM_SPI_VALID_WDTR \ 3508 CTS_SPI_VALID_BUS_WIDTH | \ 3509 CTS_SPI_VALID_SYNC_RATE | \ 3510 CTS_SPI_VALID_SYNC_OFFSET 3511 #define SYM_SPI_VALID_SDTR \ 3512 CTS_SPI_VALID_SYNC_RATE | \ 3513 CTS_SPI_VALID_SYNC_OFFSET 3514 #define SYM_SPI_VALID_PPR \ 3515 CTS_SPI_VALID_PPR_OPTIONS | \ 3516 CTS_SPI_VALID_BUS_WIDTH | \ 3517 CTS_SPI_VALID_SYNC_RATE | \ 3518 CTS_SPI_VALID_SYNC_OFFSET 3519 #else 3520 #define SYM_SPI_VALID_WDTR \ 3521 CCB_TRANS_BUS_WIDTH_VALID | \ 3522 CCB_TRANS_SYNC_RATE_VALID | \ 3523 CCB_TRANS_SYNC_OFFSET_VALID 3524 #define SYM_SPI_VALID_SDTR \ 3525 CCB_TRANS_SYNC_RATE_VALID | \ 3526 CCB_TRANS_SYNC_OFFSET_VALID 3527 #define SYM_SPI_VALID_PPR \ 3528 CCB_TRANS_BUS_WIDTH_VALID | \ 3529 CCB_TRANS_SYNC_RATE_VALID | \ 3530 CCB_TRANS_SYNC_OFFSET_VALID 3531 #endif 3532 3533 /* 3534 * We received a WDTR. 3535 * Let everything be aware of the changes. 3536 */ 3537 static void sym_setwide(hcb_p np, ccb_p cp, u_char wide) 3538 { 3539 tcb_p tp = &np->target[cp->target]; 3540 3541 sym_settrans(np, cp, 0, 0, 0, wide, 0, 0); 3542 3543 /* 3544 * Tell the SCSI layer about the new transfer parameters. 3545 */ 3546 tp->tinfo.goal.width = tp->tinfo.current.width = wide; 3547 tp->tinfo.current.offset = 0; 3548 tp->tinfo.current.period = 0; 3549 tp->tinfo.current.options = 0; 3550 3551 sym_xpt_async_transfer_neg(np, cp->target, SYM_SPI_VALID_WDTR); 3552 } 3553 3554 /* 3555 * We received a SDTR. 3556 * Let everything be aware of the changes. 3557 */ 3558 static void 3559 sym_setsync(hcb_p np, ccb_p cp, u_char ofs, u_char per, u_char div, u_char fak) 3560 { 3561 tcb_p tp = &np->target[cp->target]; 3562 u_char wide = (cp->phys.select.sel_scntl3 & EWS) ? 1 : 0; 3563 3564 sym_settrans(np, cp, 0, ofs, per, wide, div, fak); 3565 3566 /* 3567 * Tell the SCSI layer about the new transfer parameters. 3568 */ 3569 tp->tinfo.goal.period = tp->tinfo.current.period = per; 3570 tp->tinfo.goal.offset = tp->tinfo.current.offset = ofs; 3571 tp->tinfo.goal.options = tp->tinfo.current.options = 0; 3572 3573 sym_xpt_async_transfer_neg(np, cp->target, SYM_SPI_VALID_SDTR); 3574 } 3575 3576 /* 3577 * We received a PPR. 3578 * Let everything be aware of the changes. 3579 */ 3580 static void sym_setpprot(hcb_p np, ccb_p cp, u_char dt, u_char ofs, 3581 u_char per, u_char wide, u_char div, u_char fak) 3582 { 3583 tcb_p tp = &np->target[cp->target]; 3584 3585 sym_settrans(np, cp, dt, ofs, per, wide, div, fak); 3586 3587 /* 3588 * Tell the SCSI layer about the new transfer parameters. 3589 */ 3590 tp->tinfo.goal.width = tp->tinfo.current.width = wide; 3591 tp->tinfo.goal.period = tp->tinfo.current.period = per; 3592 tp->tinfo.goal.offset = tp->tinfo.current.offset = ofs; 3593 tp->tinfo.goal.options = tp->tinfo.current.options = dt; 3594 3595 sym_xpt_async_transfer_neg(np, cp->target, SYM_SPI_VALID_PPR); 3596 } 3597 3598 /* 3599 * Switch trans mode for current job and it's target. 3600 */ 3601 static void sym_settrans(hcb_p np, ccb_p cp, u_char dt, u_char ofs, 3602 u_char per, u_char wide, u_char div, u_char fak) 3603 { 3604 SYM_QUEHEAD *qp; 3605 union ccb *ccb; 3606 tcb_p tp; 3607 u_char target = INB (nc_sdid) & 0x0f; 3608 u_char sval, wval, uval; 3609 3610 assert (cp); 3611 if (!cp) return; 3612 ccb = cp->cam_ccb; 3613 assert (ccb); 3614 if (!ccb) return; 3615 assert (target == (cp->target & 0xf)); 3616 tp = &np->target[target]; 3617 3618 sval = tp->head.sval; 3619 wval = tp->head.wval; 3620 uval = tp->head.uval; 3621 3622 #if 0 3623 printf("XXXX sval=%x wval=%x uval=%x (%x)\n", 3624 sval, wval, uval, np->rv_scntl3); 3625 #endif 3626 /* 3627 * Set the offset. 3628 */ 3629 if (!(np->features & FE_C10)) 3630 sval = (sval & ~0x1f) | ofs; 3631 else 3632 sval = (sval & ~0x3f) | ofs; 3633 3634 /* 3635 * Set the sync divisor and extra clock factor. 3636 */ 3637 if (ofs != 0) { 3638 wval = (wval & ~0x70) | ((div+1) << 4); 3639 if (!(np->features & FE_C10)) 3640 sval = (sval & ~0xe0) | (fak << 5); 3641 else { 3642 uval = uval & ~(XCLKH_ST|XCLKH_DT|XCLKS_ST|XCLKS_DT); 3643 if (fak >= 1) uval |= (XCLKH_ST|XCLKH_DT); 3644 if (fak >= 2) uval |= (XCLKS_ST|XCLKS_DT); 3645 } 3646 } 3647 3648 /* 3649 * Set the bus width. 3650 */ 3651 wval = wval & ~EWS; 3652 if (wide != 0) 3653 wval |= EWS; 3654 3655 /* 3656 * Set misc. ultra enable bits. 3657 */ 3658 if (np->features & FE_C10) { 3659 uval = uval & ~(U3EN|AIPCKEN); 3660 if (dt) { 3661 assert(np->features & FE_U3EN); 3662 uval |= U3EN; 3663 } 3664 } 3665 else { 3666 wval = wval & ~ULTRA; 3667 if (per <= 12) wval |= ULTRA; 3668 } 3669 3670 /* 3671 * Stop there if sync parameters are unchanged. 3672 */ 3673 if (tp->head.sval == sval && 3674 tp->head.wval == wval && 3675 tp->head.uval == uval) 3676 return; 3677 tp->head.sval = sval; 3678 tp->head.wval = wval; 3679 tp->head.uval = uval; 3680 3681 /* 3682 * Disable extended Sreq/Sack filtering if per < 50. 3683 * Not supported on the C1010. 3684 */ 3685 if (per < 50 && !(np->features & FE_C10)) 3686 OUTOFFB (nc_stest2, EXT); 3687 3688 /* 3689 * set actual value and sync_status 3690 */ 3691 OUTB (nc_sxfer, tp->head.sval); 3692 OUTB (nc_scntl3, tp->head.wval); 3693 3694 if (np->features & FE_C10) { 3695 OUTB (nc_scntl4, tp->head.uval); 3696 } 3697 3698 /* 3699 * patch ALL busy ccbs of this target. 3700 */ 3701 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) { 3702 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 3703 if (cp->target != target) 3704 continue; 3705 cp->phys.select.sel_scntl3 = tp->head.wval; 3706 cp->phys.select.sel_sxfer = tp->head.sval; 3707 if (np->features & FE_C10) { 3708 cp->phys.select.sel_scntl4 = tp->head.uval; 3709 } 3710 } 3711 } 3712 3713 /* 3714 * log message for real hard errors 3715 * 3716 * sym0 targ 0?: ERROR (ds:si) (so-si-sd) (sxfer/scntl3) @ name (dsp:dbc). 3717 * reg: r0 r1 r2 r3 r4 r5 r6 ..... rf. 3718 * 3719 * exception register: 3720 * ds: dstat 3721 * si: sist 3722 * 3723 * SCSI bus lines: 3724 * so: control lines as driven by chip. 3725 * si: control lines as seen by chip. 3726 * sd: scsi data lines as seen by chip. 3727 * 3728 * wide/fastmode: 3729 * sxfer: (see the manual) 3730 * scntl3: (see the manual) 3731 * 3732 * current script command: 3733 * dsp: script address (relative to start of script). 3734 * dbc: first word of script command. 3735 * 3736 * First 24 register of the chip: 3737 * r0..rf 3738 */ 3739 static void sym_log_hard_error(hcb_p np, u_short sist, u_char dstat) 3740 { 3741 u32 dsp; 3742 int script_ofs; 3743 int script_size; 3744 char *script_name; 3745 u_char *script_base; 3746 int i; 3747 3748 dsp = INL (nc_dsp); 3749 3750 if (dsp > np->scripta_ba && 3751 dsp <= np->scripta_ba + np->scripta_sz) { 3752 script_ofs = dsp - np->scripta_ba; 3753 script_size = np->scripta_sz; 3754 script_base = (u_char *) np->scripta0; 3755 script_name = "scripta"; 3756 } 3757 else if (np->scriptb_ba < dsp && 3758 dsp <= np->scriptb_ba + np->scriptb_sz) { 3759 script_ofs = dsp - np->scriptb_ba; 3760 script_size = np->scriptb_sz; 3761 script_base = (u_char *) np->scriptb0; 3762 script_name = "scriptb"; 3763 } else { 3764 script_ofs = dsp; 3765 script_size = 0; 3766 script_base = 0; 3767 script_name = "mem"; 3768 } 3769 3770 printf ("%s:%d: ERROR (%x:%x) (%x-%x-%x) (%x/%x) @ (%s %x:%08x).\n", 3771 sym_name (np), (unsigned)INB (nc_sdid)&0x0f, dstat, sist, 3772 (unsigned)INB (nc_socl), (unsigned)INB (nc_sbcl), 3773 (unsigned)INB (nc_sbdl), (unsigned)INB (nc_sxfer), 3774 (unsigned)INB (nc_scntl3), script_name, script_ofs, 3775 (unsigned)INL (nc_dbc)); 3776 3777 if (((script_ofs & 3) == 0) && 3778 (unsigned)script_ofs < script_size) { 3779 printf ("%s: script cmd = %08x\n", sym_name(np), 3780 scr_to_cpu((int) *(u32 *)(script_base + script_ofs))); 3781 } 3782 3783 printf ("%s: regdump:", sym_name(np)); 3784 for (i=0; i<24;i++) 3785 printf (" %02x", (unsigned)INB_OFF(i)); 3786 printf (".\n"); 3787 3788 /* 3789 * PCI BUS error, read the PCI ststus register. 3790 */ 3791 if (dstat & (MDPE|BF)) { 3792 u_short pci_sts; 3793 pci_sts = pci_read_config(np->device, PCIR_STATUS, 2); 3794 if (pci_sts & 0xf900) { 3795 pci_write_config(np->device, PCIR_STATUS, pci_sts, 2); 3796 printf("%s: PCI STATUS = 0x%04x\n", 3797 sym_name(np), pci_sts & 0xf900); 3798 } 3799 } 3800 } 3801 3802 /* 3803 * chip interrupt handler 3804 * 3805 * In normal situations, interrupt conditions occur one at 3806 * a time. But when something bad happens on the SCSI BUS, 3807 * the chip may raise several interrupt flags before 3808 * stopping and interrupting the CPU. The additionnal 3809 * interrupt flags are stacked in some extra registers 3810 * after the SIP and/or DIP flag has been raised in the 3811 * ISTAT. After the CPU has read the interrupt condition 3812 * flag from SIST or DSTAT, the chip unstacks the other 3813 * interrupt flags and sets the corresponding bits in 3814 * SIST or DSTAT. Since the chip starts stacking once the 3815 * SIP or DIP flag is set, there is a small window of time 3816 * where the stacking does not occur. 3817 * 3818 * Typically, multiple interrupt conditions may happen in 3819 * the following situations: 3820 * 3821 * - SCSI parity error + Phase mismatch (PAR|MA) 3822 * When a parity error is detected in input phase 3823 * and the device switches to msg-in phase inside a 3824 * block MOV. 3825 * - SCSI parity error + Unexpected disconnect (PAR|UDC) 3826 * When a stupid device does not want to handle the 3827 * recovery of an SCSI parity error. 3828 * - Some combinations of STO, PAR, UDC, ... 3829 * When using non compliant SCSI stuff, when user is 3830 * doing non compliant hot tampering on the BUS, when 3831 * something really bad happens to a device, etc ... 3832 * 3833 * The heuristic suggested by SYMBIOS to handle 3834 * multiple interrupts is to try unstacking all 3835 * interrupts conditions and to handle them on some 3836 * priority based on error severity. 3837 * This will work when the unstacking has been 3838 * successful, but we cannot be 100 % sure of that, 3839 * since the CPU may have been faster to unstack than 3840 * the chip is able to stack. Hmmm ... But it seems that 3841 * such a situation is very unlikely to happen. 3842 * 3843 * If this happen, for example STO caught by the CPU 3844 * then UDC happenning before the CPU have restarted 3845 * the SCRIPTS, the driver may wrongly complete the 3846 * same command on UDC, since the SCRIPTS didn't restart 3847 * and the DSA still points to the same command. 3848 * We avoid this situation by setting the DSA to an 3849 * invalid value when the CCB is completed and before 3850 * restarting the SCRIPTS. 3851 * 3852 * Another issue is that we need some section of our 3853 * recovery procedures to be somehow uninterruptible but 3854 * the SCRIPTS processor does not provides such a 3855 * feature. For this reason, we handle recovery preferently 3856 * from the C code and check against some SCRIPTS critical 3857 * sections from the C code. 3858 * 3859 * Hopefully, the interrupt handling of the driver is now 3860 * able to resist to weird BUS error conditions, but donnot 3861 * ask me for any guarantee that it will never fail. :-) 3862 * Use at your own decision and risk. 3863 */ 3864 3865 static void sym_intr1 (hcb_p np) 3866 { 3867 u_char istat, istatc; 3868 u_char dstat; 3869 u_short sist; 3870 3871 /* 3872 * interrupt on the fly ? 3873 * 3874 * A `dummy read' is needed to ensure that the 3875 * clear of the INTF flag reaches the device 3876 * before the scanning of the DONE queue. 3877 */ 3878 istat = INB (nc_istat); 3879 if (istat & INTF) { 3880 OUTB (nc_istat, (istat & SIGP) | INTF | np->istat_sem); 3881 istat = INB (nc_istat); /* DUMMY READ */ 3882 if (DEBUG_FLAGS & DEBUG_TINY) printf ("F "); 3883 (void)sym_wakeup_done (np); 3884 }; 3885 3886 if (!(istat & (SIP|DIP))) 3887 return; 3888 3889 #if 0 /* We should never get this one */ 3890 if (istat & CABRT) 3891 OUTB (nc_istat, CABRT); 3892 #endif 3893 3894 /* 3895 * PAR and MA interrupts may occur at the same time, 3896 * and we need to know of both in order to handle 3897 * this situation properly. We try to unstack SCSI 3898 * interrupts for that reason. BTW, I dislike a LOT 3899 * such a loop inside the interrupt routine. 3900 * Even if DMA interrupt stacking is very unlikely to 3901 * happen, we also try unstacking these ones, since 3902 * this has no performance impact. 3903 */ 3904 sist = 0; 3905 dstat = 0; 3906 istatc = istat; 3907 do { 3908 if (istatc & SIP) 3909 sist |= INW (nc_sist); 3910 if (istatc & DIP) 3911 dstat |= INB (nc_dstat); 3912 istatc = INB (nc_istat); 3913 istat |= istatc; 3914 } while (istatc & (SIP|DIP)); 3915 3916 if (DEBUG_FLAGS & DEBUG_TINY) 3917 printf ("<%d|%x:%x|%x:%x>", 3918 (int)INB(nc_scr0), 3919 dstat,sist, 3920 (unsigned)INL(nc_dsp), 3921 (unsigned)INL(nc_dbc)); 3922 /* 3923 * On paper, a memory barrier may be needed here. 3924 * And since we are paranoid ... :) 3925 */ 3926 MEMORY_BARRIER(); 3927 3928 /* 3929 * First, interrupts we want to service cleanly. 3930 * 3931 * Phase mismatch (MA) is the most frequent interrupt 3932 * for chip earlier than the 896 and so we have to service 3933 * it as quickly as possible. 3934 * A SCSI parity error (PAR) may be combined with a phase 3935 * mismatch condition (MA). 3936 * Programmed interrupts (SIR) are used to call the C code 3937 * from SCRIPTS. 3938 * The single step interrupt (SSI) is not used in this 3939 * driver. 3940 */ 3941 if (!(sist & (STO|GEN|HTH|SGE|UDC|SBMC|RST)) && 3942 !(dstat & (MDPE|BF|ABRT|IID))) { 3943 if (sist & PAR) sym_int_par (np, sist); 3944 else if (sist & MA) sym_int_ma (np); 3945 else if (dstat & SIR) sym_int_sir (np); 3946 else if (dstat & SSI) OUTONB_STD (); 3947 else goto unknown_int; 3948 return; 3949 }; 3950 3951 /* 3952 * Now, interrupts that donnot happen in normal 3953 * situations and that we may need to recover from. 3954 * 3955 * On SCSI RESET (RST), we reset everything. 3956 * On SCSI BUS MODE CHANGE (SBMC), we complete all 3957 * active CCBs with RESET status, prepare all devices 3958 * for negotiating again and restart the SCRIPTS. 3959 * On STO and UDC, we complete the CCB with the corres- 3960 * ponding status and restart the SCRIPTS. 3961 */ 3962 if (sist & RST) { 3963 xpt_print_path(np->path); 3964 printf("SCSI BUS reset detected.\n"); 3965 sym_init (np, 1); 3966 return; 3967 }; 3968 3969 OUTB (nc_ctest3, np->rv_ctest3 | CLF); /* clear dma fifo */ 3970 OUTB (nc_stest3, TE|CSF); /* clear scsi fifo */ 3971 3972 if (!(sist & (GEN|HTH|SGE)) && 3973 !(dstat & (MDPE|BF|ABRT|IID))) { 3974 if (sist & SBMC) sym_int_sbmc (np); 3975 else if (sist & STO) sym_int_sto (np); 3976 else if (sist & UDC) sym_int_udc (np); 3977 else goto unknown_int; 3978 return; 3979 }; 3980 3981 /* 3982 * Now, interrupts we are not able to recover cleanly. 3983 * 3984 * Log message for hard errors. 3985 * Reset everything. 3986 */ 3987 3988 sym_log_hard_error(np, sist, dstat); 3989 3990 if ((sist & (GEN|HTH|SGE)) || 3991 (dstat & (MDPE|BF|ABRT|IID))) { 3992 sym_start_reset(np); 3993 return; 3994 }; 3995 3996 unknown_int: 3997 /* 3998 * We just miss the cause of the interrupt. :( 3999 * Print a message. The timeout will do the real work. 4000 */ 4001 printf( "%s: unknown interrupt(s) ignored, " 4002 "ISTAT=0x%x DSTAT=0x%x SIST=0x%x\n", 4003 sym_name(np), istat, dstat, sist); 4004 } 4005 4006 static void sym_intr(void *arg) 4007 { 4008 if (DEBUG_FLAGS & DEBUG_TINY) printf ("["); 4009 sym_intr1((hcb_p) arg); 4010 if (DEBUG_FLAGS & DEBUG_TINY) printf ("]"); 4011 return; 4012 } 4013 4014 static void sym_poll(struct cam_sim *sim) 4015 { 4016 int s = splcam(); 4017 sym_intr(cam_sim_softc(sim)); 4018 splx(s); 4019 } 4020 4021 4022 /* 4023 * generic recovery from scsi interrupt 4024 * 4025 * The doc says that when the chip gets an SCSI interrupt, 4026 * it tries to stop in an orderly fashion, by completing 4027 * an instruction fetch that had started or by flushing 4028 * the DMA fifo for a write to memory that was executing. 4029 * Such a fashion is not enough to know if the instruction 4030 * that was just before the current DSP value has been 4031 * executed or not. 4032 * 4033 * There are some small SCRIPTS sections that deal with 4034 * the start queue and the done queue that may break any 4035 * assomption from the C code if we are interrupted 4036 * inside, so we reset if this happens. Btw, since these 4037 * SCRIPTS sections are executed while the SCRIPTS hasn't 4038 * started SCSI operations, it is very unlikely to happen. 4039 * 4040 * All the driver data structures are supposed to be 4041 * allocated from the same 4 GB memory window, so there 4042 * is a 1 to 1 relationship between DSA and driver data 4043 * structures. Since we are careful :) to invalidate the 4044 * DSA when we complete a command or when the SCRIPTS 4045 * pushes a DSA into a queue, we can trust it when it 4046 * points to a CCB. 4047 */ 4048 static void sym_recover_scsi_int (hcb_p np, u_char hsts) 4049 { 4050 u32 dsp = INL (nc_dsp); 4051 u32 dsa = INL (nc_dsa); 4052 ccb_p cp = sym_ccb_from_dsa(np, dsa); 4053 4054 /* 4055 * If we haven't been interrupted inside the SCRIPTS 4056 * critical pathes, we can safely restart the SCRIPTS 4057 * and trust the DSA value if it matches a CCB. 4058 */ 4059 if ((!(dsp > SCRIPTA_BA (np, getjob_begin) && 4060 dsp < SCRIPTA_BA (np, getjob_end) + 1)) && 4061 (!(dsp > SCRIPTA_BA (np, ungetjob) && 4062 dsp < SCRIPTA_BA (np, reselect) + 1)) && 4063 (!(dsp > SCRIPTB_BA (np, sel_for_abort) && 4064 dsp < SCRIPTB_BA (np, sel_for_abort_1) + 1)) && 4065 (!(dsp > SCRIPTA_BA (np, done) && 4066 dsp < SCRIPTA_BA (np, done_end) + 1))) { 4067 OUTB (nc_ctest3, np->rv_ctest3 | CLF); /* clear dma fifo */ 4068 OUTB (nc_stest3, TE|CSF); /* clear scsi fifo */ 4069 /* 4070 * If we have a CCB, let the SCRIPTS call us back for 4071 * the handling of the error with SCRATCHA filled with 4072 * STARTPOS. This way, we will be able to freeze the 4073 * device queue and requeue awaiting IOs. 4074 */ 4075 if (cp) { 4076 cp->host_status = hsts; 4077 OUTL_DSP (SCRIPTA_BA (np, complete_error)); 4078 } 4079 /* 4080 * Otherwise just restart the SCRIPTS. 4081 */ 4082 else { 4083 OUTL (nc_dsa, 0xffffff); 4084 OUTL_DSP (SCRIPTA_BA (np, start)); 4085 } 4086 } 4087 else 4088 goto reset_all; 4089 4090 return; 4091 4092 reset_all: 4093 sym_start_reset(np); 4094 } 4095 4096 /* 4097 * chip exception handler for selection timeout 4098 */ 4099 static void sym_int_sto (hcb_p np) 4100 { 4101 u32 dsp = INL (nc_dsp); 4102 4103 if (DEBUG_FLAGS & DEBUG_TINY) printf ("T"); 4104 4105 if (dsp == SCRIPTA_BA (np, wf_sel_done) + 8) 4106 sym_recover_scsi_int(np, HS_SEL_TIMEOUT); 4107 else 4108 sym_start_reset(np); 4109 } 4110 4111 /* 4112 * chip exception handler for unexpected disconnect 4113 */ 4114 static void sym_int_udc (hcb_p np) 4115 { 4116 printf ("%s: unexpected disconnect\n", sym_name(np)); 4117 sym_recover_scsi_int(np, HS_UNEXPECTED); 4118 } 4119 4120 /* 4121 * chip exception handler for SCSI bus mode change 4122 * 4123 * spi2-r12 11.2.3 says a transceiver mode change must 4124 * generate a reset event and a device that detects a reset 4125 * event shall initiate a hard reset. It says also that a 4126 * device that detects a mode change shall set data transfer 4127 * mode to eight bit asynchronous, etc... 4128 * So, just reinitializing all except chip should be enough. 4129 */ 4130 static void sym_int_sbmc (hcb_p np) 4131 { 4132 u_char scsi_mode = INB (nc_stest4) & SMODE; 4133 4134 /* 4135 * Notify user. 4136 */ 4137 xpt_print_path(np->path); 4138 printf("SCSI BUS mode change from %s to %s.\n", 4139 sym_scsi_bus_mode(np->scsi_mode), sym_scsi_bus_mode(scsi_mode)); 4140 4141 /* 4142 * Should suspend command processing for a few seconds and 4143 * reinitialize all except the chip. 4144 */ 4145 sym_init (np, 2); 4146 } 4147 4148 /* 4149 * chip exception handler for SCSI parity error. 4150 * 4151 * When the chip detects a SCSI parity error and is 4152 * currently executing a (CH)MOV instruction, it does 4153 * not interrupt immediately, but tries to finish the 4154 * transfer of the current scatter entry before 4155 * interrupting. The following situations may occur: 4156 * 4157 * - The complete scatter entry has been transferred 4158 * without the device having changed phase. 4159 * The chip will then interrupt with the DSP pointing 4160 * to the instruction that follows the MOV. 4161 * 4162 * - A phase mismatch occurs before the MOV finished 4163 * and phase errors are to be handled by the C code. 4164 * The chip will then interrupt with both PAR and MA 4165 * conditions set. 4166 * 4167 * - A phase mismatch occurs before the MOV finished and 4168 * phase errors are to be handled by SCRIPTS. 4169 * The chip will load the DSP with the phase mismatch 4170 * JUMP address and interrupt the host processor. 4171 */ 4172 static void sym_int_par (hcb_p np, u_short sist) 4173 { 4174 u_char hsts = INB (HS_PRT); 4175 u32 dsp = INL (nc_dsp); 4176 u32 dbc = INL (nc_dbc); 4177 u32 dsa = INL (nc_dsa); 4178 u_char sbcl = INB (nc_sbcl); 4179 u_char cmd = dbc >> 24; 4180 int phase = cmd & 7; 4181 ccb_p cp = sym_ccb_from_dsa(np, dsa); 4182 4183 printf("%s: SCSI parity error detected: SCR1=%d DBC=%x SBCL=%x\n", 4184 sym_name(np), hsts, dbc, sbcl); 4185 4186 /* 4187 * Check that the chip is connected to the SCSI BUS. 4188 */ 4189 if (!(INB (nc_scntl1) & ISCON)) { 4190 sym_recover_scsi_int(np, HS_UNEXPECTED); 4191 return; 4192 } 4193 4194 /* 4195 * If the nexus is not clearly identified, reset the bus. 4196 * We will try to do better later. 4197 */ 4198 if (!cp) 4199 goto reset_all; 4200 4201 /* 4202 * Check instruction was a MOV, direction was INPUT and 4203 * ATN is asserted. 4204 */ 4205 if ((cmd & 0xc0) || !(phase & 1) || !(sbcl & 0x8)) 4206 goto reset_all; 4207 4208 /* 4209 * Keep track of the parity error. 4210 */ 4211 OUTONB (HF_PRT, HF_EXT_ERR); 4212 cp->xerr_status |= XE_PARITY_ERR; 4213 4214 /* 4215 * Prepare the message to send to the device. 4216 */ 4217 np->msgout[0] = (phase == 7) ? M_PARITY : M_ID_ERROR; 4218 4219 /* 4220 * If the old phase was DATA IN phase, we have to deal with 4221 * the 3 situations described above. 4222 * For other input phases (MSG IN and STATUS), the device 4223 * must resend the whole thing that failed parity checking 4224 * or signal error. So, jumping to dispatcher should be OK. 4225 */ 4226 if (phase == 1 || phase == 5) { 4227 /* Phase mismatch handled by SCRIPTS */ 4228 if (dsp == SCRIPTB_BA (np, pm_handle)) 4229 OUTL_DSP (dsp); 4230 /* Phase mismatch handled by the C code */ 4231 else if (sist & MA) 4232 sym_int_ma (np); 4233 /* No phase mismatch occurred */ 4234 else { 4235 OUTL (nc_temp, dsp); 4236 OUTL_DSP (SCRIPTA_BA (np, dispatch)); 4237 } 4238 } 4239 else 4240 OUTL_DSP (SCRIPTA_BA (np, clrack)); 4241 return; 4242 4243 reset_all: 4244 sym_start_reset(np); 4245 return; 4246 } 4247 4248 /* 4249 * chip exception handler for phase errors. 4250 * 4251 * We have to construct a new transfer descriptor, 4252 * to transfer the rest of the current block. 4253 */ 4254 static void sym_int_ma (hcb_p np) 4255 { 4256 u32 dbc; 4257 u32 rest; 4258 u32 dsp; 4259 u32 dsa; 4260 u32 nxtdsp; 4261 u32 *vdsp; 4262 u32 oadr, olen; 4263 u32 *tblp; 4264 u32 newcmd; 4265 u_int delta; 4266 u_char cmd; 4267 u_char hflags, hflags0; 4268 struct sym_pmc *pm; 4269 ccb_p cp; 4270 4271 dsp = INL (nc_dsp); 4272 dbc = INL (nc_dbc); 4273 dsa = INL (nc_dsa); 4274 4275 cmd = dbc >> 24; 4276 rest = dbc & 0xffffff; 4277 delta = 0; 4278 4279 /* 4280 * locate matching cp if any. 4281 */ 4282 cp = sym_ccb_from_dsa(np, dsa); 4283 4284 /* 4285 * Donnot take into account dma fifo and various buffers in 4286 * INPUT phase since the chip flushes everything before 4287 * raising the MA interrupt for interrupted INPUT phases. 4288 * For DATA IN phase, we will check for the SWIDE later. 4289 */ 4290 if ((cmd & 7) != 1 && (cmd & 7) != 5) { 4291 u_char ss0, ss2; 4292 4293 if (np->features & FE_DFBC) 4294 delta = INW (nc_dfbc); 4295 else { 4296 u32 dfifo; 4297 4298 /* 4299 * Read DFIFO, CTEST[4-6] using 1 PCI bus ownership. 4300 */ 4301 dfifo = INL(nc_dfifo); 4302 4303 /* 4304 * Calculate remaining bytes in DMA fifo. 4305 * (CTEST5 = dfifo >> 16) 4306 */ 4307 if (dfifo & (DFS << 16)) 4308 delta = ((((dfifo >> 8) & 0x300) | 4309 (dfifo & 0xff)) - rest) & 0x3ff; 4310 else 4311 delta = ((dfifo & 0xff) - rest) & 0x7f; 4312 } 4313 4314 /* 4315 * The data in the dma fifo has not been transfered to 4316 * the target -> add the amount to the rest 4317 * and clear the data. 4318 * Check the sstat2 register in case of wide transfer. 4319 */ 4320 rest += delta; 4321 ss0 = INB (nc_sstat0); 4322 if (ss0 & OLF) rest++; 4323 if (!(np->features & FE_C10)) 4324 if (ss0 & ORF) rest++; 4325 if (cp && (cp->phys.select.sel_scntl3 & EWS)) { 4326 ss2 = INB (nc_sstat2); 4327 if (ss2 & OLF1) rest++; 4328 if (!(np->features & FE_C10)) 4329 if (ss2 & ORF1) rest++; 4330 }; 4331 4332 /* 4333 * Clear fifos. 4334 */ 4335 OUTB (nc_ctest3, np->rv_ctest3 | CLF); /* dma fifo */ 4336 OUTB (nc_stest3, TE|CSF); /* scsi fifo */ 4337 } 4338 4339 /* 4340 * log the information 4341 */ 4342 if (DEBUG_FLAGS & (DEBUG_TINY|DEBUG_PHASE)) 4343 printf ("P%x%x RL=%d D=%d ", cmd&7, INB(nc_sbcl)&7, 4344 (unsigned) rest, (unsigned) delta); 4345 4346 /* 4347 * try to find the interrupted script command, 4348 * and the address at which to continue. 4349 */ 4350 vdsp = 0; 4351 nxtdsp = 0; 4352 if (dsp > np->scripta_ba && 4353 dsp <= np->scripta_ba + np->scripta_sz) { 4354 vdsp = (u32 *)((char*)np->scripta0 + (dsp-np->scripta_ba-8)); 4355 nxtdsp = dsp; 4356 } 4357 else if (dsp > np->scriptb_ba && 4358 dsp <= np->scriptb_ba + np->scriptb_sz) { 4359 vdsp = (u32 *)((char*)np->scriptb0 + (dsp-np->scriptb_ba-8)); 4360 nxtdsp = dsp; 4361 } 4362 4363 /* 4364 * log the information 4365 */ 4366 if (DEBUG_FLAGS & DEBUG_PHASE) { 4367 printf ("\nCP=%p DSP=%x NXT=%x VDSP=%p CMD=%x ", 4368 cp, (unsigned)dsp, (unsigned)nxtdsp, vdsp, cmd); 4369 }; 4370 4371 if (!vdsp) { 4372 printf ("%s: interrupted SCRIPT address not found.\n", 4373 sym_name (np)); 4374 goto reset_all; 4375 } 4376 4377 if (!cp) { 4378 printf ("%s: SCSI phase error fixup: CCB already dequeued.\n", 4379 sym_name (np)); 4380 goto reset_all; 4381 } 4382 4383 /* 4384 * get old startaddress and old length. 4385 */ 4386 oadr = scr_to_cpu(vdsp[1]); 4387 4388 if (cmd & 0x10) { /* Table indirect */ 4389 tblp = (u32 *) ((char*) &cp->phys + oadr); 4390 olen = scr_to_cpu(tblp[0]); 4391 oadr = scr_to_cpu(tblp[1]); 4392 } else { 4393 tblp = (u32 *) 0; 4394 olen = scr_to_cpu(vdsp[0]) & 0xffffff; 4395 }; 4396 4397 if (DEBUG_FLAGS & DEBUG_PHASE) { 4398 printf ("OCMD=%x\nTBLP=%p OLEN=%x OADR=%x\n", 4399 (unsigned) (scr_to_cpu(vdsp[0]) >> 24), 4400 tblp, 4401 (unsigned) olen, 4402 (unsigned) oadr); 4403 }; 4404 4405 /* 4406 * check cmd against assumed interrupted script command. 4407 * If dt data phase, the MOVE instruction hasn't bit 4 of 4408 * the phase. 4409 */ 4410 if (((cmd & 2) ? cmd : (cmd & ~4)) != (scr_to_cpu(vdsp[0]) >> 24)) { 4411 PRINT_ADDR(cp); 4412 printf ("internal error: cmd=%02x != %02x=(vdsp[0] >> 24)\n", 4413 (unsigned)cmd, (unsigned)scr_to_cpu(vdsp[0]) >> 24); 4414 4415 goto reset_all; 4416 }; 4417 4418 /* 4419 * if old phase not dataphase, leave here. 4420 */ 4421 if (cmd & 2) { 4422 PRINT_ADDR(cp); 4423 printf ("phase change %x-%x %d@%08x resid=%d.\n", 4424 cmd&7, INB(nc_sbcl)&7, (unsigned)olen, 4425 (unsigned)oadr, (unsigned)rest); 4426 goto unexpected_phase; 4427 }; 4428 4429 /* 4430 * Choose the correct PM save area. 4431 * 4432 * Look at the PM_SAVE SCRIPT if you want to understand 4433 * this stuff. The equivalent code is implemented in 4434 * SCRIPTS for the 895A, 896 and 1010 that are able to 4435 * handle PM from the SCRIPTS processor. 4436 */ 4437 hflags0 = INB (HF_PRT); 4438 hflags = hflags0; 4439 4440 if (hflags & (HF_IN_PM0 | HF_IN_PM1 | HF_DP_SAVED)) { 4441 if (hflags & HF_IN_PM0) 4442 nxtdsp = scr_to_cpu(cp->phys.pm0.ret); 4443 else if (hflags & HF_IN_PM1) 4444 nxtdsp = scr_to_cpu(cp->phys.pm1.ret); 4445 4446 if (hflags & HF_DP_SAVED) 4447 hflags ^= HF_ACT_PM; 4448 } 4449 4450 if (!(hflags & HF_ACT_PM)) { 4451 pm = &cp->phys.pm0; 4452 newcmd = SCRIPTA_BA (np, pm0_data); 4453 } 4454 else { 4455 pm = &cp->phys.pm1; 4456 newcmd = SCRIPTA_BA (np, pm1_data); 4457 } 4458 4459 hflags &= ~(HF_IN_PM0 | HF_IN_PM1 | HF_DP_SAVED); 4460 if (hflags != hflags0) 4461 OUTB (HF_PRT, hflags); 4462 4463 /* 4464 * fillin the phase mismatch context 4465 */ 4466 pm->sg.addr = cpu_to_scr(oadr + olen - rest); 4467 pm->sg.size = cpu_to_scr(rest); 4468 pm->ret = cpu_to_scr(nxtdsp); 4469 4470 /* 4471 * If we have a SWIDE, 4472 * - prepare the address to write the SWIDE from SCRIPTS, 4473 * - compute the SCRIPTS address to restart from, 4474 * - move current data pointer context by one byte. 4475 */ 4476 nxtdsp = SCRIPTA_BA (np, dispatch); 4477 if ((cmd & 7) == 1 && cp && (cp->phys.select.sel_scntl3 & EWS) && 4478 (INB (nc_scntl2) & WSR)) { 4479 u32 tmp; 4480 4481 /* 4482 * Set up the table indirect for the MOVE 4483 * of the residual byte and adjust the data 4484 * pointer context. 4485 */ 4486 tmp = scr_to_cpu(pm->sg.addr); 4487 cp->phys.wresid.addr = cpu_to_scr(tmp); 4488 pm->sg.addr = cpu_to_scr(tmp + 1); 4489 tmp = scr_to_cpu(pm->sg.size); 4490 cp->phys.wresid.size = cpu_to_scr((tmp&0xff000000) | 1); 4491 pm->sg.size = cpu_to_scr(tmp - 1); 4492 4493 /* 4494 * If only the residual byte is to be moved, 4495 * no PM context is needed. 4496 */ 4497 if ((tmp&0xffffff) == 1) 4498 newcmd = pm->ret; 4499 4500 /* 4501 * Prepare the address of SCRIPTS that will 4502 * move the residual byte to memory. 4503 */ 4504 nxtdsp = SCRIPTB_BA (np, wsr_ma_helper); 4505 } 4506 4507 if (DEBUG_FLAGS & DEBUG_PHASE) { 4508 PRINT_ADDR(cp); 4509 printf ("PM %x %x %x / %x %x %x.\n", 4510 hflags0, hflags, newcmd, 4511 (unsigned)scr_to_cpu(pm->sg.addr), 4512 (unsigned)scr_to_cpu(pm->sg.size), 4513 (unsigned)scr_to_cpu(pm->ret)); 4514 } 4515 4516 /* 4517 * Restart the SCRIPTS processor. 4518 */ 4519 OUTL (nc_temp, newcmd); 4520 OUTL_DSP (nxtdsp); 4521 return; 4522 4523 /* 4524 * Unexpected phase changes that occurs when the current phase 4525 * is not a DATA IN or DATA OUT phase are due to error conditions. 4526 * Such event may only happen when the SCRIPTS is using a 4527 * multibyte SCSI MOVE. 4528 * 4529 * Phase change Some possible cause 4530 * 4531 * COMMAND --> MSG IN SCSI parity error detected by target. 4532 * COMMAND --> STATUS Bad command or refused by target. 4533 * MSG OUT --> MSG IN Message rejected by target. 4534 * MSG OUT --> COMMAND Bogus target that discards extended 4535 * negotiation messages. 4536 * 4537 * The code below does not care of the new phase and so 4538 * trusts the target. Why to annoy it ? 4539 * If the interrupted phase is COMMAND phase, we restart at 4540 * dispatcher. 4541 * If a target does not get all the messages after selection, 4542 * the code assumes blindly that the target discards extended 4543 * messages and clears the negotiation status. 4544 * If the target does not want all our response to negotiation, 4545 * we force a SIR_NEGO_PROTO interrupt (it is a hack that avoids 4546 * bloat for such a should_not_happen situation). 4547 * In all other situation, we reset the BUS. 4548 * Are these assumptions reasonnable ? (Wait and see ...) 4549 */ 4550 unexpected_phase: 4551 dsp -= 8; 4552 nxtdsp = 0; 4553 4554 switch (cmd & 7) { 4555 case 2: /* COMMAND phase */ 4556 nxtdsp = SCRIPTA_BA (np, dispatch); 4557 break; 4558 #if 0 4559 case 3: /* STATUS phase */ 4560 nxtdsp = SCRIPTA_BA (np, dispatch); 4561 break; 4562 #endif 4563 case 6: /* MSG OUT phase */ 4564 /* 4565 * If the device may want to use untagged when we want 4566 * tagged, we prepare an IDENTIFY without disc. granted, 4567 * since we will not be able to handle reselect. 4568 * Otherwise, we just don't care. 4569 */ 4570 if (dsp == SCRIPTA_BA (np, send_ident)) { 4571 if (cp->tag != NO_TAG && olen - rest <= 3) { 4572 cp->host_status = HS_BUSY; 4573 np->msgout[0] = M_IDENTIFY | cp->lun; 4574 nxtdsp = SCRIPTB_BA (np, ident_break_atn); 4575 } 4576 else 4577 nxtdsp = SCRIPTB_BA (np, ident_break); 4578 } 4579 else if (dsp == SCRIPTB_BA (np, send_wdtr) || 4580 dsp == SCRIPTB_BA (np, send_sdtr) || 4581 dsp == SCRIPTB_BA (np, send_ppr)) { 4582 nxtdsp = SCRIPTB_BA (np, nego_bad_phase); 4583 } 4584 break; 4585 #if 0 4586 case 7: /* MSG IN phase */ 4587 nxtdsp = SCRIPTA_BA (np, clrack); 4588 break; 4589 #endif 4590 } 4591 4592 if (nxtdsp) { 4593 OUTL_DSP (nxtdsp); 4594 return; 4595 } 4596 4597 reset_all: 4598 sym_start_reset(np); 4599 } 4600 4601 /* 4602 * Dequeue from the START queue all CCBs that match 4603 * a given target/lun/task condition (-1 means all), 4604 * and move them from the BUSY queue to the COMP queue 4605 * with CAM_REQUEUE_REQ status condition. 4606 * This function is used during error handling/recovery. 4607 * It is called with SCRIPTS not running. 4608 */ 4609 static int 4610 sym_dequeue_from_squeue(hcb_p np, int i, int target, int lun, int task) 4611 { 4612 int j; 4613 ccb_p cp; 4614 4615 /* 4616 * Make sure the starting index is within range. 4617 */ 4618 assert((i >= 0) && (i < 2*MAX_QUEUE)); 4619 4620 /* 4621 * Walk until end of START queue and dequeue every job 4622 * that matches the target/lun/task condition. 4623 */ 4624 j = i; 4625 while (i != np->squeueput) { 4626 cp = sym_ccb_from_dsa(np, scr_to_cpu(np->squeue[i])); 4627 assert(cp); 4628 #ifdef SYM_CONF_IARB_SUPPORT 4629 /* Forget hints for IARB, they may be no longer relevant */ 4630 cp->host_flags &= ~HF_HINT_IARB; 4631 #endif 4632 if ((target == -1 || cp->target == target) && 4633 (lun == -1 || cp->lun == lun) && 4634 (task == -1 || cp->tag == task)) { 4635 sym_set_cam_status(cp->cam_ccb, CAM_REQUEUE_REQ); 4636 sym_remque(&cp->link_ccbq); 4637 sym_insque_tail(&cp->link_ccbq, &np->comp_ccbq); 4638 } 4639 else { 4640 if (i != j) 4641 np->squeue[j] = np->squeue[i]; 4642 if ((j += 2) >= MAX_QUEUE*2) j = 0; 4643 } 4644 if ((i += 2) >= MAX_QUEUE*2) i = 0; 4645 } 4646 if (i != j) /* Copy back the idle task if needed */ 4647 np->squeue[j] = np->squeue[i]; 4648 np->squeueput = j; /* Update our current start queue pointer */ 4649 4650 return (i - j) / 2; 4651 } 4652 4653 /* 4654 * Complete all CCBs queued to the COMP queue. 4655 * 4656 * These CCBs are assumed: 4657 * - Not to be referenced either by devices or 4658 * SCRIPTS-related queues and datas. 4659 * - To have to be completed with an error condition 4660 * or requeued. 4661 * 4662 * The device queue freeze count is incremented 4663 * for each CCB that does not prevent this. 4664 * This function is called when all CCBs involved 4665 * in error handling/recovery have been reaped. 4666 */ 4667 static void 4668 sym_flush_comp_queue(hcb_p np, int cam_status) 4669 { 4670 SYM_QUEHEAD *qp; 4671 ccb_p cp; 4672 4673 while ((qp = sym_remque_head(&np->comp_ccbq)) != 0) { 4674 union ccb *ccb; 4675 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 4676 sym_insque_tail(&cp->link_ccbq, &np->busy_ccbq); 4677 /* Leave quiet CCBs waiting for resources */ 4678 if (cp->host_status == HS_WAIT) 4679 continue; 4680 ccb = cp->cam_ccb; 4681 if (cam_status) 4682 sym_set_cam_status(ccb, cam_status); 4683 sym_free_ccb(np, cp); 4684 sym_freeze_cam_ccb(ccb); 4685 sym_xpt_done(np, ccb); 4686 } 4687 } 4688 4689 /* 4690 * chip handler for bad SCSI status condition 4691 * 4692 * In case of bad SCSI status, we unqueue all the tasks 4693 * currently queued to the controller but not yet started 4694 * and then restart the SCRIPTS processor immediately. 4695 * 4696 * QUEUE FULL and BUSY conditions are handled the same way. 4697 * Basically all the not yet started tasks are requeued in 4698 * device queue and the queue is frozen until a completion. 4699 * 4700 * For CHECK CONDITION and COMMAND TERMINATED status, we use 4701 * the CCB of the failed command to prepare a REQUEST SENSE 4702 * SCSI command and queue it to the controller queue. 4703 * 4704 * SCRATCHA is assumed to have been loaded with STARTPOS 4705 * before the SCRIPTS called the C code. 4706 */ 4707 static void sym_sir_bad_scsi_status(hcb_p np, int num, ccb_p cp) 4708 { 4709 tcb_p tp = &np->target[cp->target]; 4710 u32 startp; 4711 u_char s_status = cp->ssss_status; 4712 u_char h_flags = cp->host_flags; 4713 int msglen; 4714 int nego; 4715 int i; 4716 4717 /* 4718 * Compute the index of the next job to start from SCRIPTS. 4719 */ 4720 i = (INL (nc_scratcha) - np->squeue_ba) / 4; 4721 4722 /* 4723 * The last CCB queued used for IARB hint may be 4724 * no longer relevant. Forget it. 4725 */ 4726 #ifdef SYM_CONF_IARB_SUPPORT 4727 if (np->last_cp) 4728 np->last_cp = 0; 4729 #endif 4730 4731 /* 4732 * Now deal with the SCSI status. 4733 */ 4734 switch(s_status) { 4735 case S_BUSY: 4736 case S_QUEUE_FULL: 4737 if (sym_verbose >= 2) { 4738 PRINT_ADDR(cp); 4739 printf (s_status == S_BUSY ? "BUSY" : "QUEUE FULL\n"); 4740 } 4741 default: /* S_INT, S_INT_COND_MET, S_CONFLICT */ 4742 sym_complete_error (np, cp); 4743 break; 4744 case S_TERMINATED: 4745 case S_CHECK_COND: 4746 /* 4747 * If we get an SCSI error when requesting sense, give up. 4748 */ 4749 if (h_flags & HF_SENSE) { 4750 sym_complete_error (np, cp); 4751 break; 4752 } 4753 4754 /* 4755 * Dequeue all queued CCBs for that device not yet started, 4756 * and restart the SCRIPTS processor immediately. 4757 */ 4758 (void) sym_dequeue_from_squeue(np, i, cp->target, cp->lun, -1); 4759 OUTL_DSP (SCRIPTA_BA (np, start)); 4760 4761 /* 4762 * Save some info of the actual IO. 4763 * Compute the data residual. 4764 */ 4765 cp->sv_scsi_status = cp->ssss_status; 4766 cp->sv_xerr_status = cp->xerr_status; 4767 cp->sv_resid = sym_compute_residual(np, cp); 4768 4769 /* 4770 * Prepare all needed data structures for 4771 * requesting sense data. 4772 */ 4773 4774 /* 4775 * identify message 4776 */ 4777 cp->scsi_smsg2[0] = M_IDENTIFY | cp->lun; 4778 msglen = 1; 4779 4780 /* 4781 * If we are currently using anything different from 4782 * async. 8 bit data transfers with that target, 4783 * start a negotiation, since the device may want 4784 * to report us a UNIT ATTENTION condition due to 4785 * a cause we currently ignore, and we donnot want 4786 * to be stuck with WIDE and/or SYNC data transfer. 4787 * 4788 * cp->nego_status is filled by sym_prepare_nego(). 4789 */ 4790 cp->nego_status = 0; 4791 nego = 0; 4792 if (tp->tinfo.current.options & PPR_OPT_MASK) 4793 nego = NS_PPR; 4794 else if (tp->tinfo.current.width != BUS_8_BIT) 4795 nego = NS_WIDE; 4796 else if (tp->tinfo.current.offset != 0) 4797 nego = NS_SYNC; 4798 if (nego) 4799 msglen += 4800 sym_prepare_nego (np,cp, nego, &cp->scsi_smsg2[msglen]); 4801 /* 4802 * Message table indirect structure. 4803 */ 4804 cp->phys.smsg.addr = cpu_to_scr(CCB_BA (cp, scsi_smsg2)); 4805 cp->phys.smsg.size = cpu_to_scr(msglen); 4806 4807 /* 4808 * sense command 4809 */ 4810 cp->phys.cmd.addr = cpu_to_scr(CCB_BA (cp, sensecmd)); 4811 cp->phys.cmd.size = cpu_to_scr(6); 4812 4813 /* 4814 * patch requested size into sense command 4815 */ 4816 cp->sensecmd[0] = 0x03; 4817 cp->sensecmd[1] = cp->lun << 5; 4818 #ifdef FreeBSD_New_Tran_Settings 4819 if (tp->tinfo.current.scsi_version > 2 || cp->lun > 7) 4820 cp->sensecmd[1] = 0; 4821 #endif 4822 cp->sensecmd[4] = SYM_SNS_BBUF_LEN; 4823 cp->data_len = SYM_SNS_BBUF_LEN; 4824 4825 /* 4826 * sense data 4827 */ 4828 bzero(cp->sns_bbuf, SYM_SNS_BBUF_LEN); 4829 cp->phys.sense.addr = cpu_to_scr(vtobus(cp->sns_bbuf)); 4830 cp->phys.sense.size = cpu_to_scr(SYM_SNS_BBUF_LEN); 4831 4832 /* 4833 * requeue the command. 4834 */ 4835 startp = SCRIPTB_BA (np, sdata_in); 4836 4837 cp->phys.head.savep = cpu_to_scr(startp); 4838 cp->phys.head.goalp = cpu_to_scr(startp + 16); 4839 cp->phys.head.lastp = cpu_to_scr(startp); 4840 cp->startp = cpu_to_scr(startp); 4841 4842 cp->actualquirks = SYM_QUIRK_AUTOSAVE; 4843 cp->host_status = cp->nego_status ? HS_NEGOTIATE : HS_BUSY; 4844 cp->ssss_status = S_ILLEGAL; 4845 cp->host_flags = (HF_SENSE|HF_DATA_IN); 4846 cp->xerr_status = 0; 4847 cp->extra_bytes = 0; 4848 4849 cp->phys.head.go.start = cpu_to_scr(SCRIPTA_BA (np, select)); 4850 4851 /* 4852 * Requeue the command. 4853 */ 4854 sym_put_start_queue(np, cp); 4855 4856 /* 4857 * Give back to upper layer everything we have dequeued. 4858 */ 4859 sym_flush_comp_queue(np, 0); 4860 break; 4861 } 4862 } 4863 4864 /* 4865 * After a device has accepted some management message 4866 * as BUS DEVICE RESET, ABORT TASK, etc ..., or when 4867 * a device signals a UNIT ATTENTION condition, some 4868 * tasks are thrown away by the device. We are required 4869 * to reflect that on our tasks list since the device 4870 * will never complete these tasks. 4871 * 4872 * This function move from the BUSY queue to the COMP 4873 * queue all disconnected CCBs for a given target that 4874 * match the following criteria: 4875 * - lun=-1 means any logical UNIT otherwise a given one. 4876 * - task=-1 means any task, otherwise a given one. 4877 */ 4878 static int 4879 sym_clear_tasks(hcb_p np, int cam_status, int target, int lun, int task) 4880 { 4881 SYM_QUEHEAD qtmp, *qp; 4882 int i = 0; 4883 ccb_p cp; 4884 4885 /* 4886 * Move the entire BUSY queue to our temporary queue. 4887 */ 4888 sym_que_init(&qtmp); 4889 sym_que_splice(&np->busy_ccbq, &qtmp); 4890 sym_que_init(&np->busy_ccbq); 4891 4892 /* 4893 * Put all CCBs that matches our criteria into 4894 * the COMP queue and put back other ones into 4895 * the BUSY queue. 4896 */ 4897 while ((qp = sym_remque_head(&qtmp)) != 0) { 4898 union ccb *ccb; 4899 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 4900 ccb = cp->cam_ccb; 4901 if (cp->host_status != HS_DISCONNECT || 4902 cp->target != target || 4903 (lun != -1 && cp->lun != lun) || 4904 (task != -1 && 4905 (cp->tag != NO_TAG && cp->scsi_smsg[2] != task))) { 4906 sym_insque_tail(&cp->link_ccbq, &np->busy_ccbq); 4907 continue; 4908 } 4909 sym_insque_tail(&cp->link_ccbq, &np->comp_ccbq); 4910 4911 /* Preserve the software timeout condition */ 4912 if (sym_get_cam_status(ccb) != CAM_CMD_TIMEOUT) 4913 sym_set_cam_status(ccb, cam_status); 4914 ++i; 4915 #if 0 4916 printf("XXXX TASK @%p CLEARED\n", cp); 4917 #endif 4918 } 4919 return i; 4920 } 4921 4922 /* 4923 * chip handler for TASKS recovery 4924 * 4925 * We cannot safely abort a command, while the SCRIPTS 4926 * processor is running, since we just would be in race 4927 * with it. 4928 * 4929 * As long as we have tasks to abort, we keep the SEM 4930 * bit set in the ISTAT. When this bit is set, the 4931 * SCRIPTS processor interrupts (SIR_SCRIPT_STOPPED) 4932 * each time it enters the scheduler. 4933 * 4934 * If we have to reset a target, clear tasks of a unit, 4935 * or to perform the abort of a disconnected job, we 4936 * restart the SCRIPTS for selecting the target. Once 4937 * selected, the SCRIPTS interrupts (SIR_TARGET_SELECTED). 4938 * If it loses arbitration, the SCRIPTS will interrupt again 4939 * the next time it will enter its scheduler, and so on ... 4940 * 4941 * On SIR_TARGET_SELECTED, we scan for the more 4942 * appropriate thing to do: 4943 * 4944 * - If nothing, we just sent a M_ABORT message to the 4945 * target to get rid of the useless SCSI bus ownership. 4946 * According to the specs, no tasks shall be affected. 4947 * - If the target is to be reset, we send it a M_RESET 4948 * message. 4949 * - If a logical UNIT is to be cleared , we send the 4950 * IDENTIFY(lun) + M_ABORT. 4951 * - If an untagged task is to be aborted, we send the 4952 * IDENTIFY(lun) + M_ABORT. 4953 * - If a tagged task is to be aborted, we send the 4954 * IDENTIFY(lun) + task attributes + M_ABORT_TAG. 4955 * 4956 * Once our 'kiss of death' :) message has been accepted 4957 * by the target, the SCRIPTS interrupts again 4958 * (SIR_ABORT_SENT). On this interrupt, we complete 4959 * all the CCBs that should have been aborted by the 4960 * target according to our message. 4961 */ 4962 static void sym_sir_task_recovery(hcb_p np, int num) 4963 { 4964 SYM_QUEHEAD *qp; 4965 ccb_p cp; 4966 tcb_p tp; 4967 int target=-1, lun=-1, task; 4968 int i, k; 4969 4970 switch(num) { 4971 /* 4972 * The SCRIPTS processor stopped before starting 4973 * the next command in order to allow us to perform 4974 * some task recovery. 4975 */ 4976 case SIR_SCRIPT_STOPPED: 4977 /* 4978 * Do we have any target to reset or unit to clear ? 4979 */ 4980 for (i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) { 4981 tp = &np->target[i]; 4982 if (tp->to_reset || 4983 (tp->lun0p && tp->lun0p->to_clear)) { 4984 target = i; 4985 break; 4986 } 4987 if (!tp->lunmp) 4988 continue; 4989 for (k = 1 ; k < SYM_CONF_MAX_LUN ; k++) { 4990 if (tp->lunmp[k] && tp->lunmp[k]->to_clear) { 4991 target = i; 4992 break; 4993 } 4994 } 4995 if (target != -1) 4996 break; 4997 } 4998 4999 /* 5000 * If not, walk the busy queue for any 5001 * disconnected CCB to be aborted. 5002 */ 5003 if (target == -1) { 5004 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) { 5005 cp = sym_que_entry(qp,struct sym_ccb,link_ccbq); 5006 if (cp->host_status != HS_DISCONNECT) 5007 continue; 5008 if (cp->to_abort) { 5009 target = cp->target; 5010 break; 5011 } 5012 } 5013 } 5014 5015 /* 5016 * If some target is to be selected, 5017 * prepare and start the selection. 5018 */ 5019 if (target != -1) { 5020 tp = &np->target[target]; 5021 np->abrt_sel.sel_id = target; 5022 np->abrt_sel.sel_scntl3 = tp->head.wval; 5023 np->abrt_sel.sel_sxfer = tp->head.sval; 5024 OUTL(nc_dsa, np->hcb_ba); 5025 OUTL_DSP (SCRIPTB_BA (np, sel_for_abort)); 5026 return; 5027 } 5028 5029 /* 5030 * Now look for a CCB to abort that haven't started yet. 5031 * Btw, the SCRIPTS processor is still stopped, so 5032 * we are not in race. 5033 */ 5034 i = 0; 5035 cp = 0; 5036 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) { 5037 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 5038 if (cp->host_status != HS_BUSY && 5039 cp->host_status != HS_NEGOTIATE) 5040 continue; 5041 if (!cp->to_abort) 5042 continue; 5043 #ifdef SYM_CONF_IARB_SUPPORT 5044 /* 5045 * If we are using IMMEDIATE ARBITRATION, we donnot 5046 * want to cancel the last queued CCB, since the 5047 * SCRIPTS may have anticipated the selection. 5048 */ 5049 if (cp == np->last_cp) { 5050 cp->to_abort = 0; 5051 continue; 5052 } 5053 #endif 5054 i = 1; /* Means we have found some */ 5055 break; 5056 } 5057 if (!i) { 5058 /* 5059 * We are done, so we donnot need 5060 * to synchronize with the SCRIPTS anylonger. 5061 * Remove the SEM flag from the ISTAT. 5062 */ 5063 np->istat_sem = 0; 5064 OUTB (nc_istat, SIGP); 5065 break; 5066 } 5067 /* 5068 * Compute index of next position in the start 5069 * queue the SCRIPTS intends to start and dequeue 5070 * all CCBs for that device that haven't been started. 5071 */ 5072 i = (INL (nc_scratcha) - np->squeue_ba) / 4; 5073 i = sym_dequeue_from_squeue(np, i, cp->target, cp->lun, -1); 5074 5075 /* 5076 * Make sure at least our IO to abort has been dequeued. 5077 */ 5078 assert(i && sym_get_cam_status(cp->cam_ccb) == CAM_REQUEUE_REQ); 5079 5080 /* 5081 * Keep track in cam status of the reason of the abort. 5082 */ 5083 if (cp->to_abort == 2) 5084 sym_set_cam_status(cp->cam_ccb, CAM_CMD_TIMEOUT); 5085 else 5086 sym_set_cam_status(cp->cam_ccb, CAM_REQ_ABORTED); 5087 5088 /* 5089 * Complete with error everything that we have dequeued. 5090 */ 5091 sym_flush_comp_queue(np, 0); 5092 break; 5093 /* 5094 * The SCRIPTS processor has selected a target 5095 * we may have some manual recovery to perform for. 5096 */ 5097 case SIR_TARGET_SELECTED: 5098 target = (INB (nc_sdid) & 0xf); 5099 tp = &np->target[target]; 5100 5101 np->abrt_tbl.addr = cpu_to_scr(vtobus(np->abrt_msg)); 5102 5103 /* 5104 * If the target is to be reset, prepare a 5105 * M_RESET message and clear the to_reset flag 5106 * since we donnot expect this operation to fail. 5107 */ 5108 if (tp->to_reset) { 5109 np->abrt_msg[0] = M_RESET; 5110 np->abrt_tbl.size = 1; 5111 tp->to_reset = 0; 5112 break; 5113 } 5114 5115 /* 5116 * Otherwise, look for some logical unit to be cleared. 5117 */ 5118 if (tp->lun0p && tp->lun0p->to_clear) 5119 lun = 0; 5120 else if (tp->lunmp) { 5121 for (k = 1 ; k < SYM_CONF_MAX_LUN ; k++) { 5122 if (tp->lunmp[k] && tp->lunmp[k]->to_clear) { 5123 lun = k; 5124 break; 5125 } 5126 } 5127 } 5128 5129 /* 5130 * If a logical unit is to be cleared, prepare 5131 * an IDENTIFY(lun) + ABORT MESSAGE. 5132 */ 5133 if (lun != -1) { 5134 lcb_p lp = sym_lp(np, tp, lun); 5135 lp->to_clear = 0; /* We donnot expect to fail here */ 5136 np->abrt_msg[0] = M_IDENTIFY | lun; 5137 np->abrt_msg[1] = M_ABORT; 5138 np->abrt_tbl.size = 2; 5139 break; 5140 } 5141 5142 /* 5143 * Otherwise, look for some disconnected job to 5144 * abort for this target. 5145 */ 5146 i = 0; 5147 cp = 0; 5148 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) { 5149 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 5150 if (cp->host_status != HS_DISCONNECT) 5151 continue; 5152 if (cp->target != target) 5153 continue; 5154 if (!cp->to_abort) 5155 continue; 5156 i = 1; /* Means we have some */ 5157 break; 5158 } 5159 5160 /* 5161 * If we have none, probably since the device has 5162 * completed the command before we won abitration, 5163 * send a M_ABORT message without IDENTIFY. 5164 * According to the specs, the device must just 5165 * disconnect the BUS and not abort any task. 5166 */ 5167 if (!i) { 5168 np->abrt_msg[0] = M_ABORT; 5169 np->abrt_tbl.size = 1; 5170 break; 5171 } 5172 5173 /* 5174 * We have some task to abort. 5175 * Set the IDENTIFY(lun) 5176 */ 5177 np->abrt_msg[0] = M_IDENTIFY | cp->lun; 5178 5179 /* 5180 * If we want to abort an untagged command, we 5181 * will send an IDENTIFY + M_ABORT. 5182 * Otherwise (tagged command), we will send 5183 * an IDENTIFY + task attributes + ABORT TAG. 5184 */ 5185 if (cp->tag == NO_TAG) { 5186 np->abrt_msg[1] = M_ABORT; 5187 np->abrt_tbl.size = 2; 5188 } 5189 else { 5190 np->abrt_msg[1] = cp->scsi_smsg[1]; 5191 np->abrt_msg[2] = cp->scsi_smsg[2]; 5192 np->abrt_msg[3] = M_ABORT_TAG; 5193 np->abrt_tbl.size = 4; 5194 } 5195 /* 5196 * Keep track of software timeout condition, since the 5197 * peripheral driver may not count retries on abort 5198 * conditions not due to timeout. 5199 */ 5200 if (cp->to_abort == 2) 5201 sym_set_cam_status(cp->cam_ccb, CAM_CMD_TIMEOUT); 5202 cp->to_abort = 0; /* We donnot expect to fail here */ 5203 break; 5204 5205 /* 5206 * The target has accepted our message and switched 5207 * to BUS FREE phase as we expected. 5208 */ 5209 case SIR_ABORT_SENT: 5210 target = (INB (nc_sdid) & 0xf); 5211 tp = &np->target[target]; 5212 5213 /* 5214 ** If we didn't abort anything, leave here. 5215 */ 5216 if (np->abrt_msg[0] == M_ABORT) 5217 break; 5218 5219 /* 5220 * If we sent a M_RESET, then a hardware reset has 5221 * been performed by the target. 5222 * - Reset everything to async 8 bit 5223 * - Tell ourself to negotiate next time :-) 5224 * - Prepare to clear all disconnected CCBs for 5225 * this target from our task list (lun=task=-1) 5226 */ 5227 lun = -1; 5228 task = -1; 5229 if (np->abrt_msg[0] == M_RESET) { 5230 tp->head.sval = 0; 5231 tp->head.wval = np->rv_scntl3; 5232 tp->head.uval = 0; 5233 tp->tinfo.current.period = 0; 5234 tp->tinfo.current.offset = 0; 5235 tp->tinfo.current.width = BUS_8_BIT; 5236 tp->tinfo.current.options = 0; 5237 } 5238 5239 /* 5240 * Otherwise, check for the LUN and TASK(s) 5241 * concerned by the cancelation. 5242 * If it is not ABORT_TAG then it is CLEAR_QUEUE 5243 * or an ABORT message :-) 5244 */ 5245 else { 5246 lun = np->abrt_msg[0] & 0x3f; 5247 if (np->abrt_msg[1] == M_ABORT_TAG) 5248 task = np->abrt_msg[2]; 5249 } 5250 5251 /* 5252 * Complete all the CCBs the device should have 5253 * aborted due to our 'kiss of death' message. 5254 */ 5255 i = (INL (nc_scratcha) - np->squeue_ba) / 4; 5256 (void) sym_dequeue_from_squeue(np, i, target, lun, -1); 5257 (void) sym_clear_tasks(np, CAM_REQ_ABORTED, target, lun, task); 5258 sym_flush_comp_queue(np, 0); 5259 5260 /* 5261 * If we sent a BDR, make uper layer aware of that. 5262 */ 5263 if (np->abrt_msg[0] == M_RESET) 5264 xpt_async(AC_SENT_BDR, np->path, NULL); 5265 break; 5266 } 5267 5268 /* 5269 * Print to the log the message we intend to send. 5270 */ 5271 if (num == SIR_TARGET_SELECTED) { 5272 PRINT_TARGET(np, target); 5273 sym_printl_hex("control msgout:", np->abrt_msg, 5274 np->abrt_tbl.size); 5275 np->abrt_tbl.size = cpu_to_scr(np->abrt_tbl.size); 5276 } 5277 5278 /* 5279 * Let the SCRIPTS processor continue. 5280 */ 5281 OUTONB_STD (); 5282 } 5283 5284 /* 5285 * Gerard's alchemy:) that deals with with the data 5286 * pointer for both MDP and the residual calculation. 5287 * 5288 * I didn't want to bloat the code by more than 200 5289 * lignes for the handling of both MDP and the residual. 5290 * This has been achieved by using a data pointer 5291 * representation consisting in an index in the data 5292 * array (dp_sg) and a negative offset (dp_ofs) that 5293 * have the following meaning: 5294 * 5295 * - dp_sg = SYM_CONF_MAX_SG 5296 * we are at the end of the data script. 5297 * - dp_sg < SYM_CONF_MAX_SG 5298 * dp_sg points to the next entry of the scatter array 5299 * we want to transfer. 5300 * - dp_ofs < 0 5301 * dp_ofs represents the residual of bytes of the 5302 * previous entry scatter entry we will send first. 5303 * - dp_ofs = 0 5304 * no residual to send first. 5305 * 5306 * The function sym_evaluate_dp() accepts an arbitray 5307 * offset (basically from the MDP message) and returns 5308 * the corresponding values of dp_sg and dp_ofs. 5309 */ 5310 5311 static int sym_evaluate_dp(hcb_p np, ccb_p cp, u32 scr, int *ofs) 5312 { 5313 u32 dp_scr; 5314 int dp_ofs, dp_sg, dp_sgmin; 5315 int tmp; 5316 struct sym_pmc *pm; 5317 5318 /* 5319 * Compute the resulted data pointer in term of a script 5320 * address within some DATA script and a signed byte offset. 5321 */ 5322 dp_scr = scr; 5323 dp_ofs = *ofs; 5324 if (dp_scr == SCRIPTA_BA (np, pm0_data)) 5325 pm = &cp->phys.pm0; 5326 else if (dp_scr == SCRIPTA_BA (np, pm1_data)) 5327 pm = &cp->phys.pm1; 5328 else 5329 pm = 0; 5330 5331 if (pm) { 5332 dp_scr = scr_to_cpu(pm->ret); 5333 dp_ofs -= scr_to_cpu(pm->sg.size); 5334 } 5335 5336 /* 5337 * If we are auto-sensing, then we are done. 5338 */ 5339 if (cp->host_flags & HF_SENSE) { 5340 *ofs = dp_ofs; 5341 return 0; 5342 } 5343 5344 /* 5345 * Deduce the index of the sg entry. 5346 * Keep track of the index of the first valid entry. 5347 * If result is dp_sg = SYM_CONF_MAX_SG, then we are at the 5348 * end of the data. 5349 */ 5350 tmp = scr_to_cpu(cp->phys.head.goalp); 5351 dp_sg = SYM_CONF_MAX_SG; 5352 if (dp_scr != tmp) 5353 dp_sg -= (tmp - 8 - (int)dp_scr) / (2*4); 5354 dp_sgmin = SYM_CONF_MAX_SG - cp->segments; 5355 5356 /* 5357 * Move to the sg entry the data pointer belongs to. 5358 * 5359 * If we are inside the data area, we expect result to be: 5360 * 5361 * Either, 5362 * dp_ofs = 0 and dp_sg is the index of the sg entry 5363 * the data pointer belongs to (or the end of the data) 5364 * Or, 5365 * dp_ofs < 0 and dp_sg is the index of the sg entry 5366 * the data pointer belongs to + 1. 5367 */ 5368 if (dp_ofs < 0) { 5369 int n; 5370 while (dp_sg > dp_sgmin) { 5371 --dp_sg; 5372 tmp = scr_to_cpu(cp->phys.data[dp_sg].size); 5373 n = dp_ofs + (tmp & 0xffffff); 5374 if (n > 0) { 5375 ++dp_sg; 5376 break; 5377 } 5378 dp_ofs = n; 5379 } 5380 } 5381 else if (dp_ofs > 0) { 5382 while (dp_sg < SYM_CONF_MAX_SG) { 5383 tmp = scr_to_cpu(cp->phys.data[dp_sg].size); 5384 dp_ofs -= (tmp & 0xffffff); 5385 ++dp_sg; 5386 if (dp_ofs <= 0) 5387 break; 5388 } 5389 } 5390 5391 /* 5392 * Make sure the data pointer is inside the data area. 5393 * If not, return some error. 5394 */ 5395 if (dp_sg < dp_sgmin || (dp_sg == dp_sgmin && dp_ofs < 0)) 5396 goto out_err; 5397 else if (dp_sg > SYM_CONF_MAX_SG || 5398 (dp_sg == SYM_CONF_MAX_SG && dp_ofs > 0)) 5399 goto out_err; 5400 5401 /* 5402 * Save the extreme pointer if needed. 5403 */ 5404 if (dp_sg > cp->ext_sg || 5405 (dp_sg == cp->ext_sg && dp_ofs > cp->ext_ofs)) { 5406 cp->ext_sg = dp_sg; 5407 cp->ext_ofs = dp_ofs; 5408 } 5409 5410 /* 5411 * Return data. 5412 */ 5413 *ofs = dp_ofs; 5414 return dp_sg; 5415 5416 out_err: 5417 return -1; 5418 } 5419 5420 /* 5421 * chip handler for MODIFY DATA POINTER MESSAGE 5422 * 5423 * We also call this function on IGNORE WIDE RESIDUE 5424 * messages that do not match a SWIDE full condition. 5425 * Btw, we assume in that situation that such a message 5426 * is equivalent to a MODIFY DATA POINTER (offset=-1). 5427 */ 5428 5429 static void sym_modify_dp(hcb_p np, tcb_p tp, ccb_p cp, int ofs) 5430 { 5431 int dp_ofs = ofs; 5432 u32 dp_scr = INL (nc_temp); 5433 u32 dp_ret; 5434 u32 tmp; 5435 u_char hflags; 5436 int dp_sg; 5437 struct sym_pmc *pm; 5438 5439 /* 5440 * Not supported for auto-sense. 5441 */ 5442 if (cp->host_flags & HF_SENSE) 5443 goto out_reject; 5444 5445 /* 5446 * Apply our alchemy:) (see comments in sym_evaluate_dp()), 5447 * to the resulted data pointer. 5448 */ 5449 dp_sg = sym_evaluate_dp(np, cp, dp_scr, &dp_ofs); 5450 if (dp_sg < 0) 5451 goto out_reject; 5452 5453 /* 5454 * And our alchemy:) allows to easily calculate the data 5455 * script address we want to return for the next data phase. 5456 */ 5457 dp_ret = cpu_to_scr(cp->phys.head.goalp); 5458 dp_ret = dp_ret - 8 - (SYM_CONF_MAX_SG - dp_sg) * (2*4); 5459 5460 /* 5461 * If offset / scatter entry is zero we donnot need 5462 * a context for the new current data pointer. 5463 */ 5464 if (dp_ofs == 0) { 5465 dp_scr = dp_ret; 5466 goto out_ok; 5467 } 5468 5469 /* 5470 * Get a context for the new current data pointer. 5471 */ 5472 hflags = INB (HF_PRT); 5473 5474 if (hflags & HF_DP_SAVED) 5475 hflags ^= HF_ACT_PM; 5476 5477 if (!(hflags & HF_ACT_PM)) { 5478 pm = &cp->phys.pm0; 5479 dp_scr = SCRIPTA_BA (np, pm0_data); 5480 } 5481 else { 5482 pm = &cp->phys.pm1; 5483 dp_scr = SCRIPTA_BA (np, pm1_data); 5484 } 5485 5486 hflags &= ~(HF_DP_SAVED); 5487 5488 OUTB (HF_PRT, hflags); 5489 5490 /* 5491 * Set up the new current data pointer. 5492 * ofs < 0 there, and for the next data phase, we 5493 * want to transfer part of the data of the sg entry 5494 * corresponding to index dp_sg-1 prior to returning 5495 * to the main data script. 5496 */ 5497 pm->ret = cpu_to_scr(dp_ret); 5498 tmp = scr_to_cpu(cp->phys.data[dp_sg-1].addr); 5499 tmp += scr_to_cpu(cp->phys.data[dp_sg-1].size) + dp_ofs; 5500 pm->sg.addr = cpu_to_scr(tmp); 5501 pm->sg.size = cpu_to_scr(-dp_ofs); 5502 5503 out_ok: 5504 OUTL (nc_temp, dp_scr); 5505 OUTL_DSP (SCRIPTA_BA (np, clrack)); 5506 return; 5507 5508 out_reject: 5509 OUTL_DSP (SCRIPTB_BA (np, msg_bad)); 5510 } 5511 5512 5513 /* 5514 * chip calculation of the data residual. 5515 * 5516 * As I used to say, the requirement of data residual 5517 * in SCSI is broken, useless and cannot be achieved 5518 * without huge complexity. 5519 * But most OSes and even the official CAM require it. 5520 * When stupidity happens to be so widely spread inside 5521 * a community, it gets hard to convince. 5522 * 5523 * Anyway, I don't care, since I am not going to use 5524 * any software that considers this data residual as 5525 * a relevant information. :) 5526 */ 5527 5528 static int sym_compute_residual(hcb_p np, ccb_p cp) 5529 { 5530 int dp_sg, dp_sgmin, resid = 0; 5531 int dp_ofs = 0; 5532 5533 /* 5534 * Check for some data lost or just thrown away. 5535 * We are not required to be quite accurate in this 5536 * situation. Btw, if we are odd for output and the 5537 * device claims some more data, it may well happen 5538 * than our residual be zero. :-) 5539 */ 5540 if (cp->xerr_status & (XE_EXTRA_DATA|XE_SODL_UNRUN|XE_SWIDE_OVRUN)) { 5541 if (cp->xerr_status & XE_EXTRA_DATA) 5542 resid -= cp->extra_bytes; 5543 if (cp->xerr_status & XE_SODL_UNRUN) 5544 ++resid; 5545 if (cp->xerr_status & XE_SWIDE_OVRUN) 5546 --resid; 5547 } 5548 5549 /* 5550 * If all data has been transferred, 5551 * there is no residual. 5552 */ 5553 if (cp->phys.head.lastp == cp->phys.head.goalp) 5554 return resid; 5555 5556 /* 5557 * If no data transfer occurs, or if the data 5558 * pointer is weird, return full residual. 5559 */ 5560 if (cp->startp == cp->phys.head.lastp || 5561 sym_evaluate_dp(np, cp, scr_to_cpu(cp->phys.head.lastp), 5562 &dp_ofs) < 0) { 5563 return cp->data_len; 5564 } 5565 5566 /* 5567 * If we were auto-sensing, then we are done. 5568 */ 5569 if (cp->host_flags & HF_SENSE) { 5570 return -dp_ofs; 5571 } 5572 5573 /* 5574 * We are now full comfortable in the computation 5575 * of the data residual (2's complement). 5576 */ 5577 dp_sgmin = SYM_CONF_MAX_SG - cp->segments; 5578 resid = -cp->ext_ofs; 5579 for (dp_sg = cp->ext_sg; dp_sg < SYM_CONF_MAX_SG; ++dp_sg) { 5580 u_int tmp = scr_to_cpu(cp->phys.data[dp_sg].size); 5581 resid += (tmp & 0xffffff); 5582 } 5583 5584 /* 5585 * Hopefully, the result is not too wrong. 5586 */ 5587 return resid; 5588 } 5589 5590 /* 5591 * Print out the content of a SCSI message. 5592 */ 5593 5594 static int sym_show_msg (u_char * msg) 5595 { 5596 u_char i; 5597 printf ("%x",*msg); 5598 if (*msg==M_EXTENDED) { 5599 for (i=1;i<8;i++) { 5600 if (i-1>msg[1]) break; 5601 printf ("-%x",msg[i]); 5602 }; 5603 return (i+1); 5604 } else if ((*msg & 0xf0) == 0x20) { 5605 printf ("-%x",msg[1]); 5606 return (2); 5607 }; 5608 return (1); 5609 } 5610 5611 static void sym_print_msg (ccb_p cp, char *label, u_char *msg) 5612 { 5613 PRINT_ADDR(cp); 5614 if (label) 5615 printf ("%s: ", label); 5616 5617 (void) sym_show_msg (msg); 5618 printf (".\n"); 5619 } 5620 5621 /* 5622 * Negotiation for WIDE and SYNCHRONOUS DATA TRANSFER. 5623 * 5624 * When we try to negotiate, we append the negotiation message 5625 * to the identify and (maybe) simple tag message. 5626 * The host status field is set to HS_NEGOTIATE to mark this 5627 * situation. 5628 * 5629 * If the target doesn't answer this message immediately 5630 * (as required by the standard), the SIR_NEGO_FAILED interrupt 5631 * will be raised eventually. 5632 * The handler removes the HS_NEGOTIATE status, and sets the 5633 * negotiated value to the default (async / nowide). 5634 * 5635 * If we receive a matching answer immediately, we check it 5636 * for validity, and set the values. 5637 * 5638 * If we receive a Reject message immediately, we assume the 5639 * negotiation has failed, and fall back to standard values. 5640 * 5641 * If we receive a negotiation message while not in HS_NEGOTIATE 5642 * state, it's a target initiated negotiation. We prepare a 5643 * (hopefully) valid answer, set our parameters, and send back 5644 * this answer to the target. 5645 * 5646 * If the target doesn't fetch the answer (no message out phase), 5647 * we assume the negotiation has failed, and fall back to default 5648 * settings (SIR_NEGO_PROTO interrupt). 5649 * 5650 * When we set the values, we adjust them in all ccbs belonging 5651 * to this target, in the controller's register, and in the "phys" 5652 * field of the controller's struct sym_hcb. 5653 */ 5654 5655 /* 5656 * chip handler for SYNCHRONOUS DATA TRANSFER REQUEST (SDTR) message. 5657 */ 5658 static void sym_sync_nego(hcb_p np, tcb_p tp, ccb_p cp) 5659 { 5660 u_char chg, ofs, per, fak, div; 5661 int req = 1; 5662 5663 /* 5664 * Synchronous request message received. 5665 */ 5666 if (DEBUG_FLAGS & DEBUG_NEGO) { 5667 sym_print_msg(cp, "sync msgin", np->msgin); 5668 }; 5669 5670 /* 5671 * request or answer ? 5672 */ 5673 if (INB (HS_PRT) == HS_NEGOTIATE) { 5674 OUTB (HS_PRT, HS_BUSY); 5675 if (cp->nego_status && cp->nego_status != NS_SYNC) 5676 goto reject_it; 5677 req = 0; 5678 } 5679 5680 /* 5681 * get requested values. 5682 */ 5683 chg = 0; 5684 per = np->msgin[3]; 5685 ofs = np->msgin[4]; 5686 5687 /* 5688 * check values against our limits. 5689 */ 5690 if (ofs) { 5691 if (ofs > np->maxoffs) 5692 {chg = 1; ofs = np->maxoffs;} 5693 if (req) { 5694 if (ofs > tp->tinfo.user.offset) 5695 {chg = 1; ofs = tp->tinfo.user.offset;} 5696 } 5697 } 5698 5699 if (ofs) { 5700 if (per < np->minsync) 5701 {chg = 1; per = np->minsync;} 5702 if (req) { 5703 if (per < tp->tinfo.user.period) 5704 {chg = 1; per = tp->tinfo.user.period;} 5705 } 5706 } 5707 5708 div = fak = 0; 5709 if (ofs && sym_getsync(np, 0, per, &div, &fak) < 0) 5710 goto reject_it; 5711 5712 if (DEBUG_FLAGS & DEBUG_NEGO) { 5713 PRINT_ADDR(cp); 5714 printf ("sdtr: ofs=%d per=%d div=%d fak=%d chg=%d.\n", 5715 ofs, per, div, fak, chg); 5716 } 5717 5718 /* 5719 * This was an answer message 5720 */ 5721 if (req == 0) { 5722 if (chg) /* Answer wasn't acceptable. */ 5723 goto reject_it; 5724 sym_setsync (np, cp, ofs, per, div, fak); 5725 OUTL_DSP (SCRIPTA_BA (np, clrack)); 5726 return; 5727 } 5728 5729 /* 5730 * It was a request. Set value and 5731 * prepare an answer message 5732 */ 5733 sym_setsync (np, cp, ofs, per, div, fak); 5734 5735 np->msgout[0] = M_EXTENDED; 5736 np->msgout[1] = 3; 5737 np->msgout[2] = M_X_SYNC_REQ; 5738 np->msgout[3] = per; 5739 np->msgout[4] = ofs; 5740 5741 cp->nego_status = NS_SYNC; 5742 5743 if (DEBUG_FLAGS & DEBUG_NEGO) { 5744 sym_print_msg(cp, "sync msgout", np->msgout); 5745 } 5746 5747 np->msgin [0] = M_NOOP; 5748 5749 OUTL_DSP (SCRIPTB_BA (np, sdtr_resp)); 5750 return; 5751 reject_it: 5752 sym_setsync (np, cp, 0, 0, 0, 0); 5753 OUTL_DSP (SCRIPTB_BA (np, msg_bad)); 5754 } 5755 5756 /* 5757 * chip handler for PARALLEL PROTOCOL REQUEST (PPR) message. 5758 */ 5759 static void sym_ppr_nego(hcb_p np, tcb_p tp, ccb_p cp) 5760 { 5761 u_char chg, ofs, per, fak, dt, div, wide; 5762 int req = 1; 5763 5764 /* 5765 * Synchronous request message received. 5766 */ 5767 if (DEBUG_FLAGS & DEBUG_NEGO) { 5768 sym_print_msg(cp, "ppr msgin", np->msgin); 5769 }; 5770 5771 /* 5772 * get requested values. 5773 */ 5774 chg = 0; 5775 per = np->msgin[3]; 5776 ofs = np->msgin[5]; 5777 wide = np->msgin[6]; 5778 dt = np->msgin[7] & PPR_OPT_DT; 5779 5780 /* 5781 * request or answer ? 5782 */ 5783 if (INB (HS_PRT) == HS_NEGOTIATE) { 5784 OUTB (HS_PRT, HS_BUSY); 5785 if (cp->nego_status && cp->nego_status != NS_PPR) 5786 goto reject_it; 5787 req = 0; 5788 } 5789 5790 /* 5791 * check values against our limits. 5792 */ 5793 if (wide > np->maxwide) 5794 {chg = 1; wide = np->maxwide;} 5795 if (!wide || !(np->features & FE_ULTRA3)) 5796 dt &= ~PPR_OPT_DT; 5797 if (req) { 5798 if (wide > tp->tinfo.user.width) 5799 {chg = 1; wide = tp->tinfo.user.width;} 5800 } 5801 5802 if (!(np->features & FE_U3EN)) /* Broken U3EN bit not supported */ 5803 dt &= ~PPR_OPT_DT; 5804 5805 if (dt != (np->msgin[7] & PPR_OPT_MASK)) chg = 1; 5806 5807 if (ofs) { 5808 if (dt) { 5809 if (ofs > np->maxoffs_dt) 5810 {chg = 1; ofs = np->maxoffs_dt;} 5811 } 5812 else if (ofs > np->maxoffs) 5813 {chg = 1; ofs = np->maxoffs;} 5814 if (req) { 5815 if (ofs > tp->tinfo.user.offset) 5816 {chg = 1; ofs = tp->tinfo.user.offset;} 5817 } 5818 } 5819 5820 if (ofs) { 5821 if (dt) { 5822 if (per < np->minsync_dt) 5823 {chg = 1; per = np->minsync_dt;} 5824 } 5825 else if (per < np->minsync) 5826 {chg = 1; per = np->minsync;} 5827 if (req) { 5828 if (per < tp->tinfo.user.period) 5829 {chg = 1; per = tp->tinfo.user.period;} 5830 } 5831 } 5832 5833 div = fak = 0; 5834 if (ofs && sym_getsync(np, dt, per, &div, &fak) < 0) 5835 goto reject_it; 5836 5837 if (DEBUG_FLAGS & DEBUG_NEGO) { 5838 PRINT_ADDR(cp); 5839 printf ("ppr: " 5840 "dt=%x ofs=%d per=%d wide=%d div=%d fak=%d chg=%d.\n", 5841 dt, ofs, per, wide, div, fak, chg); 5842 } 5843 5844 /* 5845 * It was an answer. 5846 */ 5847 if (req == 0) { 5848 if (chg) /* Answer wasn't acceptable */ 5849 goto reject_it; 5850 sym_setpprot (np, cp, dt, ofs, per, wide, div, fak); 5851 OUTL_DSP (SCRIPTA_BA (np, clrack)); 5852 return; 5853 } 5854 5855 /* 5856 * It was a request. Set value and 5857 * prepare an answer message 5858 */ 5859 sym_setpprot (np, cp, dt, ofs, per, wide, div, fak); 5860 5861 np->msgout[0] = M_EXTENDED; 5862 np->msgout[1] = 6; 5863 np->msgout[2] = M_X_PPR_REQ; 5864 np->msgout[3] = per; 5865 np->msgout[4] = 0; 5866 np->msgout[5] = ofs; 5867 np->msgout[6] = wide; 5868 np->msgout[7] = dt; 5869 5870 cp->nego_status = NS_PPR; 5871 5872 if (DEBUG_FLAGS & DEBUG_NEGO) { 5873 sym_print_msg(cp, "ppr msgout", np->msgout); 5874 } 5875 5876 np->msgin [0] = M_NOOP; 5877 5878 OUTL_DSP (SCRIPTB_BA (np, ppr_resp)); 5879 return; 5880 reject_it: 5881 sym_setpprot (np, cp, 0, 0, 0, 0, 0, 0); 5882 OUTL_DSP (SCRIPTB_BA (np, msg_bad)); 5883 /* 5884 * If it was a device response that should result in 5885 * ST, we may want to try a legacy negotiation later. 5886 */ 5887 if (!req && !dt) { 5888 tp->tinfo.goal.options = 0; 5889 tp->tinfo.goal.width = wide; 5890 tp->tinfo.goal.period = per; 5891 tp->tinfo.goal.offset = ofs; 5892 } 5893 return; 5894 } 5895 5896 /* 5897 * chip handler for WIDE DATA TRANSFER REQUEST (WDTR) message. 5898 */ 5899 static void sym_wide_nego(hcb_p np, tcb_p tp, ccb_p cp) 5900 { 5901 u_char chg, wide; 5902 int req = 1; 5903 5904 /* 5905 * Wide request message received. 5906 */ 5907 if (DEBUG_FLAGS & DEBUG_NEGO) { 5908 sym_print_msg(cp, "wide msgin", np->msgin); 5909 }; 5910 5911 /* 5912 * Is it a request from the device? 5913 */ 5914 if (INB (HS_PRT) == HS_NEGOTIATE) { 5915 OUTB (HS_PRT, HS_BUSY); 5916 if (cp->nego_status && cp->nego_status != NS_WIDE) 5917 goto reject_it; 5918 req = 0; 5919 } 5920 5921 /* 5922 * get requested values. 5923 */ 5924 chg = 0; 5925 wide = np->msgin[3]; 5926 5927 /* 5928 * check values against driver limits. 5929 */ 5930 if (wide > np->maxwide) 5931 {chg = 1; wide = np->maxwide;} 5932 if (req) { 5933 if (wide > tp->tinfo.user.width) 5934 {chg = 1; wide = tp->tinfo.user.width;} 5935 } 5936 5937 if (DEBUG_FLAGS & DEBUG_NEGO) { 5938 PRINT_ADDR(cp); 5939 printf ("wdtr: wide=%d chg=%d.\n", wide, chg); 5940 } 5941 5942 /* 5943 * This was an answer message 5944 */ 5945 if (req == 0) { 5946 if (chg) /* Answer wasn't acceptable. */ 5947 goto reject_it; 5948 sym_setwide (np, cp, wide); 5949 5950 /* 5951 * Negotiate for SYNC immediately after WIDE response. 5952 * This allows to negotiate for both WIDE and SYNC on 5953 * a single SCSI command (Suggested by Justin Gibbs). 5954 */ 5955 if (tp->tinfo.goal.offset) { 5956 np->msgout[0] = M_EXTENDED; 5957 np->msgout[1] = 3; 5958 np->msgout[2] = M_X_SYNC_REQ; 5959 np->msgout[3] = tp->tinfo.goal.period; 5960 np->msgout[4] = tp->tinfo.goal.offset; 5961 5962 if (DEBUG_FLAGS & DEBUG_NEGO) { 5963 sym_print_msg(cp, "sync msgout", np->msgout); 5964 } 5965 5966 cp->nego_status = NS_SYNC; 5967 OUTB (HS_PRT, HS_NEGOTIATE); 5968 OUTL_DSP (SCRIPTB_BA (np, sdtr_resp)); 5969 return; 5970 } 5971 5972 OUTL_DSP (SCRIPTA_BA (np, clrack)); 5973 return; 5974 }; 5975 5976 /* 5977 * It was a request, set value and 5978 * prepare an answer message 5979 */ 5980 sym_setwide (np, cp, wide); 5981 5982 np->msgout[0] = M_EXTENDED; 5983 np->msgout[1] = 2; 5984 np->msgout[2] = M_X_WIDE_REQ; 5985 np->msgout[3] = wide; 5986 5987 np->msgin [0] = M_NOOP; 5988 5989 cp->nego_status = NS_WIDE; 5990 5991 if (DEBUG_FLAGS & DEBUG_NEGO) { 5992 sym_print_msg(cp, "wide msgout", np->msgout); 5993 } 5994 5995 OUTL_DSP (SCRIPTB_BA (np, wdtr_resp)); 5996 return; 5997 reject_it: 5998 OUTL_DSP (SCRIPTB_BA (np, msg_bad)); 5999 } 6000 6001 /* 6002 * Reset SYNC or WIDE to default settings. 6003 * 6004 * Called when a negotiation does not succeed either 6005 * on rejection or on protocol error. 6006 * 6007 * If it was a PPR that made problems, we may want to 6008 * try a legacy negotiation later. 6009 */ 6010 static void sym_nego_default(hcb_p np, tcb_p tp, ccb_p cp) 6011 { 6012 /* 6013 * any error in negotiation: 6014 * fall back to default mode. 6015 */ 6016 switch (cp->nego_status) { 6017 case NS_PPR: 6018 #if 0 6019 sym_setpprot (np, cp, 0, 0, 0, 0, 0, 0); 6020 #else 6021 tp->tinfo.goal.options = 0; 6022 if (tp->tinfo.goal.period < np->minsync) 6023 tp->tinfo.goal.period = np->minsync; 6024 if (tp->tinfo.goal.offset > np->maxoffs) 6025 tp->tinfo.goal.offset = np->maxoffs; 6026 #endif 6027 break; 6028 case NS_SYNC: 6029 sym_setsync (np, cp, 0, 0, 0, 0); 6030 break; 6031 case NS_WIDE: 6032 sym_setwide (np, cp, 0); 6033 break; 6034 }; 6035 np->msgin [0] = M_NOOP; 6036 np->msgout[0] = M_NOOP; 6037 cp->nego_status = 0; 6038 } 6039 6040 /* 6041 * chip handler for MESSAGE REJECT received in response to 6042 * a WIDE or SYNCHRONOUS negotiation. 6043 */ 6044 static void sym_nego_rejected(hcb_p np, tcb_p tp, ccb_p cp) 6045 { 6046 sym_nego_default(np, tp, cp); 6047 OUTB (HS_PRT, HS_BUSY); 6048 } 6049 6050 /* 6051 * chip exception handler for programmed interrupts. 6052 */ 6053 static void sym_int_sir (hcb_p np) 6054 { 6055 u_char num = INB (nc_dsps); 6056 u32 dsa = INL (nc_dsa); 6057 ccb_p cp = sym_ccb_from_dsa(np, dsa); 6058 u_char target = INB (nc_sdid) & 0x0f; 6059 tcb_p tp = &np->target[target]; 6060 int tmp; 6061 6062 if (DEBUG_FLAGS & DEBUG_TINY) printf ("I#%d", num); 6063 6064 switch (num) { 6065 /* 6066 * Command has been completed with error condition 6067 * or has been auto-sensed. 6068 */ 6069 case SIR_COMPLETE_ERROR: 6070 sym_complete_error(np, cp); 6071 return; 6072 /* 6073 * The C code is currently trying to recover from something. 6074 * Typically, user want to abort some command. 6075 */ 6076 case SIR_SCRIPT_STOPPED: 6077 case SIR_TARGET_SELECTED: 6078 case SIR_ABORT_SENT: 6079 sym_sir_task_recovery(np, num); 6080 return; 6081 /* 6082 * The device didn't go to MSG OUT phase after having 6083 * been selected with ATN. We donnot want to handle 6084 * that. 6085 */ 6086 case SIR_SEL_ATN_NO_MSG_OUT: 6087 printf ("%s:%d: No MSG OUT phase after selection with ATN.\n", 6088 sym_name (np), target); 6089 goto out_stuck; 6090 /* 6091 * The device didn't switch to MSG IN phase after 6092 * having reseleted the initiator. 6093 */ 6094 case SIR_RESEL_NO_MSG_IN: 6095 printf ("%s:%d: No MSG IN phase after reselection.\n", 6096 sym_name (np), target); 6097 goto out_stuck; 6098 /* 6099 * After reselection, the device sent a message that wasn't 6100 * an IDENTIFY. 6101 */ 6102 case SIR_RESEL_NO_IDENTIFY: 6103 printf ("%s:%d: No IDENTIFY after reselection.\n", 6104 sym_name (np), target); 6105 goto out_stuck; 6106 /* 6107 * The device reselected a LUN we donnot know about. 6108 */ 6109 case SIR_RESEL_BAD_LUN: 6110 np->msgout[0] = M_RESET; 6111 goto out; 6112 /* 6113 * The device reselected for an untagged nexus and we 6114 * haven't any. 6115 */ 6116 case SIR_RESEL_BAD_I_T_L: 6117 np->msgout[0] = M_ABORT; 6118 goto out; 6119 /* 6120 * The device reselected for a tagged nexus that we donnot 6121 * have. 6122 */ 6123 case SIR_RESEL_BAD_I_T_L_Q: 6124 np->msgout[0] = M_ABORT_TAG; 6125 goto out; 6126 /* 6127 * The SCRIPTS let us know that the device has grabbed 6128 * our message and will abort the job. 6129 */ 6130 case SIR_RESEL_ABORTED: 6131 np->lastmsg = np->msgout[0]; 6132 np->msgout[0] = M_NOOP; 6133 printf ("%s:%d: message %x sent on bad reselection.\n", 6134 sym_name (np), target, np->lastmsg); 6135 goto out; 6136 /* 6137 * The SCRIPTS let us know that a message has been 6138 * successfully sent to the device. 6139 */ 6140 case SIR_MSG_OUT_DONE: 6141 np->lastmsg = np->msgout[0]; 6142 np->msgout[0] = M_NOOP; 6143 /* Should we really care of that */ 6144 if (np->lastmsg == M_PARITY || np->lastmsg == M_ID_ERROR) { 6145 if (cp) { 6146 cp->xerr_status &= ~XE_PARITY_ERR; 6147 if (!cp->xerr_status) 6148 OUTOFFB (HF_PRT, HF_EXT_ERR); 6149 } 6150 } 6151 goto out; 6152 /* 6153 * The device didn't send a GOOD SCSI status. 6154 * We may have some work to do prior to allow 6155 * the SCRIPTS processor to continue. 6156 */ 6157 case SIR_BAD_SCSI_STATUS: 6158 if (!cp) 6159 goto out; 6160 sym_sir_bad_scsi_status(np, num, cp); 6161 return; 6162 /* 6163 * We are asked by the SCRIPTS to prepare a 6164 * REJECT message. 6165 */ 6166 case SIR_REJECT_TO_SEND: 6167 sym_print_msg(cp, "M_REJECT to send for ", np->msgin); 6168 np->msgout[0] = M_REJECT; 6169 goto out; 6170 /* 6171 * We have been ODD at the end of a DATA IN 6172 * transfer and the device didn't send a 6173 * IGNORE WIDE RESIDUE message. 6174 * It is a data overrun condition. 6175 */ 6176 case SIR_SWIDE_OVERRUN: 6177 if (cp) { 6178 OUTONB (HF_PRT, HF_EXT_ERR); 6179 cp->xerr_status |= XE_SWIDE_OVRUN; 6180 } 6181 goto out; 6182 /* 6183 * We have been ODD at the end of a DATA OUT 6184 * transfer. 6185 * It is a data underrun condition. 6186 */ 6187 case SIR_SODL_UNDERRUN: 6188 if (cp) { 6189 OUTONB (HF_PRT, HF_EXT_ERR); 6190 cp->xerr_status |= XE_SODL_UNRUN; 6191 } 6192 goto out; 6193 /* 6194 * The device wants us to tranfer more data than 6195 * expected or in the wrong direction. 6196 * The number of extra bytes is in scratcha. 6197 * It is a data overrun condition. 6198 */ 6199 case SIR_DATA_OVERRUN: 6200 if (cp) { 6201 OUTONB (HF_PRT, HF_EXT_ERR); 6202 cp->xerr_status |= XE_EXTRA_DATA; 6203 cp->extra_bytes += INL (nc_scratcha); 6204 } 6205 goto out; 6206 /* 6207 * The device switched to an illegal phase (4/5). 6208 */ 6209 case SIR_BAD_PHASE: 6210 if (cp) { 6211 OUTONB (HF_PRT, HF_EXT_ERR); 6212 cp->xerr_status |= XE_BAD_PHASE; 6213 } 6214 goto out; 6215 /* 6216 * We received a message. 6217 */ 6218 case SIR_MSG_RECEIVED: 6219 if (!cp) 6220 goto out_stuck; 6221 switch (np->msgin [0]) { 6222 /* 6223 * We received an extended message. 6224 * We handle MODIFY DATA POINTER, SDTR, WDTR 6225 * and reject all other extended messages. 6226 */ 6227 case M_EXTENDED: 6228 switch (np->msgin [2]) { 6229 case M_X_MODIFY_DP: 6230 if (DEBUG_FLAGS & DEBUG_POINTER) 6231 sym_print_msg(cp,"modify DP",np->msgin); 6232 tmp = (np->msgin[3]<<24) + (np->msgin[4]<<16) + 6233 (np->msgin[5]<<8) + (np->msgin[6]); 6234 sym_modify_dp(np, tp, cp, tmp); 6235 return; 6236 case M_X_SYNC_REQ: 6237 sym_sync_nego(np, tp, cp); 6238 return; 6239 case M_X_PPR_REQ: 6240 sym_ppr_nego(np, tp, cp); 6241 return; 6242 case M_X_WIDE_REQ: 6243 sym_wide_nego(np, tp, cp); 6244 return; 6245 default: 6246 goto out_reject; 6247 } 6248 break; 6249 /* 6250 * We received a 1/2 byte message not handled from SCRIPTS. 6251 * We are only expecting MESSAGE REJECT and IGNORE WIDE 6252 * RESIDUE messages that haven't been anticipated by 6253 * SCRIPTS on SWIDE full condition. Unanticipated IGNORE 6254 * WIDE RESIDUE messages are aliased as MODIFY DP (-1). 6255 */ 6256 case M_IGN_RESIDUE: 6257 if (DEBUG_FLAGS & DEBUG_POINTER) 6258 sym_print_msg(cp,"ign wide residue", np->msgin); 6259 sym_modify_dp(np, tp, cp, -1); 6260 return; 6261 case M_REJECT: 6262 if (INB (HS_PRT) == HS_NEGOTIATE) 6263 sym_nego_rejected(np, tp, cp); 6264 else { 6265 PRINT_ADDR(cp); 6266 printf ("M_REJECT received (%x:%x).\n", 6267 scr_to_cpu(np->lastmsg), np->msgout[0]); 6268 } 6269 goto out_clrack; 6270 break; 6271 default: 6272 goto out_reject; 6273 } 6274 break; 6275 /* 6276 * We received an unknown message. 6277 * Ignore all MSG IN phases and reject it. 6278 */ 6279 case SIR_MSG_WEIRD: 6280 sym_print_msg(cp, "WEIRD message received", np->msgin); 6281 OUTL_DSP (SCRIPTB_BA (np, msg_weird)); 6282 return; 6283 /* 6284 * Negotiation failed. 6285 * Target does not send us the reply. 6286 * Remove the HS_NEGOTIATE status. 6287 */ 6288 case SIR_NEGO_FAILED: 6289 OUTB (HS_PRT, HS_BUSY); 6290 /* 6291 * Negotiation failed. 6292 * Target does not want answer message. 6293 */ 6294 case SIR_NEGO_PROTO: 6295 sym_nego_default(np, tp, cp); 6296 goto out; 6297 }; 6298 6299 out: 6300 OUTONB_STD (); 6301 return; 6302 out_reject: 6303 OUTL_DSP (SCRIPTB_BA (np, msg_bad)); 6304 return; 6305 out_clrack: 6306 OUTL_DSP (SCRIPTA_BA (np, clrack)); 6307 return; 6308 out_stuck: 6309 return; 6310 } 6311 6312 /* 6313 * Acquire a control block 6314 */ 6315 static ccb_p sym_get_ccb (hcb_p np, u_char tn, u_char ln, u_char tag_order) 6316 { 6317 tcb_p tp = &np->target[tn]; 6318 lcb_p lp = sym_lp(np, tp, ln); 6319 u_short tag = NO_TAG; 6320 SYM_QUEHEAD *qp; 6321 ccb_p cp = (ccb_p) 0; 6322 6323 /* 6324 * Look for a free CCB 6325 */ 6326 if (sym_que_empty(&np->free_ccbq)) 6327 (void) sym_alloc_ccb(np); 6328 qp = sym_remque_head(&np->free_ccbq); 6329 if (!qp) 6330 goto out; 6331 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 6332 6333 /* 6334 * If the LCB is not yet available and the LUN 6335 * has been probed ok, try to allocate the LCB. 6336 */ 6337 if (!lp && sym_is_bit(tp->lun_map, ln)) { 6338 lp = sym_alloc_lcb(np, tn, ln); 6339 if (!lp) 6340 goto out_free; 6341 } 6342 6343 /* 6344 * If the LCB is not available here, then the 6345 * logical unit is not yet discovered. For those 6346 * ones only accept 1 SCSI IO per logical unit, 6347 * since we cannot allow disconnections. 6348 */ 6349 if (!lp) { 6350 if (!sym_is_bit(tp->busy0_map, ln)) 6351 sym_set_bit(tp->busy0_map, ln); 6352 else 6353 goto out_free; 6354 } else { 6355 /* 6356 * If we have been asked for a tagged command. 6357 */ 6358 if (tag_order) { 6359 /* 6360 * Debugging purpose. 6361 */ 6362 assert(lp->busy_itl == 0); 6363 /* 6364 * Allocate resources for tags if not yet. 6365 */ 6366 if (!lp->cb_tags) { 6367 sym_alloc_lcb_tags(np, tn, ln); 6368 if (!lp->cb_tags) 6369 goto out_free; 6370 } 6371 /* 6372 * Get a tag for this SCSI IO and set up 6373 * the CCB bus address for reselection, 6374 * and count it for this LUN. 6375 * Toggle reselect path to tagged. 6376 */ 6377 if (lp->busy_itlq < SYM_CONF_MAX_TASK) { 6378 tag = lp->cb_tags[lp->ia_tag]; 6379 if (++lp->ia_tag == SYM_CONF_MAX_TASK) 6380 lp->ia_tag = 0; 6381 lp->itlq_tbl[tag] = cpu_to_scr(cp->ccb_ba); 6382 ++lp->busy_itlq; 6383 lp->head.resel_sa = 6384 cpu_to_scr(SCRIPTA_BA (np, resel_tag)); 6385 } 6386 else 6387 goto out_free; 6388 } 6389 /* 6390 * This command will not be tagged. 6391 * If we already have either a tagged or untagged 6392 * one, refuse to overlap this untagged one. 6393 */ 6394 else { 6395 /* 6396 * Debugging purpose. 6397 */ 6398 assert(lp->busy_itl == 0 && lp->busy_itlq == 0); 6399 /* 6400 * Count this nexus for this LUN. 6401 * Set up the CCB bus address for reselection. 6402 * Toggle reselect path to untagged. 6403 */ 6404 if (++lp->busy_itl == 1) { 6405 lp->head.itl_task_sa = cpu_to_scr(cp->ccb_ba); 6406 lp->head.resel_sa = 6407 cpu_to_scr(SCRIPTA_BA (np, resel_no_tag)); 6408 } 6409 else 6410 goto out_free; 6411 } 6412 } 6413 /* 6414 * Put the CCB into the busy queue. 6415 */ 6416 sym_insque_tail(&cp->link_ccbq, &np->busy_ccbq); 6417 6418 /* 6419 * Remember all informations needed to free this CCB. 6420 */ 6421 cp->to_abort = 0; 6422 cp->tag = tag; 6423 cp->target = tn; 6424 cp->lun = ln; 6425 6426 if (DEBUG_FLAGS & DEBUG_TAGS) { 6427 PRINT_LUN(np, tn, ln); 6428 printf ("ccb @%p using tag %d.\n", cp, tag); 6429 } 6430 6431 out: 6432 return cp; 6433 out_free: 6434 sym_insque_head(&cp->link_ccbq, &np->free_ccbq); 6435 return (ccb_p) 0; 6436 } 6437 6438 /* 6439 * Release one control block 6440 */ 6441 static void sym_free_ccb (hcb_p np, ccb_p cp) 6442 { 6443 tcb_p tp = &np->target[cp->target]; 6444 lcb_p lp = sym_lp(np, tp, cp->lun); 6445 6446 if (DEBUG_FLAGS & DEBUG_TAGS) { 6447 PRINT_LUN(np, cp->target, cp->lun); 6448 printf ("ccb @%p freeing tag %d.\n", cp, cp->tag); 6449 } 6450 6451 /* 6452 * If LCB available, 6453 */ 6454 if (lp) { 6455 /* 6456 * If tagged, release the tag, set the relect path 6457 */ 6458 if (cp->tag != NO_TAG) { 6459 /* 6460 * Free the tag value. 6461 */ 6462 lp->cb_tags[lp->if_tag] = cp->tag; 6463 if (++lp->if_tag == SYM_CONF_MAX_TASK) 6464 lp->if_tag = 0; 6465 /* 6466 * Make the reselect path invalid, 6467 * and uncount this CCB. 6468 */ 6469 lp->itlq_tbl[cp->tag] = cpu_to_scr(np->bad_itlq_ba); 6470 --lp->busy_itlq; 6471 } else { /* Untagged */ 6472 /* 6473 * Make the reselect path invalid, 6474 * and uncount this CCB. 6475 */ 6476 lp->head.itl_task_sa = cpu_to_scr(np->bad_itl_ba); 6477 --lp->busy_itl; 6478 } 6479 /* 6480 * If no JOB active, make the LUN reselect path invalid. 6481 */ 6482 if (lp->busy_itlq == 0 && lp->busy_itl == 0) 6483 lp->head.resel_sa = 6484 cpu_to_scr(SCRIPTB_BA (np, resel_bad_lun)); 6485 } 6486 /* 6487 * Otherwise, we only accept 1 IO per LUN. 6488 * Clear the bit that keeps track of this IO. 6489 */ 6490 else 6491 sym_clr_bit(tp->busy0_map, cp->lun); 6492 6493 /* 6494 * We donnot queue more than 1 ccb per target 6495 * with negotiation at any time. If this ccb was 6496 * used for negotiation, clear this info in the tcb. 6497 */ 6498 if (cp == tp->nego_cp) 6499 tp->nego_cp = 0; 6500 6501 #ifdef SYM_CONF_IARB_SUPPORT 6502 /* 6503 * If we just complete the last queued CCB, 6504 * clear this info that is no longer relevant. 6505 */ 6506 if (cp == np->last_cp) 6507 np->last_cp = 0; 6508 #endif 6509 6510 /* 6511 * Unmap user data from DMA map if needed. 6512 */ 6513 if (cp->dmamapped) { 6514 bus_dmamap_unload(np->data_dmat, cp->dmamap); 6515 cp->dmamapped = 0; 6516 } 6517 6518 /* 6519 * Make this CCB available. 6520 */ 6521 cp->cam_ccb = 0; 6522 cp->host_status = HS_IDLE; 6523 sym_remque(&cp->link_ccbq); 6524 sym_insque_head(&cp->link_ccbq, &np->free_ccbq); 6525 } 6526 6527 /* 6528 * Allocate a CCB from memory and initialize its fixed part. 6529 */ 6530 static ccb_p sym_alloc_ccb(hcb_p np) 6531 { 6532 ccb_p cp = 0; 6533 int hcode; 6534 6535 /* 6536 * Prevent from allocating more CCBs than we can 6537 * queue to the controller. 6538 */ 6539 if (np->actccbs >= SYM_CONF_MAX_START) 6540 return 0; 6541 6542 /* 6543 * Allocate memory for this CCB. 6544 */ 6545 cp = sym_calloc_dma(sizeof(struct sym_ccb), "CCB"); 6546 if (!cp) 6547 goto out_free; 6548 6549 /* 6550 * Allocate a bounce buffer for sense data. 6551 */ 6552 cp->sns_bbuf = sym_calloc_dma(SYM_SNS_BBUF_LEN, "SNS_BBUF"); 6553 if (!cp->sns_bbuf) 6554 goto out_free; 6555 6556 /* 6557 * Allocate a map for the DMA of user data. 6558 */ 6559 if (bus_dmamap_create(np->data_dmat, 0, &cp->dmamap)) 6560 goto out_free; 6561 /* 6562 * Count it. 6563 */ 6564 np->actccbs++; 6565 6566 /* 6567 * Compute the bus address of this ccb. 6568 */ 6569 cp->ccb_ba = vtobus(cp); 6570 6571 /* 6572 * Insert this ccb into the hashed list. 6573 */ 6574 hcode = CCB_HASH_CODE(cp->ccb_ba); 6575 cp->link_ccbh = np->ccbh[hcode]; 6576 np->ccbh[hcode] = cp; 6577 6578 /* 6579 * Initialyze the start and restart actions. 6580 */ 6581 cp->phys.head.go.start = cpu_to_scr(SCRIPTA_BA (np, idle)); 6582 cp->phys.head.go.restart = cpu_to_scr(SCRIPTB_BA (np, bad_i_t_l)); 6583 6584 /* 6585 * Initilialyze some other fields. 6586 */ 6587 cp->phys.smsg_ext.addr = cpu_to_scr(HCB_BA(np, msgin[2])); 6588 6589 /* 6590 * Chain into free ccb queue. 6591 */ 6592 sym_insque_head(&cp->link_ccbq, &np->free_ccbq); 6593 6594 return cp; 6595 out_free: 6596 if (cp) { 6597 if (cp->sns_bbuf) 6598 sym_mfree_dma(cp->sns_bbuf,SYM_SNS_BBUF_LEN,"SNS_BBUF"); 6599 sym_mfree_dma(cp, sizeof(*cp), "CCB"); 6600 } 6601 return 0; 6602 } 6603 6604 /* 6605 * Look up a CCB from a DSA value. 6606 */ 6607 static ccb_p sym_ccb_from_dsa(hcb_p np, u32 dsa) 6608 { 6609 int hcode; 6610 ccb_p cp; 6611 6612 hcode = CCB_HASH_CODE(dsa); 6613 cp = np->ccbh[hcode]; 6614 while (cp) { 6615 if (cp->ccb_ba == dsa) 6616 break; 6617 cp = cp->link_ccbh; 6618 } 6619 6620 return cp; 6621 } 6622 6623 /* 6624 * Target control block initialisation. 6625 * Nothing important to do at the moment. 6626 */ 6627 static void sym_init_tcb (hcb_p np, u_char tn) 6628 { 6629 /* 6630 * Check some alignments required by the chip. 6631 */ 6632 assert (((offsetof(struct sym_reg, nc_sxfer) ^ 6633 offsetof(struct sym_tcb, head.sval)) &3) == 0); 6634 assert (((offsetof(struct sym_reg, nc_scntl3) ^ 6635 offsetof(struct sym_tcb, head.wval)) &3) == 0); 6636 } 6637 6638 /* 6639 * Lun control block allocation and initialization. 6640 */ 6641 static lcb_p sym_alloc_lcb (hcb_p np, u_char tn, u_char ln) 6642 { 6643 tcb_p tp = &np->target[tn]; 6644 lcb_p lp = sym_lp(np, tp, ln); 6645 6646 /* 6647 * Already done, just return. 6648 */ 6649 if (lp) 6650 return lp; 6651 /* 6652 * Check against some race. 6653 */ 6654 assert(!sym_is_bit(tp->busy0_map, ln)); 6655 6656 /* 6657 * Initialize the target control block if not yet. 6658 */ 6659 sym_init_tcb (np, tn); 6660 6661 /* 6662 * Allocate the LCB bus address array. 6663 * Compute the bus address of this table. 6664 */ 6665 if (ln && !tp->luntbl) { 6666 int i; 6667 6668 tp->luntbl = sym_calloc_dma(256, "LUNTBL"); 6669 if (!tp->luntbl) 6670 goto fail; 6671 for (i = 0 ; i < 64 ; i++) 6672 tp->luntbl[i] = cpu_to_scr(vtobus(&np->badlun_sa)); 6673 tp->head.luntbl_sa = cpu_to_scr(vtobus(tp->luntbl)); 6674 } 6675 6676 /* 6677 * Allocate the table of pointers for LUN(s) > 0, if needed. 6678 */ 6679 if (ln && !tp->lunmp) { 6680 tp->lunmp = sym_calloc(SYM_CONF_MAX_LUN * sizeof(lcb_p), 6681 "LUNMP"); 6682 if (!tp->lunmp) 6683 goto fail; 6684 } 6685 6686 /* 6687 * Allocate the lcb. 6688 * Make it available to the chip. 6689 */ 6690 lp = sym_calloc_dma(sizeof(struct sym_lcb), "LCB"); 6691 if (!lp) 6692 goto fail; 6693 if (ln) { 6694 tp->lunmp[ln] = lp; 6695 tp->luntbl[ln] = cpu_to_scr(vtobus(lp)); 6696 } 6697 else { 6698 tp->lun0p = lp; 6699 tp->head.lun0_sa = cpu_to_scr(vtobus(lp)); 6700 } 6701 6702 /* 6703 * Let the itl task point to error handling. 6704 */ 6705 lp->head.itl_task_sa = cpu_to_scr(np->bad_itl_ba); 6706 6707 /* 6708 * Set the reselect pattern to our default. :) 6709 */ 6710 lp->head.resel_sa = cpu_to_scr(SCRIPTB_BA (np, resel_bad_lun)); 6711 6712 /* 6713 * Set user capabilities. 6714 */ 6715 lp->user_flags = tp->usrflags & (SYM_DISC_ENABLED | SYM_TAGS_ENABLED); 6716 6717 fail: 6718 return lp; 6719 } 6720 6721 /* 6722 * Allocate LCB resources for tagged command queuing. 6723 */ 6724 static void sym_alloc_lcb_tags (hcb_p np, u_char tn, u_char ln) 6725 { 6726 tcb_p tp = &np->target[tn]; 6727 lcb_p lp = sym_lp(np, tp, ln); 6728 int i; 6729 6730 /* 6731 * If LCB not available, try to allocate it. 6732 */ 6733 if (!lp && !(lp = sym_alloc_lcb(np, tn, ln))) 6734 goto fail; 6735 6736 /* 6737 * Allocate the task table and and the tag allocation 6738 * circular buffer. We want both or none. 6739 */ 6740 lp->itlq_tbl = sym_calloc_dma(SYM_CONF_MAX_TASK*4, "ITLQ_TBL"); 6741 if (!lp->itlq_tbl) 6742 goto fail; 6743 lp->cb_tags = sym_calloc(SYM_CONF_MAX_TASK, "CB_TAGS"); 6744 if (!lp->cb_tags) { 6745 sym_mfree_dma(lp->itlq_tbl, SYM_CONF_MAX_TASK*4, "ITLQ_TBL"); 6746 lp->itlq_tbl = 0; 6747 goto fail; 6748 } 6749 6750 /* 6751 * Initialize the task table with invalid entries. 6752 */ 6753 for (i = 0 ; i < SYM_CONF_MAX_TASK ; i++) 6754 lp->itlq_tbl[i] = cpu_to_scr(np->notask_ba); 6755 6756 /* 6757 * Fill up the tag buffer with tag numbers. 6758 */ 6759 for (i = 0 ; i < SYM_CONF_MAX_TASK ; i++) 6760 lp->cb_tags[i] = i; 6761 6762 /* 6763 * Make the task table available to SCRIPTS, 6764 * And accept tagged commands now. 6765 */ 6766 lp->head.itlq_tbl_sa = cpu_to_scr(vtobus(lp->itlq_tbl)); 6767 6768 return; 6769 fail: 6770 return; 6771 } 6772 6773 /* 6774 * Test the pci bus snoop logic :-( 6775 * 6776 * Has to be called with interrupts disabled. 6777 */ 6778 #ifndef SYM_CONF_IOMAPPED 6779 static int sym_regtest (hcb_p np) 6780 { 6781 register volatile u32 data; 6782 /* 6783 * chip registers may NOT be cached. 6784 * write 0xffffffff to a read only register area, 6785 * and try to read it back. 6786 */ 6787 data = 0xffffffff; 6788 OUTL_OFF(offsetof(struct sym_reg, nc_dstat), data); 6789 data = INL_OFF(offsetof(struct sym_reg, nc_dstat)); 6790 #if 1 6791 if (data == 0xffffffff) { 6792 #else 6793 if ((data & 0xe2f0fffd) != 0x02000080) { 6794 #endif 6795 printf ("CACHE TEST FAILED: reg dstat-sstat2 readback %x.\n", 6796 (unsigned) data); 6797 return (0x10); 6798 }; 6799 return (0); 6800 } 6801 #endif 6802 6803 static int sym_snooptest (hcb_p np) 6804 { 6805 u32 sym_rd, sym_wr, sym_bk, host_rd, host_wr, pc, dstat; 6806 int i, err=0; 6807 #ifndef SYM_CONF_IOMAPPED 6808 err |= sym_regtest (np); 6809 if (err) return (err); 6810 #endif 6811 restart_test: 6812 /* 6813 * Enable Master Parity Checking as we intend 6814 * to enable it for normal operations. 6815 */ 6816 OUTB (nc_ctest4, (np->rv_ctest4 & MPEE)); 6817 /* 6818 * init 6819 */ 6820 pc = SCRIPTB0_BA (np, snooptest); 6821 host_wr = 1; 6822 sym_wr = 2; 6823 /* 6824 * Set memory and register. 6825 */ 6826 np->cache = cpu_to_scr(host_wr); 6827 OUTL (nc_temp, sym_wr); 6828 /* 6829 * Start script (exchange values) 6830 */ 6831 OUTL (nc_dsa, np->hcb_ba); 6832 OUTL_DSP (pc); 6833 /* 6834 * Wait 'til done (with timeout) 6835 */ 6836 for (i=0; i<SYM_SNOOP_TIMEOUT; i++) 6837 if (INB(nc_istat) & (INTF|SIP|DIP)) 6838 break; 6839 if (i>=SYM_SNOOP_TIMEOUT) { 6840 printf ("CACHE TEST FAILED: timeout.\n"); 6841 return (0x20); 6842 }; 6843 /* 6844 * Check for fatal DMA errors. 6845 */ 6846 dstat = INB (nc_dstat); 6847 #if 1 /* Band aiding for broken hardwares that fail PCI parity */ 6848 if ((dstat & MDPE) && (np->rv_ctest4 & MPEE)) { 6849 printf ("%s: PCI DATA PARITY ERROR DETECTED - " 6850 "DISABLING MASTER DATA PARITY CHECKING.\n", 6851 sym_name(np)); 6852 np->rv_ctest4 &= ~MPEE; 6853 goto restart_test; 6854 } 6855 #endif 6856 if (dstat & (MDPE|BF|IID)) { 6857 printf ("CACHE TEST FAILED: DMA error (dstat=0x%02x).", dstat); 6858 return (0x80); 6859 } 6860 /* 6861 * Save termination position. 6862 */ 6863 pc = INL (nc_dsp); 6864 /* 6865 * Read memory and register. 6866 */ 6867 host_rd = scr_to_cpu(np->cache); 6868 sym_rd = INL (nc_scratcha); 6869 sym_bk = INL (nc_temp); 6870 6871 /* 6872 * Check termination position. 6873 */ 6874 if (pc != SCRIPTB0_BA (np, snoopend)+8) { 6875 printf ("CACHE TEST FAILED: script execution failed.\n"); 6876 printf ("start=%08lx, pc=%08lx, end=%08lx\n", 6877 (u_long) SCRIPTB0_BA (np, snooptest), (u_long) pc, 6878 (u_long) SCRIPTB0_BA (np, snoopend) +8); 6879 return (0x40); 6880 }; 6881 /* 6882 * Show results. 6883 */ 6884 if (host_wr != sym_rd) { 6885 printf ("CACHE TEST FAILED: host wrote %d, chip read %d.\n", 6886 (int) host_wr, (int) sym_rd); 6887 err |= 1; 6888 }; 6889 if (host_rd != sym_wr) { 6890 printf ("CACHE TEST FAILED: chip wrote %d, host read %d.\n", 6891 (int) sym_wr, (int) host_rd); 6892 err |= 2; 6893 }; 6894 if (sym_bk != sym_wr) { 6895 printf ("CACHE TEST FAILED: chip wrote %d, read back %d.\n", 6896 (int) sym_wr, (int) sym_bk); 6897 err |= 4; 6898 }; 6899 6900 return (err); 6901 } 6902 6903 /* 6904 * Determine the chip's clock frequency. 6905 * 6906 * This is essential for the negotiation of the synchronous 6907 * transfer rate. 6908 * 6909 * Note: we have to return the correct value. 6910 * THERE IS NO SAFE DEFAULT VALUE. 6911 * 6912 * Most NCR/SYMBIOS boards are delivered with a 40 Mhz clock. 6913 * 53C860 and 53C875 rev. 1 support fast20 transfers but 6914 * do not have a clock doubler and so are provided with a 6915 * 80 MHz clock. All other fast20 boards incorporate a doubler 6916 * and so should be delivered with a 40 MHz clock. 6917 * The recent fast40 chips (895/896/895A/1010) use a 40 Mhz base 6918 * clock and provide a clock quadrupler (160 Mhz). 6919 */ 6920 6921 /* 6922 * Select SCSI clock frequency 6923 */ 6924 static void sym_selectclock(hcb_p np, u_char scntl3) 6925 { 6926 /* 6927 * If multiplier not present or not selected, leave here. 6928 */ 6929 if (np->multiplier <= 1) { 6930 OUTB(nc_scntl3, scntl3); 6931 return; 6932 } 6933 6934 if (sym_verbose >= 2) 6935 printf ("%s: enabling clock multiplier\n", sym_name(np)); 6936 6937 OUTB(nc_stest1, DBLEN); /* Enable clock multiplier */ 6938 /* 6939 * Wait for the LCKFRQ bit to be set if supported by the chip. 6940 * Otherwise wait 20 micro-seconds. 6941 */ 6942 if (np->features & FE_LCKFRQ) { 6943 int i = 20; 6944 while (!(INB(nc_stest4) & LCKFRQ) && --i > 0) 6945 UDELAY (20); 6946 if (!i) 6947 printf("%s: the chip cannot lock the frequency\n", 6948 sym_name(np)); 6949 } else 6950 UDELAY (20); 6951 OUTB(nc_stest3, HSC); /* Halt the scsi clock */ 6952 OUTB(nc_scntl3, scntl3); 6953 OUTB(nc_stest1, (DBLEN|DBLSEL));/* Select clock multiplier */ 6954 OUTB(nc_stest3, 0x00); /* Restart scsi clock */ 6955 } 6956 6957 /* 6958 * calculate SCSI clock frequency (in KHz) 6959 */ 6960 static unsigned getfreq (hcb_p np, int gen) 6961 { 6962 unsigned int ms = 0; 6963 unsigned int f; 6964 6965 /* 6966 * Measure GEN timer delay in order 6967 * to calculate SCSI clock frequency 6968 * 6969 * This code will never execute too 6970 * many loop iterations (if DELAY is 6971 * reasonably correct). It could get 6972 * too low a delay (too high a freq.) 6973 * if the CPU is slow executing the 6974 * loop for some reason (an NMI, for 6975 * example). For this reason we will 6976 * if multiple measurements are to be 6977 * performed trust the higher delay 6978 * (lower frequency returned). 6979 */ 6980 OUTW (nc_sien , 0); /* mask all scsi interrupts */ 6981 (void) INW (nc_sist); /* clear pending scsi interrupt */ 6982 OUTB (nc_dien , 0); /* mask all dma interrupts */ 6983 (void) INW (nc_sist); /* another one, just to be sure :) */ 6984 OUTB (nc_scntl3, 4); /* set pre-scaler to divide by 3 */ 6985 OUTB (nc_stime1, 0); /* disable general purpose timer */ 6986 OUTB (nc_stime1, gen); /* set to nominal delay of 1<<gen * 125us */ 6987 while (!(INW(nc_sist) & GEN) && ms++ < 100000) 6988 UDELAY (1000); /* count ms */ 6989 OUTB (nc_stime1, 0); /* disable general purpose timer */ 6990 /* 6991 * set prescaler to divide by whatever 0 means 6992 * 0 ought to choose divide by 2, but appears 6993 * to set divide by 3.5 mode in my 53c810 ... 6994 */ 6995 OUTB (nc_scntl3, 0); 6996 6997 /* 6998 * adjust for prescaler, and convert into KHz 6999 */ 7000 f = ms ? ((1 << gen) * 4340) / ms : 0; 7001 7002 if (sym_verbose >= 2) 7003 printf ("%s: Delay (GEN=%d): %u msec, %u KHz\n", 7004 sym_name(np), gen, ms, f); 7005 7006 return f; 7007 } 7008 7009 static unsigned sym_getfreq (hcb_p np) 7010 { 7011 u_int f1, f2; 7012 int gen = 11; 7013 7014 (void) getfreq (np, gen); /* throw away first result */ 7015 f1 = getfreq (np, gen); 7016 f2 = getfreq (np, gen); 7017 if (f1 > f2) f1 = f2; /* trust lower result */ 7018 return f1; 7019 } 7020 7021 /* 7022 * Get/probe chip SCSI clock frequency 7023 */ 7024 static void sym_getclock (hcb_p np, int mult) 7025 { 7026 unsigned char scntl3 = np->sv_scntl3; 7027 unsigned char stest1 = np->sv_stest1; 7028 unsigned f1; 7029 7030 /* 7031 * For the C10 core, assume 40 MHz. 7032 */ 7033 if (np->features & FE_C10) { 7034 np->multiplier = mult; 7035 np->clock_khz = 40000 * mult; 7036 return; 7037 } 7038 7039 np->multiplier = 1; 7040 f1 = 40000; 7041 /* 7042 * True with 875/895/896/895A with clock multiplier selected 7043 */ 7044 if (mult > 1 && (stest1 & (DBLEN+DBLSEL)) == DBLEN+DBLSEL) { 7045 if (sym_verbose >= 2) 7046 printf ("%s: clock multiplier found\n", sym_name(np)); 7047 np->multiplier = mult; 7048 } 7049 7050 /* 7051 * If multiplier not found or scntl3 not 7,5,3, 7052 * reset chip and get frequency from general purpose timer. 7053 * Otherwise trust scntl3 BIOS setting. 7054 */ 7055 if (np->multiplier != mult || (scntl3 & 7) < 3 || !(scntl3 & 1)) { 7056 OUTB (nc_stest1, 0); /* make sure doubler is OFF */ 7057 f1 = sym_getfreq (np); 7058 7059 if (sym_verbose) 7060 printf ("%s: chip clock is %uKHz\n", sym_name(np), f1); 7061 7062 if (f1 < 45000) f1 = 40000; 7063 else if (f1 < 55000) f1 = 50000; 7064 else f1 = 80000; 7065 7066 if (f1 < 80000 && mult > 1) { 7067 if (sym_verbose >= 2) 7068 printf ("%s: clock multiplier assumed\n", 7069 sym_name(np)); 7070 np->multiplier = mult; 7071 } 7072 } else { 7073 if ((scntl3 & 7) == 3) f1 = 40000; 7074 else if ((scntl3 & 7) == 5) f1 = 80000; 7075 else f1 = 160000; 7076 7077 f1 /= np->multiplier; 7078 } 7079 7080 /* 7081 * Compute controller synchronous parameters. 7082 */ 7083 f1 *= np->multiplier; 7084 np->clock_khz = f1; 7085 } 7086 7087 /* 7088 * Get/probe PCI clock frequency 7089 */ 7090 static int sym_getpciclock (hcb_p np) 7091 { 7092 int f = 0; 7093 7094 /* 7095 * For the C1010-33, this doesn't work. 7096 * For the C1010-66, this will be tested when I'll have 7097 * such a beast to play with. 7098 */ 7099 if (!(np->features & FE_C10)) { 7100 OUTB (nc_stest1, SCLK); /* Use the PCI clock as SCSI clock */ 7101 f = (int) sym_getfreq (np); 7102 OUTB (nc_stest1, 0); 7103 } 7104 np->pciclk_khz = f; 7105 7106 return f; 7107 } 7108 7109 /*============= DRIVER ACTION/COMPLETION ====================*/ 7110 7111 /* 7112 * Print something that tells about extended errors. 7113 */ 7114 static void sym_print_xerr(ccb_p cp, int x_status) 7115 { 7116 if (x_status & XE_PARITY_ERR) { 7117 PRINT_ADDR(cp); 7118 printf ("unrecovered SCSI parity error.\n"); 7119 } 7120 if (x_status & XE_EXTRA_DATA) { 7121 PRINT_ADDR(cp); 7122 printf ("extraneous data discarded.\n"); 7123 } 7124 if (x_status & XE_BAD_PHASE) { 7125 PRINT_ADDR(cp); 7126 printf ("illegal scsi phase (4/5).\n"); 7127 } 7128 if (x_status & XE_SODL_UNRUN) { 7129 PRINT_ADDR(cp); 7130 printf ("ODD transfer in DATA OUT phase.\n"); 7131 } 7132 if (x_status & XE_SWIDE_OVRUN) { 7133 PRINT_ADDR(cp); 7134 printf ("ODD transfer in DATA IN phase.\n"); 7135 } 7136 } 7137 7138 /* 7139 * Choose the more appropriate CAM status if 7140 * the IO encountered an extended error. 7141 */ 7142 static int sym_xerr_cam_status(int cam_status, int x_status) 7143 { 7144 if (x_status) { 7145 if (x_status & XE_PARITY_ERR) 7146 cam_status = CAM_UNCOR_PARITY; 7147 else if (x_status &(XE_EXTRA_DATA|XE_SODL_UNRUN|XE_SWIDE_OVRUN)) 7148 cam_status = CAM_DATA_RUN_ERR; 7149 else if (x_status & XE_BAD_PHASE) 7150 cam_status = CAM_REQ_CMP_ERR; 7151 else 7152 cam_status = CAM_REQ_CMP_ERR; 7153 } 7154 return cam_status; 7155 } 7156 7157 /* 7158 * Complete execution of a SCSI command with extented 7159 * error, SCSI status error, or having been auto-sensed. 7160 * 7161 * The SCRIPTS processor is not running there, so we 7162 * can safely access IO registers and remove JOBs from 7163 * the START queue. 7164 * SCRATCHA is assumed to have been loaded with STARTPOS 7165 * before the SCRIPTS called the C code. 7166 */ 7167 static void sym_complete_error (hcb_p np, ccb_p cp) 7168 { 7169 struct ccb_scsiio *csio; 7170 u_int cam_status; 7171 int i; 7172 7173 /* 7174 * Paranoid check. :) 7175 */ 7176 if (!cp || !cp->cam_ccb) 7177 return; 7178 7179 if (DEBUG_FLAGS & (DEBUG_TINY|DEBUG_RESULT)) { 7180 printf ("CCB=%lx STAT=%x/%x/%x DEV=%d/%d\n", (unsigned long)cp, 7181 cp->host_status, cp->ssss_status, cp->host_flags, 7182 cp->target, cp->lun); 7183 MDELAY(100); 7184 } 7185 7186 /* 7187 * Get CAM command pointer. 7188 */ 7189 csio = &cp->cam_ccb->csio; 7190 7191 /* 7192 * Check for extended errors. 7193 */ 7194 if (cp->xerr_status) { 7195 if (sym_verbose) 7196 sym_print_xerr(cp, cp->xerr_status); 7197 if (cp->host_status == HS_COMPLETE) 7198 cp->host_status = HS_COMP_ERR; 7199 } 7200 7201 /* 7202 * Calculate the residual. 7203 */ 7204 csio->sense_resid = 0; 7205 csio->resid = sym_compute_residual(np, cp); 7206 7207 if (!SYM_CONF_RESIDUAL_SUPPORT) {/* If user does not want residuals */ 7208 csio->resid = 0; /* throw them away. :) */ 7209 cp->sv_resid = 0; 7210 } 7211 7212 if (cp->host_flags & HF_SENSE) { /* Auto sense */ 7213 csio->scsi_status = cp->sv_scsi_status; /* Restore status */ 7214 csio->sense_resid = csio->resid; /* Swap residuals */ 7215 csio->resid = cp->sv_resid; 7216 cp->sv_resid = 0; 7217 if (sym_verbose && cp->sv_xerr_status) 7218 sym_print_xerr(cp, cp->sv_xerr_status); 7219 if (cp->host_status == HS_COMPLETE && 7220 cp->ssss_status == S_GOOD && 7221 cp->xerr_status == 0) { 7222 cam_status = sym_xerr_cam_status(CAM_SCSI_STATUS_ERROR, 7223 cp->sv_xerr_status); 7224 cam_status |= CAM_AUTOSNS_VALID; 7225 /* 7226 * Bounce back the sense data to user and 7227 * fix the residual. 7228 */ 7229 bzero(&csio->sense_data, csio->sense_len); 7230 bcopy(cp->sns_bbuf, &csio->sense_data, 7231 MIN(csio->sense_len, SYM_SNS_BBUF_LEN)); 7232 csio->sense_resid += csio->sense_len; 7233 csio->sense_resid -= SYM_SNS_BBUF_LEN; 7234 #if 0 7235 /* 7236 * If the device reports a UNIT ATTENTION condition 7237 * due to a RESET condition, we should consider all 7238 * disconnect CCBs for this unit as aborted. 7239 */ 7240 if (1) { 7241 u_char *p; 7242 p = (u_char *) csio->sense_data; 7243 if (p[0]==0x70 && p[2]==0x6 && p[12]==0x29) 7244 sym_clear_tasks(np, CAM_REQ_ABORTED, 7245 cp->target,cp->lun, -1); 7246 } 7247 #endif 7248 } 7249 else 7250 cam_status = CAM_AUTOSENSE_FAIL; 7251 } 7252 else if (cp->host_status == HS_COMPLETE) { /* Bad SCSI status */ 7253 csio->scsi_status = cp->ssss_status; 7254 cam_status = CAM_SCSI_STATUS_ERROR; 7255 } 7256 else if (cp->host_status == HS_SEL_TIMEOUT) /* Selection timeout */ 7257 cam_status = CAM_SEL_TIMEOUT; 7258 else if (cp->host_status == HS_UNEXPECTED) /* Unexpected BUS FREE*/ 7259 cam_status = CAM_UNEXP_BUSFREE; 7260 else { /* Extended error */ 7261 if (sym_verbose) { 7262 PRINT_ADDR(cp); 7263 printf ("COMMAND FAILED (%x %x %x).\n", 7264 cp->host_status, cp->ssss_status, 7265 cp->xerr_status); 7266 } 7267 csio->scsi_status = cp->ssss_status; 7268 /* 7269 * Set the most appropriate value for CAM status. 7270 */ 7271 cam_status = sym_xerr_cam_status(CAM_REQ_CMP_ERR, 7272 cp->xerr_status); 7273 } 7274 7275 /* 7276 * Dequeue all queued CCBs for that device 7277 * not yet started by SCRIPTS. 7278 */ 7279 i = (INL (nc_scratcha) - np->squeue_ba) / 4; 7280 (void) sym_dequeue_from_squeue(np, i, cp->target, cp->lun, -1); 7281 7282 /* 7283 * Restart the SCRIPTS processor. 7284 */ 7285 OUTL_DSP (SCRIPTA_BA (np, start)); 7286 7287 /* 7288 * Synchronize DMA map if needed. 7289 */ 7290 if (cp->dmamapped) { 7291 bus_dmamap_sync(np->data_dmat, cp->dmamap, 7292 (cp->dmamapped == SYM_DMA_READ ? 7293 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 7294 } 7295 /* 7296 * Add this one to the COMP queue. 7297 * Complete all those commands with either error 7298 * or requeue condition. 7299 */ 7300 sym_set_cam_status((union ccb *) csio, cam_status); 7301 sym_remque(&cp->link_ccbq); 7302 sym_insque_head(&cp->link_ccbq, &np->comp_ccbq); 7303 sym_flush_comp_queue(np, 0); 7304 } 7305 7306 /* 7307 * Complete execution of a successful SCSI command. 7308 * 7309 * Only successful commands go to the DONE queue, 7310 * since we need to have the SCRIPTS processor 7311 * stopped on any error condition. 7312 * The SCRIPTS processor is running while we are 7313 * completing successful commands. 7314 */ 7315 static void sym_complete_ok (hcb_p np, ccb_p cp) 7316 { 7317 struct ccb_scsiio *csio; 7318 tcb_p tp; 7319 lcb_p lp; 7320 7321 /* 7322 * Paranoid check. :) 7323 */ 7324 if (!cp || !cp->cam_ccb) 7325 return; 7326 assert (cp->host_status == HS_COMPLETE); 7327 7328 /* 7329 * Get command, target and lun pointers. 7330 */ 7331 csio = &cp->cam_ccb->csio; 7332 tp = &np->target[cp->target]; 7333 lp = sym_lp(np, tp, cp->lun); 7334 7335 /* 7336 * Assume device discovered on first success. 7337 */ 7338 if (!lp) 7339 sym_set_bit(tp->lun_map, cp->lun); 7340 7341 /* 7342 * If all data have been transferred, given than no 7343 * extended error did occur, there is no residual. 7344 */ 7345 csio->resid = 0; 7346 if (cp->phys.head.lastp != cp->phys.head.goalp) 7347 csio->resid = sym_compute_residual(np, cp); 7348 7349 /* 7350 * Wrong transfer residuals may be worse than just always 7351 * returning zero. User can disable this feature from 7352 * sym_conf.h. Residual support is enabled by default. 7353 */ 7354 if (!SYM_CONF_RESIDUAL_SUPPORT) 7355 csio->resid = 0; 7356 7357 /* 7358 * Synchronize DMA map if needed. 7359 */ 7360 if (cp->dmamapped) { 7361 bus_dmamap_sync(np->data_dmat, cp->dmamap, 7362 (cp->dmamapped == SYM_DMA_READ ? 7363 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 7364 } 7365 /* 7366 * Set status and complete the command. 7367 */ 7368 csio->scsi_status = cp->ssss_status; 7369 sym_set_cam_status((union ccb *) csio, CAM_REQ_CMP); 7370 sym_free_ccb (np, cp); 7371 sym_xpt_done(np, (union ccb *) csio); 7372 } 7373 7374 /* 7375 * Our timeout handler. 7376 */ 7377 static void sym_timeout1(void *arg) 7378 { 7379 union ccb *ccb = (union ccb *) arg; 7380 hcb_p np = ccb->ccb_h.sym_hcb_ptr; 7381 7382 /* 7383 * Check that the CAM CCB is still queued. 7384 */ 7385 if (!np) 7386 return; 7387 7388 switch(ccb->ccb_h.func_code) { 7389 case XPT_SCSI_IO: 7390 (void) sym_abort_scsiio(np, ccb, 1); 7391 break; 7392 default: 7393 break; 7394 } 7395 } 7396 7397 static void sym_timeout(void *arg) 7398 { 7399 int s = splcam(); 7400 sym_timeout1(arg); 7401 splx(s); 7402 } 7403 7404 /* 7405 * Abort an SCSI IO. 7406 */ 7407 static int sym_abort_scsiio(hcb_p np, union ccb *ccb, int timed_out) 7408 { 7409 ccb_p cp; 7410 SYM_QUEHEAD *qp; 7411 7412 /* 7413 * Look up our CCB control block. 7414 */ 7415 cp = 0; 7416 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) { 7417 ccb_p cp2 = sym_que_entry(qp, struct sym_ccb, link_ccbq); 7418 if (cp2->cam_ccb == ccb) { 7419 cp = cp2; 7420 break; 7421 } 7422 } 7423 if (!cp || cp->host_status == HS_WAIT) 7424 return -1; 7425 7426 /* 7427 * If a previous abort didn't succeed in time, 7428 * perform a BUS reset. 7429 */ 7430 if (cp->to_abort) { 7431 sym_reset_scsi_bus(np, 1); 7432 return 0; 7433 } 7434 7435 /* 7436 * Mark the CCB for abort and allow time for. 7437 */ 7438 cp->to_abort = timed_out ? 2 : 1; 7439 ccb->ccb_h.timeout_ch = timeout(sym_timeout, (caddr_t) ccb, 10*hz); 7440 7441 /* 7442 * Tell the SCRIPTS processor to stop and synchronize with us. 7443 */ 7444 np->istat_sem = SEM; 7445 OUTB (nc_istat, SIGP|SEM); 7446 return 0; 7447 } 7448 7449 /* 7450 * Reset a SCSI device (all LUNs of a target). 7451 */ 7452 static void sym_reset_dev(hcb_p np, union ccb *ccb) 7453 { 7454 tcb_p tp; 7455 struct ccb_hdr *ccb_h = &ccb->ccb_h; 7456 7457 if (ccb_h->target_id == np->myaddr || 7458 ccb_h->target_id >= SYM_CONF_MAX_TARGET || 7459 ccb_h->target_lun >= SYM_CONF_MAX_LUN) { 7460 sym_xpt_done2(np, ccb, CAM_DEV_NOT_THERE); 7461 return; 7462 } 7463 7464 tp = &np->target[ccb_h->target_id]; 7465 7466 tp->to_reset = 1; 7467 sym_xpt_done2(np, ccb, CAM_REQ_CMP); 7468 7469 np->istat_sem = SEM; 7470 OUTB (nc_istat, SIGP|SEM); 7471 return; 7472 } 7473 7474 /* 7475 * SIM action entry point. 7476 */ 7477 static void sym_action(struct cam_sim *sim, union ccb *ccb) 7478 { 7479 int s = splcam(); 7480 sym_action1(sim, ccb); 7481 splx(s); 7482 } 7483 7484 static void sym_action1(struct cam_sim *sim, union ccb *ccb) 7485 { 7486 hcb_p np; 7487 tcb_p tp; 7488 lcb_p lp; 7489 ccb_p cp; 7490 int tmp; 7491 u_char idmsg, *msgptr; 7492 u_int msglen; 7493 struct ccb_scsiio *csio; 7494 struct ccb_hdr *ccb_h; 7495 7496 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("sym_action\n")); 7497 7498 /* 7499 * Retrieve our controller data structure. 7500 */ 7501 np = (hcb_p) cam_sim_softc(sim); 7502 7503 /* 7504 * The common case is SCSI IO. 7505 * We deal with other ones elsewhere. 7506 */ 7507 if (ccb->ccb_h.func_code != XPT_SCSI_IO) { 7508 sym_action2(sim, ccb); 7509 return; 7510 } 7511 csio = &ccb->csio; 7512 ccb_h = &csio->ccb_h; 7513 7514 /* 7515 * Work around races. 7516 */ 7517 if ((ccb_h->status & CAM_STATUS_MASK) != CAM_REQ_INPROG) { 7518 xpt_done(ccb); 7519 return; 7520 } 7521 7522 /* 7523 * Minimal checkings, so that we will not 7524 * go outside our tables. 7525 */ 7526 if (ccb_h->target_id == np->myaddr || 7527 ccb_h->target_id >= SYM_CONF_MAX_TARGET || 7528 ccb_h->target_lun >= SYM_CONF_MAX_LUN) { 7529 sym_xpt_done2(np, ccb, CAM_DEV_NOT_THERE); 7530 return; 7531 } 7532 7533 /* 7534 * Retreive the target and lun descriptors. 7535 */ 7536 tp = &np->target[ccb_h->target_id]; 7537 lp = sym_lp(np, tp, ccb_h->target_lun); 7538 7539 /* 7540 * Complete the 1st INQUIRY command with error 7541 * condition if the device is flagged NOSCAN 7542 * at BOOT in the NVRAM. This may speed up 7543 * the boot and maintain coherency with BIOS 7544 * device numbering. Clearing the flag allows 7545 * user to rescan skipped devices later. 7546 * We also return error for devices not flagged 7547 * for SCAN LUNS in the NVRAM since some mono-lun 7548 * devices behave badly when asked for some non 7549 * zero LUN. Btw, this is an absolute hack.:-) 7550 */ 7551 if (!(ccb_h->flags & CAM_CDB_PHYS) && 7552 (0x12 == ((ccb_h->flags & CAM_CDB_POINTER) ? 7553 csio->cdb_io.cdb_ptr[0] : csio->cdb_io.cdb_bytes[0]))) { 7554 if ((tp->usrflags & SYM_SCAN_BOOT_DISABLED) || 7555 ((tp->usrflags & SYM_SCAN_LUNS_DISABLED) && 7556 ccb_h->target_lun != 0)) { 7557 tp->usrflags &= ~SYM_SCAN_BOOT_DISABLED; 7558 sym_xpt_done2(np, ccb, CAM_DEV_NOT_THERE); 7559 return; 7560 } 7561 } 7562 7563 /* 7564 * Get a control block for this IO. 7565 */ 7566 tmp = ((ccb_h->flags & CAM_TAG_ACTION_VALID) != 0); 7567 cp = sym_get_ccb(np, ccb_h->target_id, ccb_h->target_lun, tmp); 7568 if (!cp) { 7569 sym_xpt_done2(np, ccb, CAM_RESRC_UNAVAIL); 7570 return; 7571 } 7572 7573 /* 7574 * Keep track of the IO in our CCB. 7575 */ 7576 cp->cam_ccb = ccb; 7577 7578 /* 7579 * Build the IDENTIFY message. 7580 */ 7581 idmsg = M_IDENTIFY | cp->lun; 7582 if (cp->tag != NO_TAG || (lp && (lp->current_flags & SYM_DISC_ENABLED))) 7583 idmsg |= 0x40; 7584 7585 msgptr = cp->scsi_smsg; 7586 msglen = 0; 7587 msgptr[msglen++] = idmsg; 7588 7589 /* 7590 * Build the tag message if present. 7591 */ 7592 if (cp->tag != NO_TAG) { 7593 u_char order = csio->tag_action; 7594 7595 switch(order) { 7596 case M_ORDERED_TAG: 7597 break; 7598 case M_HEAD_TAG: 7599 break; 7600 default: 7601 order = M_SIMPLE_TAG; 7602 } 7603 msgptr[msglen++] = order; 7604 7605 /* 7606 * For less than 128 tags, actual tags are numbered 7607 * 1,3,5,..2*MAXTAGS+1,since we may have to deal 7608 * with devices that have problems with #TAG 0 or too 7609 * great #TAG numbers. For more tags (up to 256), 7610 * we use directly our tag number. 7611 */ 7612 #if SYM_CONF_MAX_TASK > (512/4) 7613 msgptr[msglen++] = cp->tag; 7614 #else 7615 msgptr[msglen++] = (cp->tag << 1) + 1; 7616 #endif 7617 } 7618 7619 /* 7620 * Build a negotiation message if needed. 7621 * (nego_status is filled by sym_prepare_nego()) 7622 */ 7623 cp->nego_status = 0; 7624 if (tp->tinfo.current.width != tp->tinfo.goal.width || 7625 tp->tinfo.current.period != tp->tinfo.goal.period || 7626 tp->tinfo.current.offset != tp->tinfo.goal.offset || 7627 tp->tinfo.current.options != tp->tinfo.goal.options) { 7628 if (!tp->nego_cp && lp) 7629 msglen += sym_prepare_nego(np, cp, 0, msgptr + msglen); 7630 } 7631 7632 /* 7633 * Fill in our ccb 7634 */ 7635 7636 /* 7637 * Startqueue 7638 */ 7639 cp->phys.head.go.start = cpu_to_scr(SCRIPTA_BA (np, select)); 7640 cp->phys.head.go.restart = cpu_to_scr(SCRIPTA_BA (np, resel_dsa)); 7641 7642 /* 7643 * select 7644 */ 7645 cp->phys.select.sel_id = cp->target; 7646 cp->phys.select.sel_scntl3 = tp->head.wval; 7647 cp->phys.select.sel_sxfer = tp->head.sval; 7648 cp->phys.select.sel_scntl4 = tp->head.uval; 7649 7650 /* 7651 * message 7652 */ 7653 cp->phys.smsg.addr = cpu_to_scr(CCB_BA (cp, scsi_smsg)); 7654 cp->phys.smsg.size = cpu_to_scr(msglen); 7655 7656 /* 7657 * command 7658 */ 7659 if (sym_setup_cdb(np, csio, cp) < 0) { 7660 sym_free_ccb(np, cp); 7661 sym_xpt_done(np, ccb); 7662 return; 7663 } 7664 7665 /* 7666 * status 7667 */ 7668 #if 0 /* Provision */ 7669 cp->actualquirks = tp->quirks; 7670 #endif 7671 cp->actualquirks = SYM_QUIRK_AUTOSAVE; 7672 cp->host_status = cp->nego_status ? HS_NEGOTIATE : HS_BUSY; 7673 cp->ssss_status = S_ILLEGAL; 7674 cp->xerr_status = 0; 7675 cp->host_flags = 0; 7676 cp->extra_bytes = 0; 7677 7678 /* 7679 * extreme data pointer. 7680 * shall be positive, so -1 is lower than lowest.:) 7681 */ 7682 cp->ext_sg = -1; 7683 cp->ext_ofs = 0; 7684 7685 /* 7686 * Build the data descriptor block 7687 * and start the IO. 7688 */ 7689 sym_setup_data_and_start(np, csio, cp); 7690 } 7691 7692 /* 7693 * Setup buffers and pointers that address the CDB. 7694 * I bet, physical CDBs will never be used on the planet, 7695 * since they can be bounced without significant overhead. 7696 */ 7697 static int sym_setup_cdb(hcb_p np, struct ccb_scsiio *csio, ccb_p cp) 7698 { 7699 struct ccb_hdr *ccb_h; 7700 u32 cmd_ba; 7701 int cmd_len; 7702 7703 ccb_h = &csio->ccb_h; 7704 7705 /* 7706 * CDB is 16 bytes max. 7707 */ 7708 if (csio->cdb_len > sizeof(cp->cdb_buf)) { 7709 sym_set_cam_status(cp->cam_ccb, CAM_REQ_INVALID); 7710 return -1; 7711 } 7712 cmd_len = csio->cdb_len; 7713 7714 if (ccb_h->flags & CAM_CDB_POINTER) { 7715 /* CDB is a pointer */ 7716 if (!(ccb_h->flags & CAM_CDB_PHYS)) { 7717 /* CDB pointer is virtual */ 7718 bcopy(csio->cdb_io.cdb_ptr, cp->cdb_buf, cmd_len); 7719 cmd_ba = CCB_BA (cp, cdb_buf[0]); 7720 } else { 7721 /* CDB pointer is physical */ 7722 #if 0 7723 cmd_ba = ((u32)csio->cdb_io.cdb_ptr) & 0xffffffff; 7724 #else 7725 sym_set_cam_status(cp->cam_ccb, CAM_REQ_INVALID); 7726 return -1; 7727 #endif 7728 } 7729 } else { 7730 /* CDB is in the CAM ccb (buffer) */ 7731 bcopy(csio->cdb_io.cdb_bytes, cp->cdb_buf, cmd_len); 7732 cmd_ba = CCB_BA (cp, cdb_buf[0]); 7733 } 7734 7735 cp->phys.cmd.addr = cpu_to_scr(cmd_ba); 7736 cp->phys.cmd.size = cpu_to_scr(cmd_len); 7737 7738 return 0; 7739 } 7740 7741 /* 7742 * Set up data pointers used by SCRIPTS. 7743 */ 7744 static void __inline 7745 sym_setup_data_pointers(hcb_p np, ccb_p cp, int dir) 7746 { 7747 u32 lastp, goalp; 7748 7749 /* 7750 * No segments means no data. 7751 */ 7752 if (!cp->segments) 7753 dir = CAM_DIR_NONE; 7754 7755 /* 7756 * Set the data pointer. 7757 */ 7758 switch(dir) { 7759 case CAM_DIR_OUT: 7760 goalp = SCRIPTA_BA (np, data_out2) + 8; 7761 lastp = goalp - 8 - (cp->segments * (2*4)); 7762 break; 7763 case CAM_DIR_IN: 7764 cp->host_flags |= HF_DATA_IN; 7765 goalp = SCRIPTA_BA (np, data_in2) + 8; 7766 lastp = goalp - 8 - (cp->segments * (2*4)); 7767 break; 7768 case CAM_DIR_NONE: 7769 default: 7770 lastp = goalp = SCRIPTB_BA (np, no_data); 7771 break; 7772 } 7773 7774 cp->phys.head.lastp = cpu_to_scr(lastp); 7775 cp->phys.head.goalp = cpu_to_scr(goalp); 7776 cp->phys.head.savep = cpu_to_scr(lastp); 7777 cp->startp = cp->phys.head.savep; 7778 } 7779 7780 7781 /* 7782 * Call back routine for the DMA map service. 7783 * If bounce buffers are used (why ?), we may sleep and then 7784 * be called there in another context. 7785 */ 7786 static void 7787 sym_execute_ccb(void *arg, bus_dma_segment_t *psegs, int nsegs, int error) 7788 { 7789 ccb_p cp; 7790 hcb_p np; 7791 union ccb *ccb; 7792 int s; 7793 7794 s = splcam(); 7795 7796 cp = (ccb_p) arg; 7797 ccb = cp->cam_ccb; 7798 np = (hcb_p) cp->arg; 7799 7800 /* 7801 * Deal with weird races. 7802 */ 7803 if (sym_get_cam_status(ccb) != CAM_REQ_INPROG) 7804 goto out_abort; 7805 7806 /* 7807 * Deal with weird errors. 7808 */ 7809 if (error) { 7810 cp->dmamapped = 0; 7811 sym_set_cam_status(cp->cam_ccb, CAM_REQ_ABORTED); 7812 goto out_abort; 7813 } 7814 7815 /* 7816 * Build the data descriptor for the chip. 7817 */ 7818 if (nsegs) { 7819 int retv; 7820 /* 896 rev 1 requires to be careful about boundaries */ 7821 if (np->device_id == PCI_ID_SYM53C896 && np->revision_id <= 1) 7822 retv = sym_scatter_sg_physical(np, cp, psegs, nsegs); 7823 else 7824 retv = sym_fast_scatter_sg_physical(np,cp, psegs,nsegs); 7825 if (retv < 0) { 7826 sym_set_cam_status(cp->cam_ccb, CAM_REQ_TOO_BIG); 7827 goto out_abort; 7828 } 7829 } 7830 7831 /* 7832 * Synchronize the DMA map only if we have 7833 * actually mapped the data. 7834 */ 7835 if (cp->dmamapped) { 7836 bus_dmamap_sync(np->data_dmat, cp->dmamap, 7837 (cp->dmamapped == SYM_DMA_READ ? 7838 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 7839 } 7840 7841 /* 7842 * Set host status to busy state. 7843 * May have been set back to HS_WAIT to avoid a race. 7844 */ 7845 cp->host_status = cp->nego_status ? HS_NEGOTIATE : HS_BUSY; 7846 7847 /* 7848 * Set data pointers. 7849 */ 7850 sym_setup_data_pointers(np, cp, (ccb->ccb_h.flags & CAM_DIR_MASK)); 7851 7852 /* 7853 * Enqueue this IO in our pending queue. 7854 */ 7855 sym_enqueue_cam_ccb(np, ccb); 7856 7857 /* 7858 * When `#ifed 1', the code below makes the driver 7859 * panic on the first attempt to write to a SCSI device. 7860 * It is the first test we want to do after a driver 7861 * change that does not seem obviously safe. :) 7862 */ 7863 #if 0 7864 switch (cp->cdb_buf[0]) { 7865 case 0x0A: case 0x2A: case 0xAA: 7866 panic("XXXXXXXXXXXXX WRITE NOT YET ALLOWED XXXXXXXXXXXXXX\n"); 7867 MDELAY(10000); 7868 break; 7869 default: 7870 break; 7871 } 7872 #endif 7873 /* 7874 * Activate this job. 7875 */ 7876 sym_put_start_queue(np, cp); 7877 out: 7878 splx(s); 7879 return; 7880 out_abort: 7881 sym_free_ccb(np, cp); 7882 sym_xpt_done(np, ccb); 7883 goto out; 7884 } 7885 7886 /* 7887 * How complex it gets to deal with the data in CAM. 7888 * The Bus Dma stuff makes things still more complex. 7889 */ 7890 static void 7891 sym_setup_data_and_start(hcb_p np, struct ccb_scsiio *csio, ccb_p cp) 7892 { 7893 struct ccb_hdr *ccb_h; 7894 int dir, retv; 7895 7896 ccb_h = &csio->ccb_h; 7897 7898 /* 7899 * Now deal with the data. 7900 */ 7901 cp->data_len = csio->dxfer_len; 7902 cp->arg = np; 7903 7904 /* 7905 * No direction means no data. 7906 */ 7907 dir = (ccb_h->flags & CAM_DIR_MASK); 7908 if (dir == CAM_DIR_NONE) { 7909 sym_execute_ccb(cp, NULL, 0, 0); 7910 return; 7911 } 7912 7913 if (!(ccb_h->flags & CAM_SCATTER_VALID)) { 7914 /* Single buffer */ 7915 if (!(ccb_h->flags & CAM_DATA_PHYS)) { 7916 /* Buffer is virtual */ 7917 int s; 7918 7919 cp->dmamapped = (dir == CAM_DIR_IN) ? 7920 SYM_DMA_READ : SYM_DMA_WRITE; 7921 s = splsoftvm(); 7922 retv = bus_dmamap_load(np->data_dmat, cp->dmamap, 7923 csio->data_ptr, csio->dxfer_len, 7924 sym_execute_ccb, cp, 0); 7925 if (retv == EINPROGRESS) { 7926 cp->host_status = HS_WAIT; 7927 xpt_freeze_simq(np->sim, 1); 7928 csio->ccb_h.status |= CAM_RELEASE_SIMQ; 7929 } 7930 splx(s); 7931 } else { 7932 /* Buffer is physical */ 7933 struct bus_dma_segment seg; 7934 7935 seg.ds_addr = (bus_addr_t) csio->data_ptr; 7936 sym_execute_ccb(cp, &seg, 1, 0); 7937 } 7938 } else { 7939 /* Scatter/gather list */ 7940 struct bus_dma_segment *segs; 7941 7942 if ((ccb_h->flags & CAM_SG_LIST_PHYS) != 0) { 7943 /* The SG list pointer is physical */ 7944 sym_set_cam_status(cp->cam_ccb, CAM_REQ_INVALID); 7945 goto out_abort; 7946 } 7947 7948 if (!(ccb_h->flags & CAM_DATA_PHYS)) { 7949 /* SG buffer pointers are virtual */ 7950 sym_set_cam_status(cp->cam_ccb, CAM_REQ_INVALID); 7951 goto out_abort; 7952 } 7953 7954 /* SG buffer pointers are physical */ 7955 segs = (struct bus_dma_segment *)csio->data_ptr; 7956 sym_execute_ccb(cp, segs, csio->sglist_cnt, 0); 7957 } 7958 return; 7959 out_abort: 7960 sym_free_ccb(np, cp); 7961 sym_xpt_done(np, (union ccb *) csio); 7962 } 7963 7964 /* 7965 * Move the scatter list to our data block. 7966 */ 7967 static int 7968 sym_fast_scatter_sg_physical(hcb_p np, ccb_p cp, 7969 bus_dma_segment_t *psegs, int nsegs) 7970 { 7971 struct sym_tblmove *data; 7972 bus_dma_segment_t *psegs2; 7973 7974 if (nsegs > SYM_CONF_MAX_SG) 7975 return -1; 7976 7977 data = &cp->phys.data[SYM_CONF_MAX_SG-1]; 7978 psegs2 = &psegs[nsegs-1]; 7979 cp->segments = nsegs; 7980 7981 while (1) { 7982 data->addr = cpu_to_scr(psegs2->ds_addr); 7983 data->size = cpu_to_scr(psegs2->ds_len); 7984 if (DEBUG_FLAGS & DEBUG_SCATTER) { 7985 printf ("%s scatter: paddr=%lx len=%ld\n", 7986 sym_name(np), (long) psegs2->ds_addr, 7987 (long) psegs2->ds_len); 7988 } 7989 if (psegs2 != psegs) { 7990 --data; 7991 --psegs2; 7992 continue; 7993 } 7994 break; 7995 } 7996 return 0; 7997 } 7998 7999 8000 /* 8001 * Scatter a SG list with physical addresses into bus addressable chunks. 8002 * We need to ensure 16MB boundaries not to be crossed during DMA of 8003 * each segment, due to some chips being flawed. 8004 */ 8005 #define BOUND_MASK ((1UL<<24)-1) 8006 static int 8007 sym_scatter_sg_physical(hcb_p np, ccb_p cp, bus_dma_segment_t *psegs, int nsegs) 8008 { 8009 u_long ps, pe, pn; 8010 u_long k; 8011 int s, t; 8012 8013 s = SYM_CONF_MAX_SG - 1; 8014 t = nsegs - 1; 8015 ps = psegs[t].ds_addr; 8016 pe = ps + psegs[t].ds_len; 8017 8018 while (s >= 0) { 8019 pn = (pe - 1) & ~BOUND_MASK; 8020 if (pn <= ps) 8021 pn = ps; 8022 k = pe - pn; 8023 if (DEBUG_FLAGS & DEBUG_SCATTER) { 8024 printf ("%s scatter: paddr=%lx len=%ld\n", 8025 sym_name(np), pn, k); 8026 } 8027 cp->phys.data[s].addr = cpu_to_scr(pn); 8028 cp->phys.data[s].size = cpu_to_scr(k); 8029 --s; 8030 if (pn == ps) { 8031 if (--t < 0) 8032 break; 8033 ps = psegs[t].ds_addr; 8034 pe = ps + psegs[t].ds_len; 8035 } 8036 else 8037 pe = pn; 8038 } 8039 8040 cp->segments = SYM_CONF_MAX_SG - 1 - s; 8041 8042 return t >= 0 ? -1 : 0; 8043 } 8044 #undef BOUND_MASK 8045 8046 /* 8047 * SIM action for non performance critical stuff. 8048 */ 8049 static void sym_action2(struct cam_sim *sim, union ccb *ccb) 8050 { 8051 hcb_p np; 8052 tcb_p tp; 8053 lcb_p lp; 8054 struct ccb_hdr *ccb_h; 8055 8056 /* 8057 * Retrieve our controller data structure. 8058 */ 8059 np = (hcb_p) cam_sim_softc(sim); 8060 8061 ccb_h = &ccb->ccb_h; 8062 8063 switch (ccb_h->func_code) { 8064 case XPT_SET_TRAN_SETTINGS: 8065 { 8066 struct ccb_trans_settings *cts; 8067 8068 cts = &ccb->cts; 8069 tp = &np->target[ccb_h->target_id]; 8070 8071 /* 8072 * Update SPI transport settings in TARGET control block. 8073 * Update SCSI device settings in LUN control block. 8074 */ 8075 lp = sym_lp(np, tp, ccb_h->target_lun); 8076 #ifdef FreeBSD_New_Tran_Settings 8077 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) { 8078 #else 8079 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) { 8080 #endif 8081 sym_update_trans(np, tp, &tp->tinfo.goal, cts); 8082 if (lp) 8083 sym_update_dflags(np, &lp->current_flags, cts); 8084 } 8085 #ifdef FreeBSD_New_Tran_Settings 8086 if (cts->type == CTS_TYPE_USER_SETTINGS) { 8087 #else 8088 if ((cts->flags & CCB_TRANS_USER_SETTINGS) != 0) { 8089 #endif 8090 sym_update_trans(np, tp, &tp->tinfo.user, cts); 8091 if (lp) 8092 sym_update_dflags(np, &lp->user_flags, cts); 8093 } 8094 8095 sym_xpt_done2(np, ccb, CAM_REQ_CMP); 8096 break; 8097 } 8098 case XPT_GET_TRAN_SETTINGS: 8099 { 8100 struct ccb_trans_settings *cts; 8101 struct sym_trans *tip; 8102 u_char dflags; 8103 8104 cts = &ccb->cts; 8105 tp = &np->target[ccb_h->target_id]; 8106 lp = sym_lp(np, tp, ccb_h->target_lun); 8107 8108 #ifdef FreeBSD_New_Tran_Settings 8109 #define cts__scsi (&cts->proto_specific.scsi) 8110 #define cts__spi (&cts->xport_specific.spi) 8111 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) { 8112 tip = &tp->tinfo.current; 8113 dflags = lp ? lp->current_flags : 0; 8114 } 8115 else { 8116 tip = &tp->tinfo.user; 8117 dflags = lp ? lp->user_flags : tp->usrflags; 8118 } 8119 8120 cts->protocol = PROTO_SCSI; 8121 cts->transport = XPORT_SPI; 8122 cts->protocol_version = tip->scsi_version; 8123 cts->transport_version = tip->spi_version; 8124 8125 cts__spi->sync_period = tip->period; 8126 cts__spi->sync_offset = tip->offset; 8127 cts__spi->bus_width = tip->width; 8128 cts__spi->ppr_options = tip->options; 8129 8130 cts__spi->valid = CTS_SPI_VALID_SYNC_RATE 8131 | CTS_SPI_VALID_SYNC_OFFSET 8132 | CTS_SPI_VALID_BUS_WIDTH 8133 | CTS_SPI_VALID_PPR_OPTIONS; 8134 8135 cts__spi->flags &= ~CTS_SPI_FLAGS_DISC_ENB; 8136 if (dflags & SYM_DISC_ENABLED) 8137 cts__spi->flags |= CTS_SPI_FLAGS_DISC_ENB; 8138 cts__spi->valid |= CTS_SPI_VALID_DISC; 8139 8140 cts__scsi->flags &= ~CTS_SCSI_FLAGS_TAG_ENB; 8141 if (dflags & SYM_TAGS_ENABLED) 8142 cts__scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB; 8143 cts__scsi->valid |= CTS_SCSI_VALID_TQ; 8144 #undef cts__spi 8145 #undef cts__scsi 8146 #else 8147 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) { 8148 tip = &tp->tinfo.current; 8149 dflags = lp ? lp->current_flags : 0; 8150 } 8151 else { 8152 tip = &tp->tinfo.user; 8153 dflags = lp ? lp->user_flags : tp->usrflags; 8154 } 8155 8156 cts->sync_period = tip->period; 8157 cts->sync_offset = tip->offset; 8158 cts->bus_width = tip->width; 8159 8160 cts->valid = CCB_TRANS_SYNC_RATE_VALID 8161 | CCB_TRANS_SYNC_OFFSET_VALID 8162 | CCB_TRANS_BUS_WIDTH_VALID; 8163 8164 cts->flags &= ~(CCB_TRANS_DISC_ENB|CCB_TRANS_TAG_ENB); 8165 8166 if (dflags & SYM_DISC_ENABLED) 8167 cts->flags |= CCB_TRANS_DISC_ENB; 8168 8169 if (dflags & SYM_TAGS_ENABLED) 8170 cts->flags |= CCB_TRANS_TAG_ENB; 8171 8172 cts->valid |= CCB_TRANS_DISC_VALID; 8173 cts->valid |= CCB_TRANS_TQ_VALID; 8174 #endif 8175 sym_xpt_done2(np, ccb, CAM_REQ_CMP); 8176 break; 8177 } 8178 case XPT_CALC_GEOMETRY: 8179 { 8180 cam_calc_geometry(&ccb->ccg, /*extended*/1); 8181 sym_xpt_done2(np, ccb, CAM_REQ_CMP); 8182 break; 8183 } 8184 case XPT_PATH_INQ: 8185 { 8186 struct ccb_pathinq *cpi = &ccb->cpi; 8187 cpi->version_num = 1; 8188 cpi->hba_inquiry = PI_MDP_ABLE|PI_SDTR_ABLE|PI_TAG_ABLE; 8189 if ((np->features & FE_WIDE) != 0) 8190 cpi->hba_inquiry |= PI_WIDE_16; 8191 cpi->target_sprt = 0; 8192 cpi->hba_misc = 0; 8193 if (np->usrflags & SYM_SCAN_TARGETS_HILO) 8194 cpi->hba_misc |= PIM_SCANHILO; 8195 if (np->usrflags & SYM_AVOID_BUS_RESET) 8196 cpi->hba_misc |= PIM_NOBUSRESET; 8197 cpi->hba_eng_cnt = 0; 8198 cpi->max_target = (np->features & FE_WIDE) ? 15 : 7; 8199 /* Semantic problem:)LUN number max = max number of LUNs - 1 */ 8200 cpi->max_lun = SYM_CONF_MAX_LUN-1; 8201 if (SYM_SETUP_MAX_LUN < SYM_CONF_MAX_LUN) 8202 cpi->max_lun = SYM_SETUP_MAX_LUN-1; 8203 cpi->bus_id = cam_sim_bus(sim); 8204 cpi->initiator_id = np->myaddr; 8205 cpi->base_transfer_speed = 3300; 8206 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 8207 strncpy(cpi->hba_vid, "Symbios", HBA_IDLEN); 8208 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 8209 cpi->unit_number = cam_sim_unit(sim); 8210 8211 #ifdef FreeBSD_New_Tran_Settings 8212 cpi->protocol = PROTO_SCSI; 8213 cpi->protocol_version = SCSI_REV_2; 8214 cpi->transport = XPORT_SPI; 8215 cpi->transport_version = 2; 8216 cpi->xport_specific.spi.ppr_options = SID_SPI_CLOCK_ST; 8217 if (np->features & FE_ULTRA3) { 8218 cpi->transport_version = 3; 8219 cpi->xport_specific.spi.ppr_options = 8220 SID_SPI_CLOCK_DT_ST; 8221 } 8222 #endif 8223 sym_xpt_done2(np, ccb, CAM_REQ_CMP); 8224 break; 8225 } 8226 case XPT_ABORT: 8227 { 8228 union ccb *abort_ccb = ccb->cab.abort_ccb; 8229 switch(abort_ccb->ccb_h.func_code) { 8230 case XPT_SCSI_IO: 8231 if (sym_abort_scsiio(np, abort_ccb, 0) == 0) { 8232 sym_xpt_done2(np, ccb, CAM_REQ_CMP); 8233 break; 8234 } 8235 default: 8236 sym_xpt_done2(np, ccb, CAM_UA_ABORT); 8237 break; 8238 } 8239 break; 8240 } 8241 case XPT_RESET_DEV: 8242 { 8243 sym_reset_dev(np, ccb); 8244 break; 8245 } 8246 case XPT_RESET_BUS: 8247 { 8248 sym_reset_scsi_bus(np, 0); 8249 if (sym_verbose) { 8250 xpt_print_path(np->path); 8251 printf("SCSI BUS reset delivered.\n"); 8252 } 8253 sym_init (np, 1); 8254 sym_xpt_done2(np, ccb, CAM_REQ_CMP); 8255 break; 8256 } 8257 case XPT_ACCEPT_TARGET_IO: 8258 case XPT_CONT_TARGET_IO: 8259 case XPT_EN_LUN: 8260 case XPT_NOTIFY_ACK: 8261 case XPT_IMMED_NOTIFY: 8262 case XPT_TERM_IO: 8263 default: 8264 sym_xpt_done2(np, ccb, CAM_REQ_INVALID); 8265 break; 8266 } 8267 } 8268 8269 /* 8270 * Asynchronous notification handler. 8271 */ 8272 static void 8273 sym_async(void *cb_arg, u32 code, struct cam_path *path, void *arg) 8274 { 8275 hcb_p np; 8276 struct cam_sim *sim; 8277 u_int tn; 8278 tcb_p tp; 8279 int s; 8280 8281 s = splcam(); 8282 8283 sim = (struct cam_sim *) cb_arg; 8284 np = (hcb_p) cam_sim_softc(sim); 8285 8286 switch (code) { 8287 case AC_LOST_DEVICE: 8288 tn = xpt_path_target_id(path); 8289 if (tn >= SYM_CONF_MAX_TARGET) 8290 break; 8291 8292 tp = &np->target[tn]; 8293 8294 tp->to_reset = 0; 8295 tp->head.sval = 0; 8296 tp->head.wval = np->rv_scntl3; 8297 tp->head.uval = 0; 8298 8299 tp->tinfo.current.period = tp->tinfo.goal.period = 0; 8300 tp->tinfo.current.offset = tp->tinfo.goal.offset = 0; 8301 tp->tinfo.current.width = tp->tinfo.goal.width = BUS_8_BIT; 8302 tp->tinfo.current.options = tp->tinfo.goal.options = 0; 8303 8304 break; 8305 default: 8306 break; 8307 } 8308 8309 splx(s); 8310 } 8311 8312 /* 8313 * Update transfer settings of a target. 8314 */ 8315 static void sym_update_trans(hcb_p np, tcb_p tp, struct sym_trans *tip, 8316 struct ccb_trans_settings *cts) 8317 { 8318 /* 8319 * Update the infos. 8320 */ 8321 #ifdef FreeBSD_New_Tran_Settings 8322 #define cts__spi (&cts->xport_specific.spi) 8323 if ((cts__spi->valid & CTS_SPI_VALID_BUS_WIDTH) != 0) 8324 tip->width = cts__spi->bus_width; 8325 if ((cts__spi->valid & CTS_SPI_VALID_SYNC_OFFSET) != 0) 8326 tip->offset = cts__spi->sync_offset; 8327 if ((cts__spi->valid & CTS_SPI_VALID_SYNC_RATE) != 0) 8328 tip->period = cts__spi->sync_period; 8329 if ((cts__spi->valid & CTS_SPI_VALID_PPR_OPTIONS) != 0) 8330 tip->options = (cts__spi->ppr_options & PPR_OPT_DT); 8331 if (cts->protocol_version != PROTO_VERSION_UNSPECIFIED && 8332 cts->protocol_version != PROTO_VERSION_UNKNOWN) 8333 tip->scsi_version = cts->protocol_version; 8334 if (cts->transport_version != XPORT_VERSION_UNSPECIFIED && 8335 cts->transport_version != XPORT_VERSION_UNKNOWN) 8336 tip->spi_version = cts->transport_version; 8337 #undef cts__spi 8338 #else 8339 if ((cts->valid & CCB_TRANS_BUS_WIDTH_VALID) != 0) 8340 tip->width = cts->bus_width; 8341 if ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) != 0) 8342 tip->offset = cts->sync_offset; 8343 if ((cts->valid & CCB_TRANS_SYNC_RATE_VALID) != 0) 8344 tip->period = cts->sync_period; 8345 #endif 8346 /* 8347 * Scale against driver configuration limits. 8348 */ 8349 if (tip->width > SYM_SETUP_MAX_WIDE) tip->width = SYM_SETUP_MAX_WIDE; 8350 if (tip->offset > SYM_SETUP_MAX_OFFS) tip->offset = SYM_SETUP_MAX_OFFS; 8351 if (tip->period < SYM_SETUP_MIN_SYNC) tip->period = SYM_SETUP_MIN_SYNC; 8352 8353 /* 8354 * Scale against actual controller BUS width. 8355 */ 8356 if (tip->width > np->maxwide) 8357 tip->width = np->maxwide; 8358 8359 #ifdef FreeBSD_New_Tran_Settings 8360 /* 8361 * Only accept DT if controller supports and SYNC/WIDE asked. 8362 */ 8363 if (!((np->features & (FE_C10|FE_ULTRA3)) == (FE_C10|FE_ULTRA3)) || 8364 !(tip->width == BUS_16_BIT && tip->offset)) { 8365 tip->options &= ~PPR_OPT_DT; 8366 } 8367 #else 8368 /* 8369 * For now, only assume DT if period <= 9, BUS 16 and offset != 0. 8370 */ 8371 tip->options = 0; 8372 if ((np->features & (FE_C10|FE_ULTRA3)) == (FE_C10|FE_ULTRA3) && 8373 tip->period <= 9 && tip->width == BUS_16_BIT && tip->offset) { 8374 tip->options |= PPR_OPT_DT; 8375 } 8376 #endif 8377 8378 /* 8379 * Scale period factor and offset against controller limits. 8380 */ 8381 if (tip->options & PPR_OPT_DT) { 8382 if (tip->period < np->minsync_dt) 8383 tip->period = np->minsync_dt; 8384 if (tip->period > np->maxsync_dt) 8385 tip->period = np->maxsync_dt; 8386 if (tip->offset > np->maxoffs_dt) 8387 tip->offset = np->maxoffs_dt; 8388 } 8389 else { 8390 if (tip->period < np->minsync) 8391 tip->period = np->minsync; 8392 if (tip->period > np->maxsync) 8393 tip->period = np->maxsync; 8394 if (tip->offset > np->maxoffs) 8395 tip->offset = np->maxoffs; 8396 } 8397 } 8398 8399 /* 8400 * Update flags for a device (logical unit). 8401 */ 8402 static void 8403 sym_update_dflags(hcb_p np, u_char *flags, struct ccb_trans_settings *cts) 8404 { 8405 #ifdef FreeBSD_New_Tran_Settings 8406 #define cts__scsi (&cts->proto_specific.scsi) 8407 #define cts__spi (&cts->xport_specific.spi) 8408 if ((cts__spi->valid & CTS_SPI_VALID_DISC) != 0) { 8409 if ((cts__spi->flags & CTS_SPI_FLAGS_DISC_ENB) != 0) 8410 *flags |= SYM_DISC_ENABLED; 8411 else 8412 *flags &= ~SYM_DISC_ENABLED; 8413 } 8414 8415 if ((cts__scsi->valid & CTS_SCSI_VALID_TQ) != 0) { 8416 if ((cts__scsi->flags & CTS_SCSI_FLAGS_TAG_ENB) != 0) 8417 *flags |= SYM_TAGS_ENABLED; 8418 else 8419 *flags &= ~SYM_TAGS_ENABLED; 8420 } 8421 #undef cts__spi 8422 #undef cts__scsi 8423 #else 8424 if ((cts->valid & CCB_TRANS_DISC_VALID) != 0) { 8425 if ((cts->flags & CCB_TRANS_DISC_ENB) != 0) 8426 *flags |= SYM_DISC_ENABLED; 8427 else 8428 *flags &= ~SYM_DISC_ENABLED; 8429 } 8430 8431 if ((cts->valid & CCB_TRANS_TQ_VALID) != 0) { 8432 if ((cts->flags & CCB_TRANS_TAG_ENB) != 0) 8433 *flags |= SYM_TAGS_ENABLED; 8434 else 8435 *flags &= ~SYM_TAGS_ENABLED; 8436 } 8437 #endif 8438 } 8439 8440 8441 /*============= DRIVER INITIALISATION ==================*/ 8442 8443 8444 static device_method_t sym_pci_methods[] = { 8445 DEVMETHOD(device_probe, sym_pci_probe), 8446 DEVMETHOD(device_attach, sym_pci_attach), 8447 { 0, 0 } 8448 }; 8449 8450 static driver_t sym_pci_driver = { 8451 "sym", 8452 sym_pci_methods, 8453 sizeof(struct sym_hcb) 8454 }; 8455 8456 static devclass_t sym_devclass; 8457 8458 DRIVER_MODULE(sym, pci, sym_pci_driver, sym_devclass, 0, 0); 8459 MODULE_DEPEND(sym, cam, 1, 1, 1); 8460 MODULE_DEPEND(sym, pci, 1, 1, 1); 8461 8462 8463 static struct sym_pci_chip sym_pci_dev_table[] = { 8464 {PCI_ID_SYM53C810, 0x0f, "810", 4, 8, 4, 64, 8465 FE_ERL} 8466 , 8467 #ifdef SYM_DEBUG_GENERIC_SUPPORT 8468 {PCI_ID_SYM53C810, 0xff, "810a", 4, 8, 4, 1, 8469 FE_BOF} 8470 , 8471 #else 8472 {PCI_ID_SYM53C810, 0xff, "810a", 4, 8, 4, 1, 8473 FE_CACHE_SET|FE_LDSTR|FE_PFEN|FE_BOF} 8474 , 8475 #endif 8476 {PCI_ID_SYM53C815, 0xff, "815", 4, 8, 4, 64, 8477 FE_BOF|FE_ERL} 8478 , 8479 {PCI_ID_SYM53C825, 0x0f, "825", 6, 8, 4, 64, 8480 FE_WIDE|FE_BOF|FE_ERL|FE_DIFF} 8481 , 8482 {PCI_ID_SYM53C825, 0xff, "825a", 6, 8, 4, 2, 8483 FE_WIDE|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM|FE_DIFF} 8484 , 8485 {PCI_ID_SYM53C860, 0xff, "860", 4, 8, 5, 1, 8486 FE_ULTRA|FE_CLK80|FE_CACHE_SET|FE_BOF|FE_LDSTR|FE_PFEN} 8487 , 8488 {PCI_ID_SYM53C875, 0x01, "875", 6, 16, 5, 2, 8489 FE_WIDE|FE_ULTRA|FE_CLK80|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 8490 FE_RAM|FE_DIFF} 8491 , 8492 {PCI_ID_SYM53C875, 0xff, "875", 6, 16, 5, 2, 8493 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 8494 FE_RAM|FE_DIFF} 8495 , 8496 {PCI_ID_SYM53C875_2, 0xff, "875", 6, 16, 5, 2, 8497 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 8498 FE_RAM|FE_DIFF} 8499 , 8500 {PCI_ID_SYM53C885, 0xff, "885", 6, 16, 5, 2, 8501 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 8502 FE_RAM|FE_DIFF} 8503 , 8504 #ifdef SYM_DEBUG_GENERIC_SUPPORT 8505 {PCI_ID_SYM53C895, 0xff, "895", 6, 31, 7, 2, 8506 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS| 8507 FE_RAM|FE_LCKFRQ} 8508 , 8509 #else 8510 {PCI_ID_SYM53C895, 0xff, "895", 6, 31, 7, 2, 8511 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 8512 FE_RAM|FE_LCKFRQ} 8513 , 8514 #endif 8515 {PCI_ID_SYM53C896, 0xff, "896", 6, 31, 7, 4, 8516 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 8517 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_LCKFRQ} 8518 , 8519 {PCI_ID_SYM53C895A, 0xff, "895a", 6, 31, 7, 4, 8520 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 8521 FE_RAM|FE_RAM8K|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_LCKFRQ} 8522 , 8523 {PCI_ID_LSI53C1010, 0x00, "1010-33", 6, 31, 7, 8, 8524 FE_WIDE|FE_ULTRA3|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFBC|FE_LDSTR|FE_PFEN| 8525 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_CRC| 8526 FE_C10} 8527 , 8528 {PCI_ID_LSI53C1010, 0xff, "1010-33", 6, 31, 7, 8, 8529 FE_WIDE|FE_ULTRA3|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFBC|FE_LDSTR|FE_PFEN| 8530 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_CRC| 8531 FE_C10|FE_U3EN} 8532 , 8533 {PCI_ID_LSI53C1010_2, 0xff, "1010-66", 6, 31, 7, 8, 8534 FE_WIDE|FE_ULTRA3|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFBC|FE_LDSTR|FE_PFEN| 8535 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_66MHZ|FE_CRC| 8536 FE_C10|FE_U3EN} 8537 , 8538 {PCI_ID_LSI53C1510D, 0xff, "1510d", 6, 31, 7, 4, 8539 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 8540 FE_RAM|FE_IO256|FE_LEDC} 8541 }; 8542 8543 #define sym_pci_num_devs \ 8544 (sizeof(sym_pci_dev_table) / sizeof(sym_pci_dev_table[0])) 8545 8546 /* 8547 * Look up the chip table. 8548 * 8549 * Return a pointer to the chip entry if found, 8550 * zero otherwise. 8551 */ 8552 static struct sym_pci_chip * 8553 sym_find_pci_chip(device_t dev) 8554 { 8555 struct sym_pci_chip *chip; 8556 int i; 8557 u_short device_id; 8558 u_char revision; 8559 8560 if (pci_get_vendor(dev) != PCI_VENDOR_NCR) 8561 return 0; 8562 8563 device_id = pci_get_device(dev); 8564 revision = pci_get_revid(dev); 8565 8566 for (i = 0; i < sym_pci_num_devs; i++) { 8567 chip = &sym_pci_dev_table[i]; 8568 if (device_id != chip->device_id) 8569 continue; 8570 if (revision > chip->revision_id) 8571 continue; 8572 return chip; 8573 } 8574 8575 return 0; 8576 } 8577 8578 /* 8579 * Tell upper layer if the chip is supported. 8580 */ 8581 static int 8582 sym_pci_probe(device_t dev) 8583 { 8584 struct sym_pci_chip *chip; 8585 8586 chip = sym_find_pci_chip(dev); 8587 if (chip && sym_find_firmware(chip)) { 8588 device_set_desc(dev, chip->name); 8589 return (chip->lp_probe_bit & SYM_SETUP_LP_PROBE_MAP)? 8590 BUS_PROBE_LOW_PRIORITY : BUS_PROBE_DEFAULT; 8591 } 8592 return ENXIO; 8593 } 8594 8595 /* 8596 * Attach a sym53c8xx device. 8597 */ 8598 static int 8599 sym_pci_attach(device_t dev) 8600 { 8601 struct sym_pci_chip *chip; 8602 u_short command; 8603 u_char cachelnsz; 8604 struct sym_hcb *np = 0; 8605 struct sym_nvram nvram; 8606 struct sym_fw *fw = 0; 8607 int i; 8608 bus_dma_tag_t bus_dmat; 8609 8610 /* 8611 * I expected to be told about a parent 8612 * DMA tag, but didn't find any. 8613 */ 8614 bus_dmat = NULL; 8615 8616 /* 8617 * Only probed devices should be attached. 8618 * We just enjoy being paranoid. :) 8619 */ 8620 chip = sym_find_pci_chip(dev); 8621 if (chip == NULL || (fw = sym_find_firmware(chip)) == NULL) 8622 return (ENXIO); 8623 8624 /* 8625 * Allocate immediately the host control block, 8626 * since we are only expecting to succeed. :) 8627 * We keep track in the HCB of all the resources that 8628 * are to be released on error. 8629 */ 8630 np = __sym_calloc_dma(bus_dmat, sizeof(*np), "HCB"); 8631 if (np) 8632 np->bus_dmat = bus_dmat; 8633 else 8634 goto attach_failed; 8635 8636 /* 8637 * Copy some useful infos to the HCB. 8638 */ 8639 np->hcb_ba = vtobus(np); 8640 np->verbose = bootverbose; 8641 np->device = dev; 8642 np->unit = device_get_unit(dev); 8643 np->device_id = pci_get_device(dev); 8644 np->revision_id = pci_get_revid(dev); 8645 np->features = chip->features; 8646 np->clock_divn = chip->nr_divisor; 8647 np->maxoffs = chip->offset_max; 8648 np->maxburst = chip->burst_max; 8649 np->scripta_sz = fw->a_size; 8650 np->scriptb_sz = fw->b_size; 8651 np->fw_setup = fw->setup; 8652 np->fw_patch = fw->patch; 8653 np->fw_name = fw->name; 8654 8655 /* 8656 * Edit its name. 8657 */ 8658 snprintf(np->inst_name, sizeof(np->inst_name), "sym%d", np->unit); 8659 8660 /* 8661 * Initialyze the CCB free and busy queues. 8662 */ 8663 sym_que_init(&np->free_ccbq); 8664 sym_que_init(&np->busy_ccbq); 8665 sym_que_init(&np->comp_ccbq); 8666 sym_que_init(&np->cam_ccbq); 8667 8668 /* 8669 * Allocate a tag for the DMA of user data. 8670 */ 8671 if (bus_dma_tag_create(np->bus_dmat, 1, (1<<24), 8672 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 8673 NULL, NULL, 8674 BUS_SPACE_MAXSIZE, SYM_CONF_MAX_SG, 8675 (1<<24), 0, busdma_lock_mutex, &Giant, 8676 &np->data_dmat)) { 8677 device_printf(dev, "failed to create DMA tag.\n"); 8678 goto attach_failed; 8679 } 8680 /* 8681 * Read and apply some fix-ups to the PCI COMMAND 8682 * register. We want the chip to be enabled for: 8683 * - BUS mastering 8684 * - PCI parity checking (reporting would also be fine) 8685 * - Write And Invalidate. 8686 */ 8687 command = pci_read_config(dev, PCIR_COMMAND, 2); 8688 command |= PCIM_CMD_BUSMASTEREN; 8689 command |= PCIM_CMD_PERRESPEN; 8690 command |= /* PCIM_CMD_MWIEN */ 0x0010; 8691 pci_write_config(dev, PCIR_COMMAND, command, 2); 8692 8693 /* 8694 * Let the device know about the cache line size, 8695 * if it doesn't yet. 8696 */ 8697 cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 8698 if (!cachelnsz) { 8699 cachelnsz = 8; 8700 pci_write_config(dev, PCIR_CACHELNSZ, cachelnsz, 1); 8701 } 8702 8703 /* 8704 * Alloc/get/map/retrieve everything that deals with MMIO. 8705 */ 8706 if ((command & PCIM_CMD_MEMEN) != 0) { 8707 int regs_id = SYM_PCI_MMIO; 8708 np->mmio_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 8709 ®s_id, RF_ACTIVE); 8710 } 8711 if (!np->mmio_res) { 8712 device_printf(dev, "failed to allocate MMIO resources\n"); 8713 goto attach_failed; 8714 } 8715 np->mmio_bsh = rman_get_bushandle(np->mmio_res); 8716 np->mmio_tag = rman_get_bustag(np->mmio_res); 8717 np->mmio_pa = rman_get_start(np->mmio_res); 8718 np->mmio_va = (vm_offset_t) rman_get_virtual(np->mmio_res); 8719 np->mmio_ba = np->mmio_pa; 8720 8721 /* 8722 * Allocate the IRQ. 8723 */ 8724 i = 0; 8725 np->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, 8726 RF_ACTIVE | RF_SHAREABLE); 8727 if (!np->irq_res) { 8728 device_printf(dev, "failed to allocate IRQ resource\n"); 8729 goto attach_failed; 8730 } 8731 8732 #ifdef SYM_CONF_IOMAPPED 8733 /* 8734 * User want us to use normal IO with PCI. 8735 * Alloc/get/map/retrieve everything that deals with IO. 8736 */ 8737 if ((command & PCI_COMMAND_IO_ENABLE) != 0) { 8738 int regs_id = SYM_PCI_IO; 8739 np->io_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 8740 ®s_id, RF_ACTIVE); 8741 } 8742 if (!np->io_res) { 8743 device_printf(dev, "failed to allocate IO resources\n"); 8744 goto attach_failed; 8745 } 8746 np->io_bsh = rman_get_bushandle(np->io_res); 8747 np->io_tag = rman_get_bustag(np->io_res); 8748 np->io_port = rman_get_start(np->io_res); 8749 8750 #endif /* SYM_CONF_IOMAPPED */ 8751 8752 /* 8753 * If the chip has RAM. 8754 * Alloc/get/map/retrieve the corresponding resources. 8755 */ 8756 if ((np->features & (FE_RAM|FE_RAM8K)) && 8757 (command & PCIM_CMD_MEMEN) != 0) { 8758 int regs_id = SYM_PCI_RAM; 8759 if (np->features & FE_64BIT) 8760 regs_id = SYM_PCI_RAM64; 8761 np->ram_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 8762 ®s_id, RF_ACTIVE); 8763 if (!np->ram_res) { 8764 device_printf(dev,"failed to allocate RAM resources\n"); 8765 goto attach_failed; 8766 } 8767 np->ram_id = regs_id; 8768 np->ram_bsh = rman_get_bushandle(np->ram_res); 8769 np->ram_tag = rman_get_bustag(np->ram_res); 8770 np->ram_pa = rman_get_start(np->ram_res); 8771 np->ram_va = (vm_offset_t) rman_get_virtual(np->ram_res); 8772 np->ram_ba = np->ram_pa; 8773 } 8774 8775 /* 8776 * Save setting of some IO registers, so we will 8777 * be able to probe specific implementations. 8778 */ 8779 sym_save_initial_setting (np); 8780 8781 /* 8782 * Reset the chip now, since it has been reported 8783 * that SCSI clock calibration may not work properly 8784 * if the chip is currently active. 8785 */ 8786 sym_chip_reset (np); 8787 8788 /* 8789 * Try to read the user set-up. 8790 */ 8791 (void) sym_read_nvram(np, &nvram); 8792 8793 /* 8794 * Prepare controller and devices settings, according 8795 * to chip features, user set-up and driver set-up. 8796 */ 8797 (void) sym_prepare_setting(np, &nvram); 8798 8799 /* 8800 * Check the PCI clock frequency. 8801 * Must be performed after prepare_setting since it destroys 8802 * STEST1 that is used to probe for the clock doubler. 8803 */ 8804 i = sym_getpciclock(np); 8805 if (i > 37000) 8806 device_printf(dev, "PCI BUS clock seems too high: %u KHz.\n",i); 8807 8808 /* 8809 * Allocate the start queue. 8810 */ 8811 np->squeue = (u32 *) sym_calloc_dma(sizeof(u32)*(MAX_QUEUE*2),"SQUEUE"); 8812 if (!np->squeue) 8813 goto attach_failed; 8814 np->squeue_ba = vtobus(np->squeue); 8815 8816 /* 8817 * Allocate the done queue. 8818 */ 8819 np->dqueue = (u32 *) sym_calloc_dma(sizeof(u32)*(MAX_QUEUE*2),"DQUEUE"); 8820 if (!np->dqueue) 8821 goto attach_failed; 8822 np->dqueue_ba = vtobus(np->dqueue); 8823 8824 /* 8825 * Allocate the target bus address array. 8826 */ 8827 np->targtbl = (u32 *) sym_calloc_dma(256, "TARGTBL"); 8828 if (!np->targtbl) 8829 goto attach_failed; 8830 np->targtbl_ba = vtobus(np->targtbl); 8831 8832 /* 8833 * Allocate SCRIPTS areas. 8834 */ 8835 np->scripta0 = sym_calloc_dma(np->scripta_sz, "SCRIPTA0"); 8836 np->scriptb0 = sym_calloc_dma(np->scriptb_sz, "SCRIPTB0"); 8837 if (!np->scripta0 || !np->scriptb0) 8838 goto attach_failed; 8839 8840 /* 8841 * Allocate some CCB. We need at least ONE. 8842 */ 8843 if (!sym_alloc_ccb(np)) 8844 goto attach_failed; 8845 8846 /* 8847 * Calculate BUS addresses where we are going 8848 * to load the SCRIPTS. 8849 */ 8850 np->scripta_ba = vtobus(np->scripta0); 8851 np->scriptb_ba = vtobus(np->scriptb0); 8852 np->scriptb0_ba = np->scriptb_ba; 8853 8854 if (np->ram_ba) { 8855 np->scripta_ba = np->ram_ba; 8856 if (np->features & FE_RAM8K) { 8857 np->ram_ws = 8192; 8858 np->scriptb_ba = np->scripta_ba + 4096; 8859 #ifdef __LP64__ 8860 np->scr_ram_seg = cpu_to_scr(np->scripta_ba >> 32); 8861 #endif 8862 } 8863 else 8864 np->ram_ws = 4096; 8865 } 8866 8867 /* 8868 * Copy scripts to controller instance. 8869 */ 8870 bcopy(fw->a_base, np->scripta0, np->scripta_sz); 8871 bcopy(fw->b_base, np->scriptb0, np->scriptb_sz); 8872 8873 /* 8874 * Setup variable parts in scripts and compute 8875 * scripts bus addresses used from the C code. 8876 */ 8877 np->fw_setup(np, fw); 8878 8879 /* 8880 * Bind SCRIPTS with physical addresses usable by the 8881 * SCRIPTS processor (as seen from the BUS = BUS addresses). 8882 */ 8883 sym_fw_bind_script(np, (u32 *) np->scripta0, np->scripta_sz); 8884 sym_fw_bind_script(np, (u32 *) np->scriptb0, np->scriptb_sz); 8885 8886 #ifdef SYM_CONF_IARB_SUPPORT 8887 /* 8888 * If user wants IARB to be set when we win arbitration 8889 * and have other jobs, compute the max number of consecutive 8890 * settings of IARB hints before we leave devices a chance to 8891 * arbitrate for reselection. 8892 */ 8893 #ifdef SYM_SETUP_IARB_MAX 8894 np->iarb_max = SYM_SETUP_IARB_MAX; 8895 #else 8896 np->iarb_max = 4; 8897 #endif 8898 #endif 8899 8900 /* 8901 * Prepare the idle and invalid task actions. 8902 */ 8903 np->idletask.start = cpu_to_scr(SCRIPTA_BA (np, idle)); 8904 np->idletask.restart = cpu_to_scr(SCRIPTB_BA (np, bad_i_t_l)); 8905 np->idletask_ba = vtobus(&np->idletask); 8906 8907 np->notask.start = cpu_to_scr(SCRIPTA_BA (np, idle)); 8908 np->notask.restart = cpu_to_scr(SCRIPTB_BA (np, bad_i_t_l)); 8909 np->notask_ba = vtobus(&np->notask); 8910 8911 np->bad_itl.start = cpu_to_scr(SCRIPTA_BA (np, idle)); 8912 np->bad_itl.restart = cpu_to_scr(SCRIPTB_BA (np, bad_i_t_l)); 8913 np->bad_itl_ba = vtobus(&np->bad_itl); 8914 8915 np->bad_itlq.start = cpu_to_scr(SCRIPTA_BA (np, idle)); 8916 np->bad_itlq.restart = cpu_to_scr(SCRIPTB_BA (np,bad_i_t_l_q)); 8917 np->bad_itlq_ba = vtobus(&np->bad_itlq); 8918 8919 /* 8920 * Allocate and prepare the lun JUMP table that is used 8921 * for a target prior the probing of devices (bad lun table). 8922 * A private table will be allocated for the target on the 8923 * first INQUIRY response received. 8924 */ 8925 np->badluntbl = sym_calloc_dma(256, "BADLUNTBL"); 8926 if (!np->badluntbl) 8927 goto attach_failed; 8928 8929 np->badlun_sa = cpu_to_scr(SCRIPTB_BA (np, resel_bad_lun)); 8930 for (i = 0 ; i < 64 ; i++) /* 64 luns/target, no less */ 8931 np->badluntbl[i] = cpu_to_scr(vtobus(&np->badlun_sa)); 8932 8933 /* 8934 * Prepare the bus address array that contains the bus 8935 * address of each target control block. 8936 * For now, assume all logical units are wrong. :) 8937 */ 8938 for (i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) { 8939 np->targtbl[i] = cpu_to_scr(vtobus(&np->target[i])); 8940 np->target[i].head.luntbl_sa = 8941 cpu_to_scr(vtobus(np->badluntbl)); 8942 np->target[i].head.lun0_sa = 8943 cpu_to_scr(vtobus(&np->badlun_sa)); 8944 } 8945 8946 /* 8947 * Now check the cache handling of the pci chipset. 8948 */ 8949 if (sym_snooptest (np)) { 8950 device_printf(dev, "CACHE INCORRECTLY CONFIGURED.\n"); 8951 goto attach_failed; 8952 }; 8953 8954 /* 8955 * Now deal with CAM. 8956 * Hopefully, we will succeed with that one.:) 8957 */ 8958 if (!sym_cam_attach(np)) 8959 goto attach_failed; 8960 8961 /* 8962 * Sigh! we are done. 8963 */ 8964 return 0; 8965 8966 /* 8967 * We have failed. 8968 * We will try to free all the resources we have 8969 * allocated, but if we are a boot device, this 8970 * will not help that much.;) 8971 */ 8972 attach_failed: 8973 if (np) 8974 sym_pci_free(np); 8975 return ENXIO; 8976 } 8977 8978 /* 8979 * Free everything that have been allocated for this device. 8980 */ 8981 static void sym_pci_free(hcb_p np) 8982 { 8983 SYM_QUEHEAD *qp; 8984 ccb_p cp; 8985 tcb_p tp; 8986 lcb_p lp; 8987 int target, lun; 8988 int s; 8989 8990 /* 8991 * First free CAM resources. 8992 */ 8993 s = splcam(); 8994 sym_cam_free(np); 8995 splx(s); 8996 8997 /* 8998 * Now every should be quiet for us to 8999 * free other resources. 9000 */ 9001 if (np->ram_res) 9002 bus_release_resource(np->device, SYS_RES_MEMORY, 9003 np->ram_id, np->ram_res); 9004 if (np->mmio_res) 9005 bus_release_resource(np->device, SYS_RES_MEMORY, 9006 SYM_PCI_MMIO, np->mmio_res); 9007 if (np->io_res) 9008 bus_release_resource(np->device, SYS_RES_IOPORT, 9009 SYM_PCI_IO, np->io_res); 9010 if (np->irq_res) 9011 bus_release_resource(np->device, SYS_RES_IRQ, 9012 0, np->irq_res); 9013 9014 if (np->scriptb0) 9015 sym_mfree_dma(np->scriptb0, np->scriptb_sz, "SCRIPTB0"); 9016 if (np->scripta0) 9017 sym_mfree_dma(np->scripta0, np->scripta_sz, "SCRIPTA0"); 9018 if (np->squeue) 9019 sym_mfree_dma(np->squeue, sizeof(u32)*(MAX_QUEUE*2), "SQUEUE"); 9020 if (np->dqueue) 9021 sym_mfree_dma(np->dqueue, sizeof(u32)*(MAX_QUEUE*2), "DQUEUE"); 9022 9023 while ((qp = sym_remque_head(&np->free_ccbq)) != 0) { 9024 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 9025 bus_dmamap_destroy(np->data_dmat, cp->dmamap); 9026 sym_mfree_dma(cp->sns_bbuf, SYM_SNS_BBUF_LEN, "SNS_BBUF"); 9027 sym_mfree_dma(cp, sizeof(*cp), "CCB"); 9028 } 9029 9030 if (np->badluntbl) 9031 sym_mfree_dma(np->badluntbl, 256,"BADLUNTBL"); 9032 9033 for (target = 0; target < SYM_CONF_MAX_TARGET ; target++) { 9034 tp = &np->target[target]; 9035 for (lun = 0 ; lun < SYM_CONF_MAX_LUN ; lun++) { 9036 lp = sym_lp(np, tp, lun); 9037 if (!lp) 9038 continue; 9039 if (lp->itlq_tbl) 9040 sym_mfree_dma(lp->itlq_tbl, SYM_CONF_MAX_TASK*4, 9041 "ITLQ_TBL"); 9042 if (lp->cb_tags) 9043 sym_mfree(lp->cb_tags, SYM_CONF_MAX_TASK, 9044 "CB_TAGS"); 9045 sym_mfree_dma(lp, sizeof(*lp), "LCB"); 9046 } 9047 #if SYM_CONF_MAX_LUN > 1 9048 if (tp->lunmp) 9049 sym_mfree(tp->lunmp, SYM_CONF_MAX_LUN*sizeof(lcb_p), 9050 "LUNMP"); 9051 #endif 9052 } 9053 if (np->targtbl) 9054 sym_mfree_dma(np->targtbl, 256, "TARGTBL"); 9055 if (np->data_dmat) 9056 bus_dma_tag_destroy(np->data_dmat); 9057 sym_mfree_dma(np, sizeof(*np), "HCB"); 9058 } 9059 9060 /* 9061 * Allocate CAM resources and register a bus to CAM. 9062 */ 9063 static int sym_cam_attach(hcb_p np) 9064 { 9065 struct cam_devq *devq = 0; 9066 struct cam_sim *sim = 0; 9067 struct cam_path *path = 0; 9068 struct ccb_setasync csa; 9069 int err, s; 9070 9071 s = splcam(); 9072 9073 /* 9074 * Establish our interrupt handler. 9075 */ 9076 err = bus_setup_intr(np->device, np->irq_res, 9077 INTR_TYPE_CAM | INTR_ENTROPY, sym_intr, np, 9078 &np->intr); 9079 if (err) { 9080 device_printf(np->device, "bus_setup_intr() failed: %d\n", 9081 err); 9082 goto fail; 9083 } 9084 9085 /* 9086 * Create the device queue for our sym SIM. 9087 */ 9088 devq = cam_simq_alloc(SYM_CONF_MAX_START); 9089 if (!devq) 9090 goto fail; 9091 9092 /* 9093 * Construct our SIM entry. 9094 */ 9095 sim = cam_sim_alloc(sym_action, sym_poll, "sym", np, np->unit, 9096 1, SYM_SETUP_MAX_TAG, devq); 9097 if (!sim) 9098 goto fail; 9099 devq = 0; 9100 9101 if (xpt_bus_register(sim, 0) != CAM_SUCCESS) 9102 goto fail; 9103 np->sim = sim; 9104 sim = 0; 9105 9106 if (xpt_create_path(&path, 0, 9107 cam_sim_path(np->sim), CAM_TARGET_WILDCARD, 9108 CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 9109 goto fail; 9110 } 9111 np->path = path; 9112 9113 /* 9114 * Establish our async notification handler. 9115 */ 9116 xpt_setup_ccb(&csa.ccb_h, np->path, 5); 9117 csa.ccb_h.func_code = XPT_SASYNC_CB; 9118 csa.event_enable = AC_LOST_DEVICE; 9119 csa.callback = sym_async; 9120 csa.callback_arg = np->sim; 9121 xpt_action((union ccb *)&csa); 9122 9123 /* 9124 * Start the chip now, without resetting the BUS, since 9125 * it seems that this must stay under control of CAM. 9126 * With LVD/SE capable chips and BUS in SE mode, we may 9127 * get a spurious SMBC interrupt. 9128 */ 9129 sym_init (np, 0); 9130 9131 splx(s); 9132 return 1; 9133 fail: 9134 if (sim) 9135 cam_sim_free(sim, FALSE); 9136 if (devq) 9137 cam_simq_free(devq); 9138 9139 sym_cam_free(np); 9140 9141 splx(s); 9142 return 0; 9143 } 9144 9145 /* 9146 * Free everything that deals with CAM. 9147 */ 9148 static void sym_cam_free(hcb_p np) 9149 { 9150 if (np->intr) { 9151 bus_teardown_intr(np->device, np->irq_res, np->intr); 9152 np->intr = NULL; 9153 } 9154 9155 if (np->sim) { 9156 xpt_bus_deregister(cam_sim_path(np->sim)); 9157 cam_sim_free(np->sim, /*free_devq*/ TRUE); 9158 np->sim = NULL; 9159 } 9160 if (np->path) { 9161 xpt_free_path(np->path); 9162 np->path = NULL; 9163 } 9164 } 9165 9166 /*============ OPTIONNAL NVRAM SUPPORT =================*/ 9167 9168 /* 9169 * Get host setup from NVRAM. 9170 */ 9171 static void sym_nvram_setup_host (hcb_p np, struct sym_nvram *nvram) 9172 { 9173 #ifdef SYM_CONF_NVRAM_SUPPORT 9174 /* 9175 * Get parity checking, host ID, verbose mode 9176 * and miscellaneous host flags from NVRAM. 9177 */ 9178 switch(nvram->type) { 9179 case SYM_SYMBIOS_NVRAM: 9180 if (!(nvram->data.Symbios.flags & SYMBIOS_PARITY_ENABLE)) 9181 np->rv_scntl0 &= ~0x0a; 9182 np->myaddr = nvram->data.Symbios.host_id & 0x0f; 9183 if (nvram->data.Symbios.flags & SYMBIOS_VERBOSE_MSGS) 9184 np->verbose += 1; 9185 if (nvram->data.Symbios.flags1 & SYMBIOS_SCAN_HI_LO) 9186 np->usrflags |= SYM_SCAN_TARGETS_HILO; 9187 if (nvram->data.Symbios.flags2 & SYMBIOS_AVOID_BUS_RESET) 9188 np->usrflags |= SYM_AVOID_BUS_RESET; 9189 break; 9190 case SYM_TEKRAM_NVRAM: 9191 np->myaddr = nvram->data.Tekram.host_id & 0x0f; 9192 break; 9193 default: 9194 break; 9195 } 9196 #endif 9197 } 9198 9199 /* 9200 * Get target setup from NVRAM. 9201 */ 9202 #ifdef SYM_CONF_NVRAM_SUPPORT 9203 static void sym_Symbios_setup_target(hcb_p np,int target, Symbios_nvram *nvram); 9204 static void sym_Tekram_setup_target(hcb_p np,int target, Tekram_nvram *nvram); 9205 #endif 9206 9207 static void 9208 sym_nvram_setup_target (hcb_p np, int target, struct sym_nvram *nvp) 9209 { 9210 #ifdef SYM_CONF_NVRAM_SUPPORT 9211 switch(nvp->type) { 9212 case SYM_SYMBIOS_NVRAM: 9213 sym_Symbios_setup_target (np, target, &nvp->data.Symbios); 9214 break; 9215 case SYM_TEKRAM_NVRAM: 9216 sym_Tekram_setup_target (np, target, &nvp->data.Tekram); 9217 break; 9218 default: 9219 break; 9220 } 9221 #endif 9222 } 9223 9224 #ifdef SYM_CONF_NVRAM_SUPPORT 9225 /* 9226 * Get target set-up from Symbios format NVRAM. 9227 */ 9228 static void 9229 sym_Symbios_setup_target(hcb_p np, int target, Symbios_nvram *nvram) 9230 { 9231 tcb_p tp = &np->target[target]; 9232 Symbios_target *tn = &nvram->target[target]; 9233 9234 tp->tinfo.user.period = tn->sync_period ? (tn->sync_period + 3) / 4 : 0; 9235 tp->tinfo.user.width = tn->bus_width == 0x10 ? BUS_16_BIT : BUS_8_BIT; 9236 tp->usrtags = 9237 (tn->flags & SYMBIOS_QUEUE_TAGS_ENABLED)? SYM_SETUP_MAX_TAG : 0; 9238 9239 if (!(tn->flags & SYMBIOS_DISCONNECT_ENABLE)) 9240 tp->usrflags &= ~SYM_DISC_ENABLED; 9241 if (!(tn->flags & SYMBIOS_SCAN_AT_BOOT_TIME)) 9242 tp->usrflags |= SYM_SCAN_BOOT_DISABLED; 9243 if (!(tn->flags & SYMBIOS_SCAN_LUNS)) 9244 tp->usrflags |= SYM_SCAN_LUNS_DISABLED; 9245 } 9246 9247 /* 9248 * Get target set-up from Tekram format NVRAM. 9249 */ 9250 static void 9251 sym_Tekram_setup_target(hcb_p np, int target, Tekram_nvram *nvram) 9252 { 9253 tcb_p tp = &np->target[target]; 9254 struct Tekram_target *tn = &nvram->target[target]; 9255 int i; 9256 9257 if (tn->flags & TEKRAM_SYNC_NEGO) { 9258 i = tn->sync_index & 0xf; 9259 tp->tinfo.user.period = Tekram_sync[i]; 9260 } 9261 9262 tp->tinfo.user.width = 9263 (tn->flags & TEKRAM_WIDE_NEGO) ? BUS_16_BIT : BUS_8_BIT; 9264 9265 if (tn->flags & TEKRAM_TAGGED_COMMANDS) { 9266 tp->usrtags = 2 << nvram->max_tags_index; 9267 } 9268 9269 if (tn->flags & TEKRAM_DISCONNECT_ENABLE) 9270 tp->usrflags |= SYM_DISC_ENABLED; 9271 9272 /* If any device does not support parity, we will not use this option */ 9273 if (!(tn->flags & TEKRAM_PARITY_CHECK)) 9274 np->rv_scntl0 &= ~0x0a; /* SCSI parity checking disabled */ 9275 } 9276 9277 #ifdef SYM_CONF_DEBUG_NVRAM 9278 /* 9279 * Dump Symbios format NVRAM for debugging purpose. 9280 */ 9281 static void sym_display_Symbios_nvram(hcb_p np, Symbios_nvram *nvram) 9282 { 9283 int i; 9284 9285 /* display Symbios nvram host data */ 9286 printf("%s: HOST ID=%d%s%s%s%s%s%s\n", 9287 sym_name(np), nvram->host_id & 0x0f, 9288 (nvram->flags & SYMBIOS_SCAM_ENABLE) ? " SCAM" :"", 9289 (nvram->flags & SYMBIOS_PARITY_ENABLE) ? " PARITY" :"", 9290 (nvram->flags & SYMBIOS_VERBOSE_MSGS) ? " VERBOSE" :"", 9291 (nvram->flags & SYMBIOS_CHS_MAPPING) ? " CHS_ALT" :"", 9292 (nvram->flags2 & SYMBIOS_AVOID_BUS_RESET)?" NO_RESET" :"", 9293 (nvram->flags1 & SYMBIOS_SCAN_HI_LO) ? " HI_LO" :""); 9294 9295 /* display Symbios nvram drive data */ 9296 for (i = 0 ; i < 15 ; i++) { 9297 struct Symbios_target *tn = &nvram->target[i]; 9298 printf("%s-%d:%s%s%s%s WIDTH=%d SYNC=%d TMO=%d\n", 9299 sym_name(np), i, 9300 (tn->flags & SYMBIOS_DISCONNECT_ENABLE) ? " DISC" : "", 9301 (tn->flags & SYMBIOS_SCAN_AT_BOOT_TIME) ? " SCAN_BOOT" : "", 9302 (tn->flags & SYMBIOS_SCAN_LUNS) ? " SCAN_LUNS" : "", 9303 (tn->flags & SYMBIOS_QUEUE_TAGS_ENABLED)? " TCQ" : "", 9304 tn->bus_width, 9305 tn->sync_period / 4, 9306 tn->timeout); 9307 } 9308 } 9309 9310 /* 9311 * Dump TEKRAM format NVRAM for debugging purpose. 9312 */ 9313 static u_char Tekram_boot_delay[7] = {3, 5, 10, 20, 30, 60, 120}; 9314 static void sym_display_Tekram_nvram(hcb_p np, Tekram_nvram *nvram) 9315 { 9316 int i, tags, boot_delay; 9317 char *rem; 9318 9319 /* display Tekram nvram host data */ 9320 tags = 2 << nvram->max_tags_index; 9321 boot_delay = 0; 9322 if (nvram->boot_delay_index < 6) 9323 boot_delay = Tekram_boot_delay[nvram->boot_delay_index]; 9324 switch((nvram->flags & TEKRAM_REMOVABLE_FLAGS) >> 6) { 9325 default: 9326 case 0: rem = ""; break; 9327 case 1: rem = " REMOVABLE=boot device"; break; 9328 case 2: rem = " REMOVABLE=all"; break; 9329 } 9330 9331 printf("%s: HOST ID=%d%s%s%s%s%s%s%s%s%s BOOT DELAY=%d tags=%d\n", 9332 sym_name(np), nvram->host_id & 0x0f, 9333 (nvram->flags1 & SYMBIOS_SCAM_ENABLE) ? " SCAM" :"", 9334 (nvram->flags & TEKRAM_MORE_THAN_2_DRIVES) ? " >2DRIVES" :"", 9335 (nvram->flags & TEKRAM_DRIVES_SUP_1GB) ? " >1GB" :"", 9336 (nvram->flags & TEKRAM_RESET_ON_POWER_ON) ? " RESET" :"", 9337 (nvram->flags & TEKRAM_ACTIVE_NEGATION) ? " ACT_NEG" :"", 9338 (nvram->flags & TEKRAM_IMMEDIATE_SEEK) ? " IMM_SEEK" :"", 9339 (nvram->flags & TEKRAM_SCAN_LUNS) ? " SCAN_LUNS" :"", 9340 (nvram->flags1 & TEKRAM_F2_F6_ENABLED) ? " F2_F6" :"", 9341 rem, boot_delay, tags); 9342 9343 /* display Tekram nvram drive data */ 9344 for (i = 0; i <= 15; i++) { 9345 int sync, j; 9346 struct Tekram_target *tn = &nvram->target[i]; 9347 j = tn->sync_index & 0xf; 9348 sync = Tekram_sync[j]; 9349 printf("%s-%d:%s%s%s%s%s%s PERIOD=%d\n", 9350 sym_name(np), i, 9351 (tn->flags & TEKRAM_PARITY_CHECK) ? " PARITY" : "", 9352 (tn->flags & TEKRAM_SYNC_NEGO) ? " SYNC" : "", 9353 (tn->flags & TEKRAM_DISCONNECT_ENABLE) ? " DISC" : "", 9354 (tn->flags & TEKRAM_START_CMD) ? " START" : "", 9355 (tn->flags & TEKRAM_TAGGED_COMMANDS) ? " TCQ" : "", 9356 (tn->flags & TEKRAM_WIDE_NEGO) ? " WIDE" : "", 9357 sync); 9358 } 9359 } 9360 #endif /* SYM_CONF_DEBUG_NVRAM */ 9361 #endif /* SYM_CONF_NVRAM_SUPPORT */ 9362 9363 9364 /* 9365 * Try reading Symbios or Tekram NVRAM 9366 */ 9367 #ifdef SYM_CONF_NVRAM_SUPPORT 9368 static int sym_read_Symbios_nvram (hcb_p np, Symbios_nvram *nvram); 9369 static int sym_read_Tekram_nvram (hcb_p np, Tekram_nvram *nvram); 9370 #endif 9371 9372 static int sym_read_nvram(hcb_p np, struct sym_nvram *nvp) 9373 { 9374 #ifdef SYM_CONF_NVRAM_SUPPORT 9375 /* 9376 * Try to read SYMBIOS nvram. 9377 * Try to read TEKRAM nvram if Symbios nvram not found. 9378 */ 9379 if (SYM_SETUP_SYMBIOS_NVRAM && 9380 !sym_read_Symbios_nvram (np, &nvp->data.Symbios)) { 9381 nvp->type = SYM_SYMBIOS_NVRAM; 9382 #ifdef SYM_CONF_DEBUG_NVRAM 9383 sym_display_Symbios_nvram(np, &nvp->data.Symbios); 9384 #endif 9385 } 9386 else if (SYM_SETUP_TEKRAM_NVRAM && 9387 !sym_read_Tekram_nvram (np, &nvp->data.Tekram)) { 9388 nvp->type = SYM_TEKRAM_NVRAM; 9389 #ifdef SYM_CONF_DEBUG_NVRAM 9390 sym_display_Tekram_nvram(np, &nvp->data.Tekram); 9391 #endif 9392 } 9393 else 9394 nvp->type = 0; 9395 #else 9396 nvp->type = 0; 9397 #endif 9398 return nvp->type; 9399 } 9400 9401 9402 #ifdef SYM_CONF_NVRAM_SUPPORT 9403 /* 9404 * 24C16 EEPROM reading. 9405 * 9406 * GPOI0 - data in/data out 9407 * GPIO1 - clock 9408 * Symbios NVRAM wiring now also used by Tekram. 9409 */ 9410 9411 #define SET_BIT 0 9412 #define CLR_BIT 1 9413 #define SET_CLK 2 9414 #define CLR_CLK 3 9415 9416 /* 9417 * Set/clear data/clock bit in GPIO0 9418 */ 9419 static void S24C16_set_bit(hcb_p np, u_char write_bit, u_char *gpreg, 9420 int bit_mode) 9421 { 9422 UDELAY (5); 9423 switch (bit_mode){ 9424 case SET_BIT: 9425 *gpreg |= write_bit; 9426 break; 9427 case CLR_BIT: 9428 *gpreg &= 0xfe; 9429 break; 9430 case SET_CLK: 9431 *gpreg |= 0x02; 9432 break; 9433 case CLR_CLK: 9434 *gpreg &= 0xfd; 9435 break; 9436 9437 } 9438 OUTB (nc_gpreg, *gpreg); 9439 UDELAY (5); 9440 } 9441 9442 /* 9443 * Send START condition to NVRAM to wake it up. 9444 */ 9445 static void S24C16_start(hcb_p np, u_char *gpreg) 9446 { 9447 S24C16_set_bit(np, 1, gpreg, SET_BIT); 9448 S24C16_set_bit(np, 0, gpreg, SET_CLK); 9449 S24C16_set_bit(np, 0, gpreg, CLR_BIT); 9450 S24C16_set_bit(np, 0, gpreg, CLR_CLK); 9451 } 9452 9453 /* 9454 * Send STOP condition to NVRAM - puts NVRAM to sleep... ZZzzzz!! 9455 */ 9456 static void S24C16_stop(hcb_p np, u_char *gpreg) 9457 { 9458 S24C16_set_bit(np, 0, gpreg, SET_CLK); 9459 S24C16_set_bit(np, 1, gpreg, SET_BIT); 9460 } 9461 9462 /* 9463 * Read or write a bit to the NVRAM, 9464 * read if GPIO0 input else write if GPIO0 output 9465 */ 9466 static void S24C16_do_bit(hcb_p np, u_char *read_bit, u_char write_bit, 9467 u_char *gpreg) 9468 { 9469 S24C16_set_bit(np, write_bit, gpreg, SET_BIT); 9470 S24C16_set_bit(np, 0, gpreg, SET_CLK); 9471 if (read_bit) 9472 *read_bit = INB (nc_gpreg); 9473 S24C16_set_bit(np, 0, gpreg, CLR_CLK); 9474 S24C16_set_bit(np, 0, gpreg, CLR_BIT); 9475 } 9476 9477 /* 9478 * Output an ACK to the NVRAM after reading, 9479 * change GPIO0 to output and when done back to an input 9480 */ 9481 static void S24C16_write_ack(hcb_p np, u_char write_bit, u_char *gpreg, 9482 u_char *gpcntl) 9483 { 9484 OUTB (nc_gpcntl, *gpcntl & 0xfe); 9485 S24C16_do_bit(np, 0, write_bit, gpreg); 9486 OUTB (nc_gpcntl, *gpcntl); 9487 } 9488 9489 /* 9490 * Input an ACK from NVRAM after writing, 9491 * change GPIO0 to input and when done back to an output 9492 */ 9493 static void S24C16_read_ack(hcb_p np, u_char *read_bit, u_char *gpreg, 9494 u_char *gpcntl) 9495 { 9496 OUTB (nc_gpcntl, *gpcntl | 0x01); 9497 S24C16_do_bit(np, read_bit, 1, gpreg); 9498 OUTB (nc_gpcntl, *gpcntl); 9499 } 9500 9501 /* 9502 * WRITE a byte to the NVRAM and then get an ACK to see it was accepted OK, 9503 * GPIO0 must already be set as an output 9504 */ 9505 static void S24C16_write_byte(hcb_p np, u_char *ack_data, u_char write_data, 9506 u_char *gpreg, u_char *gpcntl) 9507 { 9508 int x; 9509 9510 for (x = 0; x < 8; x++) 9511 S24C16_do_bit(np, 0, (write_data >> (7 - x)) & 0x01, gpreg); 9512 9513 S24C16_read_ack(np, ack_data, gpreg, gpcntl); 9514 } 9515 9516 /* 9517 * READ a byte from the NVRAM and then send an ACK to say we have got it, 9518 * GPIO0 must already be set as an input 9519 */ 9520 static void S24C16_read_byte(hcb_p np, u_char *read_data, u_char ack_data, 9521 u_char *gpreg, u_char *gpcntl) 9522 { 9523 int x; 9524 u_char read_bit; 9525 9526 *read_data = 0; 9527 for (x = 0; x < 8; x++) { 9528 S24C16_do_bit(np, &read_bit, 1, gpreg); 9529 *read_data |= ((read_bit & 0x01) << (7 - x)); 9530 } 9531 9532 S24C16_write_ack(np, ack_data, gpreg, gpcntl); 9533 } 9534 9535 /* 9536 * Read 'len' bytes starting at 'offset'. 9537 */ 9538 static int sym_read_S24C16_nvram (hcb_p np, int offset, u_char *data, int len) 9539 { 9540 u_char gpcntl, gpreg; 9541 u_char old_gpcntl, old_gpreg; 9542 u_char ack_data; 9543 int retv = 1; 9544 int x; 9545 9546 /* save current state of GPCNTL and GPREG */ 9547 old_gpreg = INB (nc_gpreg); 9548 old_gpcntl = INB (nc_gpcntl); 9549 gpcntl = old_gpcntl & 0x1c; 9550 9551 /* set up GPREG & GPCNTL to set GPIO0 and GPIO1 in to known state */ 9552 OUTB (nc_gpreg, old_gpreg); 9553 OUTB (nc_gpcntl, gpcntl); 9554 9555 /* this is to set NVRAM into a known state with GPIO0/1 both low */ 9556 gpreg = old_gpreg; 9557 S24C16_set_bit(np, 0, &gpreg, CLR_CLK); 9558 S24C16_set_bit(np, 0, &gpreg, CLR_BIT); 9559 9560 /* now set NVRAM inactive with GPIO0/1 both high */ 9561 S24C16_stop(np, &gpreg); 9562 9563 /* activate NVRAM */ 9564 S24C16_start(np, &gpreg); 9565 9566 /* write device code and random address MSB */ 9567 S24C16_write_byte(np, &ack_data, 9568 0xa0 | ((offset >> 7) & 0x0e), &gpreg, &gpcntl); 9569 if (ack_data & 0x01) 9570 goto out; 9571 9572 /* write random address LSB */ 9573 S24C16_write_byte(np, &ack_data, 9574 offset & 0xff, &gpreg, &gpcntl); 9575 if (ack_data & 0x01) 9576 goto out; 9577 9578 /* regenerate START state to set up for reading */ 9579 S24C16_start(np, &gpreg); 9580 9581 /* rewrite device code and address MSB with read bit set (lsb = 0x01) */ 9582 S24C16_write_byte(np, &ack_data, 9583 0xa1 | ((offset >> 7) & 0x0e), &gpreg, &gpcntl); 9584 if (ack_data & 0x01) 9585 goto out; 9586 9587 /* now set up GPIO0 for inputting data */ 9588 gpcntl |= 0x01; 9589 OUTB (nc_gpcntl, gpcntl); 9590 9591 /* input all requested data - only part of total NVRAM */ 9592 for (x = 0; x < len; x++) 9593 S24C16_read_byte(np, &data[x], (x == (len-1)), &gpreg, &gpcntl); 9594 9595 /* finally put NVRAM back in inactive mode */ 9596 gpcntl &= 0xfe; 9597 OUTB (nc_gpcntl, gpcntl); 9598 S24C16_stop(np, &gpreg); 9599 retv = 0; 9600 out: 9601 /* return GPIO0/1 to original states after having accessed NVRAM */ 9602 OUTB (nc_gpcntl, old_gpcntl); 9603 OUTB (nc_gpreg, old_gpreg); 9604 9605 return retv; 9606 } 9607 9608 #undef SET_BIT /* 0 */ 9609 #undef CLR_BIT /* 1 */ 9610 #undef SET_CLK /* 2 */ 9611 #undef CLR_CLK /* 3 */ 9612 9613 /* 9614 * Try reading Symbios NVRAM. 9615 * Return 0 if OK. 9616 */ 9617 static int sym_read_Symbios_nvram (hcb_p np, Symbios_nvram *nvram) 9618 { 9619 static u_char Symbios_trailer[6] = {0xfe, 0xfe, 0, 0, 0, 0}; 9620 u_char *data = (u_char *) nvram; 9621 int len = sizeof(*nvram); 9622 u_short csum; 9623 int x; 9624 9625 /* probe the 24c16 and read the SYMBIOS 24c16 area */ 9626 if (sym_read_S24C16_nvram (np, SYMBIOS_NVRAM_ADDRESS, data, len)) 9627 return 1; 9628 9629 /* check valid NVRAM signature, verify byte count and checksum */ 9630 if (nvram->type != 0 || 9631 bcmp(nvram->trailer, Symbios_trailer, 6) || 9632 nvram->byte_count != len - 12) 9633 return 1; 9634 9635 /* verify checksum */ 9636 for (x = 6, csum = 0; x < len - 6; x++) 9637 csum += data[x]; 9638 if (csum != nvram->checksum) 9639 return 1; 9640 9641 return 0; 9642 } 9643 9644 /* 9645 * 93C46 EEPROM reading. 9646 * 9647 * GPOI0 - data in 9648 * GPIO1 - data out 9649 * GPIO2 - clock 9650 * GPIO4 - chip select 9651 * 9652 * Used by Tekram. 9653 */ 9654 9655 /* 9656 * Pulse clock bit in GPIO0 9657 */ 9658 static void T93C46_Clk(hcb_p np, u_char *gpreg) 9659 { 9660 OUTB (nc_gpreg, *gpreg | 0x04); 9661 UDELAY (2); 9662 OUTB (nc_gpreg, *gpreg); 9663 } 9664 9665 /* 9666 * Read bit from NVRAM 9667 */ 9668 static void T93C46_Read_Bit(hcb_p np, u_char *read_bit, u_char *gpreg) 9669 { 9670 UDELAY (2); 9671 T93C46_Clk(np, gpreg); 9672 *read_bit = INB (nc_gpreg); 9673 } 9674 9675 /* 9676 * Write bit to GPIO0 9677 */ 9678 static void T93C46_Write_Bit(hcb_p np, u_char write_bit, u_char *gpreg) 9679 { 9680 if (write_bit & 0x01) 9681 *gpreg |= 0x02; 9682 else 9683 *gpreg &= 0xfd; 9684 9685 *gpreg |= 0x10; 9686 9687 OUTB (nc_gpreg, *gpreg); 9688 UDELAY (2); 9689 9690 T93C46_Clk(np, gpreg); 9691 } 9692 9693 /* 9694 * Send STOP condition to NVRAM - puts NVRAM to sleep... ZZZzzz!! 9695 */ 9696 static void T93C46_Stop(hcb_p np, u_char *gpreg) 9697 { 9698 *gpreg &= 0xef; 9699 OUTB (nc_gpreg, *gpreg); 9700 UDELAY (2); 9701 9702 T93C46_Clk(np, gpreg); 9703 } 9704 9705 /* 9706 * Send read command and address to NVRAM 9707 */ 9708 static void T93C46_Send_Command(hcb_p np, u_short write_data, 9709 u_char *read_bit, u_char *gpreg) 9710 { 9711 int x; 9712 9713 /* send 9 bits, start bit (1), command (2), address (6) */ 9714 for (x = 0; x < 9; x++) 9715 T93C46_Write_Bit(np, (u_char) (write_data >> (8 - x)), gpreg); 9716 9717 *read_bit = INB (nc_gpreg); 9718 } 9719 9720 /* 9721 * READ 2 bytes from the NVRAM 9722 */ 9723 static void T93C46_Read_Word(hcb_p np, u_short *nvram_data, u_char *gpreg) 9724 { 9725 int x; 9726 u_char read_bit; 9727 9728 *nvram_data = 0; 9729 for (x = 0; x < 16; x++) { 9730 T93C46_Read_Bit(np, &read_bit, gpreg); 9731 9732 if (read_bit & 0x01) 9733 *nvram_data |= (0x01 << (15 - x)); 9734 else 9735 *nvram_data &= ~(0x01 << (15 - x)); 9736 } 9737 } 9738 9739 /* 9740 * Read Tekram NvRAM data. 9741 */ 9742 static int T93C46_Read_Data(hcb_p np, u_short *data,int len,u_char *gpreg) 9743 { 9744 u_char read_bit; 9745 int x; 9746 9747 for (x = 0; x < len; x++) { 9748 9749 /* output read command and address */ 9750 T93C46_Send_Command(np, 0x180 | x, &read_bit, gpreg); 9751 if (read_bit & 0x01) 9752 return 1; /* Bad */ 9753 T93C46_Read_Word(np, &data[x], gpreg); 9754 T93C46_Stop(np, gpreg); 9755 } 9756 9757 return 0; 9758 } 9759 9760 /* 9761 * Try reading 93C46 Tekram NVRAM. 9762 */ 9763 static int sym_read_T93C46_nvram (hcb_p np, Tekram_nvram *nvram) 9764 { 9765 u_char gpcntl, gpreg; 9766 u_char old_gpcntl, old_gpreg; 9767 int retv = 1; 9768 9769 /* save current state of GPCNTL and GPREG */ 9770 old_gpreg = INB (nc_gpreg); 9771 old_gpcntl = INB (nc_gpcntl); 9772 9773 /* set up GPREG & GPCNTL to set GPIO0/1/2/4 in to known state, 0 in, 9774 1/2/4 out */ 9775 gpreg = old_gpreg & 0xe9; 9776 OUTB (nc_gpreg, gpreg); 9777 gpcntl = (old_gpcntl & 0xe9) | 0x09; 9778 OUTB (nc_gpcntl, gpcntl); 9779 9780 /* input all of NVRAM, 64 words */ 9781 retv = T93C46_Read_Data(np, (u_short *) nvram, 9782 sizeof(*nvram) / sizeof(short), &gpreg); 9783 9784 /* return GPIO0/1/2/4 to original states after having accessed NVRAM */ 9785 OUTB (nc_gpcntl, old_gpcntl); 9786 OUTB (nc_gpreg, old_gpreg); 9787 9788 return retv; 9789 } 9790 9791 /* 9792 * Try reading Tekram NVRAM. 9793 * Return 0 if OK. 9794 */ 9795 static int sym_read_Tekram_nvram (hcb_p np, Tekram_nvram *nvram) 9796 { 9797 u_char *data = (u_char *) nvram; 9798 int len = sizeof(*nvram); 9799 u_short csum; 9800 int x; 9801 9802 switch (np->device_id) { 9803 case PCI_ID_SYM53C885: 9804 case PCI_ID_SYM53C895: 9805 case PCI_ID_SYM53C896: 9806 x = sym_read_S24C16_nvram(np, TEKRAM_24C16_NVRAM_ADDRESS, 9807 data, len); 9808 break; 9809 case PCI_ID_SYM53C875: 9810 x = sym_read_S24C16_nvram(np, TEKRAM_24C16_NVRAM_ADDRESS, 9811 data, len); 9812 if (!x) 9813 break; 9814 default: 9815 x = sym_read_T93C46_nvram(np, nvram); 9816 break; 9817 } 9818 if (x) 9819 return 1; 9820 9821 /* verify checksum */ 9822 for (x = 0, csum = 0; x < len - 1; x += 2) 9823 csum += data[x] + (data[x+1] << 8); 9824 if (csum != 0x1234) 9825 return 1; 9826 9827 return 0; 9828 } 9829 9830 #endif /* SYM_CONF_NVRAM_SUPPORT */ 9831