1 /*- 2 * Device driver optimized for the Symbios/LSI 53C896/53C895A/53C1010 3 * PCI-SCSI controllers. 4 * 5 * Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr> 6 * 7 * This driver also supports the following Symbios/LSI PCI-SCSI chips: 8 * 53C810A, 53C825A, 53C860, 53C875, 53C876, 53C885, 53C895, 9 * 53C810, 53C815, 53C825 and the 53C1510D is 53C8XX mode. 10 * 11 * 12 * This driver for FreeBSD-CAM is derived from the Linux sym53c8xx driver. 13 * Copyright (C) 1998-1999 Gerard Roudier 14 * 15 * The sym53c8xx driver is derived from the ncr53c8xx driver that had been 16 * a port of the FreeBSD ncr driver to Linux-1.2.13. 17 * 18 * The original ncr driver has been written for 386bsd and FreeBSD by 19 * Wolfgang Stanglmeier <wolf@cologne.de> 20 * Stefan Esser <se@mi.Uni-Koeln.de> 21 * Copyright (C) 1994 Wolfgang Stanglmeier 22 * 23 * The initialisation code, and part of the code that addresses 24 * FreeBSD-CAM services is based on the aic7xxx driver for FreeBSD-CAM 25 * written by Justin T. Gibbs. 26 * 27 * Other major contributions: 28 * 29 * NVRAM detection and reading. 30 * Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk> 31 * 32 *----------------------------------------------------------------------------- 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 3. The name of the author may not be used to endorse or promote products 43 * derived from this software without specific prior written permission. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 49 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 __FBSDID("$FreeBSD$"); 60 61 #define SYM_DRIVER_NAME "sym-1.6.5-20000902" 62 63 /* #define SYM_DEBUG_GENERIC_SUPPORT */ 64 65 #include <sys/param.h> 66 67 /* 68 * Driver configuration options. 69 */ 70 #include "opt_sym.h" 71 #include <dev/sym/sym_conf.h> 72 73 74 #include <sys/systm.h> 75 #include <sys/malloc.h> 76 #include <sys/endian.h> 77 #include <sys/kernel.h> 78 #include <sys/lock.h> 79 #include <sys/mutex.h> 80 #include <sys/module.h> 81 #include <sys/bus.h> 82 83 #include <sys/proc.h> 84 85 #include <dev/pci/pcireg.h> 86 #include <dev/pci/pcivar.h> 87 88 #include <machine/bus.h> 89 #include <machine/resource.h> 90 #include <sys/rman.h> 91 92 #include <cam/cam.h> 93 #include <cam/cam_ccb.h> 94 #include <cam/cam_sim.h> 95 #include <cam/cam_xpt_sim.h> 96 #include <cam/cam_debug.h> 97 98 #include <cam/scsi/scsi_all.h> 99 #include <cam/scsi/scsi_message.h> 100 101 #include <vm/vm.h> 102 #include <vm/vm_param.h> 103 #include <vm/pmap.h> 104 105 /* Short and quite clear integer types */ 106 typedef int8_t s8; 107 typedef int16_t s16; 108 typedef int32_t s32; 109 typedef u_int8_t u8; 110 typedef u_int16_t u16; 111 typedef u_int32_t u32; 112 113 /* 114 * Driver definitions. 115 */ 116 #include <dev/sym/sym_defs.h> 117 #include <dev/sym/sym_fw.h> 118 119 /* 120 * IA32 architecture does not reorder STORES and prevents 121 * LOADS from passing STORES. It is called `program order' 122 * by Intel and allows device drivers to deal with memory 123 * ordering by only ensuring that the code is not reordered 124 * by the compiler when ordering is required. 125 * Other architectures implement a weaker ordering that 126 * requires memory barriers (and also IO barriers when they 127 * make sense) to be used. 128 */ 129 130 #if defined __i386__ || defined __amd64__ 131 #define MEMORY_BARRIER() do { ; } while(0) 132 #elif defined __powerpc__ 133 #define MEMORY_BARRIER() __asm__ volatile("eieio; sync" : : : "memory") 134 #elif defined __ia64__ 135 #define MEMORY_BARRIER() __asm__ volatile("mf.a; mf" : : : "memory") 136 #elif defined __sparc64__ 137 #define MEMORY_BARRIER() __asm__ volatile("membar #Sync" : : : "memory") 138 #else 139 #error "Not supported platform" 140 #endif 141 142 /* 143 * A la VMS/CAM-3 queue management. 144 */ 145 146 typedef struct sym_quehead { 147 struct sym_quehead *flink; /* Forward pointer */ 148 struct sym_quehead *blink; /* Backward pointer */ 149 } SYM_QUEHEAD; 150 151 #define sym_que_init(ptr) do { \ 152 (ptr)->flink = (ptr); (ptr)->blink = (ptr); \ 153 } while (0) 154 155 static __inline struct sym_quehead *sym_que_first(struct sym_quehead *head) 156 { 157 return (head->flink == head) ? 0 : head->flink; 158 } 159 160 static __inline struct sym_quehead *sym_que_last(struct sym_quehead *head) 161 { 162 return (head->blink == head) ? 0 : head->blink; 163 } 164 165 static __inline void __sym_que_add(struct sym_quehead * new, 166 struct sym_quehead * blink, 167 struct sym_quehead * flink) 168 { 169 flink->blink = new; 170 new->flink = flink; 171 new->blink = blink; 172 blink->flink = new; 173 } 174 175 static __inline void __sym_que_del(struct sym_quehead * blink, 176 struct sym_quehead * flink) 177 { 178 flink->blink = blink; 179 blink->flink = flink; 180 } 181 182 static __inline int sym_que_empty(struct sym_quehead *head) 183 { 184 return head->flink == head; 185 } 186 187 static __inline void sym_que_splice(struct sym_quehead *list, 188 struct sym_quehead *head) 189 { 190 struct sym_quehead *first = list->flink; 191 192 if (first != list) { 193 struct sym_quehead *last = list->blink; 194 struct sym_quehead *at = head->flink; 195 196 first->blink = head; 197 head->flink = first; 198 199 last->flink = at; 200 at->blink = last; 201 } 202 } 203 204 #define sym_que_entry(ptr, type, member) \ 205 ((type *)((char *)(ptr)-(unsigned int)(&((type *)0)->member))) 206 207 208 #define sym_insque(new, pos) __sym_que_add(new, pos, (pos)->flink) 209 210 #define sym_remque(el) __sym_que_del((el)->blink, (el)->flink) 211 212 #define sym_insque_head(new, head) __sym_que_add(new, head, (head)->flink) 213 214 static __inline struct sym_quehead *sym_remque_head(struct sym_quehead *head) 215 { 216 struct sym_quehead *elem = head->flink; 217 218 if (elem != head) 219 __sym_que_del(head, elem->flink); 220 else 221 elem = 0; 222 return elem; 223 } 224 225 #define sym_insque_tail(new, head) __sym_que_add(new, (head)->blink, head) 226 227 static __inline struct sym_quehead *sym_remque_tail(struct sym_quehead *head) 228 { 229 struct sym_quehead *elem = head->blink; 230 231 if (elem != head) 232 __sym_que_del(elem->blink, head); 233 else 234 elem = 0; 235 return elem; 236 } 237 238 /* 239 * This one may be useful. 240 */ 241 #define FOR_EACH_QUEUED_ELEMENT(head, qp) \ 242 for (qp = (head)->flink; qp != (head); qp = qp->flink) 243 /* 244 * FreeBSD does not offer our kind of queue in the CAM CCB. 245 * So, we have to cast. 246 */ 247 #define sym_qptr(p) ((struct sym_quehead *) (p)) 248 249 /* 250 * Simple bitmap operations. 251 */ 252 #define sym_set_bit(p, n) (((u32 *)(p))[(n)>>5] |= (1<<((n)&0x1f))) 253 #define sym_clr_bit(p, n) (((u32 *)(p))[(n)>>5] &= ~(1<<((n)&0x1f))) 254 #define sym_is_bit(p, n) (((u32 *)(p))[(n)>>5] & (1<<((n)&0x1f))) 255 256 /* 257 * Number of tasks per device we want to handle. 258 */ 259 #if SYM_CONF_MAX_TAG_ORDER > 8 260 #error "more than 256 tags per logical unit not allowed." 261 #endif 262 #define SYM_CONF_MAX_TASK (1<<SYM_CONF_MAX_TAG_ORDER) 263 264 /* 265 * Donnot use more tasks that we can handle. 266 */ 267 #ifndef SYM_CONF_MAX_TAG 268 #define SYM_CONF_MAX_TAG SYM_CONF_MAX_TASK 269 #endif 270 #if SYM_CONF_MAX_TAG > SYM_CONF_MAX_TASK 271 #undef SYM_CONF_MAX_TAG 272 #define SYM_CONF_MAX_TAG SYM_CONF_MAX_TASK 273 #endif 274 275 /* 276 * This one means 'NO TAG for this job' 277 */ 278 #define NO_TAG (256) 279 280 /* 281 * Number of SCSI targets. 282 */ 283 #if SYM_CONF_MAX_TARGET > 16 284 #error "more than 16 targets not allowed." 285 #endif 286 287 /* 288 * Number of logical units per target. 289 */ 290 #if SYM_CONF_MAX_LUN > 64 291 #error "more than 64 logical units per target not allowed." 292 #endif 293 294 /* 295 * Asynchronous pre-scaler (ns). Shall be 40 for 296 * the SCSI timings to be compliant. 297 */ 298 #define SYM_CONF_MIN_ASYNC (40) 299 300 /* 301 * Number of entries in the START and DONE queues. 302 * 303 * We limit to 1 PAGE in order to succeed allocation of 304 * these queues. Each entry is 8 bytes long (2 DWORDS). 305 */ 306 #ifdef SYM_CONF_MAX_START 307 #define SYM_CONF_MAX_QUEUE (SYM_CONF_MAX_START+2) 308 #else 309 #define SYM_CONF_MAX_QUEUE (7*SYM_CONF_MAX_TASK+2) 310 #define SYM_CONF_MAX_START (SYM_CONF_MAX_QUEUE-2) 311 #endif 312 313 #if SYM_CONF_MAX_QUEUE > PAGE_SIZE/8 314 #undef SYM_CONF_MAX_QUEUE 315 #define SYM_CONF_MAX_QUEUE PAGE_SIZE/8 316 #undef SYM_CONF_MAX_START 317 #define SYM_CONF_MAX_START (SYM_CONF_MAX_QUEUE-2) 318 #endif 319 320 /* 321 * For this one, we want a short name :-) 322 */ 323 #define MAX_QUEUE SYM_CONF_MAX_QUEUE 324 325 /* 326 * Active debugging tags and verbosity. 327 */ 328 #define DEBUG_ALLOC (0x0001) 329 #define DEBUG_PHASE (0x0002) 330 #define DEBUG_POLL (0x0004) 331 #define DEBUG_QUEUE (0x0008) 332 #define DEBUG_RESULT (0x0010) 333 #define DEBUG_SCATTER (0x0020) 334 #define DEBUG_SCRIPT (0x0040) 335 #define DEBUG_TINY (0x0080) 336 #define DEBUG_TIMING (0x0100) 337 #define DEBUG_NEGO (0x0200) 338 #define DEBUG_TAGS (0x0400) 339 #define DEBUG_POINTER (0x0800) 340 341 #if 0 342 static int sym_debug = 0; 343 #define DEBUG_FLAGS sym_debug 344 #else 345 /* #define DEBUG_FLAGS (0x0631) */ 346 #define DEBUG_FLAGS (0x0000) 347 348 #endif 349 #define sym_verbose (np->verbose) 350 351 /* 352 * Insert a delay in micro-seconds and milli-seconds. 353 */ 354 static void UDELAY(int us) { DELAY(us); } 355 static void MDELAY(int ms) { while (ms--) UDELAY(1000); } 356 357 /* 358 * Simple power of two buddy-like allocator. 359 * 360 * This simple code is not intended to be fast, but to 361 * provide power of 2 aligned memory allocations. 362 * Since the SCRIPTS processor only supplies 8 bit arithmetic, 363 * this allocator allows simple and fast address calculations 364 * from the SCRIPTS code. In addition, cache line alignment 365 * is guaranteed for power of 2 cache line size. 366 * 367 * This allocator has been developped for the Linux sym53c8xx 368 * driver, since this O/S does not provide naturally aligned 369 * allocations. 370 * It has the advantage of allowing the driver to use private 371 * pages of memory that will be useful if we ever need to deal 372 * with IO MMUs for PCI. 373 */ 374 375 #define MEMO_SHIFT 4 /* 16 bytes minimum memory chunk */ 376 #ifndef __amd64__ 377 #define MEMO_PAGE_ORDER 0 /* 1 PAGE maximum */ 378 #else 379 #define MEMO_PAGE_ORDER 1 /* 2 PAGEs maximum on amd64 */ 380 #endif 381 #if 0 382 #define MEMO_FREE_UNUSED /* Free unused pages immediately */ 383 #endif 384 #define MEMO_WARN 1 385 #define MEMO_CLUSTER_SHIFT (PAGE_SHIFT+MEMO_PAGE_ORDER) 386 #define MEMO_CLUSTER_SIZE (1UL << MEMO_CLUSTER_SHIFT) 387 #define MEMO_CLUSTER_MASK (MEMO_CLUSTER_SIZE-1) 388 389 #ifndef __amd64__ 390 #define get_pages() malloc(MEMO_CLUSTER_SIZE, M_DEVBUF, M_NOWAIT) 391 #define free_pages(p) free((p), M_DEVBUF) 392 #else 393 #define get_pages() contigmalloc(MEMO_CLUSTER_SIZE, M_DEVBUF, \ 394 0, 0, 1LL << 32, PAGE_SIZE, 1LL << 32) 395 #define free_pages(p) contigfree((p), MEMO_CLUSTER_SIZE, M_DEVBUF) 396 #endif 397 398 typedef u_long m_addr_t; /* Enough bits to bit-hack addresses */ 399 400 typedef struct m_link { /* Link between free memory chunks */ 401 struct m_link *next; 402 } m_link_s; 403 404 typedef struct m_vtob { /* Virtual to Bus address translation */ 405 struct m_vtob *next; 406 bus_dmamap_t dmamap; /* Map for this chunk */ 407 m_addr_t vaddr; /* Virtual address */ 408 m_addr_t baddr; /* Bus physical address */ 409 } m_vtob_s; 410 /* Hash this stuff a bit to speed up translations */ 411 #define VTOB_HASH_SHIFT 5 412 #define VTOB_HASH_SIZE (1UL << VTOB_HASH_SHIFT) 413 #define VTOB_HASH_MASK (VTOB_HASH_SIZE-1) 414 #define VTOB_HASH_CODE(m) \ 415 ((((m_addr_t) (m)) >> MEMO_CLUSTER_SHIFT) & VTOB_HASH_MASK) 416 417 typedef struct m_pool { /* Memory pool of a given kind */ 418 bus_dma_tag_t dev_dmat; /* Identifies the pool */ 419 bus_dma_tag_t dmat; /* Tag for our fixed allocations */ 420 m_addr_t (*getp)(struct m_pool *); 421 #ifdef MEMO_FREE_UNUSED 422 void (*freep)(struct m_pool *, m_addr_t); 423 #endif 424 #define M_GETP() mp->getp(mp) 425 #define M_FREEP(p) mp->freep(mp, p) 426 int nump; 427 m_vtob_s *(vtob[VTOB_HASH_SIZE]); 428 struct m_pool *next; 429 struct m_link h[MEMO_CLUSTER_SHIFT - MEMO_SHIFT + 1]; 430 } m_pool_s; 431 432 static void *___sym_malloc(m_pool_s *mp, int size) 433 { 434 int i = 0; 435 int s = (1 << MEMO_SHIFT); 436 int j; 437 m_addr_t a; 438 m_link_s *h = mp->h; 439 440 if (size > MEMO_CLUSTER_SIZE) 441 return 0; 442 443 while (size > s) { 444 s <<= 1; 445 ++i; 446 } 447 448 j = i; 449 while (!h[j].next) { 450 if (s == MEMO_CLUSTER_SIZE) { 451 h[j].next = (m_link_s *) M_GETP(); 452 if (h[j].next) 453 h[j].next->next = 0; 454 break; 455 } 456 ++j; 457 s <<= 1; 458 } 459 a = (m_addr_t) h[j].next; 460 if (a) { 461 h[j].next = h[j].next->next; 462 while (j > i) { 463 j -= 1; 464 s >>= 1; 465 h[j].next = (m_link_s *) (a+s); 466 h[j].next->next = 0; 467 } 468 } 469 #ifdef DEBUG 470 printf("___sym_malloc(%d) = %p\n", size, (void *) a); 471 #endif 472 return (void *) a; 473 } 474 475 static void ___sym_mfree(m_pool_s *mp, void *ptr, int size) 476 { 477 int i = 0; 478 int s = (1 << MEMO_SHIFT); 479 m_link_s *q; 480 m_addr_t a, b; 481 m_link_s *h = mp->h; 482 483 #ifdef DEBUG 484 printf("___sym_mfree(%p, %d)\n", ptr, size); 485 #endif 486 487 if (size > MEMO_CLUSTER_SIZE) 488 return; 489 490 while (size > s) { 491 s <<= 1; 492 ++i; 493 } 494 495 a = (m_addr_t) ptr; 496 497 while (1) { 498 #ifdef MEMO_FREE_UNUSED 499 if (s == MEMO_CLUSTER_SIZE) { 500 M_FREEP(a); 501 break; 502 } 503 #endif 504 b = a ^ s; 505 q = &h[i]; 506 while (q->next && q->next != (m_link_s *) b) { 507 q = q->next; 508 } 509 if (!q->next) { 510 ((m_link_s *) a)->next = h[i].next; 511 h[i].next = (m_link_s *) a; 512 break; 513 } 514 q->next = q->next->next; 515 a = a & b; 516 s <<= 1; 517 ++i; 518 } 519 } 520 521 static void *__sym_calloc2(m_pool_s *mp, int size, char *name, int uflags) 522 { 523 void *p; 524 525 p = ___sym_malloc(mp, size); 526 527 if (DEBUG_FLAGS & DEBUG_ALLOC) 528 printf ("new %-10s[%4d] @%p.\n", name, size, p); 529 530 if (p) 531 bzero(p, size); 532 else if (uflags & MEMO_WARN) 533 printf ("__sym_calloc2: failed to allocate %s[%d]\n", name, size); 534 535 return p; 536 } 537 538 #define __sym_calloc(mp, s, n) __sym_calloc2(mp, s, n, MEMO_WARN) 539 540 static void __sym_mfree(m_pool_s *mp, void *ptr, int size, char *name) 541 { 542 if (DEBUG_FLAGS & DEBUG_ALLOC) 543 printf ("freeing %-10s[%4d] @%p.\n", name, size, ptr); 544 545 ___sym_mfree(mp, ptr, size); 546 547 } 548 549 /* 550 * Default memory pool we donnot need to involve in DMA. 551 */ 552 /* 553 * With the `bus dma abstraction', we use a separate pool for 554 * memory we donnot need to involve in DMA. 555 */ 556 static m_addr_t ___mp0_getp(m_pool_s *mp) 557 { 558 m_addr_t m = (m_addr_t) get_pages(); 559 if (m) 560 ++mp->nump; 561 return m; 562 } 563 564 #ifdef MEMO_FREE_UNUSED 565 static void ___mp0_freep(m_pool_s *mp, m_addr_t m) 566 { 567 free_pages(m); 568 --mp->nump; 569 } 570 #endif 571 572 #ifdef MEMO_FREE_UNUSED 573 static m_pool_s mp0 = {0, 0, ___mp0_getp, ___mp0_freep}; 574 #else 575 static m_pool_s mp0 = {0, 0, ___mp0_getp}; 576 #endif 577 578 579 /* 580 * Actual memory allocation routine for non-DMAed memory. 581 */ 582 static void *sym_calloc(int size, char *name) 583 { 584 void *m; 585 /* Lock */ 586 m = __sym_calloc(&mp0, size, name); 587 /* Unlock */ 588 return m; 589 } 590 591 /* 592 * Actual memory allocation routine for non-DMAed memory. 593 */ 594 static void sym_mfree(void *ptr, int size, char *name) 595 { 596 /* Lock */ 597 __sym_mfree(&mp0, ptr, size, name); 598 /* Unlock */ 599 } 600 601 /* 602 * DMAable pools. 603 */ 604 /* 605 * With `bus dma abstraction', we use a separate pool per parent 606 * BUS handle. A reverse table (hashed) is maintained for virtual 607 * to BUS address translation. 608 */ 609 static void getbaddrcb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 610 { 611 bus_addr_t *baddr; 612 baddr = (bus_addr_t *)arg; 613 *baddr = segs->ds_addr; 614 } 615 616 static m_addr_t ___dma_getp(m_pool_s *mp) 617 { 618 m_vtob_s *vbp; 619 void *vaddr = 0; 620 bus_addr_t baddr = 0; 621 622 vbp = __sym_calloc(&mp0, sizeof(*vbp), "VTOB"); 623 if (!vbp) 624 goto out_err; 625 626 if (bus_dmamem_alloc(mp->dmat, &vaddr, 627 BUS_DMA_NOWAIT, &vbp->dmamap)) 628 goto out_err; 629 bus_dmamap_load(mp->dmat, vbp->dmamap, vaddr, 630 MEMO_CLUSTER_SIZE, getbaddrcb, &baddr, 0); 631 if (baddr) { 632 int hc = VTOB_HASH_CODE(vaddr); 633 vbp->vaddr = (m_addr_t) vaddr; 634 vbp->baddr = (m_addr_t) baddr; 635 vbp->next = mp->vtob[hc]; 636 mp->vtob[hc] = vbp; 637 ++mp->nump; 638 return (m_addr_t) vaddr; 639 } 640 out_err: 641 if (baddr) 642 bus_dmamap_unload(mp->dmat, vbp->dmamap); 643 if (vaddr) 644 bus_dmamem_free(mp->dmat, vaddr, vbp->dmamap); 645 if (vbp) { 646 if (vbp->dmamap) 647 bus_dmamap_destroy(mp->dmat, vbp->dmamap); 648 __sym_mfree(&mp0, vbp, sizeof(*vbp), "VTOB"); 649 } 650 return 0; 651 } 652 653 #ifdef MEMO_FREE_UNUSED 654 static void ___dma_freep(m_pool_s *mp, m_addr_t m) 655 { 656 m_vtob_s **vbpp, *vbp; 657 int hc = VTOB_HASH_CODE(m); 658 659 vbpp = &mp->vtob[hc]; 660 while (*vbpp && (*vbpp)->vaddr != m) 661 vbpp = &(*vbpp)->next; 662 if (*vbpp) { 663 vbp = *vbpp; 664 *vbpp = (*vbpp)->next; 665 bus_dmamap_unload(mp->dmat, vbp->dmamap); 666 bus_dmamem_free(mp->dmat, (void *) vbp->vaddr, vbp->dmamap); 667 bus_dmamap_destroy(mp->dmat, vbp->dmamap); 668 __sym_mfree(&mp0, vbp, sizeof(*vbp), "VTOB"); 669 --mp->nump; 670 } 671 } 672 #endif 673 674 static __inline m_pool_s *___get_dma_pool(bus_dma_tag_t dev_dmat) 675 { 676 m_pool_s *mp; 677 for (mp = mp0.next; mp && mp->dev_dmat != dev_dmat; mp = mp->next); 678 return mp; 679 } 680 681 static m_pool_s *___cre_dma_pool(bus_dma_tag_t dev_dmat) 682 { 683 m_pool_s *mp = 0; 684 685 mp = __sym_calloc(&mp0, sizeof(*mp), "MPOOL"); 686 if (mp) { 687 mp->dev_dmat = dev_dmat; 688 if (!bus_dma_tag_create(dev_dmat, 1, MEMO_CLUSTER_SIZE, 689 BUS_SPACE_MAXADDR_32BIT, 690 BUS_SPACE_MAXADDR_32BIT, 691 NULL, NULL, MEMO_CLUSTER_SIZE, 1, 692 MEMO_CLUSTER_SIZE, 0, 693 busdma_lock_mutex, &Giant, &mp->dmat)) { 694 mp->getp = ___dma_getp; 695 #ifdef MEMO_FREE_UNUSED 696 mp->freep = ___dma_freep; 697 #endif 698 mp->next = mp0.next; 699 mp0.next = mp; 700 return mp; 701 } 702 } 703 if (mp) 704 __sym_mfree(&mp0, mp, sizeof(*mp), "MPOOL"); 705 return 0; 706 } 707 708 #ifdef MEMO_FREE_UNUSED 709 static void ___del_dma_pool(m_pool_s *p) 710 { 711 struct m_pool **pp = &mp0.next; 712 713 while (*pp && *pp != p) 714 pp = &(*pp)->next; 715 if (*pp) { 716 *pp = (*pp)->next; 717 bus_dma_tag_destroy(p->dmat); 718 __sym_mfree(&mp0, p, sizeof(*p), "MPOOL"); 719 } 720 } 721 #endif 722 723 static void *__sym_calloc_dma(bus_dma_tag_t dev_dmat, int size, char *name) 724 { 725 struct m_pool *mp; 726 void *m = 0; 727 728 /* Lock */ 729 mp = ___get_dma_pool(dev_dmat); 730 if (!mp) 731 mp = ___cre_dma_pool(dev_dmat); 732 if (mp) 733 m = __sym_calloc(mp, size, name); 734 #ifdef MEMO_FREE_UNUSED 735 if (mp && !mp->nump) 736 ___del_dma_pool(mp); 737 #endif 738 /* Unlock */ 739 740 return m; 741 } 742 743 static void 744 __sym_mfree_dma(bus_dma_tag_t dev_dmat, void *m, int size, char *name) 745 { 746 struct m_pool *mp; 747 748 /* Lock */ 749 mp = ___get_dma_pool(dev_dmat); 750 if (mp) 751 __sym_mfree(mp, m, size, name); 752 #ifdef MEMO_FREE_UNUSED 753 if (mp && !mp->nump) 754 ___del_dma_pool(mp); 755 #endif 756 /* Unlock */ 757 } 758 759 static m_addr_t __vtobus(bus_dma_tag_t dev_dmat, void *m) 760 { 761 m_pool_s *mp; 762 int hc = VTOB_HASH_CODE(m); 763 m_vtob_s *vp = 0; 764 m_addr_t a = ((m_addr_t) m) & ~MEMO_CLUSTER_MASK; 765 766 /* Lock */ 767 mp = ___get_dma_pool(dev_dmat); 768 if (mp) { 769 vp = mp->vtob[hc]; 770 while (vp && (m_addr_t) vp->vaddr != a) 771 vp = vp->next; 772 } 773 /* Unlock */ 774 if (!vp) 775 panic("sym: VTOBUS FAILED!\n"); 776 return vp ? vp->baddr + (((m_addr_t) m) - a) : 0; 777 } 778 779 780 /* 781 * Verbs for DMAable memory handling. 782 * The _uvptv_ macro avoids a nasty warning about pointer to volatile 783 * being discarded. 784 */ 785 #define _uvptv_(p) ((void *)((vm_offset_t)(p))) 786 #define _sym_calloc_dma(np, s, n) __sym_calloc_dma(np->bus_dmat, s, n) 787 #define _sym_mfree_dma(np, p, s, n) \ 788 __sym_mfree_dma(np->bus_dmat, _uvptv_(p), s, n) 789 #define sym_calloc_dma(s, n) _sym_calloc_dma(np, s, n) 790 #define sym_mfree_dma(p, s, n) _sym_mfree_dma(np, p, s, n) 791 #define _vtobus(np, p) __vtobus(np->bus_dmat, _uvptv_(p)) 792 #define vtobus(p) _vtobus(np, p) 793 794 795 /* 796 * Print a buffer in hexadecimal format. 797 */ 798 static void sym_printb_hex (u_char *p, int n) 799 { 800 while (n-- > 0) 801 printf (" %x", *p++); 802 } 803 804 /* 805 * Same with a label at beginning and .\n at end. 806 */ 807 static void sym_printl_hex (char *label, u_char *p, int n) 808 { 809 printf ("%s", label); 810 sym_printb_hex (p, n); 811 printf (".\n"); 812 } 813 814 /* 815 * Return a string for SCSI BUS mode. 816 */ 817 static char *sym_scsi_bus_mode(int mode) 818 { 819 switch(mode) { 820 case SMODE_HVD: return "HVD"; 821 case SMODE_SE: return "SE"; 822 case SMODE_LVD: return "LVD"; 823 } 824 return "??"; 825 } 826 827 /* 828 * Some poor and bogus sync table that refers to Tekram NVRAM layout. 829 */ 830 #ifdef SYM_CONF_NVRAM_SUPPORT 831 static u_char Tekram_sync[16] = 832 {25,31,37,43, 50,62,75,125, 12,15,18,21, 6,7,9,10}; 833 #endif 834 835 /* 836 * Union of supported NVRAM formats. 837 */ 838 struct sym_nvram { 839 int type; 840 #define SYM_SYMBIOS_NVRAM (1) 841 #define SYM_TEKRAM_NVRAM (2) 842 #ifdef SYM_CONF_NVRAM_SUPPORT 843 union { 844 Symbios_nvram Symbios; 845 Tekram_nvram Tekram; 846 } data; 847 #endif 848 }; 849 850 /* 851 * This one is hopefully useless, but actually useful. :-) 852 */ 853 #ifndef assert 854 #define assert(expression) { \ 855 if (!(expression)) { \ 856 (void)panic( \ 857 "assertion \"%s\" failed: file \"%s\", line %d\n", \ 858 #expression, \ 859 __FILE__, __LINE__); \ 860 } \ 861 } 862 #endif 863 864 /* 865 * Some provision for a possible big endian mode supported by 866 * Symbios chips (never seen, by the way). 867 * For now, this stuff does not deserve any comments. :) 868 */ 869 870 #define sym_offb(o) (o) 871 #define sym_offw(o) (o) 872 873 /* 874 * Some provision for support for BIG ENDIAN CPU. 875 */ 876 877 #define cpu_to_scr(dw) htole32(dw) 878 #define scr_to_cpu(dw) le32toh(dw) 879 880 /* 881 * Access to the chip IO registers and on-chip RAM. 882 * We use the `bus space' interface under FreeBSD-4 and 883 * later kernel versions. 884 */ 885 886 887 #if defined(SYM_CONF_IOMAPPED) 888 889 #define INB_OFF(o) bus_space_read_1(np->io_tag, np->io_bsh, o) 890 #define INW_OFF(o) bus_space_read_2(np->io_tag, np->io_bsh, o) 891 #define INL_OFF(o) bus_space_read_4(np->io_tag, np->io_bsh, o) 892 893 #define OUTB_OFF(o, v) bus_space_write_1(np->io_tag, np->io_bsh, o, (v)) 894 #define OUTW_OFF(o, v) bus_space_write_2(np->io_tag, np->io_bsh, o, (v)) 895 #define OUTL_OFF(o, v) bus_space_write_4(np->io_tag, np->io_bsh, o, (v)) 896 897 #else /* Memory mapped IO */ 898 899 #define INB_OFF(o) bus_space_read_1(np->mmio_tag, np->mmio_bsh, o) 900 #define INW_OFF(o) bus_space_read_2(np->mmio_tag, np->mmio_bsh, o) 901 #define INL_OFF(o) bus_space_read_4(np->mmio_tag, np->mmio_bsh, o) 902 903 #define OUTB_OFF(o, v) bus_space_write_1(np->mmio_tag, np->mmio_bsh, o, (v)) 904 #define OUTW_OFF(o, v) bus_space_write_2(np->mmio_tag, np->mmio_bsh, o, (v)) 905 #define OUTL_OFF(o, v) bus_space_write_4(np->mmio_tag, np->mmio_bsh, o, (v)) 906 907 #endif /* SYM_CONF_IOMAPPED */ 908 909 #define OUTRAM_OFF(o, a, l) \ 910 bus_space_write_region_1(np->ram_tag, np->ram_bsh, o, (a), (l)) 911 912 913 /* 914 * Common definitions for both bus space and legacy IO methods. 915 */ 916 #define INB(r) INB_OFF(offsetof(struct sym_reg,r)) 917 #define INW(r) INW_OFF(offsetof(struct sym_reg,r)) 918 #define INL(r) INL_OFF(offsetof(struct sym_reg,r)) 919 920 #define OUTB(r, v) OUTB_OFF(offsetof(struct sym_reg,r), (v)) 921 #define OUTW(r, v) OUTW_OFF(offsetof(struct sym_reg,r), (v)) 922 #define OUTL(r, v) OUTL_OFF(offsetof(struct sym_reg,r), (v)) 923 924 #define OUTONB(r, m) OUTB(r, INB(r) | (m)) 925 #define OUTOFFB(r, m) OUTB(r, INB(r) & ~(m)) 926 #define OUTONW(r, m) OUTW(r, INW(r) | (m)) 927 #define OUTOFFW(r, m) OUTW(r, INW(r) & ~(m)) 928 #define OUTONL(r, m) OUTL(r, INL(r) | (m)) 929 #define OUTOFFL(r, m) OUTL(r, INL(r) & ~(m)) 930 931 /* 932 * We normally want the chip to have a consistent view 933 * of driver internal data structures when we restart it. 934 * Thus these macros. 935 */ 936 #define OUTL_DSP(v) \ 937 do { \ 938 MEMORY_BARRIER(); \ 939 OUTL (nc_dsp, (v)); \ 940 } while (0) 941 942 #define OUTONB_STD() \ 943 do { \ 944 MEMORY_BARRIER(); \ 945 OUTONB (nc_dcntl, (STD|NOCOM)); \ 946 } while (0) 947 948 /* 949 * Command control block states. 950 */ 951 #define HS_IDLE (0) 952 #define HS_BUSY (1) 953 #define HS_NEGOTIATE (2) /* sync/wide data transfer*/ 954 #define HS_DISCONNECT (3) /* Disconnected by target */ 955 #define HS_WAIT (4) /* waiting for resource */ 956 957 #define HS_DONEMASK (0x80) 958 #define HS_COMPLETE (4|HS_DONEMASK) 959 #define HS_SEL_TIMEOUT (5|HS_DONEMASK) /* Selection timeout */ 960 #define HS_UNEXPECTED (6|HS_DONEMASK) /* Unexpected disconnect */ 961 #define HS_COMP_ERR (7|HS_DONEMASK) /* Completed with error */ 962 963 /* 964 * Software Interrupt Codes 965 */ 966 #define SIR_BAD_SCSI_STATUS (1) 967 #define SIR_SEL_ATN_NO_MSG_OUT (2) 968 #define SIR_MSG_RECEIVED (3) 969 #define SIR_MSG_WEIRD (4) 970 #define SIR_NEGO_FAILED (5) 971 #define SIR_NEGO_PROTO (6) 972 #define SIR_SCRIPT_STOPPED (7) 973 #define SIR_REJECT_TO_SEND (8) 974 #define SIR_SWIDE_OVERRUN (9) 975 #define SIR_SODL_UNDERRUN (10) 976 #define SIR_RESEL_NO_MSG_IN (11) 977 #define SIR_RESEL_NO_IDENTIFY (12) 978 #define SIR_RESEL_BAD_LUN (13) 979 #define SIR_TARGET_SELECTED (14) 980 #define SIR_RESEL_BAD_I_T_L (15) 981 #define SIR_RESEL_BAD_I_T_L_Q (16) 982 #define SIR_ABORT_SENT (17) 983 #define SIR_RESEL_ABORTED (18) 984 #define SIR_MSG_OUT_DONE (19) 985 #define SIR_COMPLETE_ERROR (20) 986 #define SIR_DATA_OVERRUN (21) 987 #define SIR_BAD_PHASE (22) 988 #define SIR_MAX (22) 989 990 /* 991 * Extended error bit codes. 992 * xerr_status field of struct sym_ccb. 993 */ 994 #define XE_EXTRA_DATA (1) /* unexpected data phase */ 995 #define XE_BAD_PHASE (1<<1) /* illegal phase (4/5) */ 996 #define XE_PARITY_ERR (1<<2) /* unrecovered SCSI parity error */ 997 #define XE_SODL_UNRUN (1<<3) /* ODD transfer in DATA OUT phase */ 998 #define XE_SWIDE_OVRUN (1<<4) /* ODD transfer in DATA IN phase */ 999 1000 /* 1001 * Negotiation status. 1002 * nego_status field of struct sym_ccb. 1003 */ 1004 #define NS_SYNC (1) 1005 #define NS_WIDE (2) 1006 #define NS_PPR (3) 1007 1008 /* 1009 * A CCB hashed table is used to retrieve CCB address 1010 * from DSA value. 1011 */ 1012 #define CCB_HASH_SHIFT 8 1013 #define CCB_HASH_SIZE (1UL << CCB_HASH_SHIFT) 1014 #define CCB_HASH_MASK (CCB_HASH_SIZE-1) 1015 #define CCB_HASH_CODE(dsa) (((dsa) >> 9) & CCB_HASH_MASK) 1016 1017 /* 1018 * Device flags. 1019 */ 1020 #define SYM_DISC_ENABLED (1) 1021 #define SYM_TAGS_ENABLED (1<<1) 1022 #define SYM_SCAN_BOOT_DISABLED (1<<2) 1023 #define SYM_SCAN_LUNS_DISABLED (1<<3) 1024 1025 /* 1026 * Host adapter miscellaneous flags. 1027 */ 1028 #define SYM_AVOID_BUS_RESET (1) 1029 #define SYM_SCAN_TARGETS_HILO (1<<1) 1030 1031 /* 1032 * Device quirks. 1033 * Some devices, for example the CHEETAH 2 LVD, disconnects without 1034 * saving the DATA POINTER then reselects and terminates the IO. 1035 * On reselection, the automatic RESTORE DATA POINTER makes the 1036 * CURRENT DATA POINTER not point at the end of the IO. 1037 * This behaviour just breaks our calculation of the residual. 1038 * For now, we just force an AUTO SAVE on disconnection and will 1039 * fix that in a further driver version. 1040 */ 1041 #define SYM_QUIRK_AUTOSAVE 1 1042 1043 /* 1044 * Misc. 1045 */ 1046 #define SYM_SNOOP_TIMEOUT (10000000) 1047 #define SYM_PCI_IO PCIR_BAR(0) 1048 #define SYM_PCI_MMIO PCIR_BAR(1) 1049 #define SYM_PCI_RAM PCIR_BAR(2) 1050 #define SYM_PCI_RAM64 PCIR_BAR(3) 1051 1052 /* 1053 * Back-pointer from the CAM CCB to our data structures. 1054 */ 1055 #define sym_hcb_ptr spriv_ptr0 1056 /* #define sym_ccb_ptr spriv_ptr1 */ 1057 1058 /* 1059 * We mostly have to deal with pointers. 1060 * Thus these typedef's. 1061 */ 1062 typedef struct sym_tcb *tcb_p; 1063 typedef struct sym_lcb *lcb_p; 1064 typedef struct sym_ccb *ccb_p; 1065 typedef struct sym_hcb *hcb_p; 1066 1067 /* 1068 * Gather negotiable parameters value 1069 */ 1070 struct sym_trans { 1071 u8 scsi_version; 1072 u8 spi_version; 1073 u8 period; 1074 u8 offset; 1075 u8 width; 1076 u8 options; /* PPR options */ 1077 }; 1078 1079 struct sym_tinfo { 1080 struct sym_trans current; 1081 struct sym_trans goal; 1082 struct sym_trans user; 1083 }; 1084 1085 #define BUS_8_BIT MSG_EXT_WDTR_BUS_8_BIT 1086 #define BUS_16_BIT MSG_EXT_WDTR_BUS_16_BIT 1087 1088 /* 1089 * Global TCB HEADER. 1090 * 1091 * Due to lack of indirect addressing on earlier NCR chips, 1092 * this substructure is copied from the TCB to a global 1093 * address after selection. 1094 * For SYMBIOS chips that support LOAD/STORE this copy is 1095 * not needed and thus not performed. 1096 */ 1097 struct sym_tcbh { 1098 /* 1099 * Scripts bus addresses of LUN table accessed from scripts. 1100 * LUN #0 is a special case, since multi-lun devices are rare, 1101 * and we we want to speed-up the general case and not waste 1102 * resources. 1103 */ 1104 u32 luntbl_sa; /* bus address of this table */ 1105 u32 lun0_sa; /* bus address of LCB #0 */ 1106 /* 1107 * Actual SYNC/WIDE IO registers value for this target. 1108 * 'sval', 'wval' and 'uval' are read from SCRIPTS and 1109 * so have alignment constraints. 1110 */ 1111 /*0*/ u_char uval; /* -> SCNTL4 register */ 1112 /*1*/ u_char sval; /* -> SXFER io register */ 1113 /*2*/ u_char filler1; 1114 /*3*/ u_char wval; /* -> SCNTL3 io register */ 1115 }; 1116 1117 /* 1118 * Target Control Block 1119 */ 1120 struct sym_tcb { 1121 /* 1122 * TCB header. 1123 * Assumed at offset 0. 1124 */ 1125 /*0*/ struct sym_tcbh head; 1126 1127 /* 1128 * LUN table used by the SCRIPTS processor. 1129 * An array of bus addresses is used on reselection. 1130 */ 1131 u32 *luntbl; /* LCBs bus address table */ 1132 1133 /* 1134 * LUN table used by the C code. 1135 */ 1136 lcb_p lun0p; /* LCB of LUN #0 (usual case) */ 1137 #if SYM_CONF_MAX_LUN > 1 1138 lcb_p *lunmp; /* Other LCBs [1..MAX_LUN] */ 1139 #endif 1140 1141 /* 1142 * Bitmap that tells about LUNs that succeeded at least 1143 * 1 IO and therefore assumed to be a real device. 1144 * Avoid useless allocation of the LCB structure. 1145 */ 1146 u32 lun_map[(SYM_CONF_MAX_LUN+31)/32]; 1147 1148 /* 1149 * Bitmap that tells about LUNs that haven't yet an LCB 1150 * allocated (not discovered or LCB allocation failed). 1151 */ 1152 u32 busy0_map[(SYM_CONF_MAX_LUN+31)/32]; 1153 1154 /* 1155 * Transfer capabilities (SIP) 1156 */ 1157 struct sym_tinfo tinfo; 1158 1159 /* 1160 * Keep track of the CCB used for the negotiation in order 1161 * to ensure that only 1 negotiation is queued at a time. 1162 */ 1163 ccb_p nego_cp; /* CCB used for the nego */ 1164 1165 /* 1166 * Set when we want to reset the device. 1167 */ 1168 u_char to_reset; 1169 1170 /* 1171 * Other user settable limits and options. 1172 * These limits are read from the NVRAM if present. 1173 */ 1174 u_char usrflags; 1175 u_short usrtags; 1176 }; 1177 1178 /* 1179 * Global LCB HEADER. 1180 * 1181 * Due to lack of indirect addressing on earlier NCR chips, 1182 * this substructure is copied from the LCB to a global 1183 * address after selection. 1184 * For SYMBIOS chips that support LOAD/STORE this copy is 1185 * not needed and thus not performed. 1186 */ 1187 struct sym_lcbh { 1188 /* 1189 * SCRIPTS address jumped by SCRIPTS on reselection. 1190 * For not probed logical units, this address points to 1191 * SCRIPTS that deal with bad LU handling (must be at 1192 * offset zero of the LCB for that reason). 1193 */ 1194 /*0*/ u32 resel_sa; 1195 1196 /* 1197 * Task (bus address of a CCB) read from SCRIPTS that points 1198 * to the unique ITL nexus allowed to be disconnected. 1199 */ 1200 u32 itl_task_sa; 1201 1202 /* 1203 * Task table bus address (read from SCRIPTS). 1204 */ 1205 u32 itlq_tbl_sa; 1206 }; 1207 1208 /* 1209 * Logical Unit Control Block 1210 */ 1211 struct sym_lcb { 1212 /* 1213 * TCB header. 1214 * Assumed at offset 0. 1215 */ 1216 /*0*/ struct sym_lcbh head; 1217 1218 /* 1219 * Task table read from SCRIPTS that contains pointers to 1220 * ITLQ nexuses. The bus address read from SCRIPTS is 1221 * inside the header. 1222 */ 1223 u32 *itlq_tbl; /* Kernel virtual address */ 1224 1225 /* 1226 * Busy CCBs management. 1227 */ 1228 u_short busy_itlq; /* Number of busy tagged CCBs */ 1229 u_short busy_itl; /* Number of busy untagged CCBs */ 1230 1231 /* 1232 * Circular tag allocation buffer. 1233 */ 1234 u_short ia_tag; /* Tag allocation index */ 1235 u_short if_tag; /* Tag release index */ 1236 u_char *cb_tags; /* Circular tags buffer */ 1237 1238 /* 1239 * Set when we want to clear all tasks. 1240 */ 1241 u_char to_clear; 1242 1243 /* 1244 * Capabilities. 1245 */ 1246 u_char user_flags; 1247 u_char current_flags; 1248 }; 1249 1250 /* 1251 * Action from SCRIPTS on a task. 1252 * Is part of the CCB, but is also used separately to plug 1253 * error handling action to perform from SCRIPTS. 1254 */ 1255 struct sym_actscr { 1256 u32 start; /* Jumped by SCRIPTS after selection */ 1257 u32 restart; /* Jumped by SCRIPTS on relection */ 1258 }; 1259 1260 /* 1261 * Phase mismatch context. 1262 * 1263 * It is part of the CCB and is used as parameters for the 1264 * DATA pointer. We need two contexts to handle correctly the 1265 * SAVED DATA POINTER. 1266 */ 1267 struct sym_pmc { 1268 struct sym_tblmove sg; /* Updated interrupted SG block */ 1269 u32 ret; /* SCRIPT return address */ 1270 }; 1271 1272 /* 1273 * LUN control block lookup. 1274 * We use a direct pointer for LUN #0, and a table of 1275 * pointers which is only allocated for devices that support 1276 * LUN(s) > 0. 1277 */ 1278 #if SYM_CONF_MAX_LUN <= 1 1279 #define sym_lp(np, tp, lun) (!lun) ? (tp)->lun0p : 0 1280 #else 1281 #define sym_lp(np, tp, lun) \ 1282 (!lun) ? (tp)->lun0p : (tp)->lunmp ? (tp)->lunmp[(lun)] : 0 1283 #endif 1284 1285 /* 1286 * Status are used by the host and the script processor. 1287 * 1288 * The last four bytes (status[4]) are copied to the 1289 * scratchb register (declared as scr0..scr3) just after the 1290 * select/reselect, and copied back just after disconnecting. 1291 * Inside the script the XX_REG are used. 1292 */ 1293 1294 /* 1295 * Last four bytes (script) 1296 */ 1297 #define QU_REG scr0 1298 #define HS_REG scr1 1299 #define HS_PRT nc_scr1 1300 #define SS_REG scr2 1301 #define SS_PRT nc_scr2 1302 #define HF_REG scr3 1303 #define HF_PRT nc_scr3 1304 1305 /* 1306 * Last four bytes (host) 1307 */ 1308 #define actualquirks phys.head.status[0] 1309 #define host_status phys.head.status[1] 1310 #define ssss_status phys.head.status[2] 1311 #define host_flags phys.head.status[3] 1312 1313 /* 1314 * Host flags 1315 */ 1316 #define HF_IN_PM0 1u 1317 #define HF_IN_PM1 (1u<<1) 1318 #define HF_ACT_PM (1u<<2) 1319 #define HF_DP_SAVED (1u<<3) 1320 #define HF_SENSE (1u<<4) 1321 #define HF_EXT_ERR (1u<<5) 1322 #define HF_DATA_IN (1u<<6) 1323 #ifdef SYM_CONF_IARB_SUPPORT 1324 #define HF_HINT_IARB (1u<<7) 1325 #endif 1326 1327 /* 1328 * Global CCB HEADER. 1329 * 1330 * Due to lack of indirect addressing on earlier NCR chips, 1331 * this substructure is copied from the ccb to a global 1332 * address after selection (or reselection) and copied back 1333 * before disconnect. 1334 * For SYMBIOS chips that support LOAD/STORE this copy is 1335 * not needed and thus not performed. 1336 */ 1337 1338 struct sym_ccbh { 1339 /* 1340 * Start and restart SCRIPTS addresses (must be at 0). 1341 */ 1342 /*0*/ struct sym_actscr go; 1343 1344 /* 1345 * SCRIPTS jump address that deal with data pointers. 1346 * 'savep' points to the position in the script responsible 1347 * for the actual transfer of data. 1348 * It's written on reception of a SAVE_DATA_POINTER message. 1349 */ 1350 u32 savep; /* Jump address to saved data pointer */ 1351 u32 lastp; /* SCRIPTS address at end of data */ 1352 u32 goalp; /* Not accessed for now from SCRIPTS */ 1353 1354 /* 1355 * Status fields. 1356 */ 1357 u8 status[4]; 1358 }; 1359 1360 /* 1361 * Data Structure Block 1362 * 1363 * During execution of a ccb by the script processor, the 1364 * DSA (data structure address) register points to this 1365 * substructure of the ccb. 1366 */ 1367 struct sym_dsb { 1368 /* 1369 * CCB header. 1370 * Also assumed at offset 0 of the sym_ccb structure. 1371 */ 1372 /*0*/ struct sym_ccbh head; 1373 1374 /* 1375 * Phase mismatch contexts. 1376 * We need two to handle correctly the SAVED DATA POINTER. 1377 * MUST BOTH BE AT OFFSET < 256, due to using 8 bit arithmetic 1378 * for address calculation from SCRIPTS. 1379 */ 1380 struct sym_pmc pm0; 1381 struct sym_pmc pm1; 1382 1383 /* 1384 * Table data for Script 1385 */ 1386 struct sym_tblsel select; 1387 struct sym_tblmove smsg; 1388 struct sym_tblmove smsg_ext; 1389 struct sym_tblmove cmd; 1390 struct sym_tblmove sense; 1391 struct sym_tblmove wresid; 1392 struct sym_tblmove data [SYM_CONF_MAX_SG]; 1393 }; 1394 1395 /* 1396 * Our Command Control Block 1397 */ 1398 struct sym_ccb { 1399 /* 1400 * This is the data structure which is pointed by the DSA 1401 * register when it is executed by the script processor. 1402 * It must be the first entry. 1403 */ 1404 struct sym_dsb phys; 1405 1406 /* 1407 * Pointer to CAM ccb and related stuff. 1408 */ 1409 union ccb *cam_ccb; /* CAM scsiio ccb */ 1410 u8 cdb_buf[16]; /* Copy of CDB */ 1411 u8 *sns_bbuf; /* Bounce buffer for sense data */ 1412 #define SYM_SNS_BBUF_LEN sizeof(struct scsi_sense_data) 1413 int data_len; /* Total data length */ 1414 int segments; /* Number of SG segments */ 1415 1416 /* 1417 * Miscellaneous status'. 1418 */ 1419 u_char nego_status; /* Negotiation status */ 1420 u_char xerr_status; /* Extended error flags */ 1421 u32 extra_bytes; /* Extraneous bytes transferred */ 1422 1423 /* 1424 * Message areas. 1425 * We prepare a message to be sent after selection. 1426 * We may use a second one if the command is rescheduled 1427 * due to CHECK_CONDITION or COMMAND TERMINATED. 1428 * Contents are IDENTIFY and SIMPLE_TAG. 1429 * While negotiating sync or wide transfer, 1430 * a SDTR or WDTR message is appended. 1431 */ 1432 u_char scsi_smsg [12]; 1433 u_char scsi_smsg2[12]; 1434 1435 /* 1436 * Auto request sense related fields. 1437 */ 1438 u_char sensecmd[6]; /* Request Sense command */ 1439 u_char sv_scsi_status; /* Saved SCSI status */ 1440 u_char sv_xerr_status; /* Saved extended status */ 1441 int sv_resid; /* Saved residual */ 1442 1443 /* 1444 * Map for the DMA of user data. 1445 */ 1446 void *arg; /* Argument for some callback */ 1447 bus_dmamap_t dmamap; /* DMA map for user data */ 1448 u_char dmamapped; 1449 #define SYM_DMA_NONE 0 1450 #define SYM_DMA_READ 1 1451 #define SYM_DMA_WRITE 2 1452 /* 1453 * Other fields. 1454 */ 1455 u32 ccb_ba; /* BUS address of this CCB */ 1456 u_short tag; /* Tag for this transfer */ 1457 /* NO_TAG means no tag */ 1458 u_char target; 1459 u_char lun; 1460 ccb_p link_ccbh; /* Host adapter CCB hash chain */ 1461 SYM_QUEHEAD 1462 link_ccbq; /* Link to free/busy CCB queue */ 1463 u32 startp; /* Initial data pointer */ 1464 int ext_sg; /* Extreme data pointer, used */ 1465 int ext_ofs; /* to calculate the residual. */ 1466 u_char to_abort; /* Want this IO to be aborted */ 1467 }; 1468 1469 #define CCB_BA(cp,lbl) (cp->ccb_ba + offsetof(struct sym_ccb, lbl)) 1470 1471 /* 1472 * Host Control Block 1473 */ 1474 struct sym_hcb { 1475 /* 1476 * Global headers. 1477 * Due to poorness of addressing capabilities, earlier 1478 * chips (810, 815, 825) copy part of the data structures 1479 * (CCB, TCB and LCB) in fixed areas. 1480 */ 1481 #ifdef SYM_CONF_GENERIC_SUPPORT 1482 struct sym_ccbh ccb_head; 1483 struct sym_tcbh tcb_head; 1484 struct sym_lcbh lcb_head; 1485 #endif 1486 /* 1487 * Idle task and invalid task actions and 1488 * their bus addresses. 1489 */ 1490 struct sym_actscr idletask, notask, bad_itl, bad_itlq; 1491 vm_offset_t idletask_ba, notask_ba, bad_itl_ba, bad_itlq_ba; 1492 1493 /* 1494 * Dummy lun table to protect us against target 1495 * returning bad lun number on reselection. 1496 */ 1497 u32 *badluntbl; /* Table physical address */ 1498 u32 badlun_sa; /* SCRIPT handler BUS address */ 1499 1500 /* 1501 * Bus address of this host control block. 1502 */ 1503 u32 hcb_ba; 1504 1505 /* 1506 * Bit 32-63 of the on-chip RAM bus address in LE format. 1507 * The START_RAM64 script loads the MMRS and MMWS from this 1508 * field. 1509 */ 1510 u32 scr_ram_seg; 1511 1512 /* 1513 * Chip and controller indentification. 1514 */ 1515 device_t device; 1516 int unit; 1517 char inst_name[8]; 1518 1519 /* 1520 * Initial value of some IO register bits. 1521 * These values are assumed to have been set by BIOS, and may 1522 * be used to probe adapter implementation differences. 1523 */ 1524 u_char sv_scntl0, sv_scntl3, sv_dmode, sv_dcntl, sv_ctest3, sv_ctest4, 1525 sv_ctest5, sv_gpcntl, sv_stest2, sv_stest4, sv_scntl4, 1526 sv_stest1; 1527 1528 /* 1529 * Actual initial value of IO register bits used by the 1530 * driver. They are loaded at initialisation according to 1531 * features that are to be enabled/disabled. 1532 */ 1533 u_char rv_scntl0, rv_scntl3, rv_dmode, rv_dcntl, rv_ctest3, rv_ctest4, 1534 rv_ctest5, rv_stest2, rv_ccntl0, rv_ccntl1, rv_scntl4; 1535 1536 /* 1537 * Target data. 1538 */ 1539 struct sym_tcb target[SYM_CONF_MAX_TARGET]; 1540 1541 /* 1542 * Target control block bus address array used by the SCRIPT 1543 * on reselection. 1544 */ 1545 u32 *targtbl; 1546 u32 targtbl_ba; 1547 1548 /* 1549 * CAM SIM information for this instance. 1550 */ 1551 struct cam_sim *sim; 1552 struct cam_path *path; 1553 1554 /* 1555 * Allocated hardware resources. 1556 */ 1557 struct resource *irq_res; 1558 struct resource *io_res; 1559 struct resource *mmio_res; 1560 struct resource *ram_res; 1561 int ram_id; 1562 void *intr; 1563 1564 /* 1565 * Bus stuff. 1566 * 1567 * My understanding of PCI is that all agents must share the 1568 * same addressing range and model. 1569 * But some hardware architecture guys provide complex and 1570 * brain-deaded stuff that makes shit. 1571 * This driver only support PCI compliant implementations and 1572 * deals with part of the BUS stuff complexity only to fit O/S 1573 * requirements. 1574 */ 1575 bus_space_handle_t io_bsh; 1576 bus_space_tag_t io_tag; 1577 bus_space_handle_t mmio_bsh; 1578 bus_space_tag_t mmio_tag; 1579 bus_space_handle_t ram_bsh; 1580 bus_space_tag_t ram_tag; 1581 1582 /* 1583 * DMA stuff. 1584 */ 1585 bus_dma_tag_t bus_dmat; /* DMA tag from parent BUS */ 1586 bus_dma_tag_t data_dmat; /* DMA tag for user data */ 1587 /* 1588 * Virtual and physical bus addresses of the chip. 1589 */ 1590 vm_offset_t mmio_va; /* MMIO kernel virtual address */ 1591 vm_offset_t mmio_pa; /* MMIO CPU physical address */ 1592 vm_offset_t mmio_ba; /* MMIO BUS address */ 1593 int mmio_ws; /* MMIO Window size */ 1594 1595 vm_offset_t ram_va; /* RAM kernel virtual address */ 1596 vm_offset_t ram_pa; /* RAM CPU physical address */ 1597 vm_offset_t ram_ba; /* RAM BUS address */ 1598 int ram_ws; /* RAM window size */ 1599 u32 io_port; /* IO port address */ 1600 1601 /* 1602 * SCRIPTS virtual and physical bus addresses. 1603 * 'script' is loaded in the on-chip RAM if present. 1604 * 'scripth' stays in main memory for all chips except the 1605 * 53C895A, 53C896 and 53C1010 that provide 8K on-chip RAM. 1606 */ 1607 u_char *scripta0; /* Copies of script and scripth */ 1608 u_char *scriptb0; /* Copies of script and scripth */ 1609 vm_offset_t scripta_ba; /* Actual script and scripth */ 1610 vm_offset_t scriptb_ba; /* bus addresses. */ 1611 vm_offset_t scriptb0_ba; 1612 u_short scripta_sz; /* Actual size of script A */ 1613 u_short scriptb_sz; /* Actual size of script B */ 1614 1615 /* 1616 * Bus addresses, setup and patch methods for 1617 * the selected firmware. 1618 */ 1619 struct sym_fwa_ba fwa_bas; /* Useful SCRIPTA bus addresses */ 1620 struct sym_fwb_ba fwb_bas; /* Useful SCRIPTB bus addresses */ 1621 void (*fw_setup)(hcb_p np, struct sym_fw *fw); 1622 void (*fw_patch)(hcb_p np); 1623 char *fw_name; 1624 1625 /* 1626 * General controller parameters and configuration. 1627 */ 1628 u_short device_id; /* PCI device id */ 1629 u_char revision_id; /* PCI device revision id */ 1630 u_int features; /* Chip features map */ 1631 u_char myaddr; /* SCSI id of the adapter */ 1632 u_char maxburst; /* log base 2 of dwords burst */ 1633 u_char maxwide; /* Maximum transfer width */ 1634 u_char minsync; /* Min sync period factor (ST) */ 1635 u_char maxsync; /* Max sync period factor (ST) */ 1636 u_char maxoffs; /* Max scsi offset (ST) */ 1637 u_char minsync_dt; /* Min sync period factor (DT) */ 1638 u_char maxsync_dt; /* Max sync period factor (DT) */ 1639 u_char maxoffs_dt; /* Max scsi offset (DT) */ 1640 u_char multiplier; /* Clock multiplier (1,2,4) */ 1641 u_char clock_divn; /* Number of clock divisors */ 1642 u32 clock_khz; /* SCSI clock frequency in KHz */ 1643 u32 pciclk_khz; /* Estimated PCI clock in KHz */ 1644 /* 1645 * Start queue management. 1646 * It is filled up by the host processor and accessed by the 1647 * SCRIPTS processor in order to start SCSI commands. 1648 */ 1649 volatile /* Prevent code optimizations */ 1650 u32 *squeue; /* Start queue virtual address */ 1651 u32 squeue_ba; /* Start queue BUS address */ 1652 u_short squeueput; /* Next free slot of the queue */ 1653 u_short actccbs; /* Number of allocated CCBs */ 1654 1655 /* 1656 * Command completion queue. 1657 * It is the same size as the start queue to avoid overflow. 1658 */ 1659 u_short dqueueget; /* Next position to scan */ 1660 volatile /* Prevent code optimizations */ 1661 u32 *dqueue; /* Completion (done) queue */ 1662 u32 dqueue_ba; /* Done queue BUS address */ 1663 1664 /* 1665 * Miscellaneous buffers accessed by the scripts-processor. 1666 * They shall be DWORD aligned, because they may be read or 1667 * written with a script command. 1668 */ 1669 u_char msgout[8]; /* Buffer for MESSAGE OUT */ 1670 u_char msgin [8]; /* Buffer for MESSAGE IN */ 1671 u32 lastmsg; /* Last SCSI message sent */ 1672 u_char scratch; /* Scratch for SCSI receive */ 1673 1674 /* 1675 * Miscellaneous configuration and status parameters. 1676 */ 1677 u_char usrflags; /* Miscellaneous user flags */ 1678 u_char scsi_mode; /* Current SCSI BUS mode */ 1679 u_char verbose; /* Verbosity for this controller*/ 1680 u32 cache; /* Used for cache test at init. */ 1681 1682 /* 1683 * CCB lists and queue. 1684 */ 1685 ccb_p ccbh[CCB_HASH_SIZE]; /* CCB hashed by DSA value */ 1686 SYM_QUEHEAD free_ccbq; /* Queue of available CCBs */ 1687 SYM_QUEHEAD busy_ccbq; /* Queue of busy CCBs */ 1688 1689 /* 1690 * During error handling and/or recovery, 1691 * active CCBs that are to be completed with 1692 * error or requeued are moved from the busy_ccbq 1693 * to the comp_ccbq prior to completion. 1694 */ 1695 SYM_QUEHEAD comp_ccbq; 1696 1697 /* 1698 * CAM CCB pending queue. 1699 */ 1700 SYM_QUEHEAD cam_ccbq; 1701 1702 /* 1703 * IMMEDIATE ARBITRATION (IARB) control. 1704 * 1705 * We keep track in 'last_cp' of the last CCB that has been 1706 * queued to the SCRIPTS processor and clear 'last_cp' when 1707 * this CCB completes. If last_cp is not zero at the moment 1708 * we queue a new CCB, we set a flag in 'last_cp' that is 1709 * used by the SCRIPTS as a hint for setting IARB. 1710 * We donnot set more than 'iarb_max' consecutive hints for 1711 * IARB in order to leave devices a chance to reselect. 1712 * By the way, any non zero value of 'iarb_max' is unfair. :) 1713 */ 1714 #ifdef SYM_CONF_IARB_SUPPORT 1715 u_short iarb_max; /* Max. # consecutive IARB hints*/ 1716 u_short iarb_count; /* Actual # of these hints */ 1717 ccb_p last_cp; 1718 #endif 1719 1720 /* 1721 * Command abort handling. 1722 * We need to synchronize tightly with the SCRIPTS 1723 * processor in order to handle things correctly. 1724 */ 1725 u_char abrt_msg[4]; /* Message to send buffer */ 1726 struct sym_tblmove abrt_tbl; /* Table for the MOV of it */ 1727 struct sym_tblsel abrt_sel; /* Sync params for selection */ 1728 u_char istat_sem; /* Tells the chip to stop (SEM) */ 1729 }; 1730 1731 #define HCB_BA(np, lbl) (np->hcb_ba + offsetof(struct sym_hcb, lbl)) 1732 1733 /* 1734 * Return the name of the controller. 1735 */ 1736 static __inline char *sym_name(hcb_p np) 1737 { 1738 return np->inst_name; 1739 } 1740 1741 /*--------------------------------------------------------------------------*/ 1742 /*------------------------------ FIRMWARES ---------------------------------*/ 1743 /*--------------------------------------------------------------------------*/ 1744 1745 /* 1746 * This stuff will be moved to a separate source file when 1747 * the driver will be broken into several source modules. 1748 */ 1749 1750 /* 1751 * Macros used for all firmwares. 1752 */ 1753 #define SYM_GEN_A(s, label) ((short) offsetof(s, label)), 1754 #define SYM_GEN_B(s, label) ((short) offsetof(s, label)), 1755 #define PADDR_A(label) SYM_GEN_PADDR_A(struct SYM_FWA_SCR, label) 1756 #define PADDR_B(label) SYM_GEN_PADDR_B(struct SYM_FWB_SCR, label) 1757 1758 1759 #ifdef SYM_CONF_GENERIC_SUPPORT 1760 /* 1761 * Allocate firmware #1 script area. 1762 */ 1763 #define SYM_FWA_SCR sym_fw1a_scr 1764 #define SYM_FWB_SCR sym_fw1b_scr 1765 #include <dev/sym/sym_fw1.h> 1766 struct sym_fwa_ofs sym_fw1a_ofs = { 1767 SYM_GEN_FW_A(struct SYM_FWA_SCR) 1768 }; 1769 struct sym_fwb_ofs sym_fw1b_ofs = { 1770 SYM_GEN_FW_B(struct SYM_FWB_SCR) 1771 }; 1772 #undef SYM_FWA_SCR 1773 #undef SYM_FWB_SCR 1774 #endif /* SYM_CONF_GENERIC_SUPPORT */ 1775 1776 /* 1777 * Allocate firmware #2 script area. 1778 */ 1779 #define SYM_FWA_SCR sym_fw2a_scr 1780 #define SYM_FWB_SCR sym_fw2b_scr 1781 #include <dev/sym/sym_fw2.h> 1782 struct sym_fwa_ofs sym_fw2a_ofs = { 1783 SYM_GEN_FW_A(struct SYM_FWA_SCR) 1784 }; 1785 struct sym_fwb_ofs sym_fw2b_ofs = { 1786 SYM_GEN_FW_B(struct SYM_FWB_SCR) 1787 SYM_GEN_B(struct SYM_FWB_SCR, start64) 1788 SYM_GEN_B(struct SYM_FWB_SCR, pm_handle) 1789 }; 1790 #undef SYM_FWA_SCR 1791 #undef SYM_FWB_SCR 1792 1793 #undef SYM_GEN_A 1794 #undef SYM_GEN_B 1795 #undef PADDR_A 1796 #undef PADDR_B 1797 1798 #ifdef SYM_CONF_GENERIC_SUPPORT 1799 /* 1800 * Patch routine for firmware #1. 1801 */ 1802 static void 1803 sym_fw1_patch(hcb_p np) 1804 { 1805 struct sym_fw1a_scr *scripta0; 1806 struct sym_fw1b_scr *scriptb0; 1807 1808 scripta0 = (struct sym_fw1a_scr *) np->scripta0; 1809 scriptb0 = (struct sym_fw1b_scr *) np->scriptb0; 1810 1811 /* 1812 * Remove LED support if not needed. 1813 */ 1814 if (!(np->features & FE_LED0)) { 1815 scripta0->idle[0] = cpu_to_scr(SCR_NO_OP); 1816 scripta0->reselected[0] = cpu_to_scr(SCR_NO_OP); 1817 scripta0->start[0] = cpu_to_scr(SCR_NO_OP); 1818 } 1819 1820 #ifdef SYM_CONF_IARB_SUPPORT 1821 /* 1822 * If user does not want to use IMMEDIATE ARBITRATION 1823 * when we are reselected while attempting to arbitrate, 1824 * patch the SCRIPTS accordingly with a SCRIPT NO_OP. 1825 */ 1826 if (!SYM_CONF_SET_IARB_ON_ARB_LOST) 1827 scripta0->ungetjob[0] = cpu_to_scr(SCR_NO_OP); 1828 #endif 1829 /* 1830 * Patch some data in SCRIPTS. 1831 * - start and done queue initial bus address. 1832 * - target bus address table bus address. 1833 */ 1834 scriptb0->startpos[0] = cpu_to_scr(np->squeue_ba); 1835 scriptb0->done_pos[0] = cpu_to_scr(np->dqueue_ba); 1836 scriptb0->targtbl[0] = cpu_to_scr(np->targtbl_ba); 1837 } 1838 #endif /* SYM_CONF_GENERIC_SUPPORT */ 1839 1840 /* 1841 * Patch routine for firmware #2. 1842 */ 1843 static void 1844 sym_fw2_patch(hcb_p np) 1845 { 1846 struct sym_fw2a_scr *scripta0; 1847 struct sym_fw2b_scr *scriptb0; 1848 1849 scripta0 = (struct sym_fw2a_scr *) np->scripta0; 1850 scriptb0 = (struct sym_fw2b_scr *) np->scriptb0; 1851 1852 /* 1853 * Remove LED support if not needed. 1854 */ 1855 if (!(np->features & FE_LED0)) { 1856 scripta0->idle[0] = cpu_to_scr(SCR_NO_OP); 1857 scripta0->reselected[0] = cpu_to_scr(SCR_NO_OP); 1858 scripta0->start[0] = cpu_to_scr(SCR_NO_OP); 1859 } 1860 1861 #ifdef SYM_CONF_IARB_SUPPORT 1862 /* 1863 * If user does not want to use IMMEDIATE ARBITRATION 1864 * when we are reselected while attempting to arbitrate, 1865 * patch the SCRIPTS accordingly with a SCRIPT NO_OP. 1866 */ 1867 if (!SYM_CONF_SET_IARB_ON_ARB_LOST) 1868 scripta0->ungetjob[0] = cpu_to_scr(SCR_NO_OP); 1869 #endif 1870 /* 1871 * Patch some variable in SCRIPTS. 1872 * - start and done queue initial bus address. 1873 * - target bus address table bus address. 1874 */ 1875 scriptb0->startpos[0] = cpu_to_scr(np->squeue_ba); 1876 scriptb0->done_pos[0] = cpu_to_scr(np->dqueue_ba); 1877 scriptb0->targtbl[0] = cpu_to_scr(np->targtbl_ba); 1878 1879 /* 1880 * Remove the load of SCNTL4 on reselection if not a C10. 1881 */ 1882 if (!(np->features & FE_C10)) { 1883 scripta0->resel_scntl4[0] = cpu_to_scr(SCR_NO_OP); 1884 scripta0->resel_scntl4[1] = cpu_to_scr(0); 1885 } 1886 1887 /* 1888 * Remove a couple of work-arounds specific to C1010 if 1889 * they are not desirable. See `sym_fw2.h' for more details. 1890 */ 1891 if (!(np->device_id == PCI_ID_LSI53C1010_2 && 1892 np->revision_id < 0x1 && 1893 np->pciclk_khz < 60000)) { 1894 scripta0->datao_phase[0] = cpu_to_scr(SCR_NO_OP); 1895 scripta0->datao_phase[1] = cpu_to_scr(0); 1896 } 1897 if (!(np->device_id == PCI_ID_LSI53C1010 && 1898 /* np->revision_id < 0xff */ 1)) { 1899 scripta0->sel_done[0] = cpu_to_scr(SCR_NO_OP); 1900 scripta0->sel_done[1] = cpu_to_scr(0); 1901 } 1902 1903 /* 1904 * Patch some other variables in SCRIPTS. 1905 * These ones are loaded by the SCRIPTS processor. 1906 */ 1907 scriptb0->pm0_data_addr[0] = 1908 cpu_to_scr(np->scripta_ba + 1909 offsetof(struct sym_fw2a_scr, pm0_data)); 1910 scriptb0->pm1_data_addr[0] = 1911 cpu_to_scr(np->scripta_ba + 1912 offsetof(struct sym_fw2a_scr, pm1_data)); 1913 } 1914 1915 /* 1916 * Fill the data area in scripts. 1917 * To be done for all firmwares. 1918 */ 1919 static void 1920 sym_fw_fill_data (u32 *in, u32 *out) 1921 { 1922 int i; 1923 1924 for (i = 0; i < SYM_CONF_MAX_SG; i++) { 1925 *in++ = SCR_CHMOV_TBL ^ SCR_DATA_IN; 1926 *in++ = offsetof (struct sym_dsb, data[i]); 1927 *out++ = SCR_CHMOV_TBL ^ SCR_DATA_OUT; 1928 *out++ = offsetof (struct sym_dsb, data[i]); 1929 } 1930 } 1931 1932 /* 1933 * Setup useful script bus addresses. 1934 * To be done for all firmwares. 1935 */ 1936 static void 1937 sym_fw_setup_bus_addresses(hcb_p np, struct sym_fw *fw) 1938 { 1939 u32 *pa; 1940 u_short *po; 1941 int i; 1942 1943 /* 1944 * Build the bus address table for script A 1945 * from the script A offset table. 1946 */ 1947 po = (u_short *) fw->a_ofs; 1948 pa = (u32 *) &np->fwa_bas; 1949 for (i = 0 ; i < sizeof(np->fwa_bas)/sizeof(u32) ; i++) 1950 pa[i] = np->scripta_ba + po[i]; 1951 1952 /* 1953 * Same for script B. 1954 */ 1955 po = (u_short *) fw->b_ofs; 1956 pa = (u32 *) &np->fwb_bas; 1957 for (i = 0 ; i < sizeof(np->fwb_bas)/sizeof(u32) ; i++) 1958 pa[i] = np->scriptb_ba + po[i]; 1959 } 1960 1961 #ifdef SYM_CONF_GENERIC_SUPPORT 1962 /* 1963 * Setup routine for firmware #1. 1964 */ 1965 static void 1966 sym_fw1_setup(hcb_p np, struct sym_fw *fw) 1967 { 1968 struct sym_fw1a_scr *scripta0; 1969 struct sym_fw1b_scr *scriptb0; 1970 1971 scripta0 = (struct sym_fw1a_scr *) np->scripta0; 1972 scriptb0 = (struct sym_fw1b_scr *) np->scriptb0; 1973 1974 /* 1975 * Fill variable parts in scripts. 1976 */ 1977 sym_fw_fill_data(scripta0->data_in, scripta0->data_out); 1978 1979 /* 1980 * Setup bus addresses used from the C code.. 1981 */ 1982 sym_fw_setup_bus_addresses(np, fw); 1983 } 1984 #endif /* SYM_CONF_GENERIC_SUPPORT */ 1985 1986 /* 1987 * Setup routine for firmware #2. 1988 */ 1989 static void 1990 sym_fw2_setup(hcb_p np, struct sym_fw *fw) 1991 { 1992 struct sym_fw2a_scr *scripta0; 1993 struct sym_fw2b_scr *scriptb0; 1994 1995 scripta0 = (struct sym_fw2a_scr *) np->scripta0; 1996 scriptb0 = (struct sym_fw2b_scr *) np->scriptb0; 1997 1998 /* 1999 * Fill variable parts in scripts. 2000 */ 2001 sym_fw_fill_data(scripta0->data_in, scripta0->data_out); 2002 2003 /* 2004 * Setup bus addresses used from the C code.. 2005 */ 2006 sym_fw_setup_bus_addresses(np, fw); 2007 } 2008 2009 /* 2010 * Allocate firmware descriptors. 2011 */ 2012 #ifdef SYM_CONF_GENERIC_SUPPORT 2013 static struct sym_fw sym_fw1 = SYM_FW_ENTRY(sym_fw1, "NCR-generic"); 2014 #endif /* SYM_CONF_GENERIC_SUPPORT */ 2015 static struct sym_fw sym_fw2 = SYM_FW_ENTRY(sym_fw2, "LOAD/STORE-based"); 2016 2017 /* 2018 * Find the most appropriate firmware for a chip. 2019 */ 2020 static struct sym_fw * 2021 sym_find_firmware(struct sym_pci_chip *chip) 2022 { 2023 if (chip->features & FE_LDSTR) 2024 return &sym_fw2; 2025 #ifdef SYM_CONF_GENERIC_SUPPORT 2026 else if (!(chip->features & (FE_PFEN|FE_NOPM|FE_DAC))) 2027 return &sym_fw1; 2028 #endif 2029 else 2030 return 0; 2031 } 2032 2033 /* 2034 * Bind a script to physical addresses. 2035 */ 2036 static void sym_fw_bind_script (hcb_p np, u32 *start, int len) 2037 { 2038 u32 opcode, new, old, tmp1, tmp2; 2039 u32 *end, *cur; 2040 int relocs; 2041 2042 cur = start; 2043 end = start + len/4; 2044 2045 while (cur < end) { 2046 2047 opcode = *cur; 2048 2049 /* 2050 * If we forget to change the length 2051 * in scripts, a field will be 2052 * padded with 0. This is an illegal 2053 * command. 2054 */ 2055 if (opcode == 0) { 2056 printf ("%s: ERROR0 IN SCRIPT at %d.\n", 2057 sym_name(np), (int) (cur-start)); 2058 MDELAY (10000); 2059 ++cur; 2060 continue; 2061 }; 2062 2063 /* 2064 * We use the bogus value 0xf00ff00f ;-) 2065 * to reserve data area in SCRIPTS. 2066 */ 2067 if (opcode == SCR_DATA_ZERO) { 2068 *cur++ = 0; 2069 continue; 2070 } 2071 2072 if (DEBUG_FLAGS & DEBUG_SCRIPT) 2073 printf ("%d: <%x>\n", (int) (cur-start), 2074 (unsigned)opcode); 2075 2076 /* 2077 * We don't have to decode ALL commands 2078 */ 2079 switch (opcode >> 28) { 2080 case 0xf: 2081 /* 2082 * LOAD / STORE DSA relative, don't relocate. 2083 */ 2084 relocs = 0; 2085 break; 2086 case 0xe: 2087 /* 2088 * LOAD / STORE absolute. 2089 */ 2090 relocs = 1; 2091 break; 2092 case 0xc: 2093 /* 2094 * COPY has TWO arguments. 2095 */ 2096 relocs = 2; 2097 tmp1 = cur[1]; 2098 tmp2 = cur[2]; 2099 if ((tmp1 ^ tmp2) & 3) { 2100 printf ("%s: ERROR1 IN SCRIPT at %d.\n", 2101 sym_name(np), (int) (cur-start)); 2102 MDELAY (10000); 2103 } 2104 /* 2105 * If PREFETCH feature not enabled, remove 2106 * the NO FLUSH bit if present. 2107 */ 2108 if ((opcode & SCR_NO_FLUSH) && 2109 !(np->features & FE_PFEN)) { 2110 opcode = (opcode & ~SCR_NO_FLUSH); 2111 } 2112 break; 2113 case 0x0: 2114 /* 2115 * MOVE/CHMOV (absolute address) 2116 */ 2117 if (!(np->features & FE_WIDE)) 2118 opcode = (opcode | OPC_MOVE); 2119 relocs = 1; 2120 break; 2121 case 0x1: 2122 /* 2123 * MOVE/CHMOV (table indirect) 2124 */ 2125 if (!(np->features & FE_WIDE)) 2126 opcode = (opcode | OPC_MOVE); 2127 relocs = 0; 2128 break; 2129 case 0x8: 2130 /* 2131 * JUMP / CALL 2132 * dont't relocate if relative :-) 2133 */ 2134 if (opcode & 0x00800000) 2135 relocs = 0; 2136 else if ((opcode & 0xf8400000) == 0x80400000)/*JUMP64*/ 2137 relocs = 2; 2138 else 2139 relocs = 1; 2140 break; 2141 case 0x4: 2142 case 0x5: 2143 case 0x6: 2144 case 0x7: 2145 relocs = 1; 2146 break; 2147 default: 2148 relocs = 0; 2149 break; 2150 }; 2151 2152 /* 2153 * Scriptify:) the opcode. 2154 */ 2155 *cur++ = cpu_to_scr(opcode); 2156 2157 /* 2158 * If no relocation, assume 1 argument 2159 * and just scriptize:) it. 2160 */ 2161 if (!relocs) { 2162 *cur = cpu_to_scr(*cur); 2163 ++cur; 2164 continue; 2165 } 2166 2167 /* 2168 * Otherwise performs all needed relocations. 2169 */ 2170 while (relocs--) { 2171 old = *cur; 2172 2173 switch (old & RELOC_MASK) { 2174 case RELOC_REGISTER: 2175 new = (old & ~RELOC_MASK) + np->mmio_ba; 2176 break; 2177 case RELOC_LABEL_A: 2178 new = (old & ~RELOC_MASK) + np->scripta_ba; 2179 break; 2180 case RELOC_LABEL_B: 2181 new = (old & ~RELOC_MASK) + np->scriptb_ba; 2182 break; 2183 case RELOC_SOFTC: 2184 new = (old & ~RELOC_MASK) + np->hcb_ba; 2185 break; 2186 case 0: 2187 /* 2188 * Don't relocate a 0 address. 2189 * They are mostly used for patched or 2190 * script self-modified areas. 2191 */ 2192 if (old == 0) { 2193 new = old; 2194 break; 2195 } 2196 /* fall through */ 2197 default: 2198 new = 0; 2199 panic("sym_fw_bind_script: " 2200 "weird relocation %x\n", old); 2201 break; 2202 } 2203 2204 *cur++ = cpu_to_scr(new); 2205 } 2206 }; 2207 } 2208 2209 /*--------------------------------------------------------------------------*/ 2210 /*--------------------------- END OF FIRMARES -----------------------------*/ 2211 /*--------------------------------------------------------------------------*/ 2212 2213 /* 2214 * Function prototypes. 2215 */ 2216 static void sym_save_initial_setting (hcb_p np); 2217 static int sym_prepare_setting (hcb_p np, struct sym_nvram *nvram); 2218 static int sym_prepare_nego (hcb_p np, ccb_p cp, int nego, u_char *msgptr); 2219 static void sym_put_start_queue (hcb_p np, ccb_p cp); 2220 static void sym_chip_reset (hcb_p np); 2221 static void sym_soft_reset (hcb_p np); 2222 static void sym_start_reset (hcb_p np); 2223 static int sym_reset_scsi_bus (hcb_p np, int enab_int); 2224 static int sym_wakeup_done (hcb_p np); 2225 static void sym_flush_busy_queue (hcb_p np, int cam_status); 2226 static void sym_flush_comp_queue (hcb_p np, int cam_status); 2227 static void sym_init (hcb_p np, int reason); 2228 static int sym_getsync(hcb_p np, u_char dt, u_char sfac, u_char *divp, 2229 u_char *fakp); 2230 static void sym_setsync (hcb_p np, ccb_p cp, u_char ofs, u_char per, 2231 u_char div, u_char fak); 2232 static void sym_setwide (hcb_p np, ccb_p cp, u_char wide); 2233 static void sym_setpprot(hcb_p np, ccb_p cp, u_char dt, u_char ofs, 2234 u_char per, u_char wide, u_char div, u_char fak); 2235 static void sym_settrans(hcb_p np, ccb_p cp, u_char dt, u_char ofs, 2236 u_char per, u_char wide, u_char div, u_char fak); 2237 static void sym_log_hard_error (hcb_p np, u_short sist, u_char dstat); 2238 static void sym_intr (void *arg); 2239 static void sym_poll (struct cam_sim *sim); 2240 static void sym_recover_scsi_int (hcb_p np, u_char hsts); 2241 static void sym_int_sto (hcb_p np); 2242 static void sym_int_udc (hcb_p np); 2243 static void sym_int_sbmc (hcb_p np); 2244 static void sym_int_par (hcb_p np, u_short sist); 2245 static void sym_int_ma (hcb_p np); 2246 static int sym_dequeue_from_squeue(hcb_p np, int i, int target, int lun, 2247 int task); 2248 static void sym_sir_bad_scsi_status (hcb_p np, int num, ccb_p cp); 2249 static int sym_clear_tasks (hcb_p np, int status, int targ, int lun, int task); 2250 static void sym_sir_task_recovery (hcb_p np, int num); 2251 static int sym_evaluate_dp (hcb_p np, ccb_p cp, u32 scr, int *ofs); 2252 static void sym_modify_dp (hcb_p np, tcb_p tp, ccb_p cp, int ofs); 2253 static int sym_compute_residual (hcb_p np, ccb_p cp); 2254 static int sym_show_msg (u_char * msg); 2255 static void sym_print_msg (ccb_p cp, char *label, u_char *msg); 2256 static void sym_sync_nego (hcb_p np, tcb_p tp, ccb_p cp); 2257 static void sym_ppr_nego (hcb_p np, tcb_p tp, ccb_p cp); 2258 static void sym_wide_nego (hcb_p np, tcb_p tp, ccb_p cp); 2259 static void sym_nego_default (hcb_p np, tcb_p tp, ccb_p cp); 2260 static void sym_nego_rejected (hcb_p np, tcb_p tp, ccb_p cp); 2261 static void sym_int_sir (hcb_p np); 2262 static void sym_free_ccb (hcb_p np, ccb_p cp); 2263 static ccb_p sym_get_ccb (hcb_p np, u_char tn, u_char ln, u_char tag_order); 2264 static ccb_p sym_alloc_ccb (hcb_p np); 2265 static ccb_p sym_ccb_from_dsa (hcb_p np, u32 dsa); 2266 static lcb_p sym_alloc_lcb (hcb_p np, u_char tn, u_char ln); 2267 static void sym_alloc_lcb_tags (hcb_p np, u_char tn, u_char ln); 2268 static int sym_snooptest (hcb_p np); 2269 static void sym_selectclock(hcb_p np, u_char scntl3); 2270 static void sym_getclock (hcb_p np, int mult); 2271 static int sym_getpciclock (hcb_p np); 2272 static void sym_complete_ok (hcb_p np, ccb_p cp); 2273 static void sym_complete_error (hcb_p np, ccb_p cp); 2274 static void sym_timeout (void *arg); 2275 static int sym_abort_scsiio (hcb_p np, union ccb *ccb, int timed_out); 2276 static void sym_reset_dev (hcb_p np, union ccb *ccb); 2277 static void sym_action (struct cam_sim *sim, union ccb *ccb); 2278 static void sym_action1 (struct cam_sim *sim, union ccb *ccb); 2279 static int sym_setup_cdb (hcb_p np, struct ccb_scsiio *csio, ccb_p cp); 2280 static void sym_setup_data_and_start (hcb_p np, struct ccb_scsiio *csio, 2281 ccb_p cp); 2282 static int sym_fast_scatter_sg_physical(hcb_p np, ccb_p cp, 2283 bus_dma_segment_t *psegs, int nsegs); 2284 static int sym_scatter_sg_physical (hcb_p np, ccb_p cp, 2285 bus_dma_segment_t *psegs, int nsegs); 2286 static void sym_action2 (struct cam_sim *sim, union ccb *ccb); 2287 static void sym_update_trans (hcb_p np, tcb_p tp, struct sym_trans *tip, 2288 struct ccb_trans_settings *cts); 2289 static void sym_update_dflags(hcb_p np, u_char *flags, 2290 struct ccb_trans_settings *cts); 2291 2292 static struct sym_pci_chip *sym_find_pci_chip (device_t dev); 2293 static int sym_pci_probe (device_t dev); 2294 static int sym_pci_attach (device_t dev); 2295 2296 static void sym_pci_free (hcb_p np); 2297 static int sym_cam_attach (hcb_p np); 2298 static void sym_cam_free (hcb_p np); 2299 2300 static void sym_nvram_setup_host (hcb_p np, struct sym_nvram *nvram); 2301 static void sym_nvram_setup_target (hcb_p np, int targ, struct sym_nvram *nvp); 2302 static int sym_read_nvram (hcb_p np, struct sym_nvram *nvp); 2303 2304 /* 2305 * Print something which allows to retrieve the controler type, 2306 * unit, target, lun concerned by a kernel message. 2307 */ 2308 static void PRINT_TARGET (hcb_p np, int target) 2309 { 2310 printf ("%s:%d:", sym_name(np), target); 2311 } 2312 2313 static void PRINT_LUN(hcb_p np, int target, int lun) 2314 { 2315 printf ("%s:%d:%d:", sym_name(np), target, lun); 2316 } 2317 2318 static void PRINT_ADDR (ccb_p cp) 2319 { 2320 if (cp && cp->cam_ccb) 2321 xpt_print_path(cp->cam_ccb->ccb_h.path); 2322 } 2323 2324 /* 2325 * Take into account this ccb in the freeze count. 2326 */ 2327 static void sym_freeze_cam_ccb(union ccb *ccb) 2328 { 2329 if (!(ccb->ccb_h.flags & CAM_DEV_QFRZDIS)) { 2330 if (!(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 2331 ccb->ccb_h.status |= CAM_DEV_QFRZN; 2332 xpt_freeze_devq(ccb->ccb_h.path, 1); 2333 } 2334 } 2335 } 2336 2337 /* 2338 * Set the status field of a CAM CCB. 2339 */ 2340 static __inline void sym_set_cam_status(union ccb *ccb, cam_status status) 2341 { 2342 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2343 ccb->ccb_h.status |= status; 2344 } 2345 2346 /* 2347 * Get the status field of a CAM CCB. 2348 */ 2349 static __inline int sym_get_cam_status(union ccb *ccb) 2350 { 2351 return ccb->ccb_h.status & CAM_STATUS_MASK; 2352 } 2353 2354 /* 2355 * Enqueue a CAM CCB. 2356 */ 2357 static void sym_enqueue_cam_ccb(hcb_p np, union ccb *ccb) 2358 { 2359 assert(!(ccb->ccb_h.status & CAM_SIM_QUEUED)); 2360 ccb->ccb_h.status = CAM_REQ_INPROG; 2361 2362 ccb->ccb_h.timeout_ch = timeout(sym_timeout, (caddr_t) ccb, 2363 ccb->ccb_h.timeout*hz/1000); 2364 ccb->ccb_h.status |= CAM_SIM_QUEUED; 2365 ccb->ccb_h.sym_hcb_ptr = np; 2366 2367 sym_insque_tail(sym_qptr(&ccb->ccb_h.sim_links), &np->cam_ccbq); 2368 } 2369 2370 /* 2371 * Complete a pending CAM CCB. 2372 */ 2373 static void sym_xpt_done(hcb_p np, union ccb *ccb) 2374 { 2375 if (ccb->ccb_h.status & CAM_SIM_QUEUED) { 2376 untimeout(sym_timeout, (caddr_t) ccb, ccb->ccb_h.timeout_ch); 2377 sym_remque(sym_qptr(&ccb->ccb_h.sim_links)); 2378 ccb->ccb_h.status &= ~CAM_SIM_QUEUED; 2379 ccb->ccb_h.sym_hcb_ptr = 0; 2380 } 2381 if (ccb->ccb_h.flags & CAM_DEV_QFREEZE) 2382 sym_freeze_cam_ccb(ccb); 2383 xpt_done(ccb); 2384 } 2385 2386 static void sym_xpt_done2(hcb_p np, union ccb *ccb, int cam_status) 2387 { 2388 sym_set_cam_status(ccb, cam_status); 2389 sym_xpt_done(np, ccb); 2390 } 2391 2392 /* 2393 * SYMBIOS chip clock divisor table. 2394 * 2395 * Divisors are multiplied by 10,000,000 in order to make 2396 * calculations more simple. 2397 */ 2398 #define _5M 5000000 2399 static u32 div_10M[] = {2*_5M, 3*_5M, 4*_5M, 6*_5M, 8*_5M, 12*_5M, 16*_5M}; 2400 2401 /* 2402 * SYMBIOS chips allow burst lengths of 2, 4, 8, 16, 32, 64, 2403 * 128 transfers. All chips support at least 16 transfers 2404 * bursts. The 825A, 875 and 895 chips support bursts of up 2405 * to 128 transfers and the 895A and 896 support bursts of up 2406 * to 64 transfers. All other chips support up to 16 2407 * transfers bursts. 2408 * 2409 * For PCI 32 bit data transfers each transfer is a DWORD. 2410 * It is a QUADWORD (8 bytes) for PCI 64 bit data transfers. 2411 * 2412 * We use log base 2 (burst length) as internal code, with 2413 * value 0 meaning "burst disabled". 2414 */ 2415 2416 /* 2417 * Burst length from burst code. 2418 */ 2419 #define burst_length(bc) (!(bc))? 0 : 1 << (bc) 2420 2421 /* 2422 * Burst code from io register bits. 2423 */ 2424 #define burst_code(dmode, ctest4, ctest5) \ 2425 (ctest4) & 0x80? 0 : (((dmode) & 0xc0) >> 6) + ((ctest5) & 0x04) + 1 2426 2427 /* 2428 * Set initial io register bits from burst code. 2429 */ 2430 static __inline void sym_init_burst(hcb_p np, u_char bc) 2431 { 2432 np->rv_ctest4 &= ~0x80; 2433 np->rv_dmode &= ~(0x3 << 6); 2434 np->rv_ctest5 &= ~0x4; 2435 2436 if (!bc) { 2437 np->rv_ctest4 |= 0x80; 2438 } 2439 else { 2440 --bc; 2441 np->rv_dmode |= ((bc & 0x3) << 6); 2442 np->rv_ctest5 |= (bc & 0x4); 2443 } 2444 } 2445 2446 2447 /* 2448 * Print out the list of targets that have some flag disabled by user. 2449 */ 2450 static void sym_print_targets_flag(hcb_p np, int mask, char *msg) 2451 { 2452 int cnt; 2453 int i; 2454 2455 for (cnt = 0, i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) { 2456 if (i == np->myaddr) 2457 continue; 2458 if (np->target[i].usrflags & mask) { 2459 if (!cnt++) 2460 printf("%s: %s disabled for targets", 2461 sym_name(np), msg); 2462 printf(" %d", i); 2463 } 2464 } 2465 if (cnt) 2466 printf(".\n"); 2467 } 2468 2469 /* 2470 * Save initial settings of some IO registers. 2471 * Assumed to have been set by BIOS. 2472 * We cannot reset the chip prior to reading the 2473 * IO registers, since informations will be lost. 2474 * Since the SCRIPTS processor may be running, this 2475 * is not safe on paper, but it seems to work quite 2476 * well. :) 2477 */ 2478 static void sym_save_initial_setting (hcb_p np) 2479 { 2480 np->sv_scntl0 = INB(nc_scntl0) & 0x0a; 2481 np->sv_scntl3 = INB(nc_scntl3) & 0x07; 2482 np->sv_dmode = INB(nc_dmode) & 0xce; 2483 np->sv_dcntl = INB(nc_dcntl) & 0xa8; 2484 np->sv_ctest3 = INB(nc_ctest3) & 0x01; 2485 np->sv_ctest4 = INB(nc_ctest4) & 0x80; 2486 np->sv_gpcntl = INB(nc_gpcntl); 2487 np->sv_stest1 = INB(nc_stest1); 2488 np->sv_stest2 = INB(nc_stest2) & 0x20; 2489 np->sv_stest4 = INB(nc_stest4); 2490 if (np->features & FE_C10) { /* Always large DMA fifo + ultra3 */ 2491 np->sv_scntl4 = INB(nc_scntl4); 2492 np->sv_ctest5 = INB(nc_ctest5) & 0x04; 2493 } 2494 else 2495 np->sv_ctest5 = INB(nc_ctest5) & 0x24; 2496 } 2497 2498 /* 2499 * Prepare io register values used by sym_init() according 2500 * to selected and supported features. 2501 */ 2502 static int sym_prepare_setting(hcb_p np, struct sym_nvram *nvram) 2503 { 2504 u_char burst_max; 2505 u32 period; 2506 int i; 2507 2508 /* 2509 * Wide ? 2510 */ 2511 np->maxwide = (np->features & FE_WIDE)? 1 : 0; 2512 2513 /* 2514 * Get the frequency of the chip's clock. 2515 */ 2516 if (np->features & FE_QUAD) 2517 np->multiplier = 4; 2518 else if (np->features & FE_DBLR) 2519 np->multiplier = 2; 2520 else 2521 np->multiplier = 1; 2522 2523 np->clock_khz = (np->features & FE_CLK80)? 80000 : 40000; 2524 np->clock_khz *= np->multiplier; 2525 2526 if (np->clock_khz != 40000) 2527 sym_getclock(np, np->multiplier); 2528 2529 /* 2530 * Divisor to be used for async (timer pre-scaler). 2531 */ 2532 i = np->clock_divn - 1; 2533 while (--i >= 0) { 2534 if (10ul * SYM_CONF_MIN_ASYNC * np->clock_khz > div_10M[i]) { 2535 ++i; 2536 break; 2537 } 2538 } 2539 np->rv_scntl3 = i+1; 2540 2541 /* 2542 * The C1010 uses hardwired divisors for async. 2543 * So, we just throw away, the async. divisor.:-) 2544 */ 2545 if (np->features & FE_C10) 2546 np->rv_scntl3 = 0; 2547 2548 /* 2549 * Minimum synchronous period factor supported by the chip. 2550 * Btw, 'period' is in tenths of nanoseconds. 2551 */ 2552 period = (4 * div_10M[0] + np->clock_khz - 1) / np->clock_khz; 2553 if (period <= 250) np->minsync = 10; 2554 else if (period <= 303) np->minsync = 11; 2555 else if (period <= 500) np->minsync = 12; 2556 else np->minsync = (period + 40 - 1) / 40; 2557 2558 /* 2559 * Check against chip SCSI standard support (SCSI-2,ULTRA,ULTRA2). 2560 */ 2561 if (np->minsync < 25 && 2562 !(np->features & (FE_ULTRA|FE_ULTRA2|FE_ULTRA3))) 2563 np->minsync = 25; 2564 else if (np->minsync < 12 && 2565 !(np->features & (FE_ULTRA2|FE_ULTRA3))) 2566 np->minsync = 12; 2567 2568 /* 2569 * Maximum synchronous period factor supported by the chip. 2570 */ 2571 period = (11 * div_10M[np->clock_divn - 1]) / (4 * np->clock_khz); 2572 np->maxsync = period > 2540 ? 254 : period / 10; 2573 2574 /* 2575 * If chip is a C1010, guess the sync limits in DT mode. 2576 */ 2577 if ((np->features & (FE_C10|FE_ULTRA3)) == (FE_C10|FE_ULTRA3)) { 2578 if (np->clock_khz == 160000) { 2579 np->minsync_dt = 9; 2580 np->maxsync_dt = 50; 2581 np->maxoffs_dt = 62; 2582 } 2583 } 2584 2585 /* 2586 * 64 bit addressing (895A/896/1010) ? 2587 */ 2588 if (np->features & FE_DAC) 2589 #ifdef __LP64__ 2590 np->rv_ccntl1 |= (XTIMOD | EXTIBMV); 2591 #else 2592 np->rv_ccntl1 |= (DDAC); 2593 #endif 2594 2595 /* 2596 * Phase mismatch handled by SCRIPTS (895A/896/1010) ? 2597 */ 2598 if (np->features & FE_NOPM) 2599 np->rv_ccntl0 |= (ENPMJ); 2600 2601 /* 2602 * C1010 Errata. 2603 * In dual channel mode, contention occurs if internal cycles 2604 * are used. Disable internal cycles. 2605 */ 2606 if (np->device_id == PCI_ID_LSI53C1010 && 2607 np->revision_id < 0x2) 2608 np->rv_ccntl0 |= DILS; 2609 2610 /* 2611 * Select burst length (dwords) 2612 */ 2613 burst_max = SYM_SETUP_BURST_ORDER; 2614 if (burst_max == 255) 2615 burst_max = burst_code(np->sv_dmode, np->sv_ctest4, 2616 np->sv_ctest5); 2617 if (burst_max > 7) 2618 burst_max = 7; 2619 if (burst_max > np->maxburst) 2620 burst_max = np->maxburst; 2621 2622 /* 2623 * DEL 352 - 53C810 Rev x11 - Part Number 609-0392140 - ITEM 2. 2624 * This chip and the 860 Rev 1 may wrongly use PCI cache line 2625 * based transactions on LOAD/STORE instructions. So we have 2626 * to prevent these chips from using such PCI transactions in 2627 * this driver. The generic ncr driver that does not use 2628 * LOAD/STORE instructions does not need this work-around. 2629 */ 2630 if ((np->device_id == PCI_ID_SYM53C810 && 2631 np->revision_id >= 0x10 && np->revision_id <= 0x11) || 2632 (np->device_id == PCI_ID_SYM53C860 && 2633 np->revision_id <= 0x1)) 2634 np->features &= ~(FE_WRIE|FE_ERL|FE_ERMP); 2635 2636 /* 2637 * Select all supported special features. 2638 * If we are using on-board RAM for scripts, prefetch (PFEN) 2639 * does not help, but burst op fetch (BOF) does. 2640 * Disabling PFEN makes sure BOF will be used. 2641 */ 2642 if (np->features & FE_ERL) 2643 np->rv_dmode |= ERL; /* Enable Read Line */ 2644 if (np->features & FE_BOF) 2645 np->rv_dmode |= BOF; /* Burst Opcode Fetch */ 2646 if (np->features & FE_ERMP) 2647 np->rv_dmode |= ERMP; /* Enable Read Multiple */ 2648 #if 1 2649 if ((np->features & FE_PFEN) && !np->ram_ba) 2650 #else 2651 if (np->features & FE_PFEN) 2652 #endif 2653 np->rv_dcntl |= PFEN; /* Prefetch Enable */ 2654 if (np->features & FE_CLSE) 2655 np->rv_dcntl |= CLSE; /* Cache Line Size Enable */ 2656 if (np->features & FE_WRIE) 2657 np->rv_ctest3 |= WRIE; /* Write and Invalidate */ 2658 if (np->features & FE_DFS) 2659 np->rv_ctest5 |= DFS; /* Dma Fifo Size */ 2660 2661 /* 2662 * Select some other 2663 */ 2664 if (SYM_SETUP_PCI_PARITY) 2665 np->rv_ctest4 |= MPEE; /* Master parity checking */ 2666 if (SYM_SETUP_SCSI_PARITY) 2667 np->rv_scntl0 |= 0x0a; /* full arb., ena parity, par->ATN */ 2668 2669 /* 2670 * Get parity checking, host ID and verbose mode from NVRAM 2671 */ 2672 np->myaddr = 255; 2673 sym_nvram_setup_host (np, nvram); 2674 2675 /* 2676 * Get SCSI addr of host adapter (set by bios?). 2677 */ 2678 if (np->myaddr == 255) { 2679 np->myaddr = INB(nc_scid) & 0x07; 2680 if (!np->myaddr) 2681 np->myaddr = SYM_SETUP_HOST_ID; 2682 } 2683 2684 /* 2685 * Prepare initial io register bits for burst length 2686 */ 2687 sym_init_burst(np, burst_max); 2688 2689 /* 2690 * Set SCSI BUS mode. 2691 * - LVD capable chips (895/895A/896/1010) report the 2692 * current BUS mode through the STEST4 IO register. 2693 * - For previous generation chips (825/825A/875), 2694 * user has to tell us how to check against HVD, 2695 * since a 100% safe algorithm is not possible. 2696 */ 2697 np->scsi_mode = SMODE_SE; 2698 if (np->features & (FE_ULTRA2|FE_ULTRA3)) 2699 np->scsi_mode = (np->sv_stest4 & SMODE); 2700 else if (np->features & FE_DIFF) { 2701 if (SYM_SETUP_SCSI_DIFF == 1) { 2702 if (np->sv_scntl3) { 2703 if (np->sv_stest2 & 0x20) 2704 np->scsi_mode = SMODE_HVD; 2705 } 2706 else if (nvram->type == SYM_SYMBIOS_NVRAM) { 2707 if (!(INB(nc_gpreg) & 0x08)) 2708 np->scsi_mode = SMODE_HVD; 2709 } 2710 } 2711 else if (SYM_SETUP_SCSI_DIFF == 2) 2712 np->scsi_mode = SMODE_HVD; 2713 } 2714 if (np->scsi_mode == SMODE_HVD) 2715 np->rv_stest2 |= 0x20; 2716 2717 /* 2718 * Set LED support from SCRIPTS. 2719 * Ignore this feature for boards known to use a 2720 * specific GPIO wiring and for the 895A, 896 2721 * and 1010 that drive the LED directly. 2722 */ 2723 if ((SYM_SETUP_SCSI_LED || 2724 (nvram->type == SYM_SYMBIOS_NVRAM || 2725 (nvram->type == SYM_TEKRAM_NVRAM && 2726 np->device_id == PCI_ID_SYM53C895))) && 2727 !(np->features & FE_LEDC) && !(np->sv_gpcntl & 0x01)) 2728 np->features |= FE_LED0; 2729 2730 /* 2731 * Set irq mode. 2732 */ 2733 switch(SYM_SETUP_IRQ_MODE & 3) { 2734 case 2: 2735 np->rv_dcntl |= IRQM; 2736 break; 2737 case 1: 2738 np->rv_dcntl |= (np->sv_dcntl & IRQM); 2739 break; 2740 default: 2741 break; 2742 } 2743 2744 /* 2745 * Configure targets according to driver setup. 2746 * If NVRAM present get targets setup from NVRAM. 2747 */ 2748 for (i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) { 2749 tcb_p tp = &np->target[i]; 2750 2751 tp->tinfo.user.scsi_version = tp->tinfo.current.scsi_version= 2; 2752 tp->tinfo.user.spi_version = tp->tinfo.current.spi_version = 2; 2753 tp->tinfo.user.period = np->minsync; 2754 tp->tinfo.user.offset = np->maxoffs; 2755 tp->tinfo.user.width = np->maxwide ? BUS_16_BIT : BUS_8_BIT; 2756 tp->usrflags |= (SYM_DISC_ENABLED | SYM_TAGS_ENABLED); 2757 tp->usrtags = SYM_SETUP_MAX_TAG; 2758 2759 sym_nvram_setup_target (np, i, nvram); 2760 2761 /* 2762 * For now, guess PPR/DT support from the period 2763 * and BUS width. 2764 */ 2765 if (np->features & FE_ULTRA3) { 2766 if (tp->tinfo.user.period <= 9 && 2767 tp->tinfo.user.width == BUS_16_BIT) { 2768 tp->tinfo.user.options |= PPR_OPT_DT; 2769 tp->tinfo.user.offset = np->maxoffs_dt; 2770 tp->tinfo.user.spi_version = 3; 2771 } 2772 } 2773 2774 if (!tp->usrtags) 2775 tp->usrflags &= ~SYM_TAGS_ENABLED; 2776 } 2777 2778 /* 2779 * Let user know about the settings. 2780 */ 2781 i = nvram->type; 2782 printf("%s: %s NVRAM, ID %d, Fast-%d, %s, %s\n", sym_name(np), 2783 i == SYM_SYMBIOS_NVRAM ? "Symbios" : 2784 (i == SYM_TEKRAM_NVRAM ? "Tekram" : "No"), 2785 np->myaddr, 2786 (np->features & FE_ULTRA3) ? 80 : 2787 (np->features & FE_ULTRA2) ? 40 : 2788 (np->features & FE_ULTRA) ? 20 : 10, 2789 sym_scsi_bus_mode(np->scsi_mode), 2790 (np->rv_scntl0 & 0xa) ? "parity checking" : "NO parity"); 2791 /* 2792 * Tell him more on demand. 2793 */ 2794 if (sym_verbose) { 2795 printf("%s: %s IRQ line driver%s\n", 2796 sym_name(np), 2797 np->rv_dcntl & IRQM ? "totem pole" : "open drain", 2798 np->ram_ba ? ", using on-chip SRAM" : ""); 2799 printf("%s: using %s firmware.\n", sym_name(np), np->fw_name); 2800 if (np->features & FE_NOPM) 2801 printf("%s: handling phase mismatch from SCRIPTS.\n", 2802 sym_name(np)); 2803 } 2804 /* 2805 * And still more. 2806 */ 2807 if (sym_verbose > 1) { 2808 printf ("%s: initial SCNTL3/DMODE/DCNTL/CTEST3/4/5 = " 2809 "(hex) %02x/%02x/%02x/%02x/%02x/%02x\n", 2810 sym_name(np), np->sv_scntl3, np->sv_dmode, np->sv_dcntl, 2811 np->sv_ctest3, np->sv_ctest4, np->sv_ctest5); 2812 2813 printf ("%s: final SCNTL3/DMODE/DCNTL/CTEST3/4/5 = " 2814 "(hex) %02x/%02x/%02x/%02x/%02x/%02x\n", 2815 sym_name(np), np->rv_scntl3, np->rv_dmode, np->rv_dcntl, 2816 np->rv_ctest3, np->rv_ctest4, np->rv_ctest5); 2817 } 2818 /* 2819 * Let user be aware of targets that have some disable flags set. 2820 */ 2821 sym_print_targets_flag(np, SYM_SCAN_BOOT_DISABLED, "SCAN AT BOOT"); 2822 if (sym_verbose) 2823 sym_print_targets_flag(np, SYM_SCAN_LUNS_DISABLED, 2824 "SCAN FOR LUNS"); 2825 2826 return 0; 2827 } 2828 2829 /* 2830 * Prepare the next negotiation message if needed. 2831 * 2832 * Fill in the part of message buffer that contains the 2833 * negotiation and the nego_status field of the CCB. 2834 * Returns the size of the message in bytes. 2835 */ 2836 2837 static int sym_prepare_nego(hcb_p np, ccb_p cp, int nego, u_char *msgptr) 2838 { 2839 tcb_p tp = &np->target[cp->target]; 2840 int msglen = 0; 2841 2842 /* 2843 * Early C1010 chips need a work-around for DT 2844 * data transfer to work. 2845 */ 2846 if (!(np->features & FE_U3EN)) 2847 tp->tinfo.goal.options = 0; 2848 /* 2849 * negotiate using PPR ? 2850 */ 2851 if (tp->tinfo.goal.options & PPR_OPT_MASK) 2852 nego = NS_PPR; 2853 /* 2854 * negotiate wide transfers ? 2855 */ 2856 else if (tp->tinfo.current.width != tp->tinfo.goal.width) 2857 nego = NS_WIDE; 2858 /* 2859 * negotiate synchronous transfers? 2860 */ 2861 else if (tp->tinfo.current.period != tp->tinfo.goal.period || 2862 tp->tinfo.current.offset != tp->tinfo.goal.offset) 2863 nego = NS_SYNC; 2864 2865 switch (nego) { 2866 case NS_SYNC: 2867 msgptr[msglen++] = M_EXTENDED; 2868 msgptr[msglen++] = 3; 2869 msgptr[msglen++] = M_X_SYNC_REQ; 2870 msgptr[msglen++] = tp->tinfo.goal.period; 2871 msgptr[msglen++] = tp->tinfo.goal.offset; 2872 break; 2873 case NS_WIDE: 2874 msgptr[msglen++] = M_EXTENDED; 2875 msgptr[msglen++] = 2; 2876 msgptr[msglen++] = M_X_WIDE_REQ; 2877 msgptr[msglen++] = tp->tinfo.goal.width; 2878 break; 2879 case NS_PPR: 2880 msgptr[msglen++] = M_EXTENDED; 2881 msgptr[msglen++] = 6; 2882 msgptr[msglen++] = M_X_PPR_REQ; 2883 msgptr[msglen++] = tp->tinfo.goal.period; 2884 msgptr[msglen++] = 0; 2885 msgptr[msglen++] = tp->tinfo.goal.offset; 2886 msgptr[msglen++] = tp->tinfo.goal.width; 2887 msgptr[msglen++] = tp->tinfo.goal.options & PPR_OPT_DT; 2888 break; 2889 }; 2890 2891 cp->nego_status = nego; 2892 2893 if (nego) { 2894 tp->nego_cp = cp; /* Keep track a nego will be performed */ 2895 if (DEBUG_FLAGS & DEBUG_NEGO) { 2896 sym_print_msg(cp, nego == NS_SYNC ? "sync msgout" : 2897 nego == NS_WIDE ? "wide msgout" : 2898 "ppr msgout", msgptr); 2899 }; 2900 }; 2901 2902 return msglen; 2903 } 2904 2905 /* 2906 * Insert a job into the start queue. 2907 */ 2908 static void sym_put_start_queue(hcb_p np, ccb_p cp) 2909 { 2910 u_short qidx; 2911 2912 #ifdef SYM_CONF_IARB_SUPPORT 2913 /* 2914 * If the previously queued CCB is not yet done, 2915 * set the IARB hint. The SCRIPTS will go with IARB 2916 * for this job when starting the previous one. 2917 * We leave devices a chance to win arbitration by 2918 * not using more than 'iarb_max' consecutive 2919 * immediate arbitrations. 2920 */ 2921 if (np->last_cp && np->iarb_count < np->iarb_max) { 2922 np->last_cp->host_flags |= HF_HINT_IARB; 2923 ++np->iarb_count; 2924 } 2925 else 2926 np->iarb_count = 0; 2927 np->last_cp = cp; 2928 #endif 2929 2930 /* 2931 * Insert first the idle task and then our job. 2932 * The MB should ensure proper ordering. 2933 */ 2934 qidx = np->squeueput + 2; 2935 if (qidx >= MAX_QUEUE*2) qidx = 0; 2936 2937 np->squeue [qidx] = cpu_to_scr(np->idletask_ba); 2938 MEMORY_BARRIER(); 2939 np->squeue [np->squeueput] = cpu_to_scr(cp->ccb_ba); 2940 2941 np->squeueput = qidx; 2942 2943 if (DEBUG_FLAGS & DEBUG_QUEUE) 2944 printf ("%s: queuepos=%d.\n", sym_name (np), np->squeueput); 2945 2946 /* 2947 * Script processor may be waiting for reselect. 2948 * Wake it up. 2949 */ 2950 MEMORY_BARRIER(); 2951 OUTB (nc_istat, SIGP|np->istat_sem); 2952 } 2953 2954 2955 /* 2956 * Soft reset the chip. 2957 * 2958 * Raising SRST when the chip is running may cause 2959 * problems on dual function chips (see below). 2960 * On the other hand, LVD devices need some delay 2961 * to settle and report actual BUS mode in STEST4. 2962 */ 2963 static void sym_chip_reset (hcb_p np) 2964 { 2965 OUTB (nc_istat, SRST); 2966 UDELAY (10); 2967 OUTB (nc_istat, 0); 2968 UDELAY(2000); /* For BUS MODE to settle */ 2969 } 2970 2971 /* 2972 * Soft reset the chip. 2973 * 2974 * Some 896 and 876 chip revisions may hang-up if we set 2975 * the SRST (soft reset) bit at the wrong time when SCRIPTS 2976 * are running. 2977 * So, we need to abort the current operation prior to 2978 * soft resetting the chip. 2979 */ 2980 static void sym_soft_reset (hcb_p np) 2981 { 2982 u_char istat; 2983 int i; 2984 2985 OUTB (nc_istat, CABRT); 2986 for (i = 1000000 ; i ; --i) { 2987 istat = INB (nc_istat); 2988 if (istat & SIP) { 2989 INW (nc_sist); 2990 continue; 2991 } 2992 if (istat & DIP) { 2993 OUTB (nc_istat, 0); 2994 INB (nc_dstat); 2995 break; 2996 } 2997 } 2998 if (!i) 2999 printf("%s: unable to abort current chip operation.\n", 3000 sym_name(np)); 3001 sym_chip_reset (np); 3002 } 3003 3004 /* 3005 * Start reset process. 3006 * 3007 * The interrupt handler will reinitialize the chip. 3008 */ 3009 static void sym_start_reset(hcb_p np) 3010 { 3011 (void) sym_reset_scsi_bus(np, 1); 3012 } 3013 3014 static int sym_reset_scsi_bus(hcb_p np, int enab_int) 3015 { 3016 u32 term; 3017 int retv = 0; 3018 3019 sym_soft_reset(np); /* Soft reset the chip */ 3020 if (enab_int) 3021 OUTW (nc_sien, RST); 3022 /* 3023 * Enable Tolerant, reset IRQD if present and 3024 * properly set IRQ mode, prior to resetting the bus. 3025 */ 3026 OUTB (nc_stest3, TE); 3027 OUTB (nc_dcntl, (np->rv_dcntl & IRQM)); 3028 OUTB (nc_scntl1, CRST); 3029 UDELAY (200); 3030 3031 if (!SYM_SETUP_SCSI_BUS_CHECK) 3032 goto out; 3033 /* 3034 * Check for no terminators or SCSI bus shorts to ground. 3035 * Read SCSI data bus, data parity bits and control signals. 3036 * We are expecting RESET to be TRUE and other signals to be 3037 * FALSE. 3038 */ 3039 term = INB(nc_sstat0); 3040 term = ((term & 2) << 7) + ((term & 1) << 17); /* rst sdp0 */ 3041 term |= ((INB(nc_sstat2) & 0x01) << 26) | /* sdp1 */ 3042 ((INW(nc_sbdl) & 0xff) << 9) | /* d7-0 */ 3043 ((INW(nc_sbdl) & 0xff00) << 10) | /* d15-8 */ 3044 INB(nc_sbcl); /* req ack bsy sel atn msg cd io */ 3045 3046 if (!(np->features & FE_WIDE)) 3047 term &= 0x3ffff; 3048 3049 if (term != (2<<7)) { 3050 printf("%s: suspicious SCSI data while resetting the BUS.\n", 3051 sym_name(np)); 3052 printf("%s: %sdp0,d7-0,rst,req,ack,bsy,sel,atn,msg,c/d,i/o = " 3053 "0x%lx, expecting 0x%lx\n", 3054 sym_name(np), 3055 (np->features & FE_WIDE) ? "dp1,d15-8," : "", 3056 (u_long)term, (u_long)(2<<7)); 3057 if (SYM_SETUP_SCSI_BUS_CHECK == 1) 3058 retv = 1; 3059 } 3060 out: 3061 OUTB (nc_scntl1, 0); 3062 /* MDELAY(100); */ 3063 return retv; 3064 } 3065 3066 /* 3067 * The chip may have completed jobs. Look at the DONE QUEUE. 3068 * 3069 * On architectures that may reorder LOAD/STORE operations, 3070 * a memory barrier may be needed after the reading of the 3071 * so-called `flag' and prior to dealing with the data. 3072 */ 3073 static int sym_wakeup_done (hcb_p np) 3074 { 3075 ccb_p cp; 3076 int i, n; 3077 u32 dsa; 3078 3079 n = 0; 3080 i = np->dqueueget; 3081 while (1) { 3082 dsa = scr_to_cpu(np->dqueue[i]); 3083 if (!dsa) 3084 break; 3085 np->dqueue[i] = 0; 3086 if ((i = i+2) >= MAX_QUEUE*2) 3087 i = 0; 3088 3089 cp = sym_ccb_from_dsa(np, dsa); 3090 if (cp) { 3091 MEMORY_BARRIER(); 3092 sym_complete_ok (np, cp); 3093 ++n; 3094 } 3095 else 3096 printf ("%s: bad DSA (%x) in done queue.\n", 3097 sym_name(np), (u_int) dsa); 3098 } 3099 np->dqueueget = i; 3100 3101 return n; 3102 } 3103 3104 /* 3105 * Complete all active CCBs with error. 3106 * Used on CHIP/SCSI RESET. 3107 */ 3108 static void sym_flush_busy_queue (hcb_p np, int cam_status) 3109 { 3110 /* 3111 * Move all active CCBs to the COMP queue 3112 * and flush this queue. 3113 */ 3114 sym_que_splice(&np->busy_ccbq, &np->comp_ccbq); 3115 sym_que_init(&np->busy_ccbq); 3116 sym_flush_comp_queue(np, cam_status); 3117 } 3118 3119 /* 3120 * Start chip. 3121 * 3122 * 'reason' means: 3123 * 0: initialisation. 3124 * 1: SCSI BUS RESET delivered or received. 3125 * 2: SCSI BUS MODE changed. 3126 */ 3127 static void sym_init (hcb_p np, int reason) 3128 { 3129 int i; 3130 u32 phys; 3131 3132 /* 3133 * Reset chip if asked, otherwise just clear fifos. 3134 */ 3135 if (reason == 1) 3136 sym_soft_reset(np); 3137 else { 3138 OUTB (nc_stest3, TE|CSF); 3139 OUTONB (nc_ctest3, CLF); 3140 } 3141 3142 /* 3143 * Clear Start Queue 3144 */ 3145 phys = np->squeue_ba; 3146 for (i = 0; i < MAX_QUEUE*2; i += 2) { 3147 np->squeue[i] = cpu_to_scr(np->idletask_ba); 3148 np->squeue[i+1] = cpu_to_scr(phys + (i+2)*4); 3149 } 3150 np->squeue[MAX_QUEUE*2-1] = cpu_to_scr(phys); 3151 3152 /* 3153 * Start at first entry. 3154 */ 3155 np->squeueput = 0; 3156 3157 /* 3158 * Clear Done Queue 3159 */ 3160 phys = np->dqueue_ba; 3161 for (i = 0; i < MAX_QUEUE*2; i += 2) { 3162 np->dqueue[i] = 0; 3163 np->dqueue[i+1] = cpu_to_scr(phys + (i+2)*4); 3164 } 3165 np->dqueue[MAX_QUEUE*2-1] = cpu_to_scr(phys); 3166 3167 /* 3168 * Start at first entry. 3169 */ 3170 np->dqueueget = 0; 3171 3172 /* 3173 * Install patches in scripts. 3174 * This also let point to first position the start 3175 * and done queue pointers used from SCRIPTS. 3176 */ 3177 np->fw_patch(np); 3178 3179 /* 3180 * Wakeup all pending jobs. 3181 */ 3182 sym_flush_busy_queue(np, CAM_SCSI_BUS_RESET); 3183 3184 /* 3185 * Init chip. 3186 */ 3187 OUTB (nc_istat, 0x00 ); /* Remove Reset, abort */ 3188 UDELAY (2000); /* The 895 needs time for the bus mode to settle */ 3189 3190 OUTB (nc_scntl0, np->rv_scntl0 | 0xc0); 3191 /* full arb., ena parity, par->ATN */ 3192 OUTB (nc_scntl1, 0x00); /* odd parity, and remove CRST!! */ 3193 3194 sym_selectclock(np, np->rv_scntl3); /* Select SCSI clock */ 3195 3196 OUTB (nc_scid , RRE|np->myaddr); /* Adapter SCSI address */ 3197 OUTW (nc_respid, 1ul<<np->myaddr); /* Id to respond to */ 3198 OUTB (nc_istat , SIGP ); /* Signal Process */ 3199 OUTB (nc_dmode , np->rv_dmode); /* Burst length, dma mode */ 3200 OUTB (nc_ctest5, np->rv_ctest5); /* Large fifo + large burst */ 3201 3202 OUTB (nc_dcntl , NOCOM|np->rv_dcntl); /* Protect SFBR */ 3203 OUTB (nc_ctest3, np->rv_ctest3); /* Write and invalidate */ 3204 OUTB (nc_ctest4, np->rv_ctest4); /* Master parity checking */ 3205 3206 /* Extended Sreq/Sack filtering not supported on the C10 */ 3207 if (np->features & FE_C10) 3208 OUTB (nc_stest2, np->rv_stest2); 3209 else 3210 OUTB (nc_stest2, EXT|np->rv_stest2); 3211 3212 OUTB (nc_stest3, TE); /* TolerANT enable */ 3213 OUTB (nc_stime0, 0x0c); /* HTH disabled STO 0.25 sec */ 3214 3215 /* 3216 * For now, disable AIP generation on C1010-66. 3217 */ 3218 if (np->device_id == PCI_ID_LSI53C1010_2) 3219 OUTB (nc_aipcntl1, DISAIP); 3220 3221 /* 3222 * C10101 Errata. 3223 * Errant SGE's when in narrow. Write bits 4 & 5 of 3224 * STEST1 register to disable SGE. We probably should do 3225 * that from SCRIPTS for each selection/reselection, but 3226 * I just don't want. :) 3227 */ 3228 if (np->device_id == PCI_ID_LSI53C1010 && 3229 /* np->revision_id < 0xff */ 1) 3230 OUTB (nc_stest1, INB(nc_stest1) | 0x30); 3231 3232 /* 3233 * DEL 441 - 53C876 Rev 5 - Part Number 609-0392787/2788 - ITEM 2. 3234 * Disable overlapped arbitration for some dual function devices, 3235 * regardless revision id (kind of post-chip-design feature. ;-)) 3236 */ 3237 if (np->device_id == PCI_ID_SYM53C875) 3238 OUTB (nc_ctest0, (1<<5)); 3239 else if (np->device_id == PCI_ID_SYM53C896) 3240 np->rv_ccntl0 |= DPR; 3241 3242 /* 3243 * Write CCNTL0/CCNTL1 for chips capable of 64 bit addressing 3244 * and/or hardware phase mismatch, since only such chips 3245 * seem to support those IO registers. 3246 */ 3247 if (np->features & (FE_DAC|FE_NOPM)) { 3248 OUTB (nc_ccntl0, np->rv_ccntl0); 3249 OUTB (nc_ccntl1, np->rv_ccntl1); 3250 } 3251 3252 /* 3253 * If phase mismatch handled by scripts (895A/896/1010), 3254 * set PM jump addresses. 3255 */ 3256 if (np->features & FE_NOPM) { 3257 OUTL (nc_pmjad1, SCRIPTB_BA (np, pm_handle)); 3258 OUTL (nc_pmjad2, SCRIPTB_BA (np, pm_handle)); 3259 } 3260 3261 /* 3262 * Enable GPIO0 pin for writing if LED support from SCRIPTS. 3263 * Also set GPIO5 and clear GPIO6 if hardware LED control. 3264 */ 3265 if (np->features & FE_LED0) 3266 OUTB(nc_gpcntl, INB(nc_gpcntl) & ~0x01); 3267 else if (np->features & FE_LEDC) 3268 OUTB(nc_gpcntl, (INB(nc_gpcntl) & ~0x41) | 0x20); 3269 3270 /* 3271 * enable ints 3272 */ 3273 OUTW (nc_sien , STO|HTH|MA|SGE|UDC|RST|PAR); 3274 OUTB (nc_dien , MDPE|BF|SSI|SIR|IID); 3275 3276 /* 3277 * For 895/6 enable SBMC interrupt and save current SCSI bus mode. 3278 * Try to eat the spurious SBMC interrupt that may occur when 3279 * we reset the chip but not the SCSI BUS (at initialization). 3280 */ 3281 if (np->features & (FE_ULTRA2|FE_ULTRA3)) { 3282 OUTONW (nc_sien, SBMC); 3283 if (reason == 0) { 3284 MDELAY(100); 3285 INW (nc_sist); 3286 } 3287 np->scsi_mode = INB (nc_stest4) & SMODE; 3288 } 3289 3290 /* 3291 * Fill in target structure. 3292 * Reinitialize usrsync. 3293 * Reinitialize usrwide. 3294 * Prepare sync negotiation according to actual SCSI bus mode. 3295 */ 3296 for (i=0;i<SYM_CONF_MAX_TARGET;i++) { 3297 tcb_p tp = &np->target[i]; 3298 3299 tp->to_reset = 0; 3300 tp->head.sval = 0; 3301 tp->head.wval = np->rv_scntl3; 3302 tp->head.uval = 0; 3303 3304 tp->tinfo.current.period = 0; 3305 tp->tinfo.current.offset = 0; 3306 tp->tinfo.current.width = BUS_8_BIT; 3307 tp->tinfo.current.options = 0; 3308 } 3309 3310 /* 3311 * Download SCSI SCRIPTS to on-chip RAM if present, 3312 * and start script processor. 3313 */ 3314 if (np->ram_ba) { 3315 if (sym_verbose > 1) 3316 printf ("%s: Downloading SCSI SCRIPTS.\n", 3317 sym_name(np)); 3318 if (np->ram_ws == 8192) { 3319 OUTRAM_OFF(4096, np->scriptb0, np->scriptb_sz); 3320 OUTL (nc_mmws, np->scr_ram_seg); 3321 OUTL (nc_mmrs, np->scr_ram_seg); 3322 OUTL (nc_sfs, np->scr_ram_seg); 3323 phys = SCRIPTB_BA (np, start64); 3324 } 3325 else 3326 phys = SCRIPTA_BA (np, init); 3327 OUTRAM_OFF(0, np->scripta0, np->scripta_sz); 3328 } 3329 else 3330 phys = SCRIPTA_BA (np, init); 3331 3332 np->istat_sem = 0; 3333 3334 OUTL (nc_dsa, np->hcb_ba); 3335 OUTL_DSP (phys); 3336 3337 /* 3338 * Notify the XPT about the RESET condition. 3339 */ 3340 if (reason != 0) 3341 xpt_async(AC_BUS_RESET, np->path, NULL); 3342 } 3343 3344 /* 3345 * Get clock factor and sync divisor for a given 3346 * synchronous factor period. 3347 */ 3348 static int 3349 sym_getsync(hcb_p np, u_char dt, u_char sfac, u_char *divp, u_char *fakp) 3350 { 3351 u32 clk = np->clock_khz; /* SCSI clock frequency in kHz */ 3352 int div = np->clock_divn; /* Number of divisors supported */ 3353 u32 fak; /* Sync factor in sxfer */ 3354 u32 per; /* Period in tenths of ns */ 3355 u32 kpc; /* (per * clk) */ 3356 int ret; 3357 3358 /* 3359 * Compute the synchronous period in tenths of nano-seconds 3360 */ 3361 if (dt && sfac <= 9) per = 125; 3362 else if (sfac <= 10) per = 250; 3363 else if (sfac == 11) per = 303; 3364 else if (sfac == 12) per = 500; 3365 else per = 40 * sfac; 3366 ret = per; 3367 3368 kpc = per * clk; 3369 if (dt) 3370 kpc <<= 1; 3371 3372 /* 3373 * For earliest C10 revision 0, we cannot use extra 3374 * clocks for the setting of the SCSI clocking. 3375 * Note that this limits the lowest sync data transfer 3376 * to 5 Mega-transfers per second and may result in 3377 * using higher clock divisors. 3378 */ 3379 #if 1 3380 if ((np->features & (FE_C10|FE_U3EN)) == FE_C10) { 3381 /* 3382 * Look for the lowest clock divisor that allows an 3383 * output speed not faster than the period. 3384 */ 3385 while (div > 0) { 3386 --div; 3387 if (kpc > (div_10M[div] << 2)) { 3388 ++div; 3389 break; 3390 } 3391 } 3392 fak = 0; /* No extra clocks */ 3393 if (div == np->clock_divn) { /* Are we too fast ? */ 3394 ret = -1; 3395 } 3396 *divp = div; 3397 *fakp = fak; 3398 return ret; 3399 } 3400 #endif 3401 3402 /* 3403 * Look for the greatest clock divisor that allows an 3404 * input speed faster than the period. 3405 */ 3406 while (div-- > 0) 3407 if (kpc >= (div_10M[div] << 2)) break; 3408 3409 /* 3410 * Calculate the lowest clock factor that allows an output 3411 * speed not faster than the period, and the max output speed. 3412 * If fak >= 1 we will set both XCLKH_ST and XCLKH_DT. 3413 * If fak >= 2 we will also set XCLKS_ST and XCLKS_DT. 3414 */ 3415 if (dt) { 3416 fak = (kpc - 1) / (div_10M[div] << 1) + 1 - 2; 3417 /* ret = ((2+fak)*div_10M[div])/np->clock_khz; */ 3418 } 3419 else { 3420 fak = (kpc - 1) / div_10M[div] + 1 - 4; 3421 /* ret = ((4+fak)*div_10M[div])/np->clock_khz; */ 3422 } 3423 3424 /* 3425 * Check against our hardware limits, or bugs :). 3426 */ 3427 if (fak < 0) {fak = 0; ret = -1;} 3428 if (fak > 2) {fak = 2; ret = -1;} 3429 3430 /* 3431 * Compute and return sync parameters. 3432 */ 3433 *divp = div; 3434 *fakp = fak; 3435 3436 return ret; 3437 } 3438 3439 /* 3440 * Tell the SCSI layer about the new transfer parameters. 3441 */ 3442 static void 3443 sym_xpt_async_transfer_neg(hcb_p np, int target, u_int spi_valid) 3444 { 3445 struct ccb_trans_settings cts; 3446 struct cam_path *path; 3447 int sts; 3448 tcb_p tp = &np->target[target]; 3449 3450 sts = xpt_create_path(&path, NULL, cam_sim_path(np->sim), target, 3451 CAM_LUN_WILDCARD); 3452 if (sts != CAM_REQ_CMP) 3453 return; 3454 3455 bzero(&cts, sizeof(cts)); 3456 3457 #define cts__scsi (cts.proto_specific.scsi) 3458 #define cts__spi (cts.xport_specific.spi) 3459 3460 cts.type = CTS_TYPE_CURRENT_SETTINGS; 3461 cts.protocol = PROTO_SCSI; 3462 cts.transport = XPORT_SPI; 3463 cts.protocol_version = tp->tinfo.current.scsi_version; 3464 cts.transport_version = tp->tinfo.current.spi_version; 3465 3466 cts__spi.valid = spi_valid; 3467 if (spi_valid & CTS_SPI_VALID_SYNC_RATE) 3468 cts__spi.sync_period = tp->tinfo.current.period; 3469 if (spi_valid & CTS_SPI_VALID_SYNC_OFFSET) 3470 cts__spi.sync_offset = tp->tinfo.current.offset; 3471 if (spi_valid & CTS_SPI_VALID_BUS_WIDTH) 3472 cts__spi.bus_width = tp->tinfo.current.width; 3473 if (spi_valid & CTS_SPI_VALID_PPR_OPTIONS) 3474 cts__spi.ppr_options = tp->tinfo.current.options; 3475 #undef cts__spi 3476 #undef cts__scsi 3477 xpt_setup_ccb(&cts.ccb_h, path, /*priority*/1); 3478 xpt_async(AC_TRANSFER_NEG, path, &cts); 3479 xpt_free_path(path); 3480 } 3481 3482 #define SYM_SPI_VALID_WDTR \ 3483 CTS_SPI_VALID_BUS_WIDTH | \ 3484 CTS_SPI_VALID_SYNC_RATE | \ 3485 CTS_SPI_VALID_SYNC_OFFSET 3486 #define SYM_SPI_VALID_SDTR \ 3487 CTS_SPI_VALID_SYNC_RATE | \ 3488 CTS_SPI_VALID_SYNC_OFFSET 3489 #define SYM_SPI_VALID_PPR \ 3490 CTS_SPI_VALID_PPR_OPTIONS | \ 3491 CTS_SPI_VALID_BUS_WIDTH | \ 3492 CTS_SPI_VALID_SYNC_RATE | \ 3493 CTS_SPI_VALID_SYNC_OFFSET 3494 3495 /* 3496 * We received a WDTR. 3497 * Let everything be aware of the changes. 3498 */ 3499 static void sym_setwide(hcb_p np, ccb_p cp, u_char wide) 3500 { 3501 tcb_p tp = &np->target[cp->target]; 3502 3503 sym_settrans(np, cp, 0, 0, 0, wide, 0, 0); 3504 3505 /* 3506 * Tell the SCSI layer about the new transfer parameters. 3507 */ 3508 tp->tinfo.goal.width = tp->tinfo.current.width = wide; 3509 tp->tinfo.current.offset = 0; 3510 tp->tinfo.current.period = 0; 3511 tp->tinfo.current.options = 0; 3512 3513 sym_xpt_async_transfer_neg(np, cp->target, SYM_SPI_VALID_WDTR); 3514 } 3515 3516 /* 3517 * We received a SDTR. 3518 * Let everything be aware of the changes. 3519 */ 3520 static void 3521 sym_setsync(hcb_p np, ccb_p cp, u_char ofs, u_char per, u_char div, u_char fak) 3522 { 3523 tcb_p tp = &np->target[cp->target]; 3524 u_char wide = (cp->phys.select.sel_scntl3 & EWS) ? 1 : 0; 3525 3526 sym_settrans(np, cp, 0, ofs, per, wide, div, fak); 3527 3528 /* 3529 * Tell the SCSI layer about the new transfer parameters. 3530 */ 3531 tp->tinfo.goal.period = tp->tinfo.current.period = per; 3532 tp->tinfo.goal.offset = tp->tinfo.current.offset = ofs; 3533 tp->tinfo.goal.options = tp->tinfo.current.options = 0; 3534 3535 sym_xpt_async_transfer_neg(np, cp->target, SYM_SPI_VALID_SDTR); 3536 } 3537 3538 /* 3539 * We received a PPR. 3540 * Let everything be aware of the changes. 3541 */ 3542 static void sym_setpprot(hcb_p np, ccb_p cp, u_char dt, u_char ofs, 3543 u_char per, u_char wide, u_char div, u_char fak) 3544 { 3545 tcb_p tp = &np->target[cp->target]; 3546 3547 sym_settrans(np, cp, dt, ofs, per, wide, div, fak); 3548 3549 /* 3550 * Tell the SCSI layer about the new transfer parameters. 3551 */ 3552 tp->tinfo.goal.width = tp->tinfo.current.width = wide; 3553 tp->tinfo.goal.period = tp->tinfo.current.period = per; 3554 tp->tinfo.goal.offset = tp->tinfo.current.offset = ofs; 3555 tp->tinfo.goal.options = tp->tinfo.current.options = dt; 3556 3557 sym_xpt_async_transfer_neg(np, cp->target, SYM_SPI_VALID_PPR); 3558 } 3559 3560 /* 3561 * Switch trans mode for current job and it's target. 3562 */ 3563 static void sym_settrans(hcb_p np, ccb_p cp, u_char dt, u_char ofs, 3564 u_char per, u_char wide, u_char div, u_char fak) 3565 { 3566 SYM_QUEHEAD *qp; 3567 union ccb *ccb; 3568 tcb_p tp; 3569 u_char target = INB (nc_sdid) & 0x0f; 3570 u_char sval, wval, uval; 3571 3572 assert (cp); 3573 if (!cp) return; 3574 ccb = cp->cam_ccb; 3575 assert (ccb); 3576 if (!ccb) return; 3577 assert (target == (cp->target & 0xf)); 3578 tp = &np->target[target]; 3579 3580 sval = tp->head.sval; 3581 wval = tp->head.wval; 3582 uval = tp->head.uval; 3583 3584 #if 0 3585 printf("XXXX sval=%x wval=%x uval=%x (%x)\n", 3586 sval, wval, uval, np->rv_scntl3); 3587 #endif 3588 /* 3589 * Set the offset. 3590 */ 3591 if (!(np->features & FE_C10)) 3592 sval = (sval & ~0x1f) | ofs; 3593 else 3594 sval = (sval & ~0x3f) | ofs; 3595 3596 /* 3597 * Set the sync divisor and extra clock factor. 3598 */ 3599 if (ofs != 0) { 3600 wval = (wval & ~0x70) | ((div+1) << 4); 3601 if (!(np->features & FE_C10)) 3602 sval = (sval & ~0xe0) | (fak << 5); 3603 else { 3604 uval = uval & ~(XCLKH_ST|XCLKH_DT|XCLKS_ST|XCLKS_DT); 3605 if (fak >= 1) uval |= (XCLKH_ST|XCLKH_DT); 3606 if (fak >= 2) uval |= (XCLKS_ST|XCLKS_DT); 3607 } 3608 } 3609 3610 /* 3611 * Set the bus width. 3612 */ 3613 wval = wval & ~EWS; 3614 if (wide != 0) 3615 wval |= EWS; 3616 3617 /* 3618 * Set misc. ultra enable bits. 3619 */ 3620 if (np->features & FE_C10) { 3621 uval = uval & ~(U3EN|AIPCKEN); 3622 if (dt) { 3623 assert(np->features & FE_U3EN); 3624 uval |= U3EN; 3625 } 3626 } 3627 else { 3628 wval = wval & ~ULTRA; 3629 if (per <= 12) wval |= ULTRA; 3630 } 3631 3632 /* 3633 * Stop there if sync parameters are unchanged. 3634 */ 3635 if (tp->head.sval == sval && 3636 tp->head.wval == wval && 3637 tp->head.uval == uval) 3638 return; 3639 tp->head.sval = sval; 3640 tp->head.wval = wval; 3641 tp->head.uval = uval; 3642 3643 /* 3644 * Disable extended Sreq/Sack filtering if per < 50. 3645 * Not supported on the C1010. 3646 */ 3647 if (per < 50 && !(np->features & FE_C10)) 3648 OUTOFFB (nc_stest2, EXT); 3649 3650 /* 3651 * set actual value and sync_status 3652 */ 3653 OUTB (nc_sxfer, tp->head.sval); 3654 OUTB (nc_scntl3, tp->head.wval); 3655 3656 if (np->features & FE_C10) { 3657 OUTB (nc_scntl4, tp->head.uval); 3658 } 3659 3660 /* 3661 * patch ALL busy ccbs of this target. 3662 */ 3663 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) { 3664 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 3665 if (cp->target != target) 3666 continue; 3667 cp->phys.select.sel_scntl3 = tp->head.wval; 3668 cp->phys.select.sel_sxfer = tp->head.sval; 3669 if (np->features & FE_C10) { 3670 cp->phys.select.sel_scntl4 = tp->head.uval; 3671 } 3672 } 3673 } 3674 3675 /* 3676 * log message for real hard errors 3677 * 3678 * sym0 targ 0?: ERROR (ds:si) (so-si-sd) (sxfer/scntl3) @ name (dsp:dbc). 3679 * reg: r0 r1 r2 r3 r4 r5 r6 ..... rf. 3680 * 3681 * exception register: 3682 * ds: dstat 3683 * si: sist 3684 * 3685 * SCSI bus lines: 3686 * so: control lines as driven by chip. 3687 * si: control lines as seen by chip. 3688 * sd: scsi data lines as seen by chip. 3689 * 3690 * wide/fastmode: 3691 * sxfer: (see the manual) 3692 * scntl3: (see the manual) 3693 * 3694 * current script command: 3695 * dsp: script address (relative to start of script). 3696 * dbc: first word of script command. 3697 * 3698 * First 24 register of the chip: 3699 * r0..rf 3700 */ 3701 static void sym_log_hard_error(hcb_p np, u_short sist, u_char dstat) 3702 { 3703 u32 dsp; 3704 int script_ofs; 3705 int script_size; 3706 char *script_name; 3707 u_char *script_base; 3708 int i; 3709 3710 dsp = INL (nc_dsp); 3711 3712 if (dsp > np->scripta_ba && 3713 dsp <= np->scripta_ba + np->scripta_sz) { 3714 script_ofs = dsp - np->scripta_ba; 3715 script_size = np->scripta_sz; 3716 script_base = (u_char *) np->scripta0; 3717 script_name = "scripta"; 3718 } 3719 else if (np->scriptb_ba < dsp && 3720 dsp <= np->scriptb_ba + np->scriptb_sz) { 3721 script_ofs = dsp - np->scriptb_ba; 3722 script_size = np->scriptb_sz; 3723 script_base = (u_char *) np->scriptb0; 3724 script_name = "scriptb"; 3725 } else { 3726 script_ofs = dsp; 3727 script_size = 0; 3728 script_base = 0; 3729 script_name = "mem"; 3730 } 3731 3732 printf ("%s:%d: ERROR (%x:%x) (%x-%x-%x) (%x/%x) @ (%s %x:%08x).\n", 3733 sym_name (np), (unsigned)INB (nc_sdid)&0x0f, dstat, sist, 3734 (unsigned)INB (nc_socl), (unsigned)INB (nc_sbcl), 3735 (unsigned)INB (nc_sbdl), (unsigned)INB (nc_sxfer), 3736 (unsigned)INB (nc_scntl3), script_name, script_ofs, 3737 (unsigned)INL (nc_dbc)); 3738 3739 if (((script_ofs & 3) == 0) && 3740 (unsigned)script_ofs < script_size) { 3741 printf ("%s: script cmd = %08x\n", sym_name(np), 3742 scr_to_cpu((int) *(u32 *)(script_base + script_ofs))); 3743 } 3744 3745 printf ("%s: regdump:", sym_name(np)); 3746 for (i=0; i<24;i++) 3747 printf (" %02x", (unsigned)INB_OFF(i)); 3748 printf (".\n"); 3749 3750 /* 3751 * PCI BUS error, read the PCI ststus register. 3752 */ 3753 if (dstat & (MDPE|BF)) { 3754 u_short pci_sts; 3755 pci_sts = pci_read_config(np->device, PCIR_STATUS, 2); 3756 if (pci_sts & 0xf900) { 3757 pci_write_config(np->device, PCIR_STATUS, pci_sts, 2); 3758 printf("%s: PCI STATUS = 0x%04x\n", 3759 sym_name(np), pci_sts & 0xf900); 3760 } 3761 } 3762 } 3763 3764 /* 3765 * chip interrupt handler 3766 * 3767 * In normal situations, interrupt conditions occur one at 3768 * a time. But when something bad happens on the SCSI BUS, 3769 * the chip may raise several interrupt flags before 3770 * stopping and interrupting the CPU. The additionnal 3771 * interrupt flags are stacked in some extra registers 3772 * after the SIP and/or DIP flag has been raised in the 3773 * ISTAT. After the CPU has read the interrupt condition 3774 * flag from SIST or DSTAT, the chip unstacks the other 3775 * interrupt flags and sets the corresponding bits in 3776 * SIST or DSTAT. Since the chip starts stacking once the 3777 * SIP or DIP flag is set, there is a small window of time 3778 * where the stacking does not occur. 3779 * 3780 * Typically, multiple interrupt conditions may happen in 3781 * the following situations: 3782 * 3783 * - SCSI parity error + Phase mismatch (PAR|MA) 3784 * When a parity error is detected in input phase 3785 * and the device switches to msg-in phase inside a 3786 * block MOV. 3787 * - SCSI parity error + Unexpected disconnect (PAR|UDC) 3788 * When a stupid device does not want to handle the 3789 * recovery of an SCSI parity error. 3790 * - Some combinations of STO, PAR, UDC, ... 3791 * When using non compliant SCSI stuff, when user is 3792 * doing non compliant hot tampering on the BUS, when 3793 * something really bad happens to a device, etc ... 3794 * 3795 * The heuristic suggested by SYMBIOS to handle 3796 * multiple interrupts is to try unstacking all 3797 * interrupts conditions and to handle them on some 3798 * priority based on error severity. 3799 * This will work when the unstacking has been 3800 * successful, but we cannot be 100 % sure of that, 3801 * since the CPU may have been faster to unstack than 3802 * the chip is able to stack. Hmmm ... But it seems that 3803 * such a situation is very unlikely to happen. 3804 * 3805 * If this happen, for example STO caught by the CPU 3806 * then UDC happenning before the CPU have restarted 3807 * the SCRIPTS, the driver may wrongly complete the 3808 * same command on UDC, since the SCRIPTS didn't restart 3809 * and the DSA still points to the same command. 3810 * We avoid this situation by setting the DSA to an 3811 * invalid value when the CCB is completed and before 3812 * restarting the SCRIPTS. 3813 * 3814 * Another issue is that we need some section of our 3815 * recovery procedures to be somehow uninterruptible but 3816 * the SCRIPTS processor does not provides such a 3817 * feature. For this reason, we handle recovery preferently 3818 * from the C code and check against some SCRIPTS critical 3819 * sections from the C code. 3820 * 3821 * Hopefully, the interrupt handling of the driver is now 3822 * able to resist to weird BUS error conditions, but donnot 3823 * ask me for any guarantee that it will never fail. :-) 3824 * Use at your own decision and risk. 3825 */ 3826 3827 static void sym_intr1 (hcb_p np) 3828 { 3829 u_char istat, istatc; 3830 u_char dstat; 3831 u_short sist; 3832 3833 /* 3834 * interrupt on the fly ? 3835 * 3836 * A `dummy read' is needed to ensure that the 3837 * clear of the INTF flag reaches the device 3838 * before the scanning of the DONE queue. 3839 */ 3840 istat = INB (nc_istat); 3841 if (istat & INTF) { 3842 OUTB (nc_istat, (istat & SIGP) | INTF | np->istat_sem); 3843 istat = INB (nc_istat); /* DUMMY READ */ 3844 if (DEBUG_FLAGS & DEBUG_TINY) printf ("F "); 3845 (void)sym_wakeup_done (np); 3846 }; 3847 3848 if (!(istat & (SIP|DIP))) 3849 return; 3850 3851 #if 0 /* We should never get this one */ 3852 if (istat & CABRT) 3853 OUTB (nc_istat, CABRT); 3854 #endif 3855 3856 /* 3857 * PAR and MA interrupts may occur at the same time, 3858 * and we need to know of both in order to handle 3859 * this situation properly. We try to unstack SCSI 3860 * interrupts for that reason. BTW, I dislike a LOT 3861 * such a loop inside the interrupt routine. 3862 * Even if DMA interrupt stacking is very unlikely to 3863 * happen, we also try unstacking these ones, since 3864 * this has no performance impact. 3865 */ 3866 sist = 0; 3867 dstat = 0; 3868 istatc = istat; 3869 do { 3870 if (istatc & SIP) 3871 sist |= INW (nc_sist); 3872 if (istatc & DIP) 3873 dstat |= INB (nc_dstat); 3874 istatc = INB (nc_istat); 3875 istat |= istatc; 3876 } while (istatc & (SIP|DIP)); 3877 3878 if (DEBUG_FLAGS & DEBUG_TINY) 3879 printf ("<%d|%x:%x|%x:%x>", 3880 (int)INB(nc_scr0), 3881 dstat,sist, 3882 (unsigned)INL(nc_dsp), 3883 (unsigned)INL(nc_dbc)); 3884 /* 3885 * On paper, a memory barrier may be needed here. 3886 * And since we are paranoid ... :) 3887 */ 3888 MEMORY_BARRIER(); 3889 3890 /* 3891 * First, interrupts we want to service cleanly. 3892 * 3893 * Phase mismatch (MA) is the most frequent interrupt 3894 * for chip earlier than the 896 and so we have to service 3895 * it as quickly as possible. 3896 * A SCSI parity error (PAR) may be combined with a phase 3897 * mismatch condition (MA). 3898 * Programmed interrupts (SIR) are used to call the C code 3899 * from SCRIPTS. 3900 * The single step interrupt (SSI) is not used in this 3901 * driver. 3902 */ 3903 if (!(sist & (STO|GEN|HTH|SGE|UDC|SBMC|RST)) && 3904 !(dstat & (MDPE|BF|ABRT|IID))) { 3905 if (sist & PAR) sym_int_par (np, sist); 3906 else if (sist & MA) sym_int_ma (np); 3907 else if (dstat & SIR) sym_int_sir (np); 3908 else if (dstat & SSI) OUTONB_STD (); 3909 else goto unknown_int; 3910 return; 3911 }; 3912 3913 /* 3914 * Now, interrupts that donnot happen in normal 3915 * situations and that we may need to recover from. 3916 * 3917 * On SCSI RESET (RST), we reset everything. 3918 * On SCSI BUS MODE CHANGE (SBMC), we complete all 3919 * active CCBs with RESET status, prepare all devices 3920 * for negotiating again and restart the SCRIPTS. 3921 * On STO and UDC, we complete the CCB with the corres- 3922 * ponding status and restart the SCRIPTS. 3923 */ 3924 if (sist & RST) { 3925 xpt_print_path(np->path); 3926 printf("SCSI BUS reset detected.\n"); 3927 sym_init (np, 1); 3928 return; 3929 }; 3930 3931 OUTB (nc_ctest3, np->rv_ctest3 | CLF); /* clear dma fifo */ 3932 OUTB (nc_stest3, TE|CSF); /* clear scsi fifo */ 3933 3934 if (!(sist & (GEN|HTH|SGE)) && 3935 !(dstat & (MDPE|BF|ABRT|IID))) { 3936 if (sist & SBMC) sym_int_sbmc (np); 3937 else if (sist & STO) sym_int_sto (np); 3938 else if (sist & UDC) sym_int_udc (np); 3939 else goto unknown_int; 3940 return; 3941 }; 3942 3943 /* 3944 * Now, interrupts we are not able to recover cleanly. 3945 * 3946 * Log message for hard errors. 3947 * Reset everything. 3948 */ 3949 3950 sym_log_hard_error(np, sist, dstat); 3951 3952 if ((sist & (GEN|HTH|SGE)) || 3953 (dstat & (MDPE|BF|ABRT|IID))) { 3954 sym_start_reset(np); 3955 return; 3956 }; 3957 3958 unknown_int: 3959 /* 3960 * We just miss the cause of the interrupt. :( 3961 * Print a message. The timeout will do the real work. 3962 */ 3963 printf( "%s: unknown interrupt(s) ignored, " 3964 "ISTAT=0x%x DSTAT=0x%x SIST=0x%x\n", 3965 sym_name(np), istat, dstat, sist); 3966 } 3967 3968 static void sym_intr(void *arg) 3969 { 3970 if (DEBUG_FLAGS & DEBUG_TINY) printf ("["); 3971 sym_intr1((hcb_p) arg); 3972 if (DEBUG_FLAGS & DEBUG_TINY) printf ("]"); 3973 return; 3974 } 3975 3976 static void sym_poll(struct cam_sim *sim) 3977 { 3978 int s = splcam(); 3979 sym_intr(cam_sim_softc(sim)); 3980 splx(s); 3981 } 3982 3983 3984 /* 3985 * generic recovery from scsi interrupt 3986 * 3987 * The doc says that when the chip gets an SCSI interrupt, 3988 * it tries to stop in an orderly fashion, by completing 3989 * an instruction fetch that had started or by flushing 3990 * the DMA fifo for a write to memory that was executing. 3991 * Such a fashion is not enough to know if the instruction 3992 * that was just before the current DSP value has been 3993 * executed or not. 3994 * 3995 * There are some small SCRIPTS sections that deal with 3996 * the start queue and the done queue that may break any 3997 * assomption from the C code if we are interrupted 3998 * inside, so we reset if this happens. Btw, since these 3999 * SCRIPTS sections are executed while the SCRIPTS hasn't 4000 * started SCSI operations, it is very unlikely to happen. 4001 * 4002 * All the driver data structures are supposed to be 4003 * allocated from the same 4 GB memory window, so there 4004 * is a 1 to 1 relationship between DSA and driver data 4005 * structures. Since we are careful :) to invalidate the 4006 * DSA when we complete a command or when the SCRIPTS 4007 * pushes a DSA into a queue, we can trust it when it 4008 * points to a CCB. 4009 */ 4010 static void sym_recover_scsi_int (hcb_p np, u_char hsts) 4011 { 4012 u32 dsp = INL (nc_dsp); 4013 u32 dsa = INL (nc_dsa); 4014 ccb_p cp = sym_ccb_from_dsa(np, dsa); 4015 4016 /* 4017 * If we haven't been interrupted inside the SCRIPTS 4018 * critical pathes, we can safely restart the SCRIPTS 4019 * and trust the DSA value if it matches a CCB. 4020 */ 4021 if ((!(dsp > SCRIPTA_BA (np, getjob_begin) && 4022 dsp < SCRIPTA_BA (np, getjob_end) + 1)) && 4023 (!(dsp > SCRIPTA_BA (np, ungetjob) && 4024 dsp < SCRIPTA_BA (np, reselect) + 1)) && 4025 (!(dsp > SCRIPTB_BA (np, sel_for_abort) && 4026 dsp < SCRIPTB_BA (np, sel_for_abort_1) + 1)) && 4027 (!(dsp > SCRIPTA_BA (np, done) && 4028 dsp < SCRIPTA_BA (np, done_end) + 1))) { 4029 OUTB (nc_ctest3, np->rv_ctest3 | CLF); /* clear dma fifo */ 4030 OUTB (nc_stest3, TE|CSF); /* clear scsi fifo */ 4031 /* 4032 * If we have a CCB, let the SCRIPTS call us back for 4033 * the handling of the error with SCRATCHA filled with 4034 * STARTPOS. This way, we will be able to freeze the 4035 * device queue and requeue awaiting IOs. 4036 */ 4037 if (cp) { 4038 cp->host_status = hsts; 4039 OUTL_DSP (SCRIPTA_BA (np, complete_error)); 4040 } 4041 /* 4042 * Otherwise just restart the SCRIPTS. 4043 */ 4044 else { 4045 OUTL (nc_dsa, 0xffffff); 4046 OUTL_DSP (SCRIPTA_BA (np, start)); 4047 } 4048 } 4049 else 4050 goto reset_all; 4051 4052 return; 4053 4054 reset_all: 4055 sym_start_reset(np); 4056 } 4057 4058 /* 4059 * chip exception handler for selection timeout 4060 */ 4061 static void sym_int_sto (hcb_p np) 4062 { 4063 u32 dsp = INL (nc_dsp); 4064 4065 if (DEBUG_FLAGS & DEBUG_TINY) printf ("T"); 4066 4067 if (dsp == SCRIPTA_BA (np, wf_sel_done) + 8) 4068 sym_recover_scsi_int(np, HS_SEL_TIMEOUT); 4069 else 4070 sym_start_reset(np); 4071 } 4072 4073 /* 4074 * chip exception handler for unexpected disconnect 4075 */ 4076 static void sym_int_udc (hcb_p np) 4077 { 4078 printf ("%s: unexpected disconnect\n", sym_name(np)); 4079 sym_recover_scsi_int(np, HS_UNEXPECTED); 4080 } 4081 4082 /* 4083 * chip exception handler for SCSI bus mode change 4084 * 4085 * spi2-r12 11.2.3 says a transceiver mode change must 4086 * generate a reset event and a device that detects a reset 4087 * event shall initiate a hard reset. It says also that a 4088 * device that detects a mode change shall set data transfer 4089 * mode to eight bit asynchronous, etc... 4090 * So, just reinitializing all except chip should be enough. 4091 */ 4092 static void sym_int_sbmc (hcb_p np) 4093 { 4094 u_char scsi_mode = INB (nc_stest4) & SMODE; 4095 4096 /* 4097 * Notify user. 4098 */ 4099 xpt_print_path(np->path); 4100 printf("SCSI BUS mode change from %s to %s.\n", 4101 sym_scsi_bus_mode(np->scsi_mode), sym_scsi_bus_mode(scsi_mode)); 4102 4103 /* 4104 * Should suspend command processing for a few seconds and 4105 * reinitialize all except the chip. 4106 */ 4107 sym_init (np, 2); 4108 } 4109 4110 /* 4111 * chip exception handler for SCSI parity error. 4112 * 4113 * When the chip detects a SCSI parity error and is 4114 * currently executing a (CH)MOV instruction, it does 4115 * not interrupt immediately, but tries to finish the 4116 * transfer of the current scatter entry before 4117 * interrupting. The following situations may occur: 4118 * 4119 * - The complete scatter entry has been transferred 4120 * without the device having changed phase. 4121 * The chip will then interrupt with the DSP pointing 4122 * to the instruction that follows the MOV. 4123 * 4124 * - A phase mismatch occurs before the MOV finished 4125 * and phase errors are to be handled by the C code. 4126 * The chip will then interrupt with both PAR and MA 4127 * conditions set. 4128 * 4129 * - A phase mismatch occurs before the MOV finished and 4130 * phase errors are to be handled by SCRIPTS. 4131 * The chip will load the DSP with the phase mismatch 4132 * JUMP address and interrupt the host processor. 4133 */ 4134 static void sym_int_par (hcb_p np, u_short sist) 4135 { 4136 u_char hsts = INB (HS_PRT); 4137 u32 dsp = INL (nc_dsp); 4138 u32 dbc = INL (nc_dbc); 4139 u32 dsa = INL (nc_dsa); 4140 u_char sbcl = INB (nc_sbcl); 4141 u_char cmd = dbc >> 24; 4142 int phase = cmd & 7; 4143 ccb_p cp = sym_ccb_from_dsa(np, dsa); 4144 4145 printf("%s: SCSI parity error detected: SCR1=%d DBC=%x SBCL=%x\n", 4146 sym_name(np), hsts, dbc, sbcl); 4147 4148 /* 4149 * Check that the chip is connected to the SCSI BUS. 4150 */ 4151 if (!(INB (nc_scntl1) & ISCON)) { 4152 sym_recover_scsi_int(np, HS_UNEXPECTED); 4153 return; 4154 } 4155 4156 /* 4157 * If the nexus is not clearly identified, reset the bus. 4158 * We will try to do better later. 4159 */ 4160 if (!cp) 4161 goto reset_all; 4162 4163 /* 4164 * Check instruction was a MOV, direction was INPUT and 4165 * ATN is asserted. 4166 */ 4167 if ((cmd & 0xc0) || !(phase & 1) || !(sbcl & 0x8)) 4168 goto reset_all; 4169 4170 /* 4171 * Keep track of the parity error. 4172 */ 4173 OUTONB (HF_PRT, HF_EXT_ERR); 4174 cp->xerr_status |= XE_PARITY_ERR; 4175 4176 /* 4177 * Prepare the message to send to the device. 4178 */ 4179 np->msgout[0] = (phase == 7) ? M_PARITY : M_ID_ERROR; 4180 4181 /* 4182 * If the old phase was DATA IN phase, we have to deal with 4183 * the 3 situations described above. 4184 * For other input phases (MSG IN and STATUS), the device 4185 * must resend the whole thing that failed parity checking 4186 * or signal error. So, jumping to dispatcher should be OK. 4187 */ 4188 if (phase == 1 || phase == 5) { 4189 /* Phase mismatch handled by SCRIPTS */ 4190 if (dsp == SCRIPTB_BA (np, pm_handle)) 4191 OUTL_DSP (dsp); 4192 /* Phase mismatch handled by the C code */ 4193 else if (sist & MA) 4194 sym_int_ma (np); 4195 /* No phase mismatch occurred */ 4196 else { 4197 OUTL (nc_temp, dsp); 4198 OUTL_DSP (SCRIPTA_BA (np, dispatch)); 4199 } 4200 } 4201 else 4202 OUTL_DSP (SCRIPTA_BA (np, clrack)); 4203 return; 4204 4205 reset_all: 4206 sym_start_reset(np); 4207 return; 4208 } 4209 4210 /* 4211 * chip exception handler for phase errors. 4212 * 4213 * We have to construct a new transfer descriptor, 4214 * to transfer the rest of the current block. 4215 */ 4216 static void sym_int_ma (hcb_p np) 4217 { 4218 u32 dbc; 4219 u32 rest; 4220 u32 dsp; 4221 u32 dsa; 4222 u32 nxtdsp; 4223 u32 *vdsp; 4224 u32 oadr, olen; 4225 u32 *tblp; 4226 u32 newcmd; 4227 u_int delta; 4228 u_char cmd; 4229 u_char hflags, hflags0; 4230 struct sym_pmc *pm; 4231 ccb_p cp; 4232 4233 dsp = INL (nc_dsp); 4234 dbc = INL (nc_dbc); 4235 dsa = INL (nc_dsa); 4236 4237 cmd = dbc >> 24; 4238 rest = dbc & 0xffffff; 4239 delta = 0; 4240 4241 /* 4242 * locate matching cp if any. 4243 */ 4244 cp = sym_ccb_from_dsa(np, dsa); 4245 4246 /* 4247 * Donnot take into account dma fifo and various buffers in 4248 * INPUT phase since the chip flushes everything before 4249 * raising the MA interrupt for interrupted INPUT phases. 4250 * For DATA IN phase, we will check for the SWIDE later. 4251 */ 4252 if ((cmd & 7) != 1 && (cmd & 7) != 5) { 4253 u_char ss0, ss2; 4254 4255 if (np->features & FE_DFBC) 4256 delta = INW (nc_dfbc); 4257 else { 4258 u32 dfifo; 4259 4260 /* 4261 * Read DFIFO, CTEST[4-6] using 1 PCI bus ownership. 4262 */ 4263 dfifo = INL(nc_dfifo); 4264 4265 /* 4266 * Calculate remaining bytes in DMA fifo. 4267 * (CTEST5 = dfifo >> 16) 4268 */ 4269 if (dfifo & (DFS << 16)) 4270 delta = ((((dfifo >> 8) & 0x300) | 4271 (dfifo & 0xff)) - rest) & 0x3ff; 4272 else 4273 delta = ((dfifo & 0xff) - rest) & 0x7f; 4274 } 4275 4276 /* 4277 * The data in the dma fifo has not been transfered to 4278 * the target -> add the amount to the rest 4279 * and clear the data. 4280 * Check the sstat2 register in case of wide transfer. 4281 */ 4282 rest += delta; 4283 ss0 = INB (nc_sstat0); 4284 if (ss0 & OLF) rest++; 4285 if (!(np->features & FE_C10)) 4286 if (ss0 & ORF) rest++; 4287 if (cp && (cp->phys.select.sel_scntl3 & EWS)) { 4288 ss2 = INB (nc_sstat2); 4289 if (ss2 & OLF1) rest++; 4290 if (!(np->features & FE_C10)) 4291 if (ss2 & ORF1) rest++; 4292 }; 4293 4294 /* 4295 * Clear fifos. 4296 */ 4297 OUTB (nc_ctest3, np->rv_ctest3 | CLF); /* dma fifo */ 4298 OUTB (nc_stest3, TE|CSF); /* scsi fifo */ 4299 } 4300 4301 /* 4302 * log the information 4303 */ 4304 if (DEBUG_FLAGS & (DEBUG_TINY|DEBUG_PHASE)) 4305 printf ("P%x%x RL=%d D=%d ", cmd&7, INB(nc_sbcl)&7, 4306 (unsigned) rest, (unsigned) delta); 4307 4308 /* 4309 * try to find the interrupted script command, 4310 * and the address at which to continue. 4311 */ 4312 vdsp = 0; 4313 nxtdsp = 0; 4314 if (dsp > np->scripta_ba && 4315 dsp <= np->scripta_ba + np->scripta_sz) { 4316 vdsp = (u32 *)((char*)np->scripta0 + (dsp-np->scripta_ba-8)); 4317 nxtdsp = dsp; 4318 } 4319 else if (dsp > np->scriptb_ba && 4320 dsp <= np->scriptb_ba + np->scriptb_sz) { 4321 vdsp = (u32 *)((char*)np->scriptb0 + (dsp-np->scriptb_ba-8)); 4322 nxtdsp = dsp; 4323 } 4324 4325 /* 4326 * log the information 4327 */ 4328 if (DEBUG_FLAGS & DEBUG_PHASE) { 4329 printf ("\nCP=%p DSP=%x NXT=%x VDSP=%p CMD=%x ", 4330 cp, (unsigned)dsp, (unsigned)nxtdsp, vdsp, cmd); 4331 }; 4332 4333 if (!vdsp) { 4334 printf ("%s: interrupted SCRIPT address not found.\n", 4335 sym_name (np)); 4336 goto reset_all; 4337 } 4338 4339 if (!cp) { 4340 printf ("%s: SCSI phase error fixup: CCB already dequeued.\n", 4341 sym_name (np)); 4342 goto reset_all; 4343 } 4344 4345 /* 4346 * get old startaddress and old length. 4347 */ 4348 oadr = scr_to_cpu(vdsp[1]); 4349 4350 if (cmd & 0x10) { /* Table indirect */ 4351 tblp = (u32 *) ((char*) &cp->phys + oadr); 4352 olen = scr_to_cpu(tblp[0]); 4353 oadr = scr_to_cpu(tblp[1]); 4354 } else { 4355 tblp = (u32 *) 0; 4356 olen = scr_to_cpu(vdsp[0]) & 0xffffff; 4357 }; 4358 4359 if (DEBUG_FLAGS & DEBUG_PHASE) { 4360 printf ("OCMD=%x\nTBLP=%p OLEN=%x OADR=%x\n", 4361 (unsigned) (scr_to_cpu(vdsp[0]) >> 24), 4362 tblp, 4363 (unsigned) olen, 4364 (unsigned) oadr); 4365 }; 4366 4367 /* 4368 * check cmd against assumed interrupted script command. 4369 * If dt data phase, the MOVE instruction hasn't bit 4 of 4370 * the phase. 4371 */ 4372 if (((cmd & 2) ? cmd : (cmd & ~4)) != (scr_to_cpu(vdsp[0]) >> 24)) { 4373 PRINT_ADDR(cp); 4374 printf ("internal error: cmd=%02x != %02x=(vdsp[0] >> 24)\n", 4375 (unsigned)cmd, (unsigned)scr_to_cpu(vdsp[0]) >> 24); 4376 4377 goto reset_all; 4378 }; 4379 4380 /* 4381 * if old phase not dataphase, leave here. 4382 */ 4383 if (cmd & 2) { 4384 PRINT_ADDR(cp); 4385 printf ("phase change %x-%x %d@%08x resid=%d.\n", 4386 cmd&7, INB(nc_sbcl)&7, (unsigned)olen, 4387 (unsigned)oadr, (unsigned)rest); 4388 goto unexpected_phase; 4389 }; 4390 4391 /* 4392 * Choose the correct PM save area. 4393 * 4394 * Look at the PM_SAVE SCRIPT if you want to understand 4395 * this stuff. The equivalent code is implemented in 4396 * SCRIPTS for the 895A, 896 and 1010 that are able to 4397 * handle PM from the SCRIPTS processor. 4398 */ 4399 hflags0 = INB (HF_PRT); 4400 hflags = hflags0; 4401 4402 if (hflags & (HF_IN_PM0 | HF_IN_PM1 | HF_DP_SAVED)) { 4403 if (hflags & HF_IN_PM0) 4404 nxtdsp = scr_to_cpu(cp->phys.pm0.ret); 4405 else if (hflags & HF_IN_PM1) 4406 nxtdsp = scr_to_cpu(cp->phys.pm1.ret); 4407 4408 if (hflags & HF_DP_SAVED) 4409 hflags ^= HF_ACT_PM; 4410 } 4411 4412 if (!(hflags & HF_ACT_PM)) { 4413 pm = &cp->phys.pm0; 4414 newcmd = SCRIPTA_BA (np, pm0_data); 4415 } 4416 else { 4417 pm = &cp->phys.pm1; 4418 newcmd = SCRIPTA_BA (np, pm1_data); 4419 } 4420 4421 hflags &= ~(HF_IN_PM0 | HF_IN_PM1 | HF_DP_SAVED); 4422 if (hflags != hflags0) 4423 OUTB (HF_PRT, hflags); 4424 4425 /* 4426 * fillin the phase mismatch context 4427 */ 4428 pm->sg.addr = cpu_to_scr(oadr + olen - rest); 4429 pm->sg.size = cpu_to_scr(rest); 4430 pm->ret = cpu_to_scr(nxtdsp); 4431 4432 /* 4433 * If we have a SWIDE, 4434 * - prepare the address to write the SWIDE from SCRIPTS, 4435 * - compute the SCRIPTS address to restart from, 4436 * - move current data pointer context by one byte. 4437 */ 4438 nxtdsp = SCRIPTA_BA (np, dispatch); 4439 if ((cmd & 7) == 1 && cp && (cp->phys.select.sel_scntl3 & EWS) && 4440 (INB (nc_scntl2) & WSR)) { 4441 u32 tmp; 4442 4443 /* 4444 * Set up the table indirect for the MOVE 4445 * of the residual byte and adjust the data 4446 * pointer context. 4447 */ 4448 tmp = scr_to_cpu(pm->sg.addr); 4449 cp->phys.wresid.addr = cpu_to_scr(tmp); 4450 pm->sg.addr = cpu_to_scr(tmp + 1); 4451 tmp = scr_to_cpu(pm->sg.size); 4452 cp->phys.wresid.size = cpu_to_scr((tmp&0xff000000) | 1); 4453 pm->sg.size = cpu_to_scr(tmp - 1); 4454 4455 /* 4456 * If only the residual byte is to be moved, 4457 * no PM context is needed. 4458 */ 4459 if ((tmp&0xffffff) == 1) 4460 newcmd = pm->ret; 4461 4462 /* 4463 * Prepare the address of SCRIPTS that will 4464 * move the residual byte to memory. 4465 */ 4466 nxtdsp = SCRIPTB_BA (np, wsr_ma_helper); 4467 } 4468 4469 if (DEBUG_FLAGS & DEBUG_PHASE) { 4470 PRINT_ADDR(cp); 4471 printf ("PM %x %x %x / %x %x %x.\n", 4472 hflags0, hflags, newcmd, 4473 (unsigned)scr_to_cpu(pm->sg.addr), 4474 (unsigned)scr_to_cpu(pm->sg.size), 4475 (unsigned)scr_to_cpu(pm->ret)); 4476 } 4477 4478 /* 4479 * Restart the SCRIPTS processor. 4480 */ 4481 OUTL (nc_temp, newcmd); 4482 OUTL_DSP (nxtdsp); 4483 return; 4484 4485 /* 4486 * Unexpected phase changes that occurs when the current phase 4487 * is not a DATA IN or DATA OUT phase are due to error conditions. 4488 * Such event may only happen when the SCRIPTS is using a 4489 * multibyte SCSI MOVE. 4490 * 4491 * Phase change Some possible cause 4492 * 4493 * COMMAND --> MSG IN SCSI parity error detected by target. 4494 * COMMAND --> STATUS Bad command or refused by target. 4495 * MSG OUT --> MSG IN Message rejected by target. 4496 * MSG OUT --> COMMAND Bogus target that discards extended 4497 * negotiation messages. 4498 * 4499 * The code below does not care of the new phase and so 4500 * trusts the target. Why to annoy it ? 4501 * If the interrupted phase is COMMAND phase, we restart at 4502 * dispatcher. 4503 * If a target does not get all the messages after selection, 4504 * the code assumes blindly that the target discards extended 4505 * messages and clears the negotiation status. 4506 * If the target does not want all our response to negotiation, 4507 * we force a SIR_NEGO_PROTO interrupt (it is a hack that avoids 4508 * bloat for such a should_not_happen situation). 4509 * In all other situation, we reset the BUS. 4510 * Are these assumptions reasonnable ? (Wait and see ...) 4511 */ 4512 unexpected_phase: 4513 dsp -= 8; 4514 nxtdsp = 0; 4515 4516 switch (cmd & 7) { 4517 case 2: /* COMMAND phase */ 4518 nxtdsp = SCRIPTA_BA (np, dispatch); 4519 break; 4520 #if 0 4521 case 3: /* STATUS phase */ 4522 nxtdsp = SCRIPTA_BA (np, dispatch); 4523 break; 4524 #endif 4525 case 6: /* MSG OUT phase */ 4526 /* 4527 * If the device may want to use untagged when we want 4528 * tagged, we prepare an IDENTIFY without disc. granted, 4529 * since we will not be able to handle reselect. 4530 * Otherwise, we just don't care. 4531 */ 4532 if (dsp == SCRIPTA_BA (np, send_ident)) { 4533 if (cp->tag != NO_TAG && olen - rest <= 3) { 4534 cp->host_status = HS_BUSY; 4535 np->msgout[0] = M_IDENTIFY | cp->lun; 4536 nxtdsp = SCRIPTB_BA (np, ident_break_atn); 4537 } 4538 else 4539 nxtdsp = SCRIPTB_BA (np, ident_break); 4540 } 4541 else if (dsp == SCRIPTB_BA (np, send_wdtr) || 4542 dsp == SCRIPTB_BA (np, send_sdtr) || 4543 dsp == SCRIPTB_BA (np, send_ppr)) { 4544 nxtdsp = SCRIPTB_BA (np, nego_bad_phase); 4545 } 4546 break; 4547 #if 0 4548 case 7: /* MSG IN phase */ 4549 nxtdsp = SCRIPTA_BA (np, clrack); 4550 break; 4551 #endif 4552 } 4553 4554 if (nxtdsp) { 4555 OUTL_DSP (nxtdsp); 4556 return; 4557 } 4558 4559 reset_all: 4560 sym_start_reset(np); 4561 } 4562 4563 /* 4564 * Dequeue from the START queue all CCBs that match 4565 * a given target/lun/task condition (-1 means all), 4566 * and move them from the BUSY queue to the COMP queue 4567 * with CAM_REQUEUE_REQ status condition. 4568 * This function is used during error handling/recovery. 4569 * It is called with SCRIPTS not running. 4570 */ 4571 static int 4572 sym_dequeue_from_squeue(hcb_p np, int i, int target, int lun, int task) 4573 { 4574 int j; 4575 ccb_p cp; 4576 4577 /* 4578 * Make sure the starting index is within range. 4579 */ 4580 assert((i >= 0) && (i < 2*MAX_QUEUE)); 4581 4582 /* 4583 * Walk until end of START queue and dequeue every job 4584 * that matches the target/lun/task condition. 4585 */ 4586 j = i; 4587 while (i != np->squeueput) { 4588 cp = sym_ccb_from_dsa(np, scr_to_cpu(np->squeue[i])); 4589 assert(cp); 4590 #ifdef SYM_CONF_IARB_SUPPORT 4591 /* Forget hints for IARB, they may be no longer relevant */ 4592 cp->host_flags &= ~HF_HINT_IARB; 4593 #endif 4594 if ((target == -1 || cp->target == target) && 4595 (lun == -1 || cp->lun == lun) && 4596 (task == -1 || cp->tag == task)) { 4597 sym_set_cam_status(cp->cam_ccb, CAM_REQUEUE_REQ); 4598 sym_remque(&cp->link_ccbq); 4599 sym_insque_tail(&cp->link_ccbq, &np->comp_ccbq); 4600 } 4601 else { 4602 if (i != j) 4603 np->squeue[j] = np->squeue[i]; 4604 if ((j += 2) >= MAX_QUEUE*2) j = 0; 4605 } 4606 if ((i += 2) >= MAX_QUEUE*2) i = 0; 4607 } 4608 if (i != j) /* Copy back the idle task if needed */ 4609 np->squeue[j] = np->squeue[i]; 4610 np->squeueput = j; /* Update our current start queue pointer */ 4611 4612 return (i - j) / 2; 4613 } 4614 4615 /* 4616 * Complete all CCBs queued to the COMP queue. 4617 * 4618 * These CCBs are assumed: 4619 * - Not to be referenced either by devices or 4620 * SCRIPTS-related queues and datas. 4621 * - To have to be completed with an error condition 4622 * or requeued. 4623 * 4624 * The device queue freeze count is incremented 4625 * for each CCB that does not prevent this. 4626 * This function is called when all CCBs involved 4627 * in error handling/recovery have been reaped. 4628 */ 4629 static void 4630 sym_flush_comp_queue(hcb_p np, int cam_status) 4631 { 4632 SYM_QUEHEAD *qp; 4633 ccb_p cp; 4634 4635 while ((qp = sym_remque_head(&np->comp_ccbq)) != 0) { 4636 union ccb *ccb; 4637 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 4638 sym_insque_tail(&cp->link_ccbq, &np->busy_ccbq); 4639 /* Leave quiet CCBs waiting for resources */ 4640 if (cp->host_status == HS_WAIT) 4641 continue; 4642 ccb = cp->cam_ccb; 4643 if (cam_status) 4644 sym_set_cam_status(ccb, cam_status); 4645 sym_free_ccb(np, cp); 4646 sym_freeze_cam_ccb(ccb); 4647 sym_xpt_done(np, ccb); 4648 } 4649 } 4650 4651 /* 4652 * chip handler for bad SCSI status condition 4653 * 4654 * In case of bad SCSI status, we unqueue all the tasks 4655 * currently queued to the controller but not yet started 4656 * and then restart the SCRIPTS processor immediately. 4657 * 4658 * QUEUE FULL and BUSY conditions are handled the same way. 4659 * Basically all the not yet started tasks are requeued in 4660 * device queue and the queue is frozen until a completion. 4661 * 4662 * For CHECK CONDITION and COMMAND TERMINATED status, we use 4663 * the CCB of the failed command to prepare a REQUEST SENSE 4664 * SCSI command and queue it to the controller queue. 4665 * 4666 * SCRATCHA is assumed to have been loaded with STARTPOS 4667 * before the SCRIPTS called the C code. 4668 */ 4669 static void sym_sir_bad_scsi_status(hcb_p np, int num, ccb_p cp) 4670 { 4671 tcb_p tp = &np->target[cp->target]; 4672 u32 startp; 4673 u_char s_status = cp->ssss_status; 4674 u_char h_flags = cp->host_flags; 4675 int msglen; 4676 int nego; 4677 int i; 4678 4679 /* 4680 * Compute the index of the next job to start from SCRIPTS. 4681 */ 4682 i = (INL (nc_scratcha) - np->squeue_ba) / 4; 4683 4684 /* 4685 * The last CCB queued used for IARB hint may be 4686 * no longer relevant. Forget it. 4687 */ 4688 #ifdef SYM_CONF_IARB_SUPPORT 4689 if (np->last_cp) 4690 np->last_cp = 0; 4691 #endif 4692 4693 /* 4694 * Now deal with the SCSI status. 4695 */ 4696 switch(s_status) { 4697 case S_BUSY: 4698 case S_QUEUE_FULL: 4699 if (sym_verbose >= 2) { 4700 PRINT_ADDR(cp); 4701 printf (s_status == S_BUSY ? "BUSY" : "QUEUE FULL\n"); 4702 } 4703 default: /* S_INT, S_INT_COND_MET, S_CONFLICT */ 4704 sym_complete_error (np, cp); 4705 break; 4706 case S_TERMINATED: 4707 case S_CHECK_COND: 4708 /* 4709 * If we get an SCSI error when requesting sense, give up. 4710 */ 4711 if (h_flags & HF_SENSE) { 4712 sym_complete_error (np, cp); 4713 break; 4714 } 4715 4716 /* 4717 * Dequeue all queued CCBs for that device not yet started, 4718 * and restart the SCRIPTS processor immediately. 4719 */ 4720 (void) sym_dequeue_from_squeue(np, i, cp->target, cp->lun, -1); 4721 OUTL_DSP (SCRIPTA_BA (np, start)); 4722 4723 /* 4724 * Save some info of the actual IO. 4725 * Compute the data residual. 4726 */ 4727 cp->sv_scsi_status = cp->ssss_status; 4728 cp->sv_xerr_status = cp->xerr_status; 4729 cp->sv_resid = sym_compute_residual(np, cp); 4730 4731 /* 4732 * Prepare all needed data structures for 4733 * requesting sense data. 4734 */ 4735 4736 /* 4737 * identify message 4738 */ 4739 cp->scsi_smsg2[0] = M_IDENTIFY | cp->lun; 4740 msglen = 1; 4741 4742 /* 4743 * If we are currently using anything different from 4744 * async. 8 bit data transfers with that target, 4745 * start a negotiation, since the device may want 4746 * to report us a UNIT ATTENTION condition due to 4747 * a cause we currently ignore, and we donnot want 4748 * to be stuck with WIDE and/or SYNC data transfer. 4749 * 4750 * cp->nego_status is filled by sym_prepare_nego(). 4751 */ 4752 cp->nego_status = 0; 4753 nego = 0; 4754 if (tp->tinfo.current.options & PPR_OPT_MASK) 4755 nego = NS_PPR; 4756 else if (tp->tinfo.current.width != BUS_8_BIT) 4757 nego = NS_WIDE; 4758 else if (tp->tinfo.current.offset != 0) 4759 nego = NS_SYNC; 4760 if (nego) 4761 msglen += 4762 sym_prepare_nego (np,cp, nego, &cp->scsi_smsg2[msglen]); 4763 /* 4764 * Message table indirect structure. 4765 */ 4766 cp->phys.smsg.addr = cpu_to_scr(CCB_BA (cp, scsi_smsg2)); 4767 cp->phys.smsg.size = cpu_to_scr(msglen); 4768 4769 /* 4770 * sense command 4771 */ 4772 cp->phys.cmd.addr = cpu_to_scr(CCB_BA (cp, sensecmd)); 4773 cp->phys.cmd.size = cpu_to_scr(6); 4774 4775 /* 4776 * patch requested size into sense command 4777 */ 4778 cp->sensecmd[0] = 0x03; 4779 cp->sensecmd[1] = cp->lun << 5; 4780 if (tp->tinfo.current.scsi_version > 2 || cp->lun > 7) 4781 cp->sensecmd[1] = 0; 4782 cp->sensecmd[4] = SYM_SNS_BBUF_LEN; 4783 cp->data_len = SYM_SNS_BBUF_LEN; 4784 4785 /* 4786 * sense data 4787 */ 4788 bzero(cp->sns_bbuf, SYM_SNS_BBUF_LEN); 4789 cp->phys.sense.addr = cpu_to_scr(vtobus(cp->sns_bbuf)); 4790 cp->phys.sense.size = cpu_to_scr(SYM_SNS_BBUF_LEN); 4791 4792 /* 4793 * requeue the command. 4794 */ 4795 startp = SCRIPTB_BA (np, sdata_in); 4796 4797 cp->phys.head.savep = cpu_to_scr(startp); 4798 cp->phys.head.goalp = cpu_to_scr(startp + 16); 4799 cp->phys.head.lastp = cpu_to_scr(startp); 4800 cp->startp = cpu_to_scr(startp); 4801 4802 cp->actualquirks = SYM_QUIRK_AUTOSAVE; 4803 cp->host_status = cp->nego_status ? HS_NEGOTIATE : HS_BUSY; 4804 cp->ssss_status = S_ILLEGAL; 4805 cp->host_flags = (HF_SENSE|HF_DATA_IN); 4806 cp->xerr_status = 0; 4807 cp->extra_bytes = 0; 4808 4809 cp->phys.head.go.start = cpu_to_scr(SCRIPTA_BA (np, select)); 4810 4811 /* 4812 * Requeue the command. 4813 */ 4814 sym_put_start_queue(np, cp); 4815 4816 /* 4817 * Give back to upper layer everything we have dequeued. 4818 */ 4819 sym_flush_comp_queue(np, 0); 4820 break; 4821 } 4822 } 4823 4824 /* 4825 * After a device has accepted some management message 4826 * as BUS DEVICE RESET, ABORT TASK, etc ..., or when 4827 * a device signals a UNIT ATTENTION condition, some 4828 * tasks are thrown away by the device. We are required 4829 * to reflect that on our tasks list since the device 4830 * will never complete these tasks. 4831 * 4832 * This function move from the BUSY queue to the COMP 4833 * queue all disconnected CCBs for a given target that 4834 * match the following criteria: 4835 * - lun=-1 means any logical UNIT otherwise a given one. 4836 * - task=-1 means any task, otherwise a given one. 4837 */ 4838 static int 4839 sym_clear_tasks(hcb_p np, int cam_status, int target, int lun, int task) 4840 { 4841 SYM_QUEHEAD qtmp, *qp; 4842 int i = 0; 4843 ccb_p cp; 4844 4845 /* 4846 * Move the entire BUSY queue to our temporary queue. 4847 */ 4848 sym_que_init(&qtmp); 4849 sym_que_splice(&np->busy_ccbq, &qtmp); 4850 sym_que_init(&np->busy_ccbq); 4851 4852 /* 4853 * Put all CCBs that matches our criteria into 4854 * the COMP queue and put back other ones into 4855 * the BUSY queue. 4856 */ 4857 while ((qp = sym_remque_head(&qtmp)) != 0) { 4858 union ccb *ccb; 4859 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 4860 ccb = cp->cam_ccb; 4861 if (cp->host_status != HS_DISCONNECT || 4862 cp->target != target || 4863 (lun != -1 && cp->lun != lun) || 4864 (task != -1 && 4865 (cp->tag != NO_TAG && cp->scsi_smsg[2] != task))) { 4866 sym_insque_tail(&cp->link_ccbq, &np->busy_ccbq); 4867 continue; 4868 } 4869 sym_insque_tail(&cp->link_ccbq, &np->comp_ccbq); 4870 4871 /* Preserve the software timeout condition */ 4872 if (sym_get_cam_status(ccb) != CAM_CMD_TIMEOUT) 4873 sym_set_cam_status(ccb, cam_status); 4874 ++i; 4875 #if 0 4876 printf("XXXX TASK @%p CLEARED\n", cp); 4877 #endif 4878 } 4879 return i; 4880 } 4881 4882 /* 4883 * chip handler for TASKS recovery 4884 * 4885 * We cannot safely abort a command, while the SCRIPTS 4886 * processor is running, since we just would be in race 4887 * with it. 4888 * 4889 * As long as we have tasks to abort, we keep the SEM 4890 * bit set in the ISTAT. When this bit is set, the 4891 * SCRIPTS processor interrupts (SIR_SCRIPT_STOPPED) 4892 * each time it enters the scheduler. 4893 * 4894 * If we have to reset a target, clear tasks of a unit, 4895 * or to perform the abort of a disconnected job, we 4896 * restart the SCRIPTS for selecting the target. Once 4897 * selected, the SCRIPTS interrupts (SIR_TARGET_SELECTED). 4898 * If it loses arbitration, the SCRIPTS will interrupt again 4899 * the next time it will enter its scheduler, and so on ... 4900 * 4901 * On SIR_TARGET_SELECTED, we scan for the more 4902 * appropriate thing to do: 4903 * 4904 * - If nothing, we just sent a M_ABORT message to the 4905 * target to get rid of the useless SCSI bus ownership. 4906 * According to the specs, no tasks shall be affected. 4907 * - If the target is to be reset, we send it a M_RESET 4908 * message. 4909 * - If a logical UNIT is to be cleared , we send the 4910 * IDENTIFY(lun) + M_ABORT. 4911 * - If an untagged task is to be aborted, we send the 4912 * IDENTIFY(lun) + M_ABORT. 4913 * - If a tagged task is to be aborted, we send the 4914 * IDENTIFY(lun) + task attributes + M_ABORT_TAG. 4915 * 4916 * Once our 'kiss of death' :) message has been accepted 4917 * by the target, the SCRIPTS interrupts again 4918 * (SIR_ABORT_SENT). On this interrupt, we complete 4919 * all the CCBs that should have been aborted by the 4920 * target according to our message. 4921 */ 4922 static void sym_sir_task_recovery(hcb_p np, int num) 4923 { 4924 SYM_QUEHEAD *qp; 4925 ccb_p cp; 4926 tcb_p tp; 4927 int target=-1, lun=-1, task; 4928 int i, k; 4929 4930 switch(num) { 4931 /* 4932 * The SCRIPTS processor stopped before starting 4933 * the next command in order to allow us to perform 4934 * some task recovery. 4935 */ 4936 case SIR_SCRIPT_STOPPED: 4937 /* 4938 * Do we have any target to reset or unit to clear ? 4939 */ 4940 for (i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) { 4941 tp = &np->target[i]; 4942 if (tp->to_reset || 4943 (tp->lun0p && tp->lun0p->to_clear)) { 4944 target = i; 4945 break; 4946 } 4947 if (!tp->lunmp) 4948 continue; 4949 for (k = 1 ; k < SYM_CONF_MAX_LUN ; k++) { 4950 if (tp->lunmp[k] && tp->lunmp[k]->to_clear) { 4951 target = i; 4952 break; 4953 } 4954 } 4955 if (target != -1) 4956 break; 4957 } 4958 4959 /* 4960 * If not, walk the busy queue for any 4961 * disconnected CCB to be aborted. 4962 */ 4963 if (target == -1) { 4964 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) { 4965 cp = sym_que_entry(qp,struct sym_ccb,link_ccbq); 4966 if (cp->host_status != HS_DISCONNECT) 4967 continue; 4968 if (cp->to_abort) { 4969 target = cp->target; 4970 break; 4971 } 4972 } 4973 } 4974 4975 /* 4976 * If some target is to be selected, 4977 * prepare and start the selection. 4978 */ 4979 if (target != -1) { 4980 tp = &np->target[target]; 4981 np->abrt_sel.sel_id = target; 4982 np->abrt_sel.sel_scntl3 = tp->head.wval; 4983 np->abrt_sel.sel_sxfer = tp->head.sval; 4984 OUTL(nc_dsa, np->hcb_ba); 4985 OUTL_DSP (SCRIPTB_BA (np, sel_for_abort)); 4986 return; 4987 } 4988 4989 /* 4990 * Now look for a CCB to abort that haven't started yet. 4991 * Btw, the SCRIPTS processor is still stopped, so 4992 * we are not in race. 4993 */ 4994 i = 0; 4995 cp = 0; 4996 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) { 4997 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 4998 if (cp->host_status != HS_BUSY && 4999 cp->host_status != HS_NEGOTIATE) 5000 continue; 5001 if (!cp->to_abort) 5002 continue; 5003 #ifdef SYM_CONF_IARB_SUPPORT 5004 /* 5005 * If we are using IMMEDIATE ARBITRATION, we donnot 5006 * want to cancel the last queued CCB, since the 5007 * SCRIPTS may have anticipated the selection. 5008 */ 5009 if (cp == np->last_cp) { 5010 cp->to_abort = 0; 5011 continue; 5012 } 5013 #endif 5014 i = 1; /* Means we have found some */ 5015 break; 5016 } 5017 if (!i) { 5018 /* 5019 * We are done, so we donnot need 5020 * to synchronize with the SCRIPTS anylonger. 5021 * Remove the SEM flag from the ISTAT. 5022 */ 5023 np->istat_sem = 0; 5024 OUTB (nc_istat, SIGP); 5025 break; 5026 } 5027 /* 5028 * Compute index of next position in the start 5029 * queue the SCRIPTS intends to start and dequeue 5030 * all CCBs for that device that haven't been started. 5031 */ 5032 i = (INL (nc_scratcha) - np->squeue_ba) / 4; 5033 i = sym_dequeue_from_squeue(np, i, cp->target, cp->lun, -1); 5034 5035 /* 5036 * Make sure at least our IO to abort has been dequeued. 5037 */ 5038 assert(i && sym_get_cam_status(cp->cam_ccb) == CAM_REQUEUE_REQ); 5039 5040 /* 5041 * Keep track in cam status of the reason of the abort. 5042 */ 5043 if (cp->to_abort == 2) 5044 sym_set_cam_status(cp->cam_ccb, CAM_CMD_TIMEOUT); 5045 else 5046 sym_set_cam_status(cp->cam_ccb, CAM_REQ_ABORTED); 5047 5048 /* 5049 * Complete with error everything that we have dequeued. 5050 */ 5051 sym_flush_comp_queue(np, 0); 5052 break; 5053 /* 5054 * The SCRIPTS processor has selected a target 5055 * we may have some manual recovery to perform for. 5056 */ 5057 case SIR_TARGET_SELECTED: 5058 target = (INB (nc_sdid) & 0xf); 5059 tp = &np->target[target]; 5060 5061 np->abrt_tbl.addr = cpu_to_scr(vtobus(np->abrt_msg)); 5062 5063 /* 5064 * If the target is to be reset, prepare a 5065 * M_RESET message and clear the to_reset flag 5066 * since we donnot expect this operation to fail. 5067 */ 5068 if (tp->to_reset) { 5069 np->abrt_msg[0] = M_RESET; 5070 np->abrt_tbl.size = 1; 5071 tp->to_reset = 0; 5072 break; 5073 } 5074 5075 /* 5076 * Otherwise, look for some logical unit to be cleared. 5077 */ 5078 if (tp->lun0p && tp->lun0p->to_clear) 5079 lun = 0; 5080 else if (tp->lunmp) { 5081 for (k = 1 ; k < SYM_CONF_MAX_LUN ; k++) { 5082 if (tp->lunmp[k] && tp->lunmp[k]->to_clear) { 5083 lun = k; 5084 break; 5085 } 5086 } 5087 } 5088 5089 /* 5090 * If a logical unit is to be cleared, prepare 5091 * an IDENTIFY(lun) + ABORT MESSAGE. 5092 */ 5093 if (lun != -1) { 5094 lcb_p lp = sym_lp(np, tp, lun); 5095 lp->to_clear = 0; /* We donnot expect to fail here */ 5096 np->abrt_msg[0] = M_IDENTIFY | lun; 5097 np->abrt_msg[1] = M_ABORT; 5098 np->abrt_tbl.size = 2; 5099 break; 5100 } 5101 5102 /* 5103 * Otherwise, look for some disconnected job to 5104 * abort for this target. 5105 */ 5106 i = 0; 5107 cp = 0; 5108 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) { 5109 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 5110 if (cp->host_status != HS_DISCONNECT) 5111 continue; 5112 if (cp->target != target) 5113 continue; 5114 if (!cp->to_abort) 5115 continue; 5116 i = 1; /* Means we have some */ 5117 break; 5118 } 5119 5120 /* 5121 * If we have none, probably since the device has 5122 * completed the command before we won abitration, 5123 * send a M_ABORT message without IDENTIFY. 5124 * According to the specs, the device must just 5125 * disconnect the BUS and not abort any task. 5126 */ 5127 if (!i) { 5128 np->abrt_msg[0] = M_ABORT; 5129 np->abrt_tbl.size = 1; 5130 break; 5131 } 5132 5133 /* 5134 * We have some task to abort. 5135 * Set the IDENTIFY(lun) 5136 */ 5137 np->abrt_msg[0] = M_IDENTIFY | cp->lun; 5138 5139 /* 5140 * If we want to abort an untagged command, we 5141 * will send an IDENTIFY + M_ABORT. 5142 * Otherwise (tagged command), we will send 5143 * an IDENTIFY + task attributes + ABORT TAG. 5144 */ 5145 if (cp->tag == NO_TAG) { 5146 np->abrt_msg[1] = M_ABORT; 5147 np->abrt_tbl.size = 2; 5148 } 5149 else { 5150 np->abrt_msg[1] = cp->scsi_smsg[1]; 5151 np->abrt_msg[2] = cp->scsi_smsg[2]; 5152 np->abrt_msg[3] = M_ABORT_TAG; 5153 np->abrt_tbl.size = 4; 5154 } 5155 /* 5156 * Keep track of software timeout condition, since the 5157 * peripheral driver may not count retries on abort 5158 * conditions not due to timeout. 5159 */ 5160 if (cp->to_abort == 2) 5161 sym_set_cam_status(cp->cam_ccb, CAM_CMD_TIMEOUT); 5162 cp->to_abort = 0; /* We donnot expect to fail here */ 5163 break; 5164 5165 /* 5166 * The target has accepted our message and switched 5167 * to BUS FREE phase as we expected. 5168 */ 5169 case SIR_ABORT_SENT: 5170 target = (INB (nc_sdid) & 0xf); 5171 tp = &np->target[target]; 5172 5173 /* 5174 ** If we didn't abort anything, leave here. 5175 */ 5176 if (np->abrt_msg[0] == M_ABORT) 5177 break; 5178 5179 /* 5180 * If we sent a M_RESET, then a hardware reset has 5181 * been performed by the target. 5182 * - Reset everything to async 8 bit 5183 * - Tell ourself to negotiate next time :-) 5184 * - Prepare to clear all disconnected CCBs for 5185 * this target from our task list (lun=task=-1) 5186 */ 5187 lun = -1; 5188 task = -1; 5189 if (np->abrt_msg[0] == M_RESET) { 5190 tp->head.sval = 0; 5191 tp->head.wval = np->rv_scntl3; 5192 tp->head.uval = 0; 5193 tp->tinfo.current.period = 0; 5194 tp->tinfo.current.offset = 0; 5195 tp->tinfo.current.width = BUS_8_BIT; 5196 tp->tinfo.current.options = 0; 5197 } 5198 5199 /* 5200 * Otherwise, check for the LUN and TASK(s) 5201 * concerned by the cancelation. 5202 * If it is not ABORT_TAG then it is CLEAR_QUEUE 5203 * or an ABORT message :-) 5204 */ 5205 else { 5206 lun = np->abrt_msg[0] & 0x3f; 5207 if (np->abrt_msg[1] == M_ABORT_TAG) 5208 task = np->abrt_msg[2]; 5209 } 5210 5211 /* 5212 * Complete all the CCBs the device should have 5213 * aborted due to our 'kiss of death' message. 5214 */ 5215 i = (INL (nc_scratcha) - np->squeue_ba) / 4; 5216 (void) sym_dequeue_from_squeue(np, i, target, lun, -1); 5217 (void) sym_clear_tasks(np, CAM_REQ_ABORTED, target, lun, task); 5218 sym_flush_comp_queue(np, 0); 5219 5220 /* 5221 * If we sent a BDR, make uper layer aware of that. 5222 */ 5223 if (np->abrt_msg[0] == M_RESET) 5224 xpt_async(AC_SENT_BDR, np->path, NULL); 5225 break; 5226 } 5227 5228 /* 5229 * Print to the log the message we intend to send. 5230 */ 5231 if (num == SIR_TARGET_SELECTED) { 5232 PRINT_TARGET(np, target); 5233 sym_printl_hex("control msgout:", np->abrt_msg, 5234 np->abrt_tbl.size); 5235 np->abrt_tbl.size = cpu_to_scr(np->abrt_tbl.size); 5236 } 5237 5238 /* 5239 * Let the SCRIPTS processor continue. 5240 */ 5241 OUTONB_STD (); 5242 } 5243 5244 /* 5245 * Gerard's alchemy:) that deals with with the data 5246 * pointer for both MDP and the residual calculation. 5247 * 5248 * I didn't want to bloat the code by more than 200 5249 * lignes for the handling of both MDP and the residual. 5250 * This has been achieved by using a data pointer 5251 * representation consisting in an index in the data 5252 * array (dp_sg) and a negative offset (dp_ofs) that 5253 * have the following meaning: 5254 * 5255 * - dp_sg = SYM_CONF_MAX_SG 5256 * we are at the end of the data script. 5257 * - dp_sg < SYM_CONF_MAX_SG 5258 * dp_sg points to the next entry of the scatter array 5259 * we want to transfer. 5260 * - dp_ofs < 0 5261 * dp_ofs represents the residual of bytes of the 5262 * previous entry scatter entry we will send first. 5263 * - dp_ofs = 0 5264 * no residual to send first. 5265 * 5266 * The function sym_evaluate_dp() accepts an arbitray 5267 * offset (basically from the MDP message) and returns 5268 * the corresponding values of dp_sg and dp_ofs. 5269 */ 5270 5271 static int sym_evaluate_dp(hcb_p np, ccb_p cp, u32 scr, int *ofs) 5272 { 5273 u32 dp_scr; 5274 int dp_ofs, dp_sg, dp_sgmin; 5275 int tmp; 5276 struct sym_pmc *pm; 5277 5278 /* 5279 * Compute the resulted data pointer in term of a script 5280 * address within some DATA script and a signed byte offset. 5281 */ 5282 dp_scr = scr; 5283 dp_ofs = *ofs; 5284 if (dp_scr == SCRIPTA_BA (np, pm0_data)) 5285 pm = &cp->phys.pm0; 5286 else if (dp_scr == SCRIPTA_BA (np, pm1_data)) 5287 pm = &cp->phys.pm1; 5288 else 5289 pm = 0; 5290 5291 if (pm) { 5292 dp_scr = scr_to_cpu(pm->ret); 5293 dp_ofs -= scr_to_cpu(pm->sg.size); 5294 } 5295 5296 /* 5297 * If we are auto-sensing, then we are done. 5298 */ 5299 if (cp->host_flags & HF_SENSE) { 5300 *ofs = dp_ofs; 5301 return 0; 5302 } 5303 5304 /* 5305 * Deduce the index of the sg entry. 5306 * Keep track of the index of the first valid entry. 5307 * If result is dp_sg = SYM_CONF_MAX_SG, then we are at the 5308 * end of the data. 5309 */ 5310 tmp = scr_to_cpu(cp->phys.head.goalp); 5311 dp_sg = SYM_CONF_MAX_SG; 5312 if (dp_scr != tmp) 5313 dp_sg -= (tmp - 8 - (int)dp_scr) / (2*4); 5314 dp_sgmin = SYM_CONF_MAX_SG - cp->segments; 5315 5316 /* 5317 * Move to the sg entry the data pointer belongs to. 5318 * 5319 * If we are inside the data area, we expect result to be: 5320 * 5321 * Either, 5322 * dp_ofs = 0 and dp_sg is the index of the sg entry 5323 * the data pointer belongs to (or the end of the data) 5324 * Or, 5325 * dp_ofs < 0 and dp_sg is the index of the sg entry 5326 * the data pointer belongs to + 1. 5327 */ 5328 if (dp_ofs < 0) { 5329 int n; 5330 while (dp_sg > dp_sgmin) { 5331 --dp_sg; 5332 tmp = scr_to_cpu(cp->phys.data[dp_sg].size); 5333 n = dp_ofs + (tmp & 0xffffff); 5334 if (n > 0) { 5335 ++dp_sg; 5336 break; 5337 } 5338 dp_ofs = n; 5339 } 5340 } 5341 else if (dp_ofs > 0) { 5342 while (dp_sg < SYM_CONF_MAX_SG) { 5343 tmp = scr_to_cpu(cp->phys.data[dp_sg].size); 5344 dp_ofs -= (tmp & 0xffffff); 5345 ++dp_sg; 5346 if (dp_ofs <= 0) 5347 break; 5348 } 5349 } 5350 5351 /* 5352 * Make sure the data pointer is inside the data area. 5353 * If not, return some error. 5354 */ 5355 if (dp_sg < dp_sgmin || (dp_sg == dp_sgmin && dp_ofs < 0)) 5356 goto out_err; 5357 else if (dp_sg > SYM_CONF_MAX_SG || 5358 (dp_sg == SYM_CONF_MAX_SG && dp_ofs > 0)) 5359 goto out_err; 5360 5361 /* 5362 * Save the extreme pointer if needed. 5363 */ 5364 if (dp_sg > cp->ext_sg || 5365 (dp_sg == cp->ext_sg && dp_ofs > cp->ext_ofs)) { 5366 cp->ext_sg = dp_sg; 5367 cp->ext_ofs = dp_ofs; 5368 } 5369 5370 /* 5371 * Return data. 5372 */ 5373 *ofs = dp_ofs; 5374 return dp_sg; 5375 5376 out_err: 5377 return -1; 5378 } 5379 5380 /* 5381 * chip handler for MODIFY DATA POINTER MESSAGE 5382 * 5383 * We also call this function on IGNORE WIDE RESIDUE 5384 * messages that do not match a SWIDE full condition. 5385 * Btw, we assume in that situation that such a message 5386 * is equivalent to a MODIFY DATA POINTER (offset=-1). 5387 */ 5388 5389 static void sym_modify_dp(hcb_p np, tcb_p tp, ccb_p cp, int ofs) 5390 { 5391 int dp_ofs = ofs; 5392 u32 dp_scr = INL (nc_temp); 5393 u32 dp_ret; 5394 u32 tmp; 5395 u_char hflags; 5396 int dp_sg; 5397 struct sym_pmc *pm; 5398 5399 /* 5400 * Not supported for auto-sense. 5401 */ 5402 if (cp->host_flags & HF_SENSE) 5403 goto out_reject; 5404 5405 /* 5406 * Apply our alchemy:) (see comments in sym_evaluate_dp()), 5407 * to the resulted data pointer. 5408 */ 5409 dp_sg = sym_evaluate_dp(np, cp, dp_scr, &dp_ofs); 5410 if (dp_sg < 0) 5411 goto out_reject; 5412 5413 /* 5414 * And our alchemy:) allows to easily calculate the data 5415 * script address we want to return for the next data phase. 5416 */ 5417 dp_ret = cpu_to_scr(cp->phys.head.goalp); 5418 dp_ret = dp_ret - 8 - (SYM_CONF_MAX_SG - dp_sg) * (2*4); 5419 5420 /* 5421 * If offset / scatter entry is zero we donnot need 5422 * a context for the new current data pointer. 5423 */ 5424 if (dp_ofs == 0) { 5425 dp_scr = dp_ret; 5426 goto out_ok; 5427 } 5428 5429 /* 5430 * Get a context for the new current data pointer. 5431 */ 5432 hflags = INB (HF_PRT); 5433 5434 if (hflags & HF_DP_SAVED) 5435 hflags ^= HF_ACT_PM; 5436 5437 if (!(hflags & HF_ACT_PM)) { 5438 pm = &cp->phys.pm0; 5439 dp_scr = SCRIPTA_BA (np, pm0_data); 5440 } 5441 else { 5442 pm = &cp->phys.pm1; 5443 dp_scr = SCRIPTA_BA (np, pm1_data); 5444 } 5445 5446 hflags &= ~(HF_DP_SAVED); 5447 5448 OUTB (HF_PRT, hflags); 5449 5450 /* 5451 * Set up the new current data pointer. 5452 * ofs < 0 there, and for the next data phase, we 5453 * want to transfer part of the data of the sg entry 5454 * corresponding to index dp_sg-1 prior to returning 5455 * to the main data script. 5456 */ 5457 pm->ret = cpu_to_scr(dp_ret); 5458 tmp = scr_to_cpu(cp->phys.data[dp_sg-1].addr); 5459 tmp += scr_to_cpu(cp->phys.data[dp_sg-1].size) + dp_ofs; 5460 pm->sg.addr = cpu_to_scr(tmp); 5461 pm->sg.size = cpu_to_scr(-dp_ofs); 5462 5463 out_ok: 5464 OUTL (nc_temp, dp_scr); 5465 OUTL_DSP (SCRIPTA_BA (np, clrack)); 5466 return; 5467 5468 out_reject: 5469 OUTL_DSP (SCRIPTB_BA (np, msg_bad)); 5470 } 5471 5472 5473 /* 5474 * chip calculation of the data residual. 5475 * 5476 * As I used to say, the requirement of data residual 5477 * in SCSI is broken, useless and cannot be achieved 5478 * without huge complexity. 5479 * But most OSes and even the official CAM require it. 5480 * When stupidity happens to be so widely spread inside 5481 * a community, it gets hard to convince. 5482 * 5483 * Anyway, I don't care, since I am not going to use 5484 * any software that considers this data residual as 5485 * a relevant information. :) 5486 */ 5487 5488 static int sym_compute_residual(hcb_p np, ccb_p cp) 5489 { 5490 int dp_sg, dp_sgmin, resid = 0; 5491 int dp_ofs = 0; 5492 5493 /* 5494 * Check for some data lost or just thrown away. 5495 * We are not required to be quite accurate in this 5496 * situation. Btw, if we are odd for output and the 5497 * device claims some more data, it may well happen 5498 * than our residual be zero. :-) 5499 */ 5500 if (cp->xerr_status & (XE_EXTRA_DATA|XE_SODL_UNRUN|XE_SWIDE_OVRUN)) { 5501 if (cp->xerr_status & XE_EXTRA_DATA) 5502 resid -= cp->extra_bytes; 5503 if (cp->xerr_status & XE_SODL_UNRUN) 5504 ++resid; 5505 if (cp->xerr_status & XE_SWIDE_OVRUN) 5506 --resid; 5507 } 5508 5509 /* 5510 * If all data has been transferred, 5511 * there is no residual. 5512 */ 5513 if (cp->phys.head.lastp == cp->phys.head.goalp) 5514 return resid; 5515 5516 /* 5517 * If no data transfer occurs, or if the data 5518 * pointer is weird, return full residual. 5519 */ 5520 if (cp->startp == cp->phys.head.lastp || 5521 sym_evaluate_dp(np, cp, scr_to_cpu(cp->phys.head.lastp), 5522 &dp_ofs) < 0) { 5523 return cp->data_len; 5524 } 5525 5526 /* 5527 * If we were auto-sensing, then we are done. 5528 */ 5529 if (cp->host_flags & HF_SENSE) { 5530 return -dp_ofs; 5531 } 5532 5533 /* 5534 * We are now full comfortable in the computation 5535 * of the data residual (2's complement). 5536 */ 5537 dp_sgmin = SYM_CONF_MAX_SG - cp->segments; 5538 resid = -cp->ext_ofs; 5539 for (dp_sg = cp->ext_sg; dp_sg < SYM_CONF_MAX_SG; ++dp_sg) { 5540 u_int tmp = scr_to_cpu(cp->phys.data[dp_sg].size); 5541 resid += (tmp & 0xffffff); 5542 } 5543 5544 /* 5545 * Hopefully, the result is not too wrong. 5546 */ 5547 return resid; 5548 } 5549 5550 /* 5551 * Print out the content of a SCSI message. 5552 */ 5553 5554 static int sym_show_msg (u_char * msg) 5555 { 5556 u_char i; 5557 printf ("%x",*msg); 5558 if (*msg==M_EXTENDED) { 5559 for (i=1;i<8;i++) { 5560 if (i-1>msg[1]) break; 5561 printf ("-%x",msg[i]); 5562 }; 5563 return (i+1); 5564 } else if ((*msg & 0xf0) == 0x20) { 5565 printf ("-%x",msg[1]); 5566 return (2); 5567 }; 5568 return (1); 5569 } 5570 5571 static void sym_print_msg (ccb_p cp, char *label, u_char *msg) 5572 { 5573 PRINT_ADDR(cp); 5574 if (label) 5575 printf ("%s: ", label); 5576 5577 (void) sym_show_msg (msg); 5578 printf (".\n"); 5579 } 5580 5581 /* 5582 * Negotiation for WIDE and SYNCHRONOUS DATA TRANSFER. 5583 * 5584 * When we try to negotiate, we append the negotiation message 5585 * to the identify and (maybe) simple tag message. 5586 * The host status field is set to HS_NEGOTIATE to mark this 5587 * situation. 5588 * 5589 * If the target doesn't answer this message immediately 5590 * (as required by the standard), the SIR_NEGO_FAILED interrupt 5591 * will be raised eventually. 5592 * The handler removes the HS_NEGOTIATE status, and sets the 5593 * negotiated value to the default (async / nowide). 5594 * 5595 * If we receive a matching answer immediately, we check it 5596 * for validity, and set the values. 5597 * 5598 * If we receive a Reject message immediately, we assume the 5599 * negotiation has failed, and fall back to standard values. 5600 * 5601 * If we receive a negotiation message while not in HS_NEGOTIATE 5602 * state, it's a target initiated negotiation. We prepare a 5603 * (hopefully) valid answer, set our parameters, and send back 5604 * this answer to the target. 5605 * 5606 * If the target doesn't fetch the answer (no message out phase), 5607 * we assume the negotiation has failed, and fall back to default 5608 * settings (SIR_NEGO_PROTO interrupt). 5609 * 5610 * When we set the values, we adjust them in all ccbs belonging 5611 * to this target, in the controller's register, and in the "phys" 5612 * field of the controller's struct sym_hcb. 5613 */ 5614 5615 /* 5616 * chip handler for SYNCHRONOUS DATA TRANSFER REQUEST (SDTR) message. 5617 */ 5618 static void sym_sync_nego(hcb_p np, tcb_p tp, ccb_p cp) 5619 { 5620 u_char chg, ofs, per, fak, div; 5621 int req = 1; 5622 5623 /* 5624 * Synchronous request message received. 5625 */ 5626 if (DEBUG_FLAGS & DEBUG_NEGO) { 5627 sym_print_msg(cp, "sync msgin", np->msgin); 5628 }; 5629 5630 /* 5631 * request or answer ? 5632 */ 5633 if (INB (HS_PRT) == HS_NEGOTIATE) { 5634 OUTB (HS_PRT, HS_BUSY); 5635 if (cp->nego_status && cp->nego_status != NS_SYNC) 5636 goto reject_it; 5637 req = 0; 5638 } 5639 5640 /* 5641 * get requested values. 5642 */ 5643 chg = 0; 5644 per = np->msgin[3]; 5645 ofs = np->msgin[4]; 5646 5647 /* 5648 * check values against our limits. 5649 */ 5650 if (ofs) { 5651 if (ofs > np->maxoffs) 5652 {chg = 1; ofs = np->maxoffs;} 5653 if (req) { 5654 if (ofs > tp->tinfo.user.offset) 5655 {chg = 1; ofs = tp->tinfo.user.offset;} 5656 } 5657 } 5658 5659 if (ofs) { 5660 if (per < np->minsync) 5661 {chg = 1; per = np->minsync;} 5662 if (req) { 5663 if (per < tp->tinfo.user.period) 5664 {chg = 1; per = tp->tinfo.user.period;} 5665 } 5666 } 5667 5668 div = fak = 0; 5669 if (ofs && sym_getsync(np, 0, per, &div, &fak) < 0) 5670 goto reject_it; 5671 5672 if (DEBUG_FLAGS & DEBUG_NEGO) { 5673 PRINT_ADDR(cp); 5674 printf ("sdtr: ofs=%d per=%d div=%d fak=%d chg=%d.\n", 5675 ofs, per, div, fak, chg); 5676 } 5677 5678 /* 5679 * This was an answer message 5680 */ 5681 if (req == 0) { 5682 if (chg) /* Answer wasn't acceptable. */ 5683 goto reject_it; 5684 sym_setsync (np, cp, ofs, per, div, fak); 5685 OUTL_DSP (SCRIPTA_BA (np, clrack)); 5686 return; 5687 } 5688 5689 /* 5690 * It was a request. Set value and 5691 * prepare an answer message 5692 */ 5693 sym_setsync (np, cp, ofs, per, div, fak); 5694 5695 np->msgout[0] = M_EXTENDED; 5696 np->msgout[1] = 3; 5697 np->msgout[2] = M_X_SYNC_REQ; 5698 np->msgout[3] = per; 5699 np->msgout[4] = ofs; 5700 5701 cp->nego_status = NS_SYNC; 5702 5703 if (DEBUG_FLAGS & DEBUG_NEGO) { 5704 sym_print_msg(cp, "sync msgout", np->msgout); 5705 } 5706 5707 np->msgin [0] = M_NOOP; 5708 5709 OUTL_DSP (SCRIPTB_BA (np, sdtr_resp)); 5710 return; 5711 reject_it: 5712 sym_setsync (np, cp, 0, 0, 0, 0); 5713 OUTL_DSP (SCRIPTB_BA (np, msg_bad)); 5714 } 5715 5716 /* 5717 * chip handler for PARALLEL PROTOCOL REQUEST (PPR) message. 5718 */ 5719 static void sym_ppr_nego(hcb_p np, tcb_p tp, ccb_p cp) 5720 { 5721 u_char chg, ofs, per, fak, dt, div, wide; 5722 int req = 1; 5723 5724 /* 5725 * Synchronous request message received. 5726 */ 5727 if (DEBUG_FLAGS & DEBUG_NEGO) { 5728 sym_print_msg(cp, "ppr msgin", np->msgin); 5729 }; 5730 5731 /* 5732 * get requested values. 5733 */ 5734 chg = 0; 5735 per = np->msgin[3]; 5736 ofs = np->msgin[5]; 5737 wide = np->msgin[6]; 5738 dt = np->msgin[7] & PPR_OPT_DT; 5739 5740 /* 5741 * request or answer ? 5742 */ 5743 if (INB (HS_PRT) == HS_NEGOTIATE) { 5744 OUTB (HS_PRT, HS_BUSY); 5745 if (cp->nego_status && cp->nego_status != NS_PPR) 5746 goto reject_it; 5747 req = 0; 5748 } 5749 5750 /* 5751 * check values against our limits. 5752 */ 5753 if (wide > np->maxwide) 5754 {chg = 1; wide = np->maxwide;} 5755 if (!wide || !(np->features & FE_ULTRA3)) 5756 dt &= ~PPR_OPT_DT; 5757 if (req) { 5758 if (wide > tp->tinfo.user.width) 5759 {chg = 1; wide = tp->tinfo.user.width;} 5760 } 5761 5762 if (!(np->features & FE_U3EN)) /* Broken U3EN bit not supported */ 5763 dt &= ~PPR_OPT_DT; 5764 5765 if (dt != (np->msgin[7] & PPR_OPT_MASK)) chg = 1; 5766 5767 if (ofs) { 5768 if (dt) { 5769 if (ofs > np->maxoffs_dt) 5770 {chg = 1; ofs = np->maxoffs_dt;} 5771 } 5772 else if (ofs > np->maxoffs) 5773 {chg = 1; ofs = np->maxoffs;} 5774 if (req) { 5775 if (ofs > tp->tinfo.user.offset) 5776 {chg = 1; ofs = tp->tinfo.user.offset;} 5777 } 5778 } 5779 5780 if (ofs) { 5781 if (dt) { 5782 if (per < np->minsync_dt) 5783 {chg = 1; per = np->minsync_dt;} 5784 } 5785 else if (per < np->minsync) 5786 {chg = 1; per = np->minsync;} 5787 if (req) { 5788 if (per < tp->tinfo.user.period) 5789 {chg = 1; per = tp->tinfo.user.period;} 5790 } 5791 } 5792 5793 div = fak = 0; 5794 if (ofs && sym_getsync(np, dt, per, &div, &fak) < 0) 5795 goto reject_it; 5796 5797 if (DEBUG_FLAGS & DEBUG_NEGO) { 5798 PRINT_ADDR(cp); 5799 printf ("ppr: " 5800 "dt=%x ofs=%d per=%d wide=%d div=%d fak=%d chg=%d.\n", 5801 dt, ofs, per, wide, div, fak, chg); 5802 } 5803 5804 /* 5805 * It was an answer. 5806 */ 5807 if (req == 0) { 5808 if (chg) /* Answer wasn't acceptable */ 5809 goto reject_it; 5810 sym_setpprot (np, cp, dt, ofs, per, wide, div, fak); 5811 OUTL_DSP (SCRIPTA_BA (np, clrack)); 5812 return; 5813 } 5814 5815 /* 5816 * It was a request. Set value and 5817 * prepare an answer message 5818 */ 5819 sym_setpprot (np, cp, dt, ofs, per, wide, div, fak); 5820 5821 np->msgout[0] = M_EXTENDED; 5822 np->msgout[1] = 6; 5823 np->msgout[2] = M_X_PPR_REQ; 5824 np->msgout[3] = per; 5825 np->msgout[4] = 0; 5826 np->msgout[5] = ofs; 5827 np->msgout[6] = wide; 5828 np->msgout[7] = dt; 5829 5830 cp->nego_status = NS_PPR; 5831 5832 if (DEBUG_FLAGS & DEBUG_NEGO) { 5833 sym_print_msg(cp, "ppr msgout", np->msgout); 5834 } 5835 5836 np->msgin [0] = M_NOOP; 5837 5838 OUTL_DSP (SCRIPTB_BA (np, ppr_resp)); 5839 return; 5840 reject_it: 5841 sym_setpprot (np, cp, 0, 0, 0, 0, 0, 0); 5842 OUTL_DSP (SCRIPTB_BA (np, msg_bad)); 5843 /* 5844 * If it was a device response that should result in 5845 * ST, we may want to try a legacy negotiation later. 5846 */ 5847 if (!req && !dt) { 5848 tp->tinfo.goal.options = 0; 5849 tp->tinfo.goal.width = wide; 5850 tp->tinfo.goal.period = per; 5851 tp->tinfo.goal.offset = ofs; 5852 } 5853 return; 5854 } 5855 5856 /* 5857 * chip handler for WIDE DATA TRANSFER REQUEST (WDTR) message. 5858 */ 5859 static void sym_wide_nego(hcb_p np, tcb_p tp, ccb_p cp) 5860 { 5861 u_char chg, wide; 5862 int req = 1; 5863 5864 /* 5865 * Wide request message received. 5866 */ 5867 if (DEBUG_FLAGS & DEBUG_NEGO) { 5868 sym_print_msg(cp, "wide msgin", np->msgin); 5869 }; 5870 5871 /* 5872 * Is it a request from the device? 5873 */ 5874 if (INB (HS_PRT) == HS_NEGOTIATE) { 5875 OUTB (HS_PRT, HS_BUSY); 5876 if (cp->nego_status && cp->nego_status != NS_WIDE) 5877 goto reject_it; 5878 req = 0; 5879 } 5880 5881 /* 5882 * get requested values. 5883 */ 5884 chg = 0; 5885 wide = np->msgin[3]; 5886 5887 /* 5888 * check values against driver limits. 5889 */ 5890 if (wide > np->maxwide) 5891 {chg = 1; wide = np->maxwide;} 5892 if (req) { 5893 if (wide > tp->tinfo.user.width) 5894 {chg = 1; wide = tp->tinfo.user.width;} 5895 } 5896 5897 if (DEBUG_FLAGS & DEBUG_NEGO) { 5898 PRINT_ADDR(cp); 5899 printf ("wdtr: wide=%d chg=%d.\n", wide, chg); 5900 } 5901 5902 /* 5903 * This was an answer message 5904 */ 5905 if (req == 0) { 5906 if (chg) /* Answer wasn't acceptable. */ 5907 goto reject_it; 5908 sym_setwide (np, cp, wide); 5909 5910 /* 5911 * Negotiate for SYNC immediately after WIDE response. 5912 * This allows to negotiate for both WIDE and SYNC on 5913 * a single SCSI command (Suggested by Justin Gibbs). 5914 */ 5915 if (tp->tinfo.goal.offset) { 5916 np->msgout[0] = M_EXTENDED; 5917 np->msgout[1] = 3; 5918 np->msgout[2] = M_X_SYNC_REQ; 5919 np->msgout[3] = tp->tinfo.goal.period; 5920 np->msgout[4] = tp->tinfo.goal.offset; 5921 5922 if (DEBUG_FLAGS & DEBUG_NEGO) { 5923 sym_print_msg(cp, "sync msgout", np->msgout); 5924 } 5925 5926 cp->nego_status = NS_SYNC; 5927 OUTB (HS_PRT, HS_NEGOTIATE); 5928 OUTL_DSP (SCRIPTB_BA (np, sdtr_resp)); 5929 return; 5930 } 5931 5932 OUTL_DSP (SCRIPTA_BA (np, clrack)); 5933 return; 5934 }; 5935 5936 /* 5937 * It was a request, set value and 5938 * prepare an answer message 5939 */ 5940 sym_setwide (np, cp, wide); 5941 5942 np->msgout[0] = M_EXTENDED; 5943 np->msgout[1] = 2; 5944 np->msgout[2] = M_X_WIDE_REQ; 5945 np->msgout[3] = wide; 5946 5947 np->msgin [0] = M_NOOP; 5948 5949 cp->nego_status = NS_WIDE; 5950 5951 if (DEBUG_FLAGS & DEBUG_NEGO) { 5952 sym_print_msg(cp, "wide msgout", np->msgout); 5953 } 5954 5955 OUTL_DSP (SCRIPTB_BA (np, wdtr_resp)); 5956 return; 5957 reject_it: 5958 OUTL_DSP (SCRIPTB_BA (np, msg_bad)); 5959 } 5960 5961 /* 5962 * Reset SYNC or WIDE to default settings. 5963 * 5964 * Called when a negotiation does not succeed either 5965 * on rejection or on protocol error. 5966 * 5967 * If it was a PPR that made problems, we may want to 5968 * try a legacy negotiation later. 5969 */ 5970 static void sym_nego_default(hcb_p np, tcb_p tp, ccb_p cp) 5971 { 5972 /* 5973 * any error in negotiation: 5974 * fall back to default mode. 5975 */ 5976 switch (cp->nego_status) { 5977 case NS_PPR: 5978 #if 0 5979 sym_setpprot (np, cp, 0, 0, 0, 0, 0, 0); 5980 #else 5981 tp->tinfo.goal.options = 0; 5982 if (tp->tinfo.goal.period < np->minsync) 5983 tp->tinfo.goal.period = np->minsync; 5984 if (tp->tinfo.goal.offset > np->maxoffs) 5985 tp->tinfo.goal.offset = np->maxoffs; 5986 #endif 5987 break; 5988 case NS_SYNC: 5989 sym_setsync (np, cp, 0, 0, 0, 0); 5990 break; 5991 case NS_WIDE: 5992 sym_setwide (np, cp, 0); 5993 break; 5994 }; 5995 np->msgin [0] = M_NOOP; 5996 np->msgout[0] = M_NOOP; 5997 cp->nego_status = 0; 5998 } 5999 6000 /* 6001 * chip handler for MESSAGE REJECT received in response to 6002 * a WIDE or SYNCHRONOUS negotiation. 6003 */ 6004 static void sym_nego_rejected(hcb_p np, tcb_p tp, ccb_p cp) 6005 { 6006 sym_nego_default(np, tp, cp); 6007 OUTB (HS_PRT, HS_BUSY); 6008 } 6009 6010 /* 6011 * chip exception handler for programmed interrupts. 6012 */ 6013 static void sym_int_sir (hcb_p np) 6014 { 6015 u_char num = INB (nc_dsps); 6016 u32 dsa = INL (nc_dsa); 6017 ccb_p cp = sym_ccb_from_dsa(np, dsa); 6018 u_char target = INB (nc_sdid) & 0x0f; 6019 tcb_p tp = &np->target[target]; 6020 int tmp; 6021 6022 if (DEBUG_FLAGS & DEBUG_TINY) printf ("I#%d", num); 6023 6024 switch (num) { 6025 /* 6026 * Command has been completed with error condition 6027 * or has been auto-sensed. 6028 */ 6029 case SIR_COMPLETE_ERROR: 6030 sym_complete_error(np, cp); 6031 return; 6032 /* 6033 * The C code is currently trying to recover from something. 6034 * Typically, user want to abort some command. 6035 */ 6036 case SIR_SCRIPT_STOPPED: 6037 case SIR_TARGET_SELECTED: 6038 case SIR_ABORT_SENT: 6039 sym_sir_task_recovery(np, num); 6040 return; 6041 /* 6042 * The device didn't go to MSG OUT phase after having 6043 * been selected with ATN. We donnot want to handle 6044 * that. 6045 */ 6046 case SIR_SEL_ATN_NO_MSG_OUT: 6047 printf ("%s:%d: No MSG OUT phase after selection with ATN.\n", 6048 sym_name (np), target); 6049 goto out_stuck; 6050 /* 6051 * The device didn't switch to MSG IN phase after 6052 * having reseleted the initiator. 6053 */ 6054 case SIR_RESEL_NO_MSG_IN: 6055 printf ("%s:%d: No MSG IN phase after reselection.\n", 6056 sym_name (np), target); 6057 goto out_stuck; 6058 /* 6059 * After reselection, the device sent a message that wasn't 6060 * an IDENTIFY. 6061 */ 6062 case SIR_RESEL_NO_IDENTIFY: 6063 printf ("%s:%d: No IDENTIFY after reselection.\n", 6064 sym_name (np), target); 6065 goto out_stuck; 6066 /* 6067 * The device reselected a LUN we donnot know about. 6068 */ 6069 case SIR_RESEL_BAD_LUN: 6070 np->msgout[0] = M_RESET; 6071 goto out; 6072 /* 6073 * The device reselected for an untagged nexus and we 6074 * haven't any. 6075 */ 6076 case SIR_RESEL_BAD_I_T_L: 6077 np->msgout[0] = M_ABORT; 6078 goto out; 6079 /* 6080 * The device reselected for a tagged nexus that we donnot 6081 * have. 6082 */ 6083 case SIR_RESEL_BAD_I_T_L_Q: 6084 np->msgout[0] = M_ABORT_TAG; 6085 goto out; 6086 /* 6087 * The SCRIPTS let us know that the device has grabbed 6088 * our message and will abort the job. 6089 */ 6090 case SIR_RESEL_ABORTED: 6091 np->lastmsg = np->msgout[0]; 6092 np->msgout[0] = M_NOOP; 6093 printf ("%s:%d: message %x sent on bad reselection.\n", 6094 sym_name (np), target, np->lastmsg); 6095 goto out; 6096 /* 6097 * The SCRIPTS let us know that a message has been 6098 * successfully sent to the device. 6099 */ 6100 case SIR_MSG_OUT_DONE: 6101 np->lastmsg = np->msgout[0]; 6102 np->msgout[0] = M_NOOP; 6103 /* Should we really care of that */ 6104 if (np->lastmsg == M_PARITY || np->lastmsg == M_ID_ERROR) { 6105 if (cp) { 6106 cp->xerr_status &= ~XE_PARITY_ERR; 6107 if (!cp->xerr_status) 6108 OUTOFFB (HF_PRT, HF_EXT_ERR); 6109 } 6110 } 6111 goto out; 6112 /* 6113 * The device didn't send a GOOD SCSI status. 6114 * We may have some work to do prior to allow 6115 * the SCRIPTS processor to continue. 6116 */ 6117 case SIR_BAD_SCSI_STATUS: 6118 if (!cp) 6119 goto out; 6120 sym_sir_bad_scsi_status(np, num, cp); 6121 return; 6122 /* 6123 * We are asked by the SCRIPTS to prepare a 6124 * REJECT message. 6125 */ 6126 case SIR_REJECT_TO_SEND: 6127 sym_print_msg(cp, "M_REJECT to send for ", np->msgin); 6128 np->msgout[0] = M_REJECT; 6129 goto out; 6130 /* 6131 * We have been ODD at the end of a DATA IN 6132 * transfer and the device didn't send a 6133 * IGNORE WIDE RESIDUE message. 6134 * It is a data overrun condition. 6135 */ 6136 case SIR_SWIDE_OVERRUN: 6137 if (cp) { 6138 OUTONB (HF_PRT, HF_EXT_ERR); 6139 cp->xerr_status |= XE_SWIDE_OVRUN; 6140 } 6141 goto out; 6142 /* 6143 * We have been ODD at the end of a DATA OUT 6144 * transfer. 6145 * It is a data underrun condition. 6146 */ 6147 case SIR_SODL_UNDERRUN: 6148 if (cp) { 6149 OUTONB (HF_PRT, HF_EXT_ERR); 6150 cp->xerr_status |= XE_SODL_UNRUN; 6151 } 6152 goto out; 6153 /* 6154 * The device wants us to tranfer more data than 6155 * expected or in the wrong direction. 6156 * The number of extra bytes is in scratcha. 6157 * It is a data overrun condition. 6158 */ 6159 case SIR_DATA_OVERRUN: 6160 if (cp) { 6161 OUTONB (HF_PRT, HF_EXT_ERR); 6162 cp->xerr_status |= XE_EXTRA_DATA; 6163 cp->extra_bytes += INL (nc_scratcha); 6164 } 6165 goto out; 6166 /* 6167 * The device switched to an illegal phase (4/5). 6168 */ 6169 case SIR_BAD_PHASE: 6170 if (cp) { 6171 OUTONB (HF_PRT, HF_EXT_ERR); 6172 cp->xerr_status |= XE_BAD_PHASE; 6173 } 6174 goto out; 6175 /* 6176 * We received a message. 6177 */ 6178 case SIR_MSG_RECEIVED: 6179 if (!cp) 6180 goto out_stuck; 6181 switch (np->msgin [0]) { 6182 /* 6183 * We received an extended message. 6184 * We handle MODIFY DATA POINTER, SDTR, WDTR 6185 * and reject all other extended messages. 6186 */ 6187 case M_EXTENDED: 6188 switch (np->msgin [2]) { 6189 case M_X_MODIFY_DP: 6190 if (DEBUG_FLAGS & DEBUG_POINTER) 6191 sym_print_msg(cp,"modify DP",np->msgin); 6192 tmp = (np->msgin[3]<<24) + (np->msgin[4]<<16) + 6193 (np->msgin[5]<<8) + (np->msgin[6]); 6194 sym_modify_dp(np, tp, cp, tmp); 6195 return; 6196 case M_X_SYNC_REQ: 6197 sym_sync_nego(np, tp, cp); 6198 return; 6199 case M_X_PPR_REQ: 6200 sym_ppr_nego(np, tp, cp); 6201 return; 6202 case M_X_WIDE_REQ: 6203 sym_wide_nego(np, tp, cp); 6204 return; 6205 default: 6206 goto out_reject; 6207 } 6208 break; 6209 /* 6210 * We received a 1/2 byte message not handled from SCRIPTS. 6211 * We are only expecting MESSAGE REJECT and IGNORE WIDE 6212 * RESIDUE messages that haven't been anticipated by 6213 * SCRIPTS on SWIDE full condition. Unanticipated IGNORE 6214 * WIDE RESIDUE messages are aliased as MODIFY DP (-1). 6215 */ 6216 case M_IGN_RESIDUE: 6217 if (DEBUG_FLAGS & DEBUG_POINTER) 6218 sym_print_msg(cp,"ign wide residue", np->msgin); 6219 sym_modify_dp(np, tp, cp, -1); 6220 return; 6221 case M_REJECT: 6222 if (INB (HS_PRT) == HS_NEGOTIATE) 6223 sym_nego_rejected(np, tp, cp); 6224 else { 6225 PRINT_ADDR(cp); 6226 printf ("M_REJECT received (%x:%x).\n", 6227 scr_to_cpu(np->lastmsg), np->msgout[0]); 6228 } 6229 goto out_clrack; 6230 break; 6231 default: 6232 goto out_reject; 6233 } 6234 break; 6235 /* 6236 * We received an unknown message. 6237 * Ignore all MSG IN phases and reject it. 6238 */ 6239 case SIR_MSG_WEIRD: 6240 sym_print_msg(cp, "WEIRD message received", np->msgin); 6241 OUTL_DSP (SCRIPTB_BA (np, msg_weird)); 6242 return; 6243 /* 6244 * Negotiation failed. 6245 * Target does not send us the reply. 6246 * Remove the HS_NEGOTIATE status. 6247 */ 6248 case SIR_NEGO_FAILED: 6249 OUTB (HS_PRT, HS_BUSY); 6250 /* 6251 * Negotiation failed. 6252 * Target does not want answer message. 6253 */ 6254 case SIR_NEGO_PROTO: 6255 sym_nego_default(np, tp, cp); 6256 goto out; 6257 }; 6258 6259 out: 6260 OUTONB_STD (); 6261 return; 6262 out_reject: 6263 OUTL_DSP (SCRIPTB_BA (np, msg_bad)); 6264 return; 6265 out_clrack: 6266 OUTL_DSP (SCRIPTA_BA (np, clrack)); 6267 return; 6268 out_stuck: 6269 return; 6270 } 6271 6272 /* 6273 * Acquire a control block 6274 */ 6275 static ccb_p sym_get_ccb (hcb_p np, u_char tn, u_char ln, u_char tag_order) 6276 { 6277 tcb_p tp = &np->target[tn]; 6278 lcb_p lp = sym_lp(np, tp, ln); 6279 u_short tag = NO_TAG; 6280 SYM_QUEHEAD *qp; 6281 ccb_p cp = (ccb_p) 0; 6282 6283 /* 6284 * Look for a free CCB 6285 */ 6286 if (sym_que_empty(&np->free_ccbq)) 6287 (void) sym_alloc_ccb(np); 6288 qp = sym_remque_head(&np->free_ccbq); 6289 if (!qp) 6290 goto out; 6291 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 6292 6293 /* 6294 * If the LCB is not yet available and the LUN 6295 * has been probed ok, try to allocate the LCB. 6296 */ 6297 if (!lp && sym_is_bit(tp->lun_map, ln)) { 6298 lp = sym_alloc_lcb(np, tn, ln); 6299 if (!lp) 6300 goto out_free; 6301 } 6302 6303 /* 6304 * If the LCB is not available here, then the 6305 * logical unit is not yet discovered. For those 6306 * ones only accept 1 SCSI IO per logical unit, 6307 * since we cannot allow disconnections. 6308 */ 6309 if (!lp) { 6310 if (!sym_is_bit(tp->busy0_map, ln)) 6311 sym_set_bit(tp->busy0_map, ln); 6312 else 6313 goto out_free; 6314 } else { 6315 /* 6316 * If we have been asked for a tagged command. 6317 */ 6318 if (tag_order) { 6319 /* 6320 * Debugging purpose. 6321 */ 6322 assert(lp->busy_itl == 0); 6323 /* 6324 * Allocate resources for tags if not yet. 6325 */ 6326 if (!lp->cb_tags) { 6327 sym_alloc_lcb_tags(np, tn, ln); 6328 if (!lp->cb_tags) 6329 goto out_free; 6330 } 6331 /* 6332 * Get a tag for this SCSI IO and set up 6333 * the CCB bus address for reselection, 6334 * and count it for this LUN. 6335 * Toggle reselect path to tagged. 6336 */ 6337 if (lp->busy_itlq < SYM_CONF_MAX_TASK) { 6338 tag = lp->cb_tags[lp->ia_tag]; 6339 if (++lp->ia_tag == SYM_CONF_MAX_TASK) 6340 lp->ia_tag = 0; 6341 lp->itlq_tbl[tag] = cpu_to_scr(cp->ccb_ba); 6342 ++lp->busy_itlq; 6343 lp->head.resel_sa = 6344 cpu_to_scr(SCRIPTA_BA (np, resel_tag)); 6345 } 6346 else 6347 goto out_free; 6348 } 6349 /* 6350 * This command will not be tagged. 6351 * If we already have either a tagged or untagged 6352 * one, refuse to overlap this untagged one. 6353 */ 6354 else { 6355 /* 6356 * Debugging purpose. 6357 */ 6358 assert(lp->busy_itl == 0 && lp->busy_itlq == 0); 6359 /* 6360 * Count this nexus for this LUN. 6361 * Set up the CCB bus address for reselection. 6362 * Toggle reselect path to untagged. 6363 */ 6364 if (++lp->busy_itl == 1) { 6365 lp->head.itl_task_sa = cpu_to_scr(cp->ccb_ba); 6366 lp->head.resel_sa = 6367 cpu_to_scr(SCRIPTA_BA (np, resel_no_tag)); 6368 } 6369 else 6370 goto out_free; 6371 } 6372 } 6373 /* 6374 * Put the CCB into the busy queue. 6375 */ 6376 sym_insque_tail(&cp->link_ccbq, &np->busy_ccbq); 6377 6378 /* 6379 * Remember all informations needed to free this CCB. 6380 */ 6381 cp->to_abort = 0; 6382 cp->tag = tag; 6383 cp->target = tn; 6384 cp->lun = ln; 6385 6386 if (DEBUG_FLAGS & DEBUG_TAGS) { 6387 PRINT_LUN(np, tn, ln); 6388 printf ("ccb @%p using tag %d.\n", cp, tag); 6389 } 6390 6391 out: 6392 return cp; 6393 out_free: 6394 sym_insque_head(&cp->link_ccbq, &np->free_ccbq); 6395 return (ccb_p) 0; 6396 } 6397 6398 /* 6399 * Release one control block 6400 */ 6401 static void sym_free_ccb (hcb_p np, ccb_p cp) 6402 { 6403 tcb_p tp = &np->target[cp->target]; 6404 lcb_p lp = sym_lp(np, tp, cp->lun); 6405 6406 if (DEBUG_FLAGS & DEBUG_TAGS) { 6407 PRINT_LUN(np, cp->target, cp->lun); 6408 printf ("ccb @%p freeing tag %d.\n", cp, cp->tag); 6409 } 6410 6411 /* 6412 * If LCB available, 6413 */ 6414 if (lp) { 6415 /* 6416 * If tagged, release the tag, set the relect path 6417 */ 6418 if (cp->tag != NO_TAG) { 6419 /* 6420 * Free the tag value. 6421 */ 6422 lp->cb_tags[lp->if_tag] = cp->tag; 6423 if (++lp->if_tag == SYM_CONF_MAX_TASK) 6424 lp->if_tag = 0; 6425 /* 6426 * Make the reselect path invalid, 6427 * and uncount this CCB. 6428 */ 6429 lp->itlq_tbl[cp->tag] = cpu_to_scr(np->bad_itlq_ba); 6430 --lp->busy_itlq; 6431 } else { /* Untagged */ 6432 /* 6433 * Make the reselect path invalid, 6434 * and uncount this CCB. 6435 */ 6436 lp->head.itl_task_sa = cpu_to_scr(np->bad_itl_ba); 6437 --lp->busy_itl; 6438 } 6439 /* 6440 * If no JOB active, make the LUN reselect path invalid. 6441 */ 6442 if (lp->busy_itlq == 0 && lp->busy_itl == 0) 6443 lp->head.resel_sa = 6444 cpu_to_scr(SCRIPTB_BA (np, resel_bad_lun)); 6445 } 6446 /* 6447 * Otherwise, we only accept 1 IO per LUN. 6448 * Clear the bit that keeps track of this IO. 6449 */ 6450 else 6451 sym_clr_bit(tp->busy0_map, cp->lun); 6452 6453 /* 6454 * We donnot queue more than 1 ccb per target 6455 * with negotiation at any time. If this ccb was 6456 * used for negotiation, clear this info in the tcb. 6457 */ 6458 if (cp == tp->nego_cp) 6459 tp->nego_cp = 0; 6460 6461 #ifdef SYM_CONF_IARB_SUPPORT 6462 /* 6463 * If we just complete the last queued CCB, 6464 * clear this info that is no longer relevant. 6465 */ 6466 if (cp == np->last_cp) 6467 np->last_cp = 0; 6468 #endif 6469 6470 /* 6471 * Unmap user data from DMA map if needed. 6472 */ 6473 if (cp->dmamapped) { 6474 bus_dmamap_unload(np->data_dmat, cp->dmamap); 6475 cp->dmamapped = 0; 6476 } 6477 6478 /* 6479 * Make this CCB available. 6480 */ 6481 cp->cam_ccb = 0; 6482 cp->host_status = HS_IDLE; 6483 sym_remque(&cp->link_ccbq); 6484 sym_insque_head(&cp->link_ccbq, &np->free_ccbq); 6485 } 6486 6487 /* 6488 * Allocate a CCB from memory and initialize its fixed part. 6489 */ 6490 static ccb_p sym_alloc_ccb(hcb_p np) 6491 { 6492 ccb_p cp = 0; 6493 int hcode; 6494 6495 /* 6496 * Prevent from allocating more CCBs than we can 6497 * queue to the controller. 6498 */ 6499 if (np->actccbs >= SYM_CONF_MAX_START) 6500 return 0; 6501 6502 /* 6503 * Allocate memory for this CCB. 6504 */ 6505 cp = sym_calloc_dma(sizeof(struct sym_ccb), "CCB"); 6506 if (!cp) 6507 goto out_free; 6508 6509 /* 6510 * Allocate a bounce buffer for sense data. 6511 */ 6512 cp->sns_bbuf = sym_calloc_dma(SYM_SNS_BBUF_LEN, "SNS_BBUF"); 6513 if (!cp->sns_bbuf) 6514 goto out_free; 6515 6516 /* 6517 * Allocate a map for the DMA of user data. 6518 */ 6519 if (bus_dmamap_create(np->data_dmat, 0, &cp->dmamap)) 6520 goto out_free; 6521 /* 6522 * Count it. 6523 */ 6524 np->actccbs++; 6525 6526 /* 6527 * Compute the bus address of this ccb. 6528 */ 6529 cp->ccb_ba = vtobus(cp); 6530 6531 /* 6532 * Insert this ccb into the hashed list. 6533 */ 6534 hcode = CCB_HASH_CODE(cp->ccb_ba); 6535 cp->link_ccbh = np->ccbh[hcode]; 6536 np->ccbh[hcode] = cp; 6537 6538 /* 6539 * Initialyze the start and restart actions. 6540 */ 6541 cp->phys.head.go.start = cpu_to_scr(SCRIPTA_BA (np, idle)); 6542 cp->phys.head.go.restart = cpu_to_scr(SCRIPTB_BA (np, bad_i_t_l)); 6543 6544 /* 6545 * Initilialyze some other fields. 6546 */ 6547 cp->phys.smsg_ext.addr = cpu_to_scr(HCB_BA(np, msgin[2])); 6548 6549 /* 6550 * Chain into free ccb queue. 6551 */ 6552 sym_insque_head(&cp->link_ccbq, &np->free_ccbq); 6553 6554 return cp; 6555 out_free: 6556 if (cp) { 6557 if (cp->sns_bbuf) 6558 sym_mfree_dma(cp->sns_bbuf,SYM_SNS_BBUF_LEN,"SNS_BBUF"); 6559 sym_mfree_dma(cp, sizeof(*cp), "CCB"); 6560 } 6561 return 0; 6562 } 6563 6564 /* 6565 * Look up a CCB from a DSA value. 6566 */ 6567 static ccb_p sym_ccb_from_dsa(hcb_p np, u32 dsa) 6568 { 6569 int hcode; 6570 ccb_p cp; 6571 6572 hcode = CCB_HASH_CODE(dsa); 6573 cp = np->ccbh[hcode]; 6574 while (cp) { 6575 if (cp->ccb_ba == dsa) 6576 break; 6577 cp = cp->link_ccbh; 6578 } 6579 6580 return cp; 6581 } 6582 6583 /* 6584 * Target control block initialisation. 6585 * Nothing important to do at the moment. 6586 */ 6587 static void sym_init_tcb (hcb_p np, u_char tn) 6588 { 6589 /* 6590 * Check some alignments required by the chip. 6591 */ 6592 assert (((offsetof(struct sym_reg, nc_sxfer) ^ 6593 offsetof(struct sym_tcb, head.sval)) &3) == 0); 6594 assert (((offsetof(struct sym_reg, nc_scntl3) ^ 6595 offsetof(struct sym_tcb, head.wval)) &3) == 0); 6596 } 6597 6598 /* 6599 * Lun control block allocation and initialization. 6600 */ 6601 static lcb_p sym_alloc_lcb (hcb_p np, u_char tn, u_char ln) 6602 { 6603 tcb_p tp = &np->target[tn]; 6604 lcb_p lp = sym_lp(np, tp, ln); 6605 6606 /* 6607 * Already done, just return. 6608 */ 6609 if (lp) 6610 return lp; 6611 /* 6612 * Check against some race. 6613 */ 6614 assert(!sym_is_bit(tp->busy0_map, ln)); 6615 6616 /* 6617 * Initialize the target control block if not yet. 6618 */ 6619 sym_init_tcb (np, tn); 6620 6621 /* 6622 * Allocate the LCB bus address array. 6623 * Compute the bus address of this table. 6624 */ 6625 if (ln && !tp->luntbl) { 6626 int i; 6627 6628 tp->luntbl = sym_calloc_dma(256, "LUNTBL"); 6629 if (!tp->luntbl) 6630 goto fail; 6631 for (i = 0 ; i < 64 ; i++) 6632 tp->luntbl[i] = cpu_to_scr(vtobus(&np->badlun_sa)); 6633 tp->head.luntbl_sa = cpu_to_scr(vtobus(tp->luntbl)); 6634 } 6635 6636 /* 6637 * Allocate the table of pointers for LUN(s) > 0, if needed. 6638 */ 6639 if (ln && !tp->lunmp) { 6640 tp->lunmp = sym_calloc(SYM_CONF_MAX_LUN * sizeof(lcb_p), 6641 "LUNMP"); 6642 if (!tp->lunmp) 6643 goto fail; 6644 } 6645 6646 /* 6647 * Allocate the lcb. 6648 * Make it available to the chip. 6649 */ 6650 lp = sym_calloc_dma(sizeof(struct sym_lcb), "LCB"); 6651 if (!lp) 6652 goto fail; 6653 if (ln) { 6654 tp->lunmp[ln] = lp; 6655 tp->luntbl[ln] = cpu_to_scr(vtobus(lp)); 6656 } 6657 else { 6658 tp->lun0p = lp; 6659 tp->head.lun0_sa = cpu_to_scr(vtobus(lp)); 6660 } 6661 6662 /* 6663 * Let the itl task point to error handling. 6664 */ 6665 lp->head.itl_task_sa = cpu_to_scr(np->bad_itl_ba); 6666 6667 /* 6668 * Set the reselect pattern to our default. :) 6669 */ 6670 lp->head.resel_sa = cpu_to_scr(SCRIPTB_BA (np, resel_bad_lun)); 6671 6672 /* 6673 * Set user capabilities. 6674 */ 6675 lp->user_flags = tp->usrflags & (SYM_DISC_ENABLED | SYM_TAGS_ENABLED); 6676 6677 fail: 6678 return lp; 6679 } 6680 6681 /* 6682 * Allocate LCB resources for tagged command queuing. 6683 */ 6684 static void sym_alloc_lcb_tags (hcb_p np, u_char tn, u_char ln) 6685 { 6686 tcb_p tp = &np->target[tn]; 6687 lcb_p lp = sym_lp(np, tp, ln); 6688 int i; 6689 6690 /* 6691 * If LCB not available, try to allocate it. 6692 */ 6693 if (!lp && !(lp = sym_alloc_lcb(np, tn, ln))) 6694 goto fail; 6695 6696 /* 6697 * Allocate the task table and and the tag allocation 6698 * circular buffer. We want both or none. 6699 */ 6700 lp->itlq_tbl = sym_calloc_dma(SYM_CONF_MAX_TASK*4, "ITLQ_TBL"); 6701 if (!lp->itlq_tbl) 6702 goto fail; 6703 lp->cb_tags = sym_calloc(SYM_CONF_MAX_TASK, "CB_TAGS"); 6704 if (!lp->cb_tags) { 6705 sym_mfree_dma(lp->itlq_tbl, SYM_CONF_MAX_TASK*4, "ITLQ_TBL"); 6706 lp->itlq_tbl = 0; 6707 goto fail; 6708 } 6709 6710 /* 6711 * Initialize the task table with invalid entries. 6712 */ 6713 for (i = 0 ; i < SYM_CONF_MAX_TASK ; i++) 6714 lp->itlq_tbl[i] = cpu_to_scr(np->notask_ba); 6715 6716 /* 6717 * Fill up the tag buffer with tag numbers. 6718 */ 6719 for (i = 0 ; i < SYM_CONF_MAX_TASK ; i++) 6720 lp->cb_tags[i] = i; 6721 6722 /* 6723 * Make the task table available to SCRIPTS, 6724 * And accept tagged commands now. 6725 */ 6726 lp->head.itlq_tbl_sa = cpu_to_scr(vtobus(lp->itlq_tbl)); 6727 6728 return; 6729 fail: 6730 return; 6731 } 6732 6733 /* 6734 * Test the pci bus snoop logic :-( 6735 * 6736 * Has to be called with interrupts disabled. 6737 */ 6738 #ifndef SYM_CONF_IOMAPPED 6739 static int sym_regtest (hcb_p np) 6740 { 6741 register volatile u32 data; 6742 /* 6743 * chip registers may NOT be cached. 6744 * write 0xffffffff to a read only register area, 6745 * and try to read it back. 6746 */ 6747 data = 0xffffffff; 6748 OUTL_OFF(offsetof(struct sym_reg, nc_dstat), data); 6749 data = INL_OFF(offsetof(struct sym_reg, nc_dstat)); 6750 #if 1 6751 if (data == 0xffffffff) { 6752 #else 6753 if ((data & 0xe2f0fffd) != 0x02000080) { 6754 #endif 6755 printf ("CACHE TEST FAILED: reg dstat-sstat2 readback %x.\n", 6756 (unsigned) data); 6757 return (0x10); 6758 }; 6759 return (0); 6760 } 6761 #endif 6762 6763 static int sym_snooptest (hcb_p np) 6764 { 6765 u32 sym_rd, sym_wr, sym_bk, host_rd, host_wr, pc, dstat; 6766 int i, err=0; 6767 #ifndef SYM_CONF_IOMAPPED 6768 err |= sym_regtest (np); 6769 if (err) return (err); 6770 #endif 6771 restart_test: 6772 /* 6773 * Enable Master Parity Checking as we intend 6774 * to enable it for normal operations. 6775 */ 6776 OUTB (nc_ctest4, (np->rv_ctest4 & MPEE)); 6777 /* 6778 * init 6779 */ 6780 pc = SCRIPTB0_BA (np, snooptest); 6781 host_wr = 1; 6782 sym_wr = 2; 6783 /* 6784 * Set memory and register. 6785 */ 6786 np->cache = cpu_to_scr(host_wr); 6787 OUTL (nc_temp, sym_wr); 6788 /* 6789 * Start script (exchange values) 6790 */ 6791 OUTL (nc_dsa, np->hcb_ba); 6792 OUTL_DSP (pc); 6793 /* 6794 * Wait 'til done (with timeout) 6795 */ 6796 for (i=0; i<SYM_SNOOP_TIMEOUT; i++) 6797 if (INB(nc_istat) & (INTF|SIP|DIP)) 6798 break; 6799 if (i>=SYM_SNOOP_TIMEOUT) { 6800 printf ("CACHE TEST FAILED: timeout.\n"); 6801 return (0x20); 6802 }; 6803 /* 6804 * Check for fatal DMA errors. 6805 */ 6806 dstat = INB (nc_dstat); 6807 #if 1 /* Band aiding for broken hardwares that fail PCI parity */ 6808 if ((dstat & MDPE) && (np->rv_ctest4 & MPEE)) { 6809 printf ("%s: PCI DATA PARITY ERROR DETECTED - " 6810 "DISABLING MASTER DATA PARITY CHECKING.\n", 6811 sym_name(np)); 6812 np->rv_ctest4 &= ~MPEE; 6813 goto restart_test; 6814 } 6815 #endif 6816 if (dstat & (MDPE|BF|IID)) { 6817 printf ("CACHE TEST FAILED: DMA error (dstat=0x%02x).", dstat); 6818 return (0x80); 6819 } 6820 /* 6821 * Save termination position. 6822 */ 6823 pc = INL (nc_dsp); 6824 /* 6825 * Read memory and register. 6826 */ 6827 host_rd = scr_to_cpu(np->cache); 6828 sym_rd = INL (nc_scratcha); 6829 sym_bk = INL (nc_temp); 6830 6831 /* 6832 * Check termination position. 6833 */ 6834 if (pc != SCRIPTB0_BA (np, snoopend)+8) { 6835 printf ("CACHE TEST FAILED: script execution failed.\n"); 6836 printf ("start=%08lx, pc=%08lx, end=%08lx\n", 6837 (u_long) SCRIPTB0_BA (np, snooptest), (u_long) pc, 6838 (u_long) SCRIPTB0_BA (np, snoopend) +8); 6839 return (0x40); 6840 }; 6841 /* 6842 * Show results. 6843 */ 6844 if (host_wr != sym_rd) { 6845 printf ("CACHE TEST FAILED: host wrote %d, chip read %d.\n", 6846 (int) host_wr, (int) sym_rd); 6847 err |= 1; 6848 }; 6849 if (host_rd != sym_wr) { 6850 printf ("CACHE TEST FAILED: chip wrote %d, host read %d.\n", 6851 (int) sym_wr, (int) host_rd); 6852 err |= 2; 6853 }; 6854 if (sym_bk != sym_wr) { 6855 printf ("CACHE TEST FAILED: chip wrote %d, read back %d.\n", 6856 (int) sym_wr, (int) sym_bk); 6857 err |= 4; 6858 }; 6859 6860 return (err); 6861 } 6862 6863 /* 6864 * Determine the chip's clock frequency. 6865 * 6866 * This is essential for the negotiation of the synchronous 6867 * transfer rate. 6868 * 6869 * Note: we have to return the correct value. 6870 * THERE IS NO SAFE DEFAULT VALUE. 6871 * 6872 * Most NCR/SYMBIOS boards are delivered with a 40 Mhz clock. 6873 * 53C860 and 53C875 rev. 1 support fast20 transfers but 6874 * do not have a clock doubler and so are provided with a 6875 * 80 MHz clock. All other fast20 boards incorporate a doubler 6876 * and so should be delivered with a 40 MHz clock. 6877 * The recent fast40 chips (895/896/895A/1010) use a 40 Mhz base 6878 * clock and provide a clock quadrupler (160 Mhz). 6879 */ 6880 6881 /* 6882 * Select SCSI clock frequency 6883 */ 6884 static void sym_selectclock(hcb_p np, u_char scntl3) 6885 { 6886 /* 6887 * If multiplier not present or not selected, leave here. 6888 */ 6889 if (np->multiplier <= 1) { 6890 OUTB(nc_scntl3, scntl3); 6891 return; 6892 } 6893 6894 if (sym_verbose >= 2) 6895 printf ("%s: enabling clock multiplier\n", sym_name(np)); 6896 6897 OUTB(nc_stest1, DBLEN); /* Enable clock multiplier */ 6898 /* 6899 * Wait for the LCKFRQ bit to be set if supported by the chip. 6900 * Otherwise wait 20 micro-seconds. 6901 */ 6902 if (np->features & FE_LCKFRQ) { 6903 int i = 20; 6904 while (!(INB(nc_stest4) & LCKFRQ) && --i > 0) 6905 UDELAY (20); 6906 if (!i) 6907 printf("%s: the chip cannot lock the frequency\n", 6908 sym_name(np)); 6909 } else 6910 UDELAY (20); 6911 OUTB(nc_stest3, HSC); /* Halt the scsi clock */ 6912 OUTB(nc_scntl3, scntl3); 6913 OUTB(nc_stest1, (DBLEN|DBLSEL));/* Select clock multiplier */ 6914 OUTB(nc_stest3, 0x00); /* Restart scsi clock */ 6915 } 6916 6917 /* 6918 * calculate SCSI clock frequency (in KHz) 6919 */ 6920 static unsigned getfreq (hcb_p np, int gen) 6921 { 6922 unsigned int ms = 0; 6923 unsigned int f; 6924 6925 /* 6926 * Measure GEN timer delay in order 6927 * to calculate SCSI clock frequency 6928 * 6929 * This code will never execute too 6930 * many loop iterations (if DELAY is 6931 * reasonably correct). It could get 6932 * too low a delay (too high a freq.) 6933 * if the CPU is slow executing the 6934 * loop for some reason (an NMI, for 6935 * example). For this reason we will 6936 * if multiple measurements are to be 6937 * performed trust the higher delay 6938 * (lower frequency returned). 6939 */ 6940 OUTW (nc_sien , 0); /* mask all scsi interrupts */ 6941 (void) INW (nc_sist); /* clear pending scsi interrupt */ 6942 OUTB (nc_dien , 0); /* mask all dma interrupts */ 6943 (void) INW (nc_sist); /* another one, just to be sure :) */ 6944 OUTB (nc_scntl3, 4); /* set pre-scaler to divide by 3 */ 6945 OUTB (nc_stime1, 0); /* disable general purpose timer */ 6946 OUTB (nc_stime1, gen); /* set to nominal delay of 1<<gen * 125us */ 6947 while (!(INW(nc_sist) & GEN) && ms++ < 100000) 6948 UDELAY (1000); /* count ms */ 6949 OUTB (nc_stime1, 0); /* disable general purpose timer */ 6950 /* 6951 * set prescaler to divide by whatever 0 means 6952 * 0 ought to choose divide by 2, but appears 6953 * to set divide by 3.5 mode in my 53c810 ... 6954 */ 6955 OUTB (nc_scntl3, 0); 6956 6957 /* 6958 * adjust for prescaler, and convert into KHz 6959 */ 6960 f = ms ? ((1 << gen) * 4340) / ms : 0; 6961 6962 if (sym_verbose >= 2) 6963 printf ("%s: Delay (GEN=%d): %u msec, %u KHz\n", 6964 sym_name(np), gen, ms, f); 6965 6966 return f; 6967 } 6968 6969 static unsigned sym_getfreq (hcb_p np) 6970 { 6971 u_int f1, f2; 6972 int gen = 11; 6973 6974 (void) getfreq (np, gen); /* throw away first result */ 6975 f1 = getfreq (np, gen); 6976 f2 = getfreq (np, gen); 6977 if (f1 > f2) f1 = f2; /* trust lower result */ 6978 return f1; 6979 } 6980 6981 /* 6982 * Get/probe chip SCSI clock frequency 6983 */ 6984 static void sym_getclock (hcb_p np, int mult) 6985 { 6986 unsigned char scntl3 = np->sv_scntl3; 6987 unsigned char stest1 = np->sv_stest1; 6988 unsigned f1; 6989 6990 /* 6991 * For the C10 core, assume 40 MHz. 6992 */ 6993 if (np->features & FE_C10) { 6994 np->multiplier = mult; 6995 np->clock_khz = 40000 * mult; 6996 return; 6997 } 6998 6999 np->multiplier = 1; 7000 f1 = 40000; 7001 /* 7002 * True with 875/895/896/895A with clock multiplier selected 7003 */ 7004 if (mult > 1 && (stest1 & (DBLEN+DBLSEL)) == DBLEN+DBLSEL) { 7005 if (sym_verbose >= 2) 7006 printf ("%s: clock multiplier found\n", sym_name(np)); 7007 np->multiplier = mult; 7008 } 7009 7010 /* 7011 * If multiplier not found or scntl3 not 7,5,3, 7012 * reset chip and get frequency from general purpose timer. 7013 * Otherwise trust scntl3 BIOS setting. 7014 */ 7015 if (np->multiplier != mult || (scntl3 & 7) < 3 || !(scntl3 & 1)) { 7016 OUTB (nc_stest1, 0); /* make sure doubler is OFF */ 7017 f1 = sym_getfreq (np); 7018 7019 if (sym_verbose) 7020 printf ("%s: chip clock is %uKHz\n", sym_name(np), f1); 7021 7022 if (f1 < 45000) f1 = 40000; 7023 else if (f1 < 55000) f1 = 50000; 7024 else f1 = 80000; 7025 7026 if (f1 < 80000 && mult > 1) { 7027 if (sym_verbose >= 2) 7028 printf ("%s: clock multiplier assumed\n", 7029 sym_name(np)); 7030 np->multiplier = mult; 7031 } 7032 } else { 7033 if ((scntl3 & 7) == 3) f1 = 40000; 7034 else if ((scntl3 & 7) == 5) f1 = 80000; 7035 else f1 = 160000; 7036 7037 f1 /= np->multiplier; 7038 } 7039 7040 /* 7041 * Compute controller synchronous parameters. 7042 */ 7043 f1 *= np->multiplier; 7044 np->clock_khz = f1; 7045 } 7046 7047 /* 7048 * Get/probe PCI clock frequency 7049 */ 7050 static int sym_getpciclock (hcb_p np) 7051 { 7052 int f = 0; 7053 7054 /* 7055 * For the C1010-33, this doesn't work. 7056 * For the C1010-66, this will be tested when I'll have 7057 * such a beast to play with. 7058 */ 7059 if (!(np->features & FE_C10)) { 7060 OUTB (nc_stest1, SCLK); /* Use the PCI clock as SCSI clock */ 7061 f = (int) sym_getfreq (np); 7062 OUTB (nc_stest1, 0); 7063 } 7064 np->pciclk_khz = f; 7065 7066 return f; 7067 } 7068 7069 /*============= DRIVER ACTION/COMPLETION ====================*/ 7070 7071 /* 7072 * Print something that tells about extended errors. 7073 */ 7074 static void sym_print_xerr(ccb_p cp, int x_status) 7075 { 7076 if (x_status & XE_PARITY_ERR) { 7077 PRINT_ADDR(cp); 7078 printf ("unrecovered SCSI parity error.\n"); 7079 } 7080 if (x_status & XE_EXTRA_DATA) { 7081 PRINT_ADDR(cp); 7082 printf ("extraneous data discarded.\n"); 7083 } 7084 if (x_status & XE_BAD_PHASE) { 7085 PRINT_ADDR(cp); 7086 printf ("illegal scsi phase (4/5).\n"); 7087 } 7088 if (x_status & XE_SODL_UNRUN) { 7089 PRINT_ADDR(cp); 7090 printf ("ODD transfer in DATA OUT phase.\n"); 7091 } 7092 if (x_status & XE_SWIDE_OVRUN) { 7093 PRINT_ADDR(cp); 7094 printf ("ODD transfer in DATA IN phase.\n"); 7095 } 7096 } 7097 7098 /* 7099 * Choose the more appropriate CAM status if 7100 * the IO encountered an extended error. 7101 */ 7102 static int sym_xerr_cam_status(int cam_status, int x_status) 7103 { 7104 if (x_status) { 7105 if (x_status & XE_PARITY_ERR) 7106 cam_status = CAM_UNCOR_PARITY; 7107 else if (x_status &(XE_EXTRA_DATA|XE_SODL_UNRUN|XE_SWIDE_OVRUN)) 7108 cam_status = CAM_DATA_RUN_ERR; 7109 else if (x_status & XE_BAD_PHASE) 7110 cam_status = CAM_REQ_CMP_ERR; 7111 else 7112 cam_status = CAM_REQ_CMP_ERR; 7113 } 7114 return cam_status; 7115 } 7116 7117 /* 7118 * Complete execution of a SCSI command with extented 7119 * error, SCSI status error, or having been auto-sensed. 7120 * 7121 * The SCRIPTS processor is not running there, so we 7122 * can safely access IO registers and remove JOBs from 7123 * the START queue. 7124 * SCRATCHA is assumed to have been loaded with STARTPOS 7125 * before the SCRIPTS called the C code. 7126 */ 7127 static void sym_complete_error (hcb_p np, ccb_p cp) 7128 { 7129 struct ccb_scsiio *csio; 7130 u_int cam_status; 7131 int i; 7132 7133 /* 7134 * Paranoid check. :) 7135 */ 7136 if (!cp || !cp->cam_ccb) 7137 return; 7138 7139 if (DEBUG_FLAGS & (DEBUG_TINY|DEBUG_RESULT)) { 7140 printf ("CCB=%lx STAT=%x/%x/%x DEV=%d/%d\n", (unsigned long)cp, 7141 cp->host_status, cp->ssss_status, cp->host_flags, 7142 cp->target, cp->lun); 7143 MDELAY(100); 7144 } 7145 7146 /* 7147 * Get CAM command pointer. 7148 */ 7149 csio = &cp->cam_ccb->csio; 7150 7151 /* 7152 * Check for extended errors. 7153 */ 7154 if (cp->xerr_status) { 7155 if (sym_verbose) 7156 sym_print_xerr(cp, cp->xerr_status); 7157 if (cp->host_status == HS_COMPLETE) 7158 cp->host_status = HS_COMP_ERR; 7159 } 7160 7161 /* 7162 * Calculate the residual. 7163 */ 7164 csio->sense_resid = 0; 7165 csio->resid = sym_compute_residual(np, cp); 7166 7167 if (!SYM_CONF_RESIDUAL_SUPPORT) {/* If user does not want residuals */ 7168 csio->resid = 0; /* throw them away. :) */ 7169 cp->sv_resid = 0; 7170 } 7171 7172 if (cp->host_flags & HF_SENSE) { /* Auto sense */ 7173 csio->scsi_status = cp->sv_scsi_status; /* Restore status */ 7174 csio->sense_resid = csio->resid; /* Swap residuals */ 7175 csio->resid = cp->sv_resid; 7176 cp->sv_resid = 0; 7177 if (sym_verbose && cp->sv_xerr_status) 7178 sym_print_xerr(cp, cp->sv_xerr_status); 7179 if (cp->host_status == HS_COMPLETE && 7180 cp->ssss_status == S_GOOD && 7181 cp->xerr_status == 0) { 7182 cam_status = sym_xerr_cam_status(CAM_SCSI_STATUS_ERROR, 7183 cp->sv_xerr_status); 7184 cam_status |= CAM_AUTOSNS_VALID; 7185 /* 7186 * Bounce back the sense data to user and 7187 * fix the residual. 7188 */ 7189 bzero(&csio->sense_data, csio->sense_len); 7190 bcopy(cp->sns_bbuf, &csio->sense_data, 7191 MIN(csio->sense_len, SYM_SNS_BBUF_LEN)); 7192 csio->sense_resid += csio->sense_len; 7193 csio->sense_resid -= SYM_SNS_BBUF_LEN; 7194 #if 0 7195 /* 7196 * If the device reports a UNIT ATTENTION condition 7197 * due to a RESET condition, we should consider all 7198 * disconnect CCBs for this unit as aborted. 7199 */ 7200 if (1) { 7201 u_char *p; 7202 p = (u_char *) csio->sense_data; 7203 if (p[0]==0x70 && p[2]==0x6 && p[12]==0x29) 7204 sym_clear_tasks(np, CAM_REQ_ABORTED, 7205 cp->target,cp->lun, -1); 7206 } 7207 #endif 7208 } 7209 else 7210 cam_status = CAM_AUTOSENSE_FAIL; 7211 } 7212 else if (cp->host_status == HS_COMPLETE) { /* Bad SCSI status */ 7213 csio->scsi_status = cp->ssss_status; 7214 cam_status = CAM_SCSI_STATUS_ERROR; 7215 } 7216 else if (cp->host_status == HS_SEL_TIMEOUT) /* Selection timeout */ 7217 cam_status = CAM_SEL_TIMEOUT; 7218 else if (cp->host_status == HS_UNEXPECTED) /* Unexpected BUS FREE*/ 7219 cam_status = CAM_UNEXP_BUSFREE; 7220 else { /* Extended error */ 7221 if (sym_verbose) { 7222 PRINT_ADDR(cp); 7223 printf ("COMMAND FAILED (%x %x %x).\n", 7224 cp->host_status, cp->ssss_status, 7225 cp->xerr_status); 7226 } 7227 csio->scsi_status = cp->ssss_status; 7228 /* 7229 * Set the most appropriate value for CAM status. 7230 */ 7231 cam_status = sym_xerr_cam_status(CAM_REQ_CMP_ERR, 7232 cp->xerr_status); 7233 } 7234 7235 /* 7236 * Dequeue all queued CCBs for that device 7237 * not yet started by SCRIPTS. 7238 */ 7239 i = (INL (nc_scratcha) - np->squeue_ba) / 4; 7240 (void) sym_dequeue_from_squeue(np, i, cp->target, cp->lun, -1); 7241 7242 /* 7243 * Restart the SCRIPTS processor. 7244 */ 7245 OUTL_DSP (SCRIPTA_BA (np, start)); 7246 7247 /* 7248 * Synchronize DMA map if needed. 7249 */ 7250 if (cp->dmamapped) { 7251 bus_dmamap_sync(np->data_dmat, cp->dmamap, 7252 (cp->dmamapped == SYM_DMA_READ ? 7253 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 7254 } 7255 /* 7256 * Add this one to the COMP queue. 7257 * Complete all those commands with either error 7258 * or requeue condition. 7259 */ 7260 sym_set_cam_status((union ccb *) csio, cam_status); 7261 sym_remque(&cp->link_ccbq); 7262 sym_insque_head(&cp->link_ccbq, &np->comp_ccbq); 7263 sym_flush_comp_queue(np, 0); 7264 } 7265 7266 /* 7267 * Complete execution of a successful SCSI command. 7268 * 7269 * Only successful commands go to the DONE queue, 7270 * since we need to have the SCRIPTS processor 7271 * stopped on any error condition. 7272 * The SCRIPTS processor is running while we are 7273 * completing successful commands. 7274 */ 7275 static void sym_complete_ok (hcb_p np, ccb_p cp) 7276 { 7277 struct ccb_scsiio *csio; 7278 tcb_p tp; 7279 lcb_p lp; 7280 7281 /* 7282 * Paranoid check. :) 7283 */ 7284 if (!cp || !cp->cam_ccb) 7285 return; 7286 assert (cp->host_status == HS_COMPLETE); 7287 7288 /* 7289 * Get command, target and lun pointers. 7290 */ 7291 csio = &cp->cam_ccb->csio; 7292 tp = &np->target[cp->target]; 7293 lp = sym_lp(np, tp, cp->lun); 7294 7295 /* 7296 * Assume device discovered on first success. 7297 */ 7298 if (!lp) 7299 sym_set_bit(tp->lun_map, cp->lun); 7300 7301 /* 7302 * If all data have been transferred, given than no 7303 * extended error did occur, there is no residual. 7304 */ 7305 csio->resid = 0; 7306 if (cp->phys.head.lastp != cp->phys.head.goalp) 7307 csio->resid = sym_compute_residual(np, cp); 7308 7309 /* 7310 * Wrong transfer residuals may be worse than just always 7311 * returning zero. User can disable this feature from 7312 * sym_conf.h. Residual support is enabled by default. 7313 */ 7314 if (!SYM_CONF_RESIDUAL_SUPPORT) 7315 csio->resid = 0; 7316 7317 /* 7318 * Synchronize DMA map if needed. 7319 */ 7320 if (cp->dmamapped) { 7321 bus_dmamap_sync(np->data_dmat, cp->dmamap, 7322 (cp->dmamapped == SYM_DMA_READ ? 7323 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 7324 } 7325 /* 7326 * Set status and complete the command. 7327 */ 7328 csio->scsi_status = cp->ssss_status; 7329 sym_set_cam_status((union ccb *) csio, CAM_REQ_CMP); 7330 sym_free_ccb (np, cp); 7331 sym_xpt_done(np, (union ccb *) csio); 7332 } 7333 7334 /* 7335 * Our timeout handler. 7336 */ 7337 static void sym_timeout1(void *arg) 7338 { 7339 union ccb *ccb = (union ccb *) arg; 7340 hcb_p np = ccb->ccb_h.sym_hcb_ptr; 7341 7342 /* 7343 * Check that the CAM CCB is still queued. 7344 */ 7345 if (!np) 7346 return; 7347 7348 switch(ccb->ccb_h.func_code) { 7349 case XPT_SCSI_IO: 7350 (void) sym_abort_scsiio(np, ccb, 1); 7351 break; 7352 default: 7353 break; 7354 } 7355 } 7356 7357 static void sym_timeout(void *arg) 7358 { 7359 int s = splcam(); 7360 sym_timeout1(arg); 7361 splx(s); 7362 } 7363 7364 /* 7365 * Abort an SCSI IO. 7366 */ 7367 static int sym_abort_scsiio(hcb_p np, union ccb *ccb, int timed_out) 7368 { 7369 ccb_p cp; 7370 SYM_QUEHEAD *qp; 7371 7372 /* 7373 * Look up our CCB control block. 7374 */ 7375 cp = 0; 7376 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) { 7377 ccb_p cp2 = sym_que_entry(qp, struct sym_ccb, link_ccbq); 7378 if (cp2->cam_ccb == ccb) { 7379 cp = cp2; 7380 break; 7381 } 7382 } 7383 if (!cp || cp->host_status == HS_WAIT) 7384 return -1; 7385 7386 /* 7387 * If a previous abort didn't succeed in time, 7388 * perform a BUS reset. 7389 */ 7390 if (cp->to_abort) { 7391 sym_reset_scsi_bus(np, 1); 7392 return 0; 7393 } 7394 7395 /* 7396 * Mark the CCB for abort and allow time for. 7397 */ 7398 cp->to_abort = timed_out ? 2 : 1; 7399 ccb->ccb_h.timeout_ch = timeout(sym_timeout, (caddr_t) ccb, 10*hz); 7400 7401 /* 7402 * Tell the SCRIPTS processor to stop and synchronize with us. 7403 */ 7404 np->istat_sem = SEM; 7405 OUTB (nc_istat, SIGP|SEM); 7406 return 0; 7407 } 7408 7409 /* 7410 * Reset a SCSI device (all LUNs of a target). 7411 */ 7412 static void sym_reset_dev(hcb_p np, union ccb *ccb) 7413 { 7414 tcb_p tp; 7415 struct ccb_hdr *ccb_h = &ccb->ccb_h; 7416 7417 if (ccb_h->target_id == np->myaddr || 7418 ccb_h->target_id >= SYM_CONF_MAX_TARGET || 7419 ccb_h->target_lun >= SYM_CONF_MAX_LUN) { 7420 sym_xpt_done2(np, ccb, CAM_DEV_NOT_THERE); 7421 return; 7422 } 7423 7424 tp = &np->target[ccb_h->target_id]; 7425 7426 tp->to_reset = 1; 7427 sym_xpt_done2(np, ccb, CAM_REQ_CMP); 7428 7429 np->istat_sem = SEM; 7430 OUTB (nc_istat, SIGP|SEM); 7431 return; 7432 } 7433 7434 /* 7435 * SIM action entry point. 7436 */ 7437 static void sym_action(struct cam_sim *sim, union ccb *ccb) 7438 { 7439 int s = splcam(); 7440 sym_action1(sim, ccb); 7441 splx(s); 7442 } 7443 7444 static void sym_action1(struct cam_sim *sim, union ccb *ccb) 7445 { 7446 hcb_p np; 7447 tcb_p tp; 7448 lcb_p lp; 7449 ccb_p cp; 7450 int tmp; 7451 u_char idmsg, *msgptr; 7452 u_int msglen; 7453 struct ccb_scsiio *csio; 7454 struct ccb_hdr *ccb_h; 7455 7456 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("sym_action\n")); 7457 7458 /* 7459 * Retrieve our controller data structure. 7460 */ 7461 np = (hcb_p) cam_sim_softc(sim); 7462 7463 /* 7464 * The common case is SCSI IO. 7465 * We deal with other ones elsewhere. 7466 */ 7467 if (ccb->ccb_h.func_code != XPT_SCSI_IO) { 7468 sym_action2(sim, ccb); 7469 return; 7470 } 7471 csio = &ccb->csio; 7472 ccb_h = &csio->ccb_h; 7473 7474 /* 7475 * Work around races. 7476 */ 7477 if ((ccb_h->status & CAM_STATUS_MASK) != CAM_REQ_INPROG) { 7478 xpt_done(ccb); 7479 return; 7480 } 7481 7482 /* 7483 * Minimal checkings, so that we will not 7484 * go outside our tables. 7485 */ 7486 if (ccb_h->target_id == np->myaddr || 7487 ccb_h->target_id >= SYM_CONF_MAX_TARGET || 7488 ccb_h->target_lun >= SYM_CONF_MAX_LUN) { 7489 sym_xpt_done2(np, ccb, CAM_DEV_NOT_THERE); 7490 return; 7491 } 7492 7493 /* 7494 * Retreive the target and lun descriptors. 7495 */ 7496 tp = &np->target[ccb_h->target_id]; 7497 lp = sym_lp(np, tp, ccb_h->target_lun); 7498 7499 /* 7500 * Complete the 1st INQUIRY command with error 7501 * condition if the device is flagged NOSCAN 7502 * at BOOT in the NVRAM. This may speed up 7503 * the boot and maintain coherency with BIOS 7504 * device numbering. Clearing the flag allows 7505 * user to rescan skipped devices later. 7506 * We also return error for devices not flagged 7507 * for SCAN LUNS in the NVRAM since some mono-lun 7508 * devices behave badly when asked for some non 7509 * zero LUN. Btw, this is an absolute hack.:-) 7510 */ 7511 if (!(ccb_h->flags & CAM_CDB_PHYS) && 7512 (0x12 == ((ccb_h->flags & CAM_CDB_POINTER) ? 7513 csio->cdb_io.cdb_ptr[0] : csio->cdb_io.cdb_bytes[0]))) { 7514 if ((tp->usrflags & SYM_SCAN_BOOT_DISABLED) || 7515 ((tp->usrflags & SYM_SCAN_LUNS_DISABLED) && 7516 ccb_h->target_lun != 0)) { 7517 tp->usrflags &= ~SYM_SCAN_BOOT_DISABLED; 7518 sym_xpt_done2(np, ccb, CAM_DEV_NOT_THERE); 7519 return; 7520 } 7521 } 7522 7523 /* 7524 * Get a control block for this IO. 7525 */ 7526 tmp = ((ccb_h->flags & CAM_TAG_ACTION_VALID) != 0); 7527 cp = sym_get_ccb(np, ccb_h->target_id, ccb_h->target_lun, tmp); 7528 if (!cp) { 7529 sym_xpt_done2(np, ccb, CAM_RESRC_UNAVAIL); 7530 return; 7531 } 7532 7533 /* 7534 * Keep track of the IO in our CCB. 7535 */ 7536 cp->cam_ccb = ccb; 7537 7538 /* 7539 * Build the IDENTIFY message. 7540 */ 7541 idmsg = M_IDENTIFY | cp->lun; 7542 if (cp->tag != NO_TAG || (lp && (lp->current_flags & SYM_DISC_ENABLED))) 7543 idmsg |= 0x40; 7544 7545 msgptr = cp->scsi_smsg; 7546 msglen = 0; 7547 msgptr[msglen++] = idmsg; 7548 7549 /* 7550 * Build the tag message if present. 7551 */ 7552 if (cp->tag != NO_TAG) { 7553 u_char order = csio->tag_action; 7554 7555 switch(order) { 7556 case M_ORDERED_TAG: 7557 break; 7558 case M_HEAD_TAG: 7559 break; 7560 default: 7561 order = M_SIMPLE_TAG; 7562 } 7563 msgptr[msglen++] = order; 7564 7565 /* 7566 * For less than 128 tags, actual tags are numbered 7567 * 1,3,5,..2*MAXTAGS+1,since we may have to deal 7568 * with devices that have problems with #TAG 0 or too 7569 * great #TAG numbers. For more tags (up to 256), 7570 * we use directly our tag number. 7571 */ 7572 #if SYM_CONF_MAX_TASK > (512/4) 7573 msgptr[msglen++] = cp->tag; 7574 #else 7575 msgptr[msglen++] = (cp->tag << 1) + 1; 7576 #endif 7577 } 7578 7579 /* 7580 * Build a negotiation message if needed. 7581 * (nego_status is filled by sym_prepare_nego()) 7582 */ 7583 cp->nego_status = 0; 7584 if (tp->tinfo.current.width != tp->tinfo.goal.width || 7585 tp->tinfo.current.period != tp->tinfo.goal.period || 7586 tp->tinfo.current.offset != tp->tinfo.goal.offset || 7587 tp->tinfo.current.options != tp->tinfo.goal.options) { 7588 if (!tp->nego_cp && lp) 7589 msglen += sym_prepare_nego(np, cp, 0, msgptr + msglen); 7590 } 7591 7592 /* 7593 * Fill in our ccb 7594 */ 7595 7596 /* 7597 * Startqueue 7598 */ 7599 cp->phys.head.go.start = cpu_to_scr(SCRIPTA_BA (np, select)); 7600 cp->phys.head.go.restart = cpu_to_scr(SCRIPTA_BA (np, resel_dsa)); 7601 7602 /* 7603 * select 7604 */ 7605 cp->phys.select.sel_id = cp->target; 7606 cp->phys.select.sel_scntl3 = tp->head.wval; 7607 cp->phys.select.sel_sxfer = tp->head.sval; 7608 cp->phys.select.sel_scntl4 = tp->head.uval; 7609 7610 /* 7611 * message 7612 */ 7613 cp->phys.smsg.addr = cpu_to_scr(CCB_BA (cp, scsi_smsg)); 7614 cp->phys.smsg.size = cpu_to_scr(msglen); 7615 7616 /* 7617 * command 7618 */ 7619 if (sym_setup_cdb(np, csio, cp) < 0) { 7620 sym_free_ccb(np, cp); 7621 sym_xpt_done(np, ccb); 7622 return; 7623 } 7624 7625 /* 7626 * status 7627 */ 7628 #if 0 /* Provision */ 7629 cp->actualquirks = tp->quirks; 7630 #endif 7631 cp->actualquirks = SYM_QUIRK_AUTOSAVE; 7632 cp->host_status = cp->nego_status ? HS_NEGOTIATE : HS_BUSY; 7633 cp->ssss_status = S_ILLEGAL; 7634 cp->xerr_status = 0; 7635 cp->host_flags = 0; 7636 cp->extra_bytes = 0; 7637 7638 /* 7639 * extreme data pointer. 7640 * shall be positive, so -1 is lower than lowest.:) 7641 */ 7642 cp->ext_sg = -1; 7643 cp->ext_ofs = 0; 7644 7645 /* 7646 * Build the data descriptor block 7647 * and start the IO. 7648 */ 7649 sym_setup_data_and_start(np, csio, cp); 7650 } 7651 7652 /* 7653 * Setup buffers and pointers that address the CDB. 7654 * I bet, physical CDBs will never be used on the planet, 7655 * since they can be bounced without significant overhead. 7656 */ 7657 static int sym_setup_cdb(hcb_p np, struct ccb_scsiio *csio, ccb_p cp) 7658 { 7659 struct ccb_hdr *ccb_h; 7660 u32 cmd_ba; 7661 int cmd_len; 7662 7663 ccb_h = &csio->ccb_h; 7664 7665 /* 7666 * CDB is 16 bytes max. 7667 */ 7668 if (csio->cdb_len > sizeof(cp->cdb_buf)) { 7669 sym_set_cam_status(cp->cam_ccb, CAM_REQ_INVALID); 7670 return -1; 7671 } 7672 cmd_len = csio->cdb_len; 7673 7674 if (ccb_h->flags & CAM_CDB_POINTER) { 7675 /* CDB is a pointer */ 7676 if (!(ccb_h->flags & CAM_CDB_PHYS)) { 7677 /* CDB pointer is virtual */ 7678 bcopy(csio->cdb_io.cdb_ptr, cp->cdb_buf, cmd_len); 7679 cmd_ba = CCB_BA (cp, cdb_buf[0]); 7680 } else { 7681 /* CDB pointer is physical */ 7682 #if 0 7683 cmd_ba = ((u32)csio->cdb_io.cdb_ptr) & 0xffffffff; 7684 #else 7685 sym_set_cam_status(cp->cam_ccb, CAM_REQ_INVALID); 7686 return -1; 7687 #endif 7688 } 7689 } else { 7690 /* CDB is in the CAM ccb (buffer) */ 7691 bcopy(csio->cdb_io.cdb_bytes, cp->cdb_buf, cmd_len); 7692 cmd_ba = CCB_BA (cp, cdb_buf[0]); 7693 } 7694 7695 cp->phys.cmd.addr = cpu_to_scr(cmd_ba); 7696 cp->phys.cmd.size = cpu_to_scr(cmd_len); 7697 7698 return 0; 7699 } 7700 7701 /* 7702 * Set up data pointers used by SCRIPTS. 7703 */ 7704 static void __inline 7705 sym_setup_data_pointers(hcb_p np, ccb_p cp, int dir) 7706 { 7707 u32 lastp, goalp; 7708 7709 /* 7710 * No segments means no data. 7711 */ 7712 if (!cp->segments) 7713 dir = CAM_DIR_NONE; 7714 7715 /* 7716 * Set the data pointer. 7717 */ 7718 switch(dir) { 7719 case CAM_DIR_OUT: 7720 goalp = SCRIPTA_BA (np, data_out2) + 8; 7721 lastp = goalp - 8 - (cp->segments * (2*4)); 7722 break; 7723 case CAM_DIR_IN: 7724 cp->host_flags |= HF_DATA_IN; 7725 goalp = SCRIPTA_BA (np, data_in2) + 8; 7726 lastp = goalp - 8 - (cp->segments * (2*4)); 7727 break; 7728 case CAM_DIR_NONE: 7729 default: 7730 lastp = goalp = SCRIPTB_BA (np, no_data); 7731 break; 7732 } 7733 7734 cp->phys.head.lastp = cpu_to_scr(lastp); 7735 cp->phys.head.goalp = cpu_to_scr(goalp); 7736 cp->phys.head.savep = cpu_to_scr(lastp); 7737 cp->startp = cp->phys.head.savep; 7738 } 7739 7740 7741 /* 7742 * Call back routine for the DMA map service. 7743 * If bounce buffers are used (why ?), we may sleep and then 7744 * be called there in another context. 7745 */ 7746 static void 7747 sym_execute_ccb(void *arg, bus_dma_segment_t *psegs, int nsegs, int error) 7748 { 7749 ccb_p cp; 7750 hcb_p np; 7751 union ccb *ccb; 7752 int s; 7753 7754 s = splcam(); 7755 7756 cp = (ccb_p) arg; 7757 ccb = cp->cam_ccb; 7758 np = (hcb_p) cp->arg; 7759 7760 /* 7761 * Deal with weird races. 7762 */ 7763 if (sym_get_cam_status(ccb) != CAM_REQ_INPROG) 7764 goto out_abort; 7765 7766 /* 7767 * Deal with weird errors. 7768 */ 7769 if (error) { 7770 cp->dmamapped = 0; 7771 sym_set_cam_status(cp->cam_ccb, CAM_REQ_ABORTED); 7772 goto out_abort; 7773 } 7774 7775 /* 7776 * Build the data descriptor for the chip. 7777 */ 7778 if (nsegs) { 7779 int retv; 7780 /* 896 rev 1 requires to be careful about boundaries */ 7781 if (np->device_id == PCI_ID_SYM53C896 && np->revision_id <= 1) 7782 retv = sym_scatter_sg_physical(np, cp, psegs, nsegs); 7783 else 7784 retv = sym_fast_scatter_sg_physical(np,cp, psegs,nsegs); 7785 if (retv < 0) { 7786 sym_set_cam_status(cp->cam_ccb, CAM_REQ_TOO_BIG); 7787 goto out_abort; 7788 } 7789 } 7790 7791 /* 7792 * Synchronize the DMA map only if we have 7793 * actually mapped the data. 7794 */ 7795 if (cp->dmamapped) { 7796 bus_dmamap_sync(np->data_dmat, cp->dmamap, 7797 (cp->dmamapped == SYM_DMA_READ ? 7798 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 7799 } 7800 7801 /* 7802 * Set host status to busy state. 7803 * May have been set back to HS_WAIT to avoid a race. 7804 */ 7805 cp->host_status = cp->nego_status ? HS_NEGOTIATE : HS_BUSY; 7806 7807 /* 7808 * Set data pointers. 7809 */ 7810 sym_setup_data_pointers(np, cp, (ccb->ccb_h.flags & CAM_DIR_MASK)); 7811 7812 /* 7813 * Enqueue this IO in our pending queue. 7814 */ 7815 sym_enqueue_cam_ccb(np, ccb); 7816 7817 /* 7818 * When `#ifed 1', the code below makes the driver 7819 * panic on the first attempt to write to a SCSI device. 7820 * It is the first test we want to do after a driver 7821 * change that does not seem obviously safe. :) 7822 */ 7823 #if 0 7824 switch (cp->cdb_buf[0]) { 7825 case 0x0A: case 0x2A: case 0xAA: 7826 panic("XXXXXXXXXXXXX WRITE NOT YET ALLOWED XXXXXXXXXXXXXX\n"); 7827 MDELAY(10000); 7828 break; 7829 default: 7830 break; 7831 } 7832 #endif 7833 /* 7834 * Activate this job. 7835 */ 7836 sym_put_start_queue(np, cp); 7837 out: 7838 splx(s); 7839 return; 7840 out_abort: 7841 sym_free_ccb(np, cp); 7842 sym_xpt_done(np, ccb); 7843 goto out; 7844 } 7845 7846 /* 7847 * How complex it gets to deal with the data in CAM. 7848 * The Bus Dma stuff makes things still more complex. 7849 */ 7850 static void 7851 sym_setup_data_and_start(hcb_p np, struct ccb_scsiio *csio, ccb_p cp) 7852 { 7853 struct ccb_hdr *ccb_h; 7854 int dir, retv; 7855 7856 ccb_h = &csio->ccb_h; 7857 7858 /* 7859 * Now deal with the data. 7860 */ 7861 cp->data_len = csio->dxfer_len; 7862 cp->arg = np; 7863 7864 /* 7865 * No direction means no data. 7866 */ 7867 dir = (ccb_h->flags & CAM_DIR_MASK); 7868 if (dir == CAM_DIR_NONE) { 7869 sym_execute_ccb(cp, NULL, 0, 0); 7870 return; 7871 } 7872 7873 if (!(ccb_h->flags & CAM_SCATTER_VALID)) { 7874 /* Single buffer */ 7875 if (!(ccb_h->flags & CAM_DATA_PHYS)) { 7876 /* Buffer is virtual */ 7877 int s; 7878 7879 cp->dmamapped = (dir == CAM_DIR_IN) ? 7880 SYM_DMA_READ : SYM_DMA_WRITE; 7881 s = splsoftvm(); 7882 retv = bus_dmamap_load(np->data_dmat, cp->dmamap, 7883 csio->data_ptr, csio->dxfer_len, 7884 sym_execute_ccb, cp, 0); 7885 if (retv == EINPROGRESS) { 7886 cp->host_status = HS_WAIT; 7887 xpt_freeze_simq(np->sim, 1); 7888 csio->ccb_h.status |= CAM_RELEASE_SIMQ; 7889 } 7890 splx(s); 7891 } else { 7892 /* Buffer is physical */ 7893 struct bus_dma_segment seg; 7894 7895 seg.ds_addr = (bus_addr_t) csio->data_ptr; 7896 sym_execute_ccb(cp, &seg, 1, 0); 7897 } 7898 } else { 7899 /* Scatter/gather list */ 7900 struct bus_dma_segment *segs; 7901 7902 if ((ccb_h->flags & CAM_SG_LIST_PHYS) != 0) { 7903 /* The SG list pointer is physical */ 7904 sym_set_cam_status(cp->cam_ccb, CAM_REQ_INVALID); 7905 goto out_abort; 7906 } 7907 7908 if (!(ccb_h->flags & CAM_DATA_PHYS)) { 7909 /* SG buffer pointers are virtual */ 7910 sym_set_cam_status(cp->cam_ccb, CAM_REQ_INVALID); 7911 goto out_abort; 7912 } 7913 7914 /* SG buffer pointers are physical */ 7915 segs = (struct bus_dma_segment *)csio->data_ptr; 7916 sym_execute_ccb(cp, segs, csio->sglist_cnt, 0); 7917 } 7918 return; 7919 out_abort: 7920 sym_free_ccb(np, cp); 7921 sym_xpt_done(np, (union ccb *) csio); 7922 } 7923 7924 /* 7925 * Move the scatter list to our data block. 7926 */ 7927 static int 7928 sym_fast_scatter_sg_physical(hcb_p np, ccb_p cp, 7929 bus_dma_segment_t *psegs, int nsegs) 7930 { 7931 struct sym_tblmove *data; 7932 bus_dma_segment_t *psegs2; 7933 7934 if (nsegs > SYM_CONF_MAX_SG) 7935 return -1; 7936 7937 data = &cp->phys.data[SYM_CONF_MAX_SG-1]; 7938 psegs2 = &psegs[nsegs-1]; 7939 cp->segments = nsegs; 7940 7941 while (1) { 7942 data->addr = cpu_to_scr(psegs2->ds_addr); 7943 data->size = cpu_to_scr(psegs2->ds_len); 7944 if (DEBUG_FLAGS & DEBUG_SCATTER) { 7945 printf ("%s scatter: paddr=%lx len=%ld\n", 7946 sym_name(np), (long) psegs2->ds_addr, 7947 (long) psegs2->ds_len); 7948 } 7949 if (psegs2 != psegs) { 7950 --data; 7951 --psegs2; 7952 continue; 7953 } 7954 break; 7955 } 7956 return 0; 7957 } 7958 7959 7960 /* 7961 * Scatter a SG list with physical addresses into bus addressable chunks. 7962 * We need to ensure 16MB boundaries not to be crossed during DMA of 7963 * each segment, due to some chips being flawed. 7964 */ 7965 #define BOUND_MASK ((1UL<<24)-1) 7966 static int 7967 sym_scatter_sg_physical(hcb_p np, ccb_p cp, bus_dma_segment_t *psegs, int nsegs) 7968 { 7969 u_long ps, pe, pn; 7970 u_long k; 7971 int s, t; 7972 7973 s = SYM_CONF_MAX_SG - 1; 7974 t = nsegs - 1; 7975 ps = psegs[t].ds_addr; 7976 pe = ps + psegs[t].ds_len; 7977 7978 while (s >= 0) { 7979 pn = (pe - 1) & ~BOUND_MASK; 7980 if (pn <= ps) 7981 pn = ps; 7982 k = pe - pn; 7983 if (DEBUG_FLAGS & DEBUG_SCATTER) { 7984 printf ("%s scatter: paddr=%lx len=%ld\n", 7985 sym_name(np), pn, k); 7986 } 7987 cp->phys.data[s].addr = cpu_to_scr(pn); 7988 cp->phys.data[s].size = cpu_to_scr(k); 7989 --s; 7990 if (pn == ps) { 7991 if (--t < 0) 7992 break; 7993 ps = psegs[t].ds_addr; 7994 pe = ps + psegs[t].ds_len; 7995 } 7996 else 7997 pe = pn; 7998 } 7999 8000 cp->segments = SYM_CONF_MAX_SG - 1 - s; 8001 8002 return t >= 0 ? -1 : 0; 8003 } 8004 #undef BOUND_MASK 8005 8006 /* 8007 * SIM action for non performance critical stuff. 8008 */ 8009 static void sym_action2(struct cam_sim *sim, union ccb *ccb) 8010 { 8011 hcb_p np; 8012 tcb_p tp; 8013 lcb_p lp; 8014 struct ccb_hdr *ccb_h; 8015 8016 /* 8017 * Retrieve our controller data structure. 8018 */ 8019 np = (hcb_p) cam_sim_softc(sim); 8020 8021 ccb_h = &ccb->ccb_h; 8022 8023 switch (ccb_h->func_code) { 8024 case XPT_SET_TRAN_SETTINGS: 8025 { 8026 struct ccb_trans_settings *cts; 8027 8028 cts = &ccb->cts; 8029 tp = &np->target[ccb_h->target_id]; 8030 8031 /* 8032 * Update SPI transport settings in TARGET control block. 8033 * Update SCSI device settings in LUN control block. 8034 */ 8035 lp = sym_lp(np, tp, ccb_h->target_lun); 8036 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) { 8037 sym_update_trans(np, tp, &tp->tinfo.goal, cts); 8038 if (lp) 8039 sym_update_dflags(np, &lp->current_flags, cts); 8040 } 8041 if (cts->type == CTS_TYPE_USER_SETTINGS) { 8042 sym_update_trans(np, tp, &tp->tinfo.user, cts); 8043 if (lp) 8044 sym_update_dflags(np, &lp->user_flags, cts); 8045 } 8046 8047 sym_xpt_done2(np, ccb, CAM_REQ_CMP); 8048 break; 8049 } 8050 case XPT_GET_TRAN_SETTINGS: 8051 { 8052 struct ccb_trans_settings *cts; 8053 struct sym_trans *tip; 8054 u_char dflags; 8055 8056 cts = &ccb->cts; 8057 tp = &np->target[ccb_h->target_id]; 8058 lp = sym_lp(np, tp, ccb_h->target_lun); 8059 8060 #define cts__scsi (&cts->proto_specific.scsi) 8061 #define cts__spi (&cts->xport_specific.spi) 8062 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) { 8063 tip = &tp->tinfo.current; 8064 dflags = lp ? lp->current_flags : 0; 8065 } 8066 else { 8067 tip = &tp->tinfo.user; 8068 dflags = lp ? lp->user_flags : tp->usrflags; 8069 } 8070 8071 cts->protocol = PROTO_SCSI; 8072 cts->transport = XPORT_SPI; 8073 cts->protocol_version = tip->scsi_version; 8074 cts->transport_version = tip->spi_version; 8075 8076 cts__spi->sync_period = tip->period; 8077 cts__spi->sync_offset = tip->offset; 8078 cts__spi->bus_width = tip->width; 8079 cts__spi->ppr_options = tip->options; 8080 8081 cts__spi->valid = CTS_SPI_VALID_SYNC_RATE 8082 | CTS_SPI_VALID_SYNC_OFFSET 8083 | CTS_SPI_VALID_BUS_WIDTH 8084 | CTS_SPI_VALID_PPR_OPTIONS; 8085 8086 cts__spi->flags &= ~CTS_SPI_FLAGS_DISC_ENB; 8087 if (dflags & SYM_DISC_ENABLED) 8088 cts__spi->flags |= CTS_SPI_FLAGS_DISC_ENB; 8089 cts__spi->valid |= CTS_SPI_VALID_DISC; 8090 8091 cts__scsi->flags &= ~CTS_SCSI_FLAGS_TAG_ENB; 8092 if (dflags & SYM_TAGS_ENABLED) 8093 cts__scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB; 8094 cts__scsi->valid |= CTS_SCSI_VALID_TQ; 8095 #undef cts__spi 8096 #undef cts__scsi 8097 sym_xpt_done2(np, ccb, CAM_REQ_CMP); 8098 break; 8099 } 8100 case XPT_CALC_GEOMETRY: 8101 { 8102 cam_calc_geometry(&ccb->ccg, /*extended*/1); 8103 sym_xpt_done2(np, ccb, CAM_REQ_CMP); 8104 break; 8105 } 8106 case XPT_PATH_INQ: 8107 { 8108 struct ccb_pathinq *cpi = &ccb->cpi; 8109 cpi->version_num = 1; 8110 cpi->hba_inquiry = PI_MDP_ABLE|PI_SDTR_ABLE|PI_TAG_ABLE; 8111 if ((np->features & FE_WIDE) != 0) 8112 cpi->hba_inquiry |= PI_WIDE_16; 8113 cpi->target_sprt = 0; 8114 cpi->hba_misc = 0; 8115 if (np->usrflags & SYM_SCAN_TARGETS_HILO) 8116 cpi->hba_misc |= PIM_SCANHILO; 8117 if (np->usrflags & SYM_AVOID_BUS_RESET) 8118 cpi->hba_misc |= PIM_NOBUSRESET; 8119 cpi->hba_eng_cnt = 0; 8120 cpi->max_target = (np->features & FE_WIDE) ? 15 : 7; 8121 /* Semantic problem:)LUN number max = max number of LUNs - 1 */ 8122 cpi->max_lun = SYM_CONF_MAX_LUN-1; 8123 if (SYM_SETUP_MAX_LUN < SYM_CONF_MAX_LUN) 8124 cpi->max_lun = SYM_SETUP_MAX_LUN-1; 8125 cpi->bus_id = cam_sim_bus(sim); 8126 cpi->initiator_id = np->myaddr; 8127 cpi->base_transfer_speed = 3300; 8128 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 8129 strncpy(cpi->hba_vid, "Symbios", HBA_IDLEN); 8130 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 8131 cpi->unit_number = cam_sim_unit(sim); 8132 8133 cpi->protocol = PROTO_SCSI; 8134 cpi->protocol_version = SCSI_REV_2; 8135 cpi->transport = XPORT_SPI; 8136 cpi->transport_version = 2; 8137 cpi->xport_specific.spi.ppr_options = SID_SPI_CLOCK_ST; 8138 if (np->features & FE_ULTRA3) { 8139 cpi->transport_version = 3; 8140 cpi->xport_specific.spi.ppr_options = 8141 SID_SPI_CLOCK_DT_ST; 8142 } 8143 sym_xpt_done2(np, ccb, CAM_REQ_CMP); 8144 break; 8145 } 8146 case XPT_ABORT: 8147 { 8148 union ccb *abort_ccb = ccb->cab.abort_ccb; 8149 switch(abort_ccb->ccb_h.func_code) { 8150 case XPT_SCSI_IO: 8151 if (sym_abort_scsiio(np, abort_ccb, 0) == 0) { 8152 sym_xpt_done2(np, ccb, CAM_REQ_CMP); 8153 break; 8154 } 8155 default: 8156 sym_xpt_done2(np, ccb, CAM_UA_ABORT); 8157 break; 8158 } 8159 break; 8160 } 8161 case XPT_RESET_DEV: 8162 { 8163 sym_reset_dev(np, ccb); 8164 break; 8165 } 8166 case XPT_RESET_BUS: 8167 { 8168 sym_reset_scsi_bus(np, 0); 8169 if (sym_verbose) { 8170 xpt_print_path(np->path); 8171 printf("SCSI BUS reset delivered.\n"); 8172 } 8173 sym_init (np, 1); 8174 sym_xpt_done2(np, ccb, CAM_REQ_CMP); 8175 break; 8176 } 8177 case XPT_ACCEPT_TARGET_IO: 8178 case XPT_CONT_TARGET_IO: 8179 case XPT_EN_LUN: 8180 case XPT_NOTIFY_ACK: 8181 case XPT_IMMED_NOTIFY: 8182 case XPT_TERM_IO: 8183 default: 8184 sym_xpt_done2(np, ccb, CAM_REQ_INVALID); 8185 break; 8186 } 8187 } 8188 8189 /* 8190 * Asynchronous notification handler. 8191 */ 8192 static void 8193 sym_async(void *cb_arg, u32 code, struct cam_path *path, void *arg) 8194 { 8195 hcb_p np; 8196 struct cam_sim *sim; 8197 u_int tn; 8198 tcb_p tp; 8199 int s; 8200 8201 s = splcam(); 8202 8203 sim = (struct cam_sim *) cb_arg; 8204 np = (hcb_p) cam_sim_softc(sim); 8205 8206 switch (code) { 8207 case AC_LOST_DEVICE: 8208 tn = xpt_path_target_id(path); 8209 if (tn >= SYM_CONF_MAX_TARGET) 8210 break; 8211 8212 tp = &np->target[tn]; 8213 8214 tp->to_reset = 0; 8215 tp->head.sval = 0; 8216 tp->head.wval = np->rv_scntl3; 8217 tp->head.uval = 0; 8218 8219 tp->tinfo.current.period = tp->tinfo.goal.period = 0; 8220 tp->tinfo.current.offset = tp->tinfo.goal.offset = 0; 8221 tp->tinfo.current.width = tp->tinfo.goal.width = BUS_8_BIT; 8222 tp->tinfo.current.options = tp->tinfo.goal.options = 0; 8223 8224 break; 8225 default: 8226 break; 8227 } 8228 8229 splx(s); 8230 } 8231 8232 /* 8233 * Update transfer settings of a target. 8234 */ 8235 static void sym_update_trans(hcb_p np, tcb_p tp, struct sym_trans *tip, 8236 struct ccb_trans_settings *cts) 8237 { 8238 /* 8239 * Update the infos. 8240 */ 8241 #define cts__spi (&cts->xport_specific.spi) 8242 if ((cts__spi->valid & CTS_SPI_VALID_BUS_WIDTH) != 0) 8243 tip->width = cts__spi->bus_width; 8244 if ((cts__spi->valid & CTS_SPI_VALID_SYNC_OFFSET) != 0) 8245 tip->offset = cts__spi->sync_offset; 8246 if ((cts__spi->valid & CTS_SPI_VALID_SYNC_RATE) != 0) 8247 tip->period = cts__spi->sync_period; 8248 if ((cts__spi->valid & CTS_SPI_VALID_PPR_OPTIONS) != 0) 8249 tip->options = (cts__spi->ppr_options & PPR_OPT_DT); 8250 if (cts->protocol_version != PROTO_VERSION_UNSPECIFIED && 8251 cts->protocol_version != PROTO_VERSION_UNKNOWN) 8252 tip->scsi_version = cts->protocol_version; 8253 if (cts->transport_version != XPORT_VERSION_UNSPECIFIED && 8254 cts->transport_version != XPORT_VERSION_UNKNOWN) 8255 tip->spi_version = cts->transport_version; 8256 #undef cts__spi 8257 /* 8258 * Scale against driver configuration limits. 8259 */ 8260 if (tip->width > SYM_SETUP_MAX_WIDE) tip->width = SYM_SETUP_MAX_WIDE; 8261 if (tip->offset > SYM_SETUP_MAX_OFFS) tip->offset = SYM_SETUP_MAX_OFFS; 8262 if (tip->period < SYM_SETUP_MIN_SYNC) tip->period = SYM_SETUP_MIN_SYNC; 8263 8264 /* 8265 * Scale against actual controller BUS width. 8266 */ 8267 if (tip->width > np->maxwide) 8268 tip->width = np->maxwide; 8269 8270 /* 8271 * Only accept DT if controller supports and SYNC/WIDE asked. 8272 */ 8273 if (!((np->features & (FE_C10|FE_ULTRA3)) == (FE_C10|FE_ULTRA3)) || 8274 !(tip->width == BUS_16_BIT && tip->offset)) { 8275 tip->options &= ~PPR_OPT_DT; 8276 } 8277 8278 /* 8279 * Scale period factor and offset against controller limits. 8280 */ 8281 if (tip->options & PPR_OPT_DT) { 8282 if (tip->period < np->minsync_dt) 8283 tip->period = np->minsync_dt; 8284 if (tip->period > np->maxsync_dt) 8285 tip->period = np->maxsync_dt; 8286 if (tip->offset > np->maxoffs_dt) 8287 tip->offset = np->maxoffs_dt; 8288 } 8289 else { 8290 if (tip->period < np->minsync) 8291 tip->period = np->minsync; 8292 if (tip->period > np->maxsync) 8293 tip->period = np->maxsync; 8294 if (tip->offset > np->maxoffs) 8295 tip->offset = np->maxoffs; 8296 } 8297 } 8298 8299 /* 8300 * Update flags for a device (logical unit). 8301 */ 8302 static void 8303 sym_update_dflags(hcb_p np, u_char *flags, struct ccb_trans_settings *cts) 8304 { 8305 #define cts__scsi (&cts->proto_specific.scsi) 8306 #define cts__spi (&cts->xport_specific.spi) 8307 if ((cts__spi->valid & CTS_SPI_VALID_DISC) != 0) { 8308 if ((cts__spi->flags & CTS_SPI_FLAGS_DISC_ENB) != 0) 8309 *flags |= SYM_DISC_ENABLED; 8310 else 8311 *flags &= ~SYM_DISC_ENABLED; 8312 } 8313 8314 if ((cts__scsi->valid & CTS_SCSI_VALID_TQ) != 0) { 8315 if ((cts__scsi->flags & CTS_SCSI_FLAGS_TAG_ENB) != 0) 8316 *flags |= SYM_TAGS_ENABLED; 8317 else 8318 *flags &= ~SYM_TAGS_ENABLED; 8319 } 8320 #undef cts__spi 8321 #undef cts__scsi 8322 } 8323 8324 8325 /*============= DRIVER INITIALISATION ==================*/ 8326 8327 8328 static device_method_t sym_pci_methods[] = { 8329 DEVMETHOD(device_probe, sym_pci_probe), 8330 DEVMETHOD(device_attach, sym_pci_attach), 8331 { 0, 0 } 8332 }; 8333 8334 static driver_t sym_pci_driver = { 8335 "sym", 8336 sym_pci_methods, 8337 sizeof(struct sym_hcb) 8338 }; 8339 8340 static devclass_t sym_devclass; 8341 8342 DRIVER_MODULE(sym, pci, sym_pci_driver, sym_devclass, 0, 0); 8343 MODULE_DEPEND(sym, cam, 1, 1, 1); 8344 MODULE_DEPEND(sym, pci, 1, 1, 1); 8345 8346 8347 static struct sym_pci_chip sym_pci_dev_table[] = { 8348 {PCI_ID_SYM53C810, 0x0f, "810", 4, 8, 4, 64, 8349 FE_ERL} 8350 , 8351 #ifdef SYM_DEBUG_GENERIC_SUPPORT 8352 {PCI_ID_SYM53C810, 0xff, "810a", 4, 8, 4, 1, 8353 FE_BOF} 8354 , 8355 #else 8356 {PCI_ID_SYM53C810, 0xff, "810a", 4, 8, 4, 1, 8357 FE_CACHE_SET|FE_LDSTR|FE_PFEN|FE_BOF} 8358 , 8359 #endif 8360 {PCI_ID_SYM53C815, 0xff, "815", 4, 8, 4, 64, 8361 FE_BOF|FE_ERL} 8362 , 8363 {PCI_ID_SYM53C825, 0x0f, "825", 6, 8, 4, 64, 8364 FE_WIDE|FE_BOF|FE_ERL|FE_DIFF} 8365 , 8366 {PCI_ID_SYM53C825, 0xff, "825a", 6, 8, 4, 2, 8367 FE_WIDE|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM|FE_DIFF} 8368 , 8369 {PCI_ID_SYM53C860, 0xff, "860", 4, 8, 5, 1, 8370 FE_ULTRA|FE_CLK80|FE_CACHE_SET|FE_BOF|FE_LDSTR|FE_PFEN} 8371 , 8372 {PCI_ID_SYM53C875, 0x01, "875", 6, 16, 5, 2, 8373 FE_WIDE|FE_ULTRA|FE_CLK80|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 8374 FE_RAM|FE_DIFF} 8375 , 8376 {PCI_ID_SYM53C875, 0xff, "875", 6, 16, 5, 2, 8377 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 8378 FE_RAM|FE_DIFF} 8379 , 8380 {PCI_ID_SYM53C875_2, 0xff, "875", 6, 16, 5, 2, 8381 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 8382 FE_RAM|FE_DIFF} 8383 , 8384 {PCI_ID_SYM53C885, 0xff, "885", 6, 16, 5, 2, 8385 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 8386 FE_RAM|FE_DIFF} 8387 , 8388 #ifdef SYM_DEBUG_GENERIC_SUPPORT 8389 {PCI_ID_SYM53C895, 0xff, "895", 6, 31, 7, 2, 8390 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS| 8391 FE_RAM|FE_LCKFRQ} 8392 , 8393 #else 8394 {PCI_ID_SYM53C895, 0xff, "895", 6, 31, 7, 2, 8395 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 8396 FE_RAM|FE_LCKFRQ} 8397 , 8398 #endif 8399 {PCI_ID_SYM53C896, 0xff, "896", 6, 31, 7, 4, 8400 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 8401 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_LCKFRQ} 8402 , 8403 {PCI_ID_SYM53C895A, 0xff, "895a", 6, 31, 7, 4, 8404 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 8405 FE_RAM|FE_RAM8K|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_LCKFRQ} 8406 , 8407 {PCI_ID_LSI53C1010, 0x00, "1010-33", 6, 31, 7, 8, 8408 FE_WIDE|FE_ULTRA3|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFBC|FE_LDSTR|FE_PFEN| 8409 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_CRC| 8410 FE_C10} 8411 , 8412 {PCI_ID_LSI53C1010, 0xff, "1010-33", 6, 31, 7, 8, 8413 FE_WIDE|FE_ULTRA3|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFBC|FE_LDSTR|FE_PFEN| 8414 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_CRC| 8415 FE_C10|FE_U3EN} 8416 , 8417 {PCI_ID_LSI53C1010_2, 0xff, "1010-66", 6, 31, 7, 8, 8418 FE_WIDE|FE_ULTRA3|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFBC|FE_LDSTR|FE_PFEN| 8419 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_66MHZ|FE_CRC| 8420 FE_C10|FE_U3EN} 8421 , 8422 {PCI_ID_LSI53C1510D, 0xff, "1510d", 6, 31, 7, 4, 8423 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 8424 FE_RAM|FE_IO256|FE_LEDC} 8425 }; 8426 8427 #define sym_pci_num_devs \ 8428 (sizeof(sym_pci_dev_table) / sizeof(sym_pci_dev_table[0])) 8429 8430 /* 8431 * Look up the chip table. 8432 * 8433 * Return a pointer to the chip entry if found, 8434 * zero otherwise. 8435 */ 8436 static struct sym_pci_chip * 8437 sym_find_pci_chip(device_t dev) 8438 { 8439 struct sym_pci_chip *chip; 8440 int i; 8441 u_short device_id; 8442 u_char revision; 8443 8444 if (pci_get_vendor(dev) != PCI_VENDOR_NCR) 8445 return 0; 8446 8447 device_id = pci_get_device(dev); 8448 revision = pci_get_revid(dev); 8449 8450 for (i = 0; i < sym_pci_num_devs; i++) { 8451 chip = &sym_pci_dev_table[i]; 8452 if (device_id != chip->device_id) 8453 continue; 8454 if (revision > chip->revision_id) 8455 continue; 8456 return chip; 8457 } 8458 8459 return 0; 8460 } 8461 8462 /* 8463 * Tell upper layer if the chip is supported. 8464 */ 8465 static int 8466 sym_pci_probe(device_t dev) 8467 { 8468 struct sym_pci_chip *chip; 8469 8470 chip = sym_find_pci_chip(dev); 8471 if (chip && sym_find_firmware(chip)) { 8472 device_set_desc(dev, chip->name); 8473 return (chip->lp_probe_bit & SYM_SETUP_LP_PROBE_MAP)? 8474 BUS_PROBE_LOW_PRIORITY : BUS_PROBE_DEFAULT; 8475 } 8476 return ENXIO; 8477 } 8478 8479 /* 8480 * Attach a sym53c8xx device. 8481 */ 8482 static int 8483 sym_pci_attach(device_t dev) 8484 { 8485 struct sym_pci_chip *chip; 8486 u_short command; 8487 u_char cachelnsz; 8488 struct sym_hcb *np = 0; 8489 struct sym_nvram nvram; 8490 struct sym_fw *fw = 0; 8491 int i; 8492 bus_dma_tag_t bus_dmat; 8493 8494 bus_dmat = bus_get_dma_tag(dev); 8495 8496 /* 8497 * Only probed devices should be attached. 8498 * We just enjoy being paranoid. :) 8499 */ 8500 chip = sym_find_pci_chip(dev); 8501 if (chip == NULL || (fw = sym_find_firmware(chip)) == NULL) 8502 return (ENXIO); 8503 8504 /* 8505 * Allocate immediately the host control block, 8506 * since we are only expecting to succeed. :) 8507 * We keep track in the HCB of all the resources that 8508 * are to be released on error. 8509 */ 8510 np = __sym_calloc_dma(bus_dmat, sizeof(*np), "HCB"); 8511 if (np) 8512 np->bus_dmat = bus_dmat; 8513 else 8514 goto attach_failed; 8515 8516 /* 8517 * Copy some useful infos to the HCB. 8518 */ 8519 np->hcb_ba = vtobus(np); 8520 np->verbose = bootverbose; 8521 np->device = dev; 8522 np->unit = device_get_unit(dev); 8523 np->device_id = pci_get_device(dev); 8524 np->revision_id = pci_get_revid(dev); 8525 np->features = chip->features; 8526 np->clock_divn = chip->nr_divisor; 8527 np->maxoffs = chip->offset_max; 8528 np->maxburst = chip->burst_max; 8529 np->scripta_sz = fw->a_size; 8530 np->scriptb_sz = fw->b_size; 8531 np->fw_setup = fw->setup; 8532 np->fw_patch = fw->patch; 8533 np->fw_name = fw->name; 8534 8535 /* 8536 * Edit its name. 8537 */ 8538 snprintf(np->inst_name, sizeof(np->inst_name), "sym%d", np->unit); 8539 8540 /* 8541 * Initialyze the CCB free and busy queues. 8542 */ 8543 sym_que_init(&np->free_ccbq); 8544 sym_que_init(&np->busy_ccbq); 8545 sym_que_init(&np->comp_ccbq); 8546 sym_que_init(&np->cam_ccbq); 8547 8548 /* 8549 * Allocate a tag for the DMA of user data. 8550 */ 8551 if (bus_dma_tag_create(np->bus_dmat, 1, (1<<24), 8552 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 8553 NULL, NULL, 8554 BUS_SPACE_MAXSIZE, SYM_CONF_MAX_SG, 8555 (1<<24), 0, busdma_lock_mutex, &Giant, 8556 &np->data_dmat)) { 8557 device_printf(dev, "failed to create DMA tag.\n"); 8558 goto attach_failed; 8559 } 8560 /* 8561 * Read and apply some fix-ups to the PCI COMMAND 8562 * register. We want the chip to be enabled for: 8563 * - BUS mastering 8564 * - PCI parity checking (reporting would also be fine) 8565 * - Write And Invalidate. 8566 */ 8567 command = pci_read_config(dev, PCIR_COMMAND, 2); 8568 command |= PCIM_CMD_BUSMASTEREN; 8569 command |= PCIM_CMD_PERRESPEN; 8570 command |= /* PCIM_CMD_MWIEN */ 0x0010; 8571 pci_write_config(dev, PCIR_COMMAND, command, 2); 8572 8573 /* 8574 * Let the device know about the cache line size, 8575 * if it doesn't yet. 8576 */ 8577 cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 8578 if (!cachelnsz) { 8579 cachelnsz = 8; 8580 pci_write_config(dev, PCIR_CACHELNSZ, cachelnsz, 1); 8581 } 8582 8583 /* 8584 * Alloc/get/map/retrieve everything that deals with MMIO. 8585 */ 8586 if ((command & PCIM_CMD_MEMEN) != 0) { 8587 int regs_id = SYM_PCI_MMIO; 8588 np->mmio_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 8589 ®s_id, RF_ACTIVE); 8590 } 8591 if (!np->mmio_res) { 8592 device_printf(dev, "failed to allocate MMIO resources\n"); 8593 goto attach_failed; 8594 } 8595 np->mmio_bsh = rman_get_bushandle(np->mmio_res); 8596 np->mmio_tag = rman_get_bustag(np->mmio_res); 8597 np->mmio_pa = rman_get_start(np->mmio_res); 8598 np->mmio_va = (vm_offset_t) rman_get_virtual(np->mmio_res); 8599 np->mmio_ba = np->mmio_pa; 8600 8601 /* 8602 * Allocate the IRQ. 8603 */ 8604 i = 0; 8605 np->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, 8606 RF_ACTIVE | RF_SHAREABLE); 8607 if (!np->irq_res) { 8608 device_printf(dev, "failed to allocate IRQ resource\n"); 8609 goto attach_failed; 8610 } 8611 8612 #ifdef SYM_CONF_IOMAPPED 8613 /* 8614 * User want us to use normal IO with PCI. 8615 * Alloc/get/map/retrieve everything that deals with IO. 8616 */ 8617 if ((command & PCI_COMMAND_IO_ENABLE) != 0) { 8618 int regs_id = SYM_PCI_IO; 8619 np->io_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 8620 ®s_id, RF_ACTIVE); 8621 } 8622 if (!np->io_res) { 8623 device_printf(dev, "failed to allocate IO resources\n"); 8624 goto attach_failed; 8625 } 8626 np->io_bsh = rman_get_bushandle(np->io_res); 8627 np->io_tag = rman_get_bustag(np->io_res); 8628 np->io_port = rman_get_start(np->io_res); 8629 8630 #endif /* SYM_CONF_IOMAPPED */ 8631 8632 /* 8633 * If the chip has RAM. 8634 * Alloc/get/map/retrieve the corresponding resources. 8635 */ 8636 if ((np->features & (FE_RAM|FE_RAM8K)) && 8637 (command & PCIM_CMD_MEMEN) != 0) { 8638 int regs_id = SYM_PCI_RAM; 8639 if (np->features & FE_64BIT) 8640 regs_id = SYM_PCI_RAM64; 8641 np->ram_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 8642 ®s_id, RF_ACTIVE); 8643 if (!np->ram_res) { 8644 device_printf(dev,"failed to allocate RAM resources\n"); 8645 goto attach_failed; 8646 } 8647 np->ram_id = regs_id; 8648 np->ram_bsh = rman_get_bushandle(np->ram_res); 8649 np->ram_tag = rman_get_bustag(np->ram_res); 8650 np->ram_pa = rman_get_start(np->ram_res); 8651 np->ram_va = (vm_offset_t) rman_get_virtual(np->ram_res); 8652 np->ram_ba = np->ram_pa; 8653 } 8654 8655 /* 8656 * Save setting of some IO registers, so we will 8657 * be able to probe specific implementations. 8658 */ 8659 sym_save_initial_setting (np); 8660 8661 /* 8662 * Reset the chip now, since it has been reported 8663 * that SCSI clock calibration may not work properly 8664 * if the chip is currently active. 8665 */ 8666 sym_chip_reset (np); 8667 8668 /* 8669 * Try to read the user set-up. 8670 */ 8671 (void) sym_read_nvram(np, &nvram); 8672 8673 /* 8674 * Prepare controller and devices settings, according 8675 * to chip features, user set-up and driver set-up. 8676 */ 8677 (void) sym_prepare_setting(np, &nvram); 8678 8679 /* 8680 * Check the PCI clock frequency. 8681 * Must be performed after prepare_setting since it destroys 8682 * STEST1 that is used to probe for the clock doubler. 8683 */ 8684 i = sym_getpciclock(np); 8685 if (i > 37000) 8686 device_printf(dev, "PCI BUS clock seems too high: %u KHz.\n",i); 8687 8688 /* 8689 * Allocate the start queue. 8690 */ 8691 np->squeue = (u32 *) sym_calloc_dma(sizeof(u32)*(MAX_QUEUE*2),"SQUEUE"); 8692 if (!np->squeue) 8693 goto attach_failed; 8694 np->squeue_ba = vtobus(np->squeue); 8695 8696 /* 8697 * Allocate the done queue. 8698 */ 8699 np->dqueue = (u32 *) sym_calloc_dma(sizeof(u32)*(MAX_QUEUE*2),"DQUEUE"); 8700 if (!np->dqueue) 8701 goto attach_failed; 8702 np->dqueue_ba = vtobus(np->dqueue); 8703 8704 /* 8705 * Allocate the target bus address array. 8706 */ 8707 np->targtbl = (u32 *) sym_calloc_dma(256, "TARGTBL"); 8708 if (!np->targtbl) 8709 goto attach_failed; 8710 np->targtbl_ba = vtobus(np->targtbl); 8711 8712 /* 8713 * Allocate SCRIPTS areas. 8714 */ 8715 np->scripta0 = sym_calloc_dma(np->scripta_sz, "SCRIPTA0"); 8716 np->scriptb0 = sym_calloc_dma(np->scriptb_sz, "SCRIPTB0"); 8717 if (!np->scripta0 || !np->scriptb0) 8718 goto attach_failed; 8719 8720 /* 8721 * Allocate some CCB. We need at least ONE. 8722 */ 8723 if (!sym_alloc_ccb(np)) 8724 goto attach_failed; 8725 8726 /* 8727 * Calculate BUS addresses where we are going 8728 * to load the SCRIPTS. 8729 */ 8730 np->scripta_ba = vtobus(np->scripta0); 8731 np->scriptb_ba = vtobus(np->scriptb0); 8732 np->scriptb0_ba = np->scriptb_ba; 8733 8734 if (np->ram_ba) { 8735 np->scripta_ba = np->ram_ba; 8736 if (np->features & FE_RAM8K) { 8737 np->ram_ws = 8192; 8738 np->scriptb_ba = np->scripta_ba + 4096; 8739 #ifdef __LP64__ 8740 np->scr_ram_seg = cpu_to_scr(np->scripta_ba >> 32); 8741 #endif 8742 } 8743 else 8744 np->ram_ws = 4096; 8745 } 8746 8747 /* 8748 * Copy scripts to controller instance. 8749 */ 8750 bcopy(fw->a_base, np->scripta0, np->scripta_sz); 8751 bcopy(fw->b_base, np->scriptb0, np->scriptb_sz); 8752 8753 /* 8754 * Setup variable parts in scripts and compute 8755 * scripts bus addresses used from the C code. 8756 */ 8757 np->fw_setup(np, fw); 8758 8759 /* 8760 * Bind SCRIPTS with physical addresses usable by the 8761 * SCRIPTS processor (as seen from the BUS = BUS addresses). 8762 */ 8763 sym_fw_bind_script(np, (u32 *) np->scripta0, np->scripta_sz); 8764 sym_fw_bind_script(np, (u32 *) np->scriptb0, np->scriptb_sz); 8765 8766 #ifdef SYM_CONF_IARB_SUPPORT 8767 /* 8768 * If user wants IARB to be set when we win arbitration 8769 * and have other jobs, compute the max number of consecutive 8770 * settings of IARB hints before we leave devices a chance to 8771 * arbitrate for reselection. 8772 */ 8773 #ifdef SYM_SETUP_IARB_MAX 8774 np->iarb_max = SYM_SETUP_IARB_MAX; 8775 #else 8776 np->iarb_max = 4; 8777 #endif 8778 #endif 8779 8780 /* 8781 * Prepare the idle and invalid task actions. 8782 */ 8783 np->idletask.start = cpu_to_scr(SCRIPTA_BA (np, idle)); 8784 np->idletask.restart = cpu_to_scr(SCRIPTB_BA (np, bad_i_t_l)); 8785 np->idletask_ba = vtobus(&np->idletask); 8786 8787 np->notask.start = cpu_to_scr(SCRIPTA_BA (np, idle)); 8788 np->notask.restart = cpu_to_scr(SCRIPTB_BA (np, bad_i_t_l)); 8789 np->notask_ba = vtobus(&np->notask); 8790 8791 np->bad_itl.start = cpu_to_scr(SCRIPTA_BA (np, idle)); 8792 np->bad_itl.restart = cpu_to_scr(SCRIPTB_BA (np, bad_i_t_l)); 8793 np->bad_itl_ba = vtobus(&np->bad_itl); 8794 8795 np->bad_itlq.start = cpu_to_scr(SCRIPTA_BA (np, idle)); 8796 np->bad_itlq.restart = cpu_to_scr(SCRIPTB_BA (np,bad_i_t_l_q)); 8797 np->bad_itlq_ba = vtobus(&np->bad_itlq); 8798 8799 /* 8800 * Allocate and prepare the lun JUMP table that is used 8801 * for a target prior the probing of devices (bad lun table). 8802 * A private table will be allocated for the target on the 8803 * first INQUIRY response received. 8804 */ 8805 np->badluntbl = sym_calloc_dma(256, "BADLUNTBL"); 8806 if (!np->badluntbl) 8807 goto attach_failed; 8808 8809 np->badlun_sa = cpu_to_scr(SCRIPTB_BA (np, resel_bad_lun)); 8810 for (i = 0 ; i < 64 ; i++) /* 64 luns/target, no less */ 8811 np->badluntbl[i] = cpu_to_scr(vtobus(&np->badlun_sa)); 8812 8813 /* 8814 * Prepare the bus address array that contains the bus 8815 * address of each target control block. 8816 * For now, assume all logical units are wrong. :) 8817 */ 8818 for (i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) { 8819 np->targtbl[i] = cpu_to_scr(vtobus(&np->target[i])); 8820 np->target[i].head.luntbl_sa = 8821 cpu_to_scr(vtobus(np->badluntbl)); 8822 np->target[i].head.lun0_sa = 8823 cpu_to_scr(vtobus(&np->badlun_sa)); 8824 } 8825 8826 /* 8827 * Now check the cache handling of the pci chipset. 8828 */ 8829 if (sym_snooptest (np)) { 8830 device_printf(dev, "CACHE INCORRECTLY CONFIGURED.\n"); 8831 goto attach_failed; 8832 }; 8833 8834 /* 8835 * Now deal with CAM. 8836 * Hopefully, we will succeed with that one.:) 8837 */ 8838 if (!sym_cam_attach(np)) 8839 goto attach_failed; 8840 8841 /* 8842 * Sigh! we are done. 8843 */ 8844 return 0; 8845 8846 /* 8847 * We have failed. 8848 * We will try to free all the resources we have 8849 * allocated, but if we are a boot device, this 8850 * will not help that much.;) 8851 */ 8852 attach_failed: 8853 if (np) 8854 sym_pci_free(np); 8855 return ENXIO; 8856 } 8857 8858 /* 8859 * Free everything that have been allocated for this device. 8860 */ 8861 static void sym_pci_free(hcb_p np) 8862 { 8863 SYM_QUEHEAD *qp; 8864 ccb_p cp; 8865 tcb_p tp; 8866 lcb_p lp; 8867 int target, lun; 8868 int s; 8869 8870 /* 8871 * First free CAM resources. 8872 */ 8873 s = splcam(); 8874 sym_cam_free(np); 8875 splx(s); 8876 8877 /* 8878 * Now every should be quiet for us to 8879 * free other resources. 8880 */ 8881 if (np->ram_res) 8882 bus_release_resource(np->device, SYS_RES_MEMORY, 8883 np->ram_id, np->ram_res); 8884 if (np->mmio_res) 8885 bus_release_resource(np->device, SYS_RES_MEMORY, 8886 SYM_PCI_MMIO, np->mmio_res); 8887 if (np->io_res) 8888 bus_release_resource(np->device, SYS_RES_IOPORT, 8889 SYM_PCI_IO, np->io_res); 8890 if (np->irq_res) 8891 bus_release_resource(np->device, SYS_RES_IRQ, 8892 0, np->irq_res); 8893 8894 if (np->scriptb0) 8895 sym_mfree_dma(np->scriptb0, np->scriptb_sz, "SCRIPTB0"); 8896 if (np->scripta0) 8897 sym_mfree_dma(np->scripta0, np->scripta_sz, "SCRIPTA0"); 8898 if (np->squeue) 8899 sym_mfree_dma(np->squeue, sizeof(u32)*(MAX_QUEUE*2), "SQUEUE"); 8900 if (np->dqueue) 8901 sym_mfree_dma(np->dqueue, sizeof(u32)*(MAX_QUEUE*2), "DQUEUE"); 8902 8903 while ((qp = sym_remque_head(&np->free_ccbq)) != 0) { 8904 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 8905 bus_dmamap_destroy(np->data_dmat, cp->dmamap); 8906 sym_mfree_dma(cp->sns_bbuf, SYM_SNS_BBUF_LEN, "SNS_BBUF"); 8907 sym_mfree_dma(cp, sizeof(*cp), "CCB"); 8908 } 8909 8910 if (np->badluntbl) 8911 sym_mfree_dma(np->badluntbl, 256,"BADLUNTBL"); 8912 8913 for (target = 0; target < SYM_CONF_MAX_TARGET ; target++) { 8914 tp = &np->target[target]; 8915 for (lun = 0 ; lun < SYM_CONF_MAX_LUN ; lun++) { 8916 lp = sym_lp(np, tp, lun); 8917 if (!lp) 8918 continue; 8919 if (lp->itlq_tbl) 8920 sym_mfree_dma(lp->itlq_tbl, SYM_CONF_MAX_TASK*4, 8921 "ITLQ_TBL"); 8922 if (lp->cb_tags) 8923 sym_mfree(lp->cb_tags, SYM_CONF_MAX_TASK, 8924 "CB_TAGS"); 8925 sym_mfree_dma(lp, sizeof(*lp), "LCB"); 8926 } 8927 #if SYM_CONF_MAX_LUN > 1 8928 if (tp->lunmp) 8929 sym_mfree(tp->lunmp, SYM_CONF_MAX_LUN*sizeof(lcb_p), 8930 "LUNMP"); 8931 #endif 8932 } 8933 if (np->targtbl) 8934 sym_mfree_dma(np->targtbl, 256, "TARGTBL"); 8935 if (np->data_dmat) 8936 bus_dma_tag_destroy(np->data_dmat); 8937 sym_mfree_dma(np, sizeof(*np), "HCB"); 8938 } 8939 8940 /* 8941 * Allocate CAM resources and register a bus to CAM. 8942 */ 8943 static int sym_cam_attach(hcb_p np) 8944 { 8945 struct cam_devq *devq = 0; 8946 struct cam_sim *sim = 0; 8947 struct cam_path *path = 0; 8948 struct ccb_setasync csa; 8949 int err, s; 8950 8951 s = splcam(); 8952 8953 /* 8954 * Establish our interrupt handler. 8955 */ 8956 err = bus_setup_intr(np->device, np->irq_res, 8957 INTR_TYPE_CAM | INTR_ENTROPY, sym_intr, np, 8958 &np->intr); 8959 if (err) { 8960 device_printf(np->device, "bus_setup_intr() failed: %d\n", 8961 err); 8962 goto fail; 8963 } 8964 8965 /* 8966 * Create the device queue for our sym SIM. 8967 */ 8968 devq = cam_simq_alloc(SYM_CONF_MAX_START); 8969 if (!devq) 8970 goto fail; 8971 8972 /* 8973 * Construct our SIM entry. 8974 */ 8975 sim = cam_sim_alloc(sym_action, sym_poll, "sym", np, np->unit, 8976 1, SYM_SETUP_MAX_TAG, devq); 8977 if (!sim) 8978 goto fail; 8979 devq = 0; 8980 8981 if (xpt_bus_register(sim, 0) != CAM_SUCCESS) 8982 goto fail; 8983 np->sim = sim; 8984 sim = 0; 8985 8986 if (xpt_create_path(&path, 0, 8987 cam_sim_path(np->sim), CAM_TARGET_WILDCARD, 8988 CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 8989 goto fail; 8990 } 8991 np->path = path; 8992 8993 /* 8994 * Establish our async notification handler. 8995 */ 8996 xpt_setup_ccb(&csa.ccb_h, np->path, 5); 8997 csa.ccb_h.func_code = XPT_SASYNC_CB; 8998 csa.event_enable = AC_LOST_DEVICE; 8999 csa.callback = sym_async; 9000 csa.callback_arg = np->sim; 9001 xpt_action((union ccb *)&csa); 9002 9003 /* 9004 * Start the chip now, without resetting the BUS, since 9005 * it seems that this must stay under control of CAM. 9006 * With LVD/SE capable chips and BUS in SE mode, we may 9007 * get a spurious SMBC interrupt. 9008 */ 9009 sym_init (np, 0); 9010 9011 splx(s); 9012 return 1; 9013 fail: 9014 if (sim) 9015 cam_sim_free(sim, FALSE); 9016 if (devq) 9017 cam_simq_free(devq); 9018 9019 sym_cam_free(np); 9020 9021 splx(s); 9022 return 0; 9023 } 9024 9025 /* 9026 * Free everything that deals with CAM. 9027 */ 9028 static void sym_cam_free(hcb_p np) 9029 { 9030 if (np->intr) { 9031 bus_teardown_intr(np->device, np->irq_res, np->intr); 9032 np->intr = NULL; 9033 } 9034 9035 if (np->sim) { 9036 xpt_bus_deregister(cam_sim_path(np->sim)); 9037 cam_sim_free(np->sim, /*free_devq*/ TRUE); 9038 np->sim = NULL; 9039 } 9040 if (np->path) { 9041 xpt_free_path(np->path); 9042 np->path = NULL; 9043 } 9044 } 9045 9046 /*============ OPTIONNAL NVRAM SUPPORT =================*/ 9047 9048 /* 9049 * Get host setup from NVRAM. 9050 */ 9051 static void sym_nvram_setup_host (hcb_p np, struct sym_nvram *nvram) 9052 { 9053 #ifdef SYM_CONF_NVRAM_SUPPORT 9054 /* 9055 * Get parity checking, host ID, verbose mode 9056 * and miscellaneous host flags from NVRAM. 9057 */ 9058 switch(nvram->type) { 9059 case SYM_SYMBIOS_NVRAM: 9060 if (!(nvram->data.Symbios.flags & SYMBIOS_PARITY_ENABLE)) 9061 np->rv_scntl0 &= ~0x0a; 9062 np->myaddr = nvram->data.Symbios.host_id & 0x0f; 9063 if (nvram->data.Symbios.flags & SYMBIOS_VERBOSE_MSGS) 9064 np->verbose += 1; 9065 if (nvram->data.Symbios.flags1 & SYMBIOS_SCAN_HI_LO) 9066 np->usrflags |= SYM_SCAN_TARGETS_HILO; 9067 if (nvram->data.Symbios.flags2 & SYMBIOS_AVOID_BUS_RESET) 9068 np->usrflags |= SYM_AVOID_BUS_RESET; 9069 break; 9070 case SYM_TEKRAM_NVRAM: 9071 np->myaddr = nvram->data.Tekram.host_id & 0x0f; 9072 break; 9073 default: 9074 break; 9075 } 9076 #endif 9077 } 9078 9079 /* 9080 * Get target setup from NVRAM. 9081 */ 9082 #ifdef SYM_CONF_NVRAM_SUPPORT 9083 static void sym_Symbios_setup_target(hcb_p np,int target, Symbios_nvram *nvram); 9084 static void sym_Tekram_setup_target(hcb_p np,int target, Tekram_nvram *nvram); 9085 #endif 9086 9087 static void 9088 sym_nvram_setup_target (hcb_p np, int target, struct sym_nvram *nvp) 9089 { 9090 #ifdef SYM_CONF_NVRAM_SUPPORT 9091 switch(nvp->type) { 9092 case SYM_SYMBIOS_NVRAM: 9093 sym_Symbios_setup_target (np, target, &nvp->data.Symbios); 9094 break; 9095 case SYM_TEKRAM_NVRAM: 9096 sym_Tekram_setup_target (np, target, &nvp->data.Tekram); 9097 break; 9098 default: 9099 break; 9100 } 9101 #endif 9102 } 9103 9104 #ifdef SYM_CONF_NVRAM_SUPPORT 9105 /* 9106 * Get target set-up from Symbios format NVRAM. 9107 */ 9108 static void 9109 sym_Symbios_setup_target(hcb_p np, int target, Symbios_nvram *nvram) 9110 { 9111 tcb_p tp = &np->target[target]; 9112 Symbios_target *tn = &nvram->target[target]; 9113 9114 tp->tinfo.user.period = tn->sync_period ? (tn->sync_period + 3) / 4 : 0; 9115 tp->tinfo.user.width = tn->bus_width == 0x10 ? BUS_16_BIT : BUS_8_BIT; 9116 tp->usrtags = 9117 (tn->flags & SYMBIOS_QUEUE_TAGS_ENABLED)? SYM_SETUP_MAX_TAG : 0; 9118 9119 if (!(tn->flags & SYMBIOS_DISCONNECT_ENABLE)) 9120 tp->usrflags &= ~SYM_DISC_ENABLED; 9121 if (!(tn->flags & SYMBIOS_SCAN_AT_BOOT_TIME)) 9122 tp->usrflags |= SYM_SCAN_BOOT_DISABLED; 9123 if (!(tn->flags & SYMBIOS_SCAN_LUNS)) 9124 tp->usrflags |= SYM_SCAN_LUNS_DISABLED; 9125 } 9126 9127 /* 9128 * Get target set-up from Tekram format NVRAM. 9129 */ 9130 static void 9131 sym_Tekram_setup_target(hcb_p np, int target, Tekram_nvram *nvram) 9132 { 9133 tcb_p tp = &np->target[target]; 9134 struct Tekram_target *tn = &nvram->target[target]; 9135 int i; 9136 9137 if (tn->flags & TEKRAM_SYNC_NEGO) { 9138 i = tn->sync_index & 0xf; 9139 tp->tinfo.user.period = Tekram_sync[i]; 9140 } 9141 9142 tp->tinfo.user.width = 9143 (tn->flags & TEKRAM_WIDE_NEGO) ? BUS_16_BIT : BUS_8_BIT; 9144 9145 if (tn->flags & TEKRAM_TAGGED_COMMANDS) { 9146 tp->usrtags = 2 << nvram->max_tags_index; 9147 } 9148 9149 if (tn->flags & TEKRAM_DISCONNECT_ENABLE) 9150 tp->usrflags |= SYM_DISC_ENABLED; 9151 9152 /* If any device does not support parity, we will not use this option */ 9153 if (!(tn->flags & TEKRAM_PARITY_CHECK)) 9154 np->rv_scntl0 &= ~0x0a; /* SCSI parity checking disabled */ 9155 } 9156 9157 #ifdef SYM_CONF_DEBUG_NVRAM 9158 /* 9159 * Dump Symbios format NVRAM for debugging purpose. 9160 */ 9161 static void sym_display_Symbios_nvram(hcb_p np, Symbios_nvram *nvram) 9162 { 9163 int i; 9164 9165 /* display Symbios nvram host data */ 9166 printf("%s: HOST ID=%d%s%s%s%s%s%s\n", 9167 sym_name(np), nvram->host_id & 0x0f, 9168 (nvram->flags & SYMBIOS_SCAM_ENABLE) ? " SCAM" :"", 9169 (nvram->flags & SYMBIOS_PARITY_ENABLE) ? " PARITY" :"", 9170 (nvram->flags & SYMBIOS_VERBOSE_MSGS) ? " VERBOSE" :"", 9171 (nvram->flags & SYMBIOS_CHS_MAPPING) ? " CHS_ALT" :"", 9172 (nvram->flags2 & SYMBIOS_AVOID_BUS_RESET)?" NO_RESET" :"", 9173 (nvram->flags1 & SYMBIOS_SCAN_HI_LO) ? " HI_LO" :""); 9174 9175 /* display Symbios nvram drive data */ 9176 for (i = 0 ; i < 15 ; i++) { 9177 struct Symbios_target *tn = &nvram->target[i]; 9178 printf("%s-%d:%s%s%s%s WIDTH=%d SYNC=%d TMO=%d\n", 9179 sym_name(np), i, 9180 (tn->flags & SYMBIOS_DISCONNECT_ENABLE) ? " DISC" : "", 9181 (tn->flags & SYMBIOS_SCAN_AT_BOOT_TIME) ? " SCAN_BOOT" : "", 9182 (tn->flags & SYMBIOS_SCAN_LUNS) ? " SCAN_LUNS" : "", 9183 (tn->flags & SYMBIOS_QUEUE_TAGS_ENABLED)? " TCQ" : "", 9184 tn->bus_width, 9185 tn->sync_period / 4, 9186 tn->timeout); 9187 } 9188 } 9189 9190 /* 9191 * Dump TEKRAM format NVRAM for debugging purpose. 9192 */ 9193 static u_char Tekram_boot_delay[7] = {3, 5, 10, 20, 30, 60, 120}; 9194 static void sym_display_Tekram_nvram(hcb_p np, Tekram_nvram *nvram) 9195 { 9196 int i, tags, boot_delay; 9197 char *rem; 9198 9199 /* display Tekram nvram host data */ 9200 tags = 2 << nvram->max_tags_index; 9201 boot_delay = 0; 9202 if (nvram->boot_delay_index < 6) 9203 boot_delay = Tekram_boot_delay[nvram->boot_delay_index]; 9204 switch((nvram->flags & TEKRAM_REMOVABLE_FLAGS) >> 6) { 9205 default: 9206 case 0: rem = ""; break; 9207 case 1: rem = " REMOVABLE=boot device"; break; 9208 case 2: rem = " REMOVABLE=all"; break; 9209 } 9210 9211 printf("%s: HOST ID=%d%s%s%s%s%s%s%s%s%s BOOT DELAY=%d tags=%d\n", 9212 sym_name(np), nvram->host_id & 0x0f, 9213 (nvram->flags1 & SYMBIOS_SCAM_ENABLE) ? " SCAM" :"", 9214 (nvram->flags & TEKRAM_MORE_THAN_2_DRIVES) ? " >2DRIVES" :"", 9215 (nvram->flags & TEKRAM_DRIVES_SUP_1GB) ? " >1GB" :"", 9216 (nvram->flags & TEKRAM_RESET_ON_POWER_ON) ? " RESET" :"", 9217 (nvram->flags & TEKRAM_ACTIVE_NEGATION) ? " ACT_NEG" :"", 9218 (nvram->flags & TEKRAM_IMMEDIATE_SEEK) ? " IMM_SEEK" :"", 9219 (nvram->flags & TEKRAM_SCAN_LUNS) ? " SCAN_LUNS" :"", 9220 (nvram->flags1 & TEKRAM_F2_F6_ENABLED) ? " F2_F6" :"", 9221 rem, boot_delay, tags); 9222 9223 /* display Tekram nvram drive data */ 9224 for (i = 0; i <= 15; i++) { 9225 int sync, j; 9226 struct Tekram_target *tn = &nvram->target[i]; 9227 j = tn->sync_index & 0xf; 9228 sync = Tekram_sync[j]; 9229 printf("%s-%d:%s%s%s%s%s%s PERIOD=%d\n", 9230 sym_name(np), i, 9231 (tn->flags & TEKRAM_PARITY_CHECK) ? " PARITY" : "", 9232 (tn->flags & TEKRAM_SYNC_NEGO) ? " SYNC" : "", 9233 (tn->flags & TEKRAM_DISCONNECT_ENABLE) ? " DISC" : "", 9234 (tn->flags & TEKRAM_START_CMD) ? " START" : "", 9235 (tn->flags & TEKRAM_TAGGED_COMMANDS) ? " TCQ" : "", 9236 (tn->flags & TEKRAM_WIDE_NEGO) ? " WIDE" : "", 9237 sync); 9238 } 9239 } 9240 #endif /* SYM_CONF_DEBUG_NVRAM */ 9241 #endif /* SYM_CONF_NVRAM_SUPPORT */ 9242 9243 9244 /* 9245 * Try reading Symbios or Tekram NVRAM 9246 */ 9247 #ifdef SYM_CONF_NVRAM_SUPPORT 9248 static int sym_read_Symbios_nvram (hcb_p np, Symbios_nvram *nvram); 9249 static int sym_read_Tekram_nvram (hcb_p np, Tekram_nvram *nvram); 9250 #endif 9251 9252 static int sym_read_nvram(hcb_p np, struct sym_nvram *nvp) 9253 { 9254 #ifdef SYM_CONF_NVRAM_SUPPORT 9255 /* 9256 * Try to read SYMBIOS nvram. 9257 * Try to read TEKRAM nvram if Symbios nvram not found. 9258 */ 9259 if (SYM_SETUP_SYMBIOS_NVRAM && 9260 !sym_read_Symbios_nvram (np, &nvp->data.Symbios)) { 9261 nvp->type = SYM_SYMBIOS_NVRAM; 9262 #ifdef SYM_CONF_DEBUG_NVRAM 9263 sym_display_Symbios_nvram(np, &nvp->data.Symbios); 9264 #endif 9265 } 9266 else if (SYM_SETUP_TEKRAM_NVRAM && 9267 !sym_read_Tekram_nvram (np, &nvp->data.Tekram)) { 9268 nvp->type = SYM_TEKRAM_NVRAM; 9269 #ifdef SYM_CONF_DEBUG_NVRAM 9270 sym_display_Tekram_nvram(np, &nvp->data.Tekram); 9271 #endif 9272 } 9273 else 9274 nvp->type = 0; 9275 #else 9276 nvp->type = 0; 9277 #endif 9278 return nvp->type; 9279 } 9280 9281 9282 #ifdef SYM_CONF_NVRAM_SUPPORT 9283 /* 9284 * 24C16 EEPROM reading. 9285 * 9286 * GPOI0 - data in/data out 9287 * GPIO1 - clock 9288 * Symbios NVRAM wiring now also used by Tekram. 9289 */ 9290 9291 #define SET_BIT 0 9292 #define CLR_BIT 1 9293 #define SET_CLK 2 9294 #define CLR_CLK 3 9295 9296 /* 9297 * Set/clear data/clock bit in GPIO0 9298 */ 9299 static void S24C16_set_bit(hcb_p np, u_char write_bit, u_char *gpreg, 9300 int bit_mode) 9301 { 9302 UDELAY (5); 9303 switch (bit_mode){ 9304 case SET_BIT: 9305 *gpreg |= write_bit; 9306 break; 9307 case CLR_BIT: 9308 *gpreg &= 0xfe; 9309 break; 9310 case SET_CLK: 9311 *gpreg |= 0x02; 9312 break; 9313 case CLR_CLK: 9314 *gpreg &= 0xfd; 9315 break; 9316 9317 } 9318 OUTB (nc_gpreg, *gpreg); 9319 UDELAY (5); 9320 } 9321 9322 /* 9323 * Send START condition to NVRAM to wake it up. 9324 */ 9325 static void S24C16_start(hcb_p np, u_char *gpreg) 9326 { 9327 S24C16_set_bit(np, 1, gpreg, SET_BIT); 9328 S24C16_set_bit(np, 0, gpreg, SET_CLK); 9329 S24C16_set_bit(np, 0, gpreg, CLR_BIT); 9330 S24C16_set_bit(np, 0, gpreg, CLR_CLK); 9331 } 9332 9333 /* 9334 * Send STOP condition to NVRAM - puts NVRAM to sleep... ZZzzzz!! 9335 */ 9336 static void S24C16_stop(hcb_p np, u_char *gpreg) 9337 { 9338 S24C16_set_bit(np, 0, gpreg, SET_CLK); 9339 S24C16_set_bit(np, 1, gpreg, SET_BIT); 9340 } 9341 9342 /* 9343 * Read or write a bit to the NVRAM, 9344 * read if GPIO0 input else write if GPIO0 output 9345 */ 9346 static void S24C16_do_bit(hcb_p np, u_char *read_bit, u_char write_bit, 9347 u_char *gpreg) 9348 { 9349 S24C16_set_bit(np, write_bit, gpreg, SET_BIT); 9350 S24C16_set_bit(np, 0, gpreg, SET_CLK); 9351 if (read_bit) 9352 *read_bit = INB (nc_gpreg); 9353 S24C16_set_bit(np, 0, gpreg, CLR_CLK); 9354 S24C16_set_bit(np, 0, gpreg, CLR_BIT); 9355 } 9356 9357 /* 9358 * Output an ACK to the NVRAM after reading, 9359 * change GPIO0 to output and when done back to an input 9360 */ 9361 static void S24C16_write_ack(hcb_p np, u_char write_bit, u_char *gpreg, 9362 u_char *gpcntl) 9363 { 9364 OUTB (nc_gpcntl, *gpcntl & 0xfe); 9365 S24C16_do_bit(np, 0, write_bit, gpreg); 9366 OUTB (nc_gpcntl, *gpcntl); 9367 } 9368 9369 /* 9370 * Input an ACK from NVRAM after writing, 9371 * change GPIO0 to input and when done back to an output 9372 */ 9373 static void S24C16_read_ack(hcb_p np, u_char *read_bit, u_char *gpreg, 9374 u_char *gpcntl) 9375 { 9376 OUTB (nc_gpcntl, *gpcntl | 0x01); 9377 S24C16_do_bit(np, read_bit, 1, gpreg); 9378 OUTB (nc_gpcntl, *gpcntl); 9379 } 9380 9381 /* 9382 * WRITE a byte to the NVRAM and then get an ACK to see it was accepted OK, 9383 * GPIO0 must already be set as an output 9384 */ 9385 static void S24C16_write_byte(hcb_p np, u_char *ack_data, u_char write_data, 9386 u_char *gpreg, u_char *gpcntl) 9387 { 9388 int x; 9389 9390 for (x = 0; x < 8; x++) 9391 S24C16_do_bit(np, 0, (write_data >> (7 - x)) & 0x01, gpreg); 9392 9393 S24C16_read_ack(np, ack_data, gpreg, gpcntl); 9394 } 9395 9396 /* 9397 * READ a byte from the NVRAM and then send an ACK to say we have got it, 9398 * GPIO0 must already be set as an input 9399 */ 9400 static void S24C16_read_byte(hcb_p np, u_char *read_data, u_char ack_data, 9401 u_char *gpreg, u_char *gpcntl) 9402 { 9403 int x; 9404 u_char read_bit; 9405 9406 *read_data = 0; 9407 for (x = 0; x < 8; x++) { 9408 S24C16_do_bit(np, &read_bit, 1, gpreg); 9409 *read_data |= ((read_bit & 0x01) << (7 - x)); 9410 } 9411 9412 S24C16_write_ack(np, ack_data, gpreg, gpcntl); 9413 } 9414 9415 /* 9416 * Read 'len' bytes starting at 'offset'. 9417 */ 9418 static int sym_read_S24C16_nvram (hcb_p np, int offset, u_char *data, int len) 9419 { 9420 u_char gpcntl, gpreg; 9421 u_char old_gpcntl, old_gpreg; 9422 u_char ack_data; 9423 int retv = 1; 9424 int x; 9425 9426 /* save current state of GPCNTL and GPREG */ 9427 old_gpreg = INB (nc_gpreg); 9428 old_gpcntl = INB (nc_gpcntl); 9429 gpcntl = old_gpcntl & 0x1c; 9430 9431 /* set up GPREG & GPCNTL to set GPIO0 and GPIO1 in to known state */ 9432 OUTB (nc_gpreg, old_gpreg); 9433 OUTB (nc_gpcntl, gpcntl); 9434 9435 /* this is to set NVRAM into a known state with GPIO0/1 both low */ 9436 gpreg = old_gpreg; 9437 S24C16_set_bit(np, 0, &gpreg, CLR_CLK); 9438 S24C16_set_bit(np, 0, &gpreg, CLR_BIT); 9439 9440 /* now set NVRAM inactive with GPIO0/1 both high */ 9441 S24C16_stop(np, &gpreg); 9442 9443 /* activate NVRAM */ 9444 S24C16_start(np, &gpreg); 9445 9446 /* write device code and random address MSB */ 9447 S24C16_write_byte(np, &ack_data, 9448 0xa0 | ((offset >> 7) & 0x0e), &gpreg, &gpcntl); 9449 if (ack_data & 0x01) 9450 goto out; 9451 9452 /* write random address LSB */ 9453 S24C16_write_byte(np, &ack_data, 9454 offset & 0xff, &gpreg, &gpcntl); 9455 if (ack_data & 0x01) 9456 goto out; 9457 9458 /* regenerate START state to set up for reading */ 9459 S24C16_start(np, &gpreg); 9460 9461 /* rewrite device code and address MSB with read bit set (lsb = 0x01) */ 9462 S24C16_write_byte(np, &ack_data, 9463 0xa1 | ((offset >> 7) & 0x0e), &gpreg, &gpcntl); 9464 if (ack_data & 0x01) 9465 goto out; 9466 9467 /* now set up GPIO0 for inputting data */ 9468 gpcntl |= 0x01; 9469 OUTB (nc_gpcntl, gpcntl); 9470 9471 /* input all requested data - only part of total NVRAM */ 9472 for (x = 0; x < len; x++) 9473 S24C16_read_byte(np, &data[x], (x == (len-1)), &gpreg, &gpcntl); 9474 9475 /* finally put NVRAM back in inactive mode */ 9476 gpcntl &= 0xfe; 9477 OUTB (nc_gpcntl, gpcntl); 9478 S24C16_stop(np, &gpreg); 9479 retv = 0; 9480 out: 9481 /* return GPIO0/1 to original states after having accessed NVRAM */ 9482 OUTB (nc_gpcntl, old_gpcntl); 9483 OUTB (nc_gpreg, old_gpreg); 9484 9485 return retv; 9486 } 9487 9488 #undef SET_BIT /* 0 */ 9489 #undef CLR_BIT /* 1 */ 9490 #undef SET_CLK /* 2 */ 9491 #undef CLR_CLK /* 3 */ 9492 9493 /* 9494 * Try reading Symbios NVRAM. 9495 * Return 0 if OK. 9496 */ 9497 static int sym_read_Symbios_nvram (hcb_p np, Symbios_nvram *nvram) 9498 { 9499 static u_char Symbios_trailer[6] = {0xfe, 0xfe, 0, 0, 0, 0}; 9500 u_char *data = (u_char *) nvram; 9501 int len = sizeof(*nvram); 9502 u_short csum; 9503 int x; 9504 9505 /* probe the 24c16 and read the SYMBIOS 24c16 area */ 9506 if (sym_read_S24C16_nvram (np, SYMBIOS_NVRAM_ADDRESS, data, len)) 9507 return 1; 9508 9509 /* check valid NVRAM signature, verify byte count and checksum */ 9510 if (nvram->type != 0 || 9511 bcmp(nvram->trailer, Symbios_trailer, 6) || 9512 nvram->byte_count != len - 12) 9513 return 1; 9514 9515 /* verify checksum */ 9516 for (x = 6, csum = 0; x < len - 6; x++) 9517 csum += data[x]; 9518 if (csum != nvram->checksum) 9519 return 1; 9520 9521 return 0; 9522 } 9523 9524 /* 9525 * 93C46 EEPROM reading. 9526 * 9527 * GPOI0 - data in 9528 * GPIO1 - data out 9529 * GPIO2 - clock 9530 * GPIO4 - chip select 9531 * 9532 * Used by Tekram. 9533 */ 9534 9535 /* 9536 * Pulse clock bit in GPIO0 9537 */ 9538 static void T93C46_Clk(hcb_p np, u_char *gpreg) 9539 { 9540 OUTB (nc_gpreg, *gpreg | 0x04); 9541 UDELAY (2); 9542 OUTB (nc_gpreg, *gpreg); 9543 } 9544 9545 /* 9546 * Read bit from NVRAM 9547 */ 9548 static void T93C46_Read_Bit(hcb_p np, u_char *read_bit, u_char *gpreg) 9549 { 9550 UDELAY (2); 9551 T93C46_Clk(np, gpreg); 9552 *read_bit = INB (nc_gpreg); 9553 } 9554 9555 /* 9556 * Write bit to GPIO0 9557 */ 9558 static void T93C46_Write_Bit(hcb_p np, u_char write_bit, u_char *gpreg) 9559 { 9560 if (write_bit & 0x01) 9561 *gpreg |= 0x02; 9562 else 9563 *gpreg &= 0xfd; 9564 9565 *gpreg |= 0x10; 9566 9567 OUTB (nc_gpreg, *gpreg); 9568 UDELAY (2); 9569 9570 T93C46_Clk(np, gpreg); 9571 } 9572 9573 /* 9574 * Send STOP condition to NVRAM - puts NVRAM to sleep... ZZZzzz!! 9575 */ 9576 static void T93C46_Stop(hcb_p np, u_char *gpreg) 9577 { 9578 *gpreg &= 0xef; 9579 OUTB (nc_gpreg, *gpreg); 9580 UDELAY (2); 9581 9582 T93C46_Clk(np, gpreg); 9583 } 9584 9585 /* 9586 * Send read command and address to NVRAM 9587 */ 9588 static void T93C46_Send_Command(hcb_p np, u_short write_data, 9589 u_char *read_bit, u_char *gpreg) 9590 { 9591 int x; 9592 9593 /* send 9 bits, start bit (1), command (2), address (6) */ 9594 for (x = 0; x < 9; x++) 9595 T93C46_Write_Bit(np, (u_char) (write_data >> (8 - x)), gpreg); 9596 9597 *read_bit = INB (nc_gpreg); 9598 } 9599 9600 /* 9601 * READ 2 bytes from the NVRAM 9602 */ 9603 static void T93C46_Read_Word(hcb_p np, u_short *nvram_data, u_char *gpreg) 9604 { 9605 int x; 9606 u_char read_bit; 9607 9608 *nvram_data = 0; 9609 for (x = 0; x < 16; x++) { 9610 T93C46_Read_Bit(np, &read_bit, gpreg); 9611 9612 if (read_bit & 0x01) 9613 *nvram_data |= (0x01 << (15 - x)); 9614 else 9615 *nvram_data &= ~(0x01 << (15 - x)); 9616 } 9617 } 9618 9619 /* 9620 * Read Tekram NvRAM data. 9621 */ 9622 static int T93C46_Read_Data(hcb_p np, u_short *data,int len,u_char *gpreg) 9623 { 9624 u_char read_bit; 9625 int x; 9626 9627 for (x = 0; x < len; x++) { 9628 9629 /* output read command and address */ 9630 T93C46_Send_Command(np, 0x180 | x, &read_bit, gpreg); 9631 if (read_bit & 0x01) 9632 return 1; /* Bad */ 9633 T93C46_Read_Word(np, &data[x], gpreg); 9634 T93C46_Stop(np, gpreg); 9635 } 9636 9637 return 0; 9638 } 9639 9640 /* 9641 * Try reading 93C46 Tekram NVRAM. 9642 */ 9643 static int sym_read_T93C46_nvram (hcb_p np, Tekram_nvram *nvram) 9644 { 9645 u_char gpcntl, gpreg; 9646 u_char old_gpcntl, old_gpreg; 9647 int retv = 1; 9648 9649 /* save current state of GPCNTL and GPREG */ 9650 old_gpreg = INB (nc_gpreg); 9651 old_gpcntl = INB (nc_gpcntl); 9652 9653 /* set up GPREG & GPCNTL to set GPIO0/1/2/4 in to known state, 0 in, 9654 1/2/4 out */ 9655 gpreg = old_gpreg & 0xe9; 9656 OUTB (nc_gpreg, gpreg); 9657 gpcntl = (old_gpcntl & 0xe9) | 0x09; 9658 OUTB (nc_gpcntl, gpcntl); 9659 9660 /* input all of NVRAM, 64 words */ 9661 retv = T93C46_Read_Data(np, (u_short *) nvram, 9662 sizeof(*nvram) / sizeof(short), &gpreg); 9663 9664 /* return GPIO0/1/2/4 to original states after having accessed NVRAM */ 9665 OUTB (nc_gpcntl, old_gpcntl); 9666 OUTB (nc_gpreg, old_gpreg); 9667 9668 return retv; 9669 } 9670 9671 /* 9672 * Try reading Tekram NVRAM. 9673 * Return 0 if OK. 9674 */ 9675 static int sym_read_Tekram_nvram (hcb_p np, Tekram_nvram *nvram) 9676 { 9677 u_char *data = (u_char *) nvram; 9678 int len = sizeof(*nvram); 9679 u_short csum; 9680 int x; 9681 9682 switch (np->device_id) { 9683 case PCI_ID_SYM53C885: 9684 case PCI_ID_SYM53C895: 9685 case PCI_ID_SYM53C896: 9686 x = sym_read_S24C16_nvram(np, TEKRAM_24C16_NVRAM_ADDRESS, 9687 data, len); 9688 break; 9689 case PCI_ID_SYM53C875: 9690 x = sym_read_S24C16_nvram(np, TEKRAM_24C16_NVRAM_ADDRESS, 9691 data, len); 9692 if (!x) 9693 break; 9694 default: 9695 x = sym_read_T93C46_nvram(np, nvram); 9696 break; 9697 } 9698 if (x) 9699 return 1; 9700 9701 /* verify checksum */ 9702 for (x = 0, csum = 0; x < len - 1; x += 2) 9703 csum += data[x] + (data[x+1] << 8); 9704 if (csum != 0x1234) 9705 return 1; 9706 9707 return 0; 9708 } 9709 9710 #endif /* SYM_CONF_NVRAM_SUPPORT */ 9711