1 /* 2 * Device driver optimized for the Symbios/LSI 53C896/53C895A/53C1010 3 * PCI-SCSI controllers. 4 * 5 * Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr> 6 * 7 * This driver also supports the following Symbios/LSI PCI-SCSI chips: 8 * 53C810A, 53C825A, 53C860, 53C875, 53C876, 53C885, 53C895, 9 * 53C810, 53C815, 53C825 and the 53C1510D is 53C8XX mode. 10 * 11 * 12 * This driver for FreeBSD-CAM is derived from the Linux sym53c8xx driver. 13 * Copyright (C) 1998-1999 Gerard Roudier 14 * 15 * The sym53c8xx driver is derived from the ncr53c8xx driver that had been 16 * a port of the FreeBSD ncr driver to Linux-1.2.13. 17 * 18 * The original ncr driver has been written for 386bsd and FreeBSD by 19 * Wolfgang Stanglmeier <wolf@cologne.de> 20 * Stefan Esser <se@mi.Uni-Koeln.de> 21 * Copyright (C) 1994 Wolfgang Stanglmeier 22 * 23 * The initialisation code, and part of the code that addresses 24 * FreeBSD-CAM services is based on the aic7xxx driver for FreeBSD-CAM 25 * written by Justin T. Gibbs. 26 * 27 * Other major contributions: 28 * 29 * NVRAM detection and reading. 30 * Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk> 31 * 32 *----------------------------------------------------------------------------- 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 3. The name of the author may not be used to endorse or promote products 43 * derived from this software without specific prior written permission. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 49 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 /* $FreeBSD$ */ 59 60 #define SYM_DRIVER_NAME "sym-1.6.5-20000902" 61 62 /* #define SYM_DEBUG_GENERIC_SUPPORT */ 63 /* #define CAM_NEW_TRAN_CODE */ 64 65 #include <sys/param.h> 66 67 /* 68 * Only use the BUS stuff for PCI under FreeBSD 4 and later versions. 69 * Note that the old BUS stuff also works for FreeBSD 4 and spares 70 * about 1 KB for the driver object file. 71 */ 72 #if __FreeBSD_version >= 400000 73 #define FreeBSD_Bus_Dma_Abstraction 74 #define FreeBSD_Bus_Io_Abstraction 75 #define FreeBSD_Bus_Space_Abstraction 76 #endif 77 78 /* 79 * Driver configuration options. 80 */ 81 #include "opt_sym.h" 82 #include <dev/sym/sym_conf.h> 83 84 #ifndef FreeBSD_Bus_Io_Abstraction 85 #include "ncr.h" /* To know if the ncr has been configured */ 86 #endif 87 88 #include <sys/systm.h> 89 #include <sys/malloc.h> 90 #include <sys/endian.h> 91 #include <sys/kernel.h> 92 #ifdef FreeBSD_Bus_Io_Abstraction 93 #include <sys/module.h> 94 #include <sys/bus.h> 95 #endif 96 97 #include <sys/proc.h> 98 99 #include <pci/pcireg.h> 100 #include <pci/pcivar.h> 101 102 #ifdef FreeBSD_Bus_Space_Abstraction 103 #include <machine/bus_memio.h> 104 /* 105 * Only include bus_pio if needed. 106 * This avoids bus space primitives to be uselessly bloated 107 * by out-of-age PIO operations. 108 */ 109 #ifdef SYM_CONF_IOMAPPED 110 #include <machine/bus_pio.h> 111 #endif 112 #endif 113 #include <machine/bus.h> 114 115 #ifdef FreeBSD_Bus_Io_Abstraction 116 #include <machine/resource.h> 117 #include <sys/rman.h> 118 #endif 119 120 #include <cam/cam.h> 121 #include <cam/cam_ccb.h> 122 #include <cam/cam_sim.h> 123 #include <cam/cam_xpt_sim.h> 124 #include <cam/cam_debug.h> 125 126 #include <cam/scsi/scsi_all.h> 127 #include <cam/scsi/scsi_message.h> 128 129 #include <vm/vm.h> 130 #include <vm/vm_param.h> 131 #include <vm/pmap.h> 132 133 /* Short and quite clear integer types */ 134 typedef int8_t s8; 135 typedef int16_t s16; 136 typedef int32_t s32; 137 typedef u_int8_t u8; 138 typedef u_int16_t u16; 139 typedef u_int32_t u32; 140 141 /* 142 * From 'cam.error_recovery_diffs.20010313.context' patch. 143 */ 144 #ifdef CAM_NEW_TRAN_CODE 145 #define FreeBSD_New_Tran_Settings 146 #endif /* CAM_NEW_TRAN_CODE */ 147 148 /* 149 * Driver definitions. 150 */ 151 #include <dev/sym/sym_defs.h> 152 #include <dev/sym/sym_fw.h> 153 154 /* 155 * IA32 architecture does not reorder STORES and prevents 156 * LOADS from passing STORES. It is called `program order' 157 * by Intel and allows device drivers to deal with memory 158 * ordering by only ensuring that the code is not reordered 159 * by the compiler when ordering is required. 160 * Other architectures implement a weaker ordering that 161 * requires memory barriers (and also IO barriers when they 162 * make sense) to be used. 163 */ 164 165 #if defined __i386__ 166 #define MEMORY_BARRIER() do { ; } while(0) 167 #elif defined __alpha__ 168 #define MEMORY_BARRIER() alpha_mb() 169 #elif defined __powerpc__ 170 #define MEMORY_BARRIER() __asm__ volatile("eieio; sync" : : : "memory") 171 #elif defined __ia64__ 172 #define MEMORY_BARRIER() __asm__ volatile("mf.a; mf" : : : "memory") 173 #elif defined __sparc64__ 174 #define MEMORY_BARRIER() __asm__ volatile("membar #Sync" : : : "memory") 175 #else 176 #error "Not supported platform" 177 #endif 178 179 /* 180 * Portable but silly implemented byte order primitives. 181 * We define the primitives we need, since FreeBSD doesn't 182 * seem to have them yet. 183 */ 184 #if BYTE_ORDER == BIG_ENDIAN 185 186 #define __revb16(x) ( (((u16)(x) & (u16)0x00ffU) << 8) | \ 187 (((u16)(x) & (u16)0xff00U) >> 8) ) 188 #define __revb32(x) ( (((u32)(x) & 0x000000ffU) << 24) | \ 189 (((u32)(x) & 0x0000ff00U) << 8) | \ 190 (((u32)(x) & 0x00ff0000U) >> 8) | \ 191 (((u32)(x) & 0xff000000U) >> 24) ) 192 193 #define __htole16(v) __revb16(v) 194 #define __htole32(v) __revb32(v) 195 #define __le16toh(v) __htole16(v) 196 #define __le32toh(v) __htole32(v) 197 198 static __inline u16 _htole16(u16 v) { return __htole16(v); } 199 static __inline u32 _htole32(u32 v) { return __htole32(v); } 200 #define _le16toh _htole16 201 #define _le32toh _htole32 202 203 #else /* LITTLE ENDIAN */ 204 205 #define __htole16(v) (v) 206 #define __htole32(v) (v) 207 #define __le16toh(v) (v) 208 #define __le32toh(v) (v) 209 210 #define _htole16(v) (v) 211 #define _htole32(v) (v) 212 #define _le16toh(v) (v) 213 #define _le32toh(v) (v) 214 215 #endif /* BYTE_ORDER */ 216 217 /* 218 * A la VMS/CAM-3 queue management. 219 */ 220 221 typedef struct sym_quehead { 222 struct sym_quehead *flink; /* Forward pointer */ 223 struct sym_quehead *blink; /* Backward pointer */ 224 } SYM_QUEHEAD; 225 226 #define sym_que_init(ptr) do { \ 227 (ptr)->flink = (ptr); (ptr)->blink = (ptr); \ 228 } while (0) 229 230 static __inline struct sym_quehead *sym_que_first(struct sym_quehead *head) 231 { 232 return (head->flink == head) ? 0 : head->flink; 233 } 234 235 static __inline struct sym_quehead *sym_que_last(struct sym_quehead *head) 236 { 237 return (head->blink == head) ? 0 : head->blink; 238 } 239 240 static __inline void __sym_que_add(struct sym_quehead * new, 241 struct sym_quehead * blink, 242 struct sym_quehead * flink) 243 { 244 flink->blink = new; 245 new->flink = flink; 246 new->blink = blink; 247 blink->flink = new; 248 } 249 250 static __inline void __sym_que_del(struct sym_quehead * blink, 251 struct sym_quehead * flink) 252 { 253 flink->blink = blink; 254 blink->flink = flink; 255 } 256 257 static __inline int sym_que_empty(struct sym_quehead *head) 258 { 259 return head->flink == head; 260 } 261 262 static __inline void sym_que_splice(struct sym_quehead *list, 263 struct sym_quehead *head) 264 { 265 struct sym_quehead *first = list->flink; 266 267 if (first != list) { 268 struct sym_quehead *last = list->blink; 269 struct sym_quehead *at = head->flink; 270 271 first->blink = head; 272 head->flink = first; 273 274 last->flink = at; 275 at->blink = last; 276 } 277 } 278 279 #define sym_que_entry(ptr, type, member) \ 280 ((type *)((char *)(ptr)-(unsigned int)(&((type *)0)->member))) 281 282 283 #define sym_insque(new, pos) __sym_que_add(new, pos, (pos)->flink) 284 285 #define sym_remque(el) __sym_que_del((el)->blink, (el)->flink) 286 287 #define sym_insque_head(new, head) __sym_que_add(new, head, (head)->flink) 288 289 static __inline struct sym_quehead *sym_remque_head(struct sym_quehead *head) 290 { 291 struct sym_quehead *elem = head->flink; 292 293 if (elem != head) 294 __sym_que_del(head, elem->flink); 295 else 296 elem = 0; 297 return elem; 298 } 299 300 #define sym_insque_tail(new, head) __sym_que_add(new, (head)->blink, head) 301 302 static __inline struct sym_quehead *sym_remque_tail(struct sym_quehead *head) 303 { 304 struct sym_quehead *elem = head->blink; 305 306 if (elem != head) 307 __sym_que_del(elem->blink, head); 308 else 309 elem = 0; 310 return elem; 311 } 312 313 /* 314 * This one may be useful. 315 */ 316 #define FOR_EACH_QUEUED_ELEMENT(head, qp) \ 317 for (qp = (head)->flink; qp != (head); qp = qp->flink) 318 /* 319 * FreeBSD does not offer our kind of queue in the CAM CCB. 320 * So, we have to cast. 321 */ 322 #define sym_qptr(p) ((struct sym_quehead *) (p)) 323 324 /* 325 * Simple bitmap operations. 326 */ 327 #define sym_set_bit(p, n) (((u32 *)(p))[(n)>>5] |= (1<<((n)&0x1f))) 328 #define sym_clr_bit(p, n) (((u32 *)(p))[(n)>>5] &= ~(1<<((n)&0x1f))) 329 #define sym_is_bit(p, n) (((u32 *)(p))[(n)>>5] & (1<<((n)&0x1f))) 330 331 /* 332 * Number of tasks per device we want to handle. 333 */ 334 #if SYM_CONF_MAX_TAG_ORDER > 8 335 #error "more than 256 tags per logical unit not allowed." 336 #endif 337 #define SYM_CONF_MAX_TASK (1<<SYM_CONF_MAX_TAG_ORDER) 338 339 /* 340 * Donnot use more tasks that we can handle. 341 */ 342 #ifndef SYM_CONF_MAX_TAG 343 #define SYM_CONF_MAX_TAG SYM_CONF_MAX_TASK 344 #endif 345 #if SYM_CONF_MAX_TAG > SYM_CONF_MAX_TASK 346 #undef SYM_CONF_MAX_TAG 347 #define SYM_CONF_MAX_TAG SYM_CONF_MAX_TASK 348 #endif 349 350 /* 351 * This one means 'NO TAG for this job' 352 */ 353 #define NO_TAG (256) 354 355 /* 356 * Number of SCSI targets. 357 */ 358 #if SYM_CONF_MAX_TARGET > 16 359 #error "more than 16 targets not allowed." 360 #endif 361 362 /* 363 * Number of logical units per target. 364 */ 365 #if SYM_CONF_MAX_LUN > 64 366 #error "more than 64 logical units per target not allowed." 367 #endif 368 369 /* 370 * Asynchronous pre-scaler (ns). Shall be 40 for 371 * the SCSI timings to be compliant. 372 */ 373 #define SYM_CONF_MIN_ASYNC (40) 374 375 /* 376 * Number of entries in the START and DONE queues. 377 * 378 * We limit to 1 PAGE in order to succeed allocation of 379 * these queues. Each entry is 8 bytes long (2 DWORDS). 380 */ 381 #ifdef SYM_CONF_MAX_START 382 #define SYM_CONF_MAX_QUEUE (SYM_CONF_MAX_START+2) 383 #else 384 #define SYM_CONF_MAX_QUEUE (7*SYM_CONF_MAX_TASK+2) 385 #define SYM_CONF_MAX_START (SYM_CONF_MAX_QUEUE-2) 386 #endif 387 388 #if SYM_CONF_MAX_QUEUE > PAGE_SIZE/8 389 #undef SYM_CONF_MAX_QUEUE 390 #define SYM_CONF_MAX_QUEUE PAGE_SIZE/8 391 #undef SYM_CONF_MAX_START 392 #define SYM_CONF_MAX_START (SYM_CONF_MAX_QUEUE-2) 393 #endif 394 395 /* 396 * For this one, we want a short name :-) 397 */ 398 #define MAX_QUEUE SYM_CONF_MAX_QUEUE 399 400 /* 401 * Active debugging tags and verbosity. 402 */ 403 #define DEBUG_ALLOC (0x0001) 404 #define DEBUG_PHASE (0x0002) 405 #define DEBUG_POLL (0x0004) 406 #define DEBUG_QUEUE (0x0008) 407 #define DEBUG_RESULT (0x0010) 408 #define DEBUG_SCATTER (0x0020) 409 #define DEBUG_SCRIPT (0x0040) 410 #define DEBUG_TINY (0x0080) 411 #define DEBUG_TIMING (0x0100) 412 #define DEBUG_NEGO (0x0200) 413 #define DEBUG_TAGS (0x0400) 414 #define DEBUG_POINTER (0x0800) 415 416 #if 0 417 static int sym_debug = 0; 418 #define DEBUG_FLAGS sym_debug 419 #else 420 /* #define DEBUG_FLAGS (0x0631) */ 421 #define DEBUG_FLAGS (0x0000) 422 423 #endif 424 #define sym_verbose (np->verbose) 425 426 /* 427 * Insert a delay in micro-seconds and milli-seconds. 428 */ 429 static void UDELAY(int us) { DELAY(us); } 430 static void MDELAY(int ms) { while (ms--) UDELAY(1000); } 431 432 /* 433 * Simple power of two buddy-like allocator. 434 * 435 * This simple code is not intended to be fast, but to 436 * provide power of 2 aligned memory allocations. 437 * Since the SCRIPTS processor only supplies 8 bit arithmetic, 438 * this allocator allows simple and fast address calculations 439 * from the SCRIPTS code. In addition, cache line alignment 440 * is guaranteed for power of 2 cache line size. 441 * 442 * This allocator has been developped for the Linux sym53c8xx 443 * driver, since this O/S does not provide naturally aligned 444 * allocations. 445 * It has the advantage of allowing the driver to use private 446 * pages of memory that will be useful if we ever need to deal 447 * with IO MMUs for PCI. 448 */ 449 450 #define MEMO_SHIFT 4 /* 16 bytes minimum memory chunk */ 451 #define MEMO_PAGE_ORDER 0 /* 1 PAGE maximum */ 452 #if 0 453 #define MEMO_FREE_UNUSED /* Free unused pages immediately */ 454 #endif 455 #define MEMO_WARN 1 456 #define MEMO_CLUSTER_SHIFT (PAGE_SHIFT+MEMO_PAGE_ORDER) 457 #define MEMO_CLUSTER_SIZE (1UL << MEMO_CLUSTER_SHIFT) 458 #define MEMO_CLUSTER_MASK (MEMO_CLUSTER_SIZE-1) 459 460 #define get_pages() malloc(MEMO_CLUSTER_SIZE, M_DEVBUF, M_NOWAIT) 461 #define free_pages(p) free((p), M_DEVBUF) 462 463 typedef u_long m_addr_t; /* Enough bits to bit-hack addresses */ 464 465 typedef struct m_link { /* Link between free memory chunks */ 466 struct m_link *next; 467 } m_link_s; 468 469 #ifdef FreeBSD_Bus_Dma_Abstraction 470 typedef struct m_vtob { /* Virtual to Bus address translation */ 471 struct m_vtob *next; 472 bus_dmamap_t dmamap; /* Map for this chunk */ 473 m_addr_t vaddr; /* Virtual address */ 474 m_addr_t baddr; /* Bus physical address */ 475 } m_vtob_s; 476 /* Hash this stuff a bit to speed up translations */ 477 #define VTOB_HASH_SHIFT 5 478 #define VTOB_HASH_SIZE (1UL << VTOB_HASH_SHIFT) 479 #define VTOB_HASH_MASK (VTOB_HASH_SIZE-1) 480 #define VTOB_HASH_CODE(m) \ 481 ((((m_addr_t) (m)) >> MEMO_CLUSTER_SHIFT) & VTOB_HASH_MASK) 482 #endif 483 484 typedef struct m_pool { /* Memory pool of a given kind */ 485 #ifdef FreeBSD_Bus_Dma_Abstraction 486 bus_dma_tag_t dev_dmat; /* Identifies the pool */ 487 bus_dma_tag_t dmat; /* Tag for our fixed allocations */ 488 m_addr_t (*getp)(struct m_pool *); 489 #ifdef MEMO_FREE_UNUSED 490 void (*freep)(struct m_pool *, m_addr_t); 491 #endif 492 #define M_GETP() mp->getp(mp) 493 #define M_FREEP(p) mp->freep(mp, p) 494 int nump; 495 m_vtob_s *(vtob[VTOB_HASH_SIZE]); 496 struct m_pool *next; 497 #else 498 #define M_GETP() get_pages() 499 #define M_FREEP(p) free_pages(p) 500 #endif /* FreeBSD_Bus_Dma_Abstraction */ 501 struct m_link h[MEMO_CLUSTER_SHIFT - MEMO_SHIFT + 1]; 502 } m_pool_s; 503 504 static void *___sym_malloc(m_pool_s *mp, int size) 505 { 506 int i = 0; 507 int s = (1 << MEMO_SHIFT); 508 int j; 509 m_addr_t a; 510 m_link_s *h = mp->h; 511 512 if (size > MEMO_CLUSTER_SIZE) 513 return 0; 514 515 while (size > s) { 516 s <<= 1; 517 ++i; 518 } 519 520 j = i; 521 while (!h[j].next) { 522 if (s == MEMO_CLUSTER_SIZE) { 523 h[j].next = (m_link_s *) M_GETP(); 524 if (h[j].next) 525 h[j].next->next = 0; 526 break; 527 } 528 ++j; 529 s <<= 1; 530 } 531 a = (m_addr_t) h[j].next; 532 if (a) { 533 h[j].next = h[j].next->next; 534 while (j > i) { 535 j -= 1; 536 s >>= 1; 537 h[j].next = (m_link_s *) (a+s); 538 h[j].next->next = 0; 539 } 540 } 541 #ifdef DEBUG 542 printf("___sym_malloc(%d) = %p\n", size, (void *) a); 543 #endif 544 return (void *) a; 545 } 546 547 static void ___sym_mfree(m_pool_s *mp, void *ptr, int size) 548 { 549 int i = 0; 550 int s = (1 << MEMO_SHIFT); 551 m_link_s *q; 552 m_addr_t a, b; 553 m_link_s *h = mp->h; 554 555 #ifdef DEBUG 556 printf("___sym_mfree(%p, %d)\n", ptr, size); 557 #endif 558 559 if (size > MEMO_CLUSTER_SIZE) 560 return; 561 562 while (size > s) { 563 s <<= 1; 564 ++i; 565 } 566 567 a = (m_addr_t) ptr; 568 569 while (1) { 570 #ifdef MEMO_FREE_UNUSED 571 if (s == MEMO_CLUSTER_SIZE) { 572 M_FREEP(a); 573 break; 574 } 575 #endif 576 b = a ^ s; 577 q = &h[i]; 578 while (q->next && q->next != (m_link_s *) b) { 579 q = q->next; 580 } 581 if (!q->next) { 582 ((m_link_s *) a)->next = h[i].next; 583 h[i].next = (m_link_s *) a; 584 break; 585 } 586 q->next = q->next->next; 587 a = a & b; 588 s <<= 1; 589 ++i; 590 } 591 } 592 593 static void *__sym_calloc2(m_pool_s *mp, int size, char *name, int uflags) 594 { 595 void *p; 596 597 p = ___sym_malloc(mp, size); 598 599 if (DEBUG_FLAGS & DEBUG_ALLOC) 600 printf ("new %-10s[%4d] @%p.\n", name, size, p); 601 602 if (p) 603 bzero(p, size); 604 else if (uflags & MEMO_WARN) 605 printf ("__sym_calloc2: failed to allocate %s[%d]\n", name, size); 606 607 return p; 608 } 609 610 #define __sym_calloc(mp, s, n) __sym_calloc2(mp, s, n, MEMO_WARN) 611 612 static void __sym_mfree(m_pool_s *mp, void *ptr, int size, char *name) 613 { 614 if (DEBUG_FLAGS & DEBUG_ALLOC) 615 printf ("freeing %-10s[%4d] @%p.\n", name, size, ptr); 616 617 ___sym_mfree(mp, ptr, size); 618 619 } 620 621 /* 622 * Default memory pool we donnot need to involve in DMA. 623 */ 624 #ifndef FreeBSD_Bus_Dma_Abstraction 625 /* 626 * Without the `bus dma abstraction', all the memory is assumed 627 * DMAable and a single pool is all what we need. 628 */ 629 static m_pool_s mp0; 630 631 #else 632 /* 633 * With the `bus dma abstraction', we use a separate pool for 634 * memory we donnot need to involve in DMA. 635 */ 636 static m_addr_t ___mp0_getp(m_pool_s *mp) 637 { 638 m_addr_t m = (m_addr_t) get_pages(); 639 if (m) 640 ++mp->nump; 641 return m; 642 } 643 644 #ifdef MEMO_FREE_UNUSED 645 static void ___mp0_freep(m_pool_s *mp, m_addr_t m) 646 { 647 free_pages(m); 648 --mp->nump; 649 } 650 #endif 651 652 #ifdef MEMO_FREE_UNUSED 653 static m_pool_s mp0 = {0, 0, ___mp0_getp, ___mp0_freep}; 654 #else 655 static m_pool_s mp0 = {0, 0, ___mp0_getp}; 656 #endif 657 658 #endif /* FreeBSD_Bus_Dma_Abstraction */ 659 660 /* 661 * Actual memory allocation routine for non-DMAed memory. 662 */ 663 static void *sym_calloc(int size, char *name) 664 { 665 void *m; 666 /* Lock */ 667 m = __sym_calloc(&mp0, size, name); 668 /* Unlock */ 669 return m; 670 } 671 672 /* 673 * Actual memory allocation routine for non-DMAed memory. 674 */ 675 static void sym_mfree(void *ptr, int size, char *name) 676 { 677 /* Lock */ 678 __sym_mfree(&mp0, ptr, size, name); 679 /* Unlock */ 680 } 681 682 /* 683 * DMAable pools. 684 */ 685 #ifndef FreeBSD_Bus_Dma_Abstraction 686 /* 687 * Without `bus dma abstraction', all the memory is DMAable, and 688 * only a single pool is needed (vtophys() is our friend). 689 */ 690 #define __sym_calloc_dma(b, s, n) sym_calloc(s, n) 691 #define __sym_mfree_dma(b, p, s, n) sym_mfree(p, s, n) 692 #ifdef __alpha__ 693 #define __vtobus(b, p) alpha_XXX_dmamap((vm_offset_t)(p)) 694 #else /*__i386__, __sparc64__*/ 695 #define __vtobus(b, p) vtophys(p) 696 #endif 697 698 #else 699 /* 700 * With `bus dma abstraction', we use a separate pool per parent 701 * BUS handle. A reverse table (hashed) is maintained for virtual 702 * to BUS address translation. 703 */ 704 static void getbaddrcb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 705 { 706 bus_addr_t *baddr; 707 baddr = (bus_addr_t *)arg; 708 *baddr = segs->ds_addr; 709 } 710 711 static m_addr_t ___dma_getp(m_pool_s *mp) 712 { 713 m_vtob_s *vbp; 714 void *vaddr = 0; 715 bus_addr_t baddr = 0; 716 717 vbp = __sym_calloc(&mp0, sizeof(*vbp), "VTOB"); 718 if (!vbp) 719 goto out_err; 720 721 if (bus_dmamem_alloc(mp->dmat, &vaddr, 722 BUS_DMA_NOWAIT, &vbp->dmamap)) 723 goto out_err; 724 bus_dmamap_load(mp->dmat, vbp->dmamap, vaddr, 725 MEMO_CLUSTER_SIZE, getbaddrcb, &baddr, 0); 726 if (baddr) { 727 int hc = VTOB_HASH_CODE(vaddr); 728 vbp->vaddr = (m_addr_t) vaddr; 729 vbp->baddr = (m_addr_t) baddr; 730 vbp->next = mp->vtob[hc]; 731 mp->vtob[hc] = vbp; 732 ++mp->nump; 733 return (m_addr_t) vaddr; 734 } 735 out_err: 736 if (baddr) 737 bus_dmamap_unload(mp->dmat, vbp->dmamap); 738 if (vaddr) 739 bus_dmamem_free(mp->dmat, vaddr, vbp->dmamap); 740 if (vbp->dmamap) 741 bus_dmamap_destroy(mp->dmat, vbp->dmamap); 742 if (vbp) 743 __sym_mfree(&mp0, vbp, sizeof(*vbp), "VTOB"); 744 return 0; 745 } 746 747 #ifdef MEMO_FREE_UNUSED 748 static void ___dma_freep(m_pool_s *mp, m_addr_t m) 749 { 750 m_vtob_s **vbpp, *vbp; 751 int hc = VTOB_HASH_CODE(m); 752 753 vbpp = &mp->vtob[hc]; 754 while (*vbpp && (*vbpp)->vaddr != m) 755 vbpp = &(*vbpp)->next; 756 if (*vbpp) { 757 vbp = *vbpp; 758 *vbpp = (*vbpp)->next; 759 bus_dmamap_unload(mp->dmat, vbp->dmamap); 760 bus_dmamem_free(mp->dmat, (void *) vbp->vaddr, vbp->dmamap); 761 bus_dmamap_destroy(mp->dmat, vbp->dmamap); 762 __sym_mfree(&mp0, vbp, sizeof(*vbp), "VTOB"); 763 --mp->nump; 764 } 765 } 766 #endif 767 768 static __inline m_pool_s *___get_dma_pool(bus_dma_tag_t dev_dmat) 769 { 770 m_pool_s *mp; 771 for (mp = mp0.next; mp && mp->dev_dmat != dev_dmat; mp = mp->next); 772 return mp; 773 } 774 775 static m_pool_s *___cre_dma_pool(bus_dma_tag_t dev_dmat) 776 { 777 m_pool_s *mp = 0; 778 779 mp = __sym_calloc(&mp0, sizeof(*mp), "MPOOL"); 780 if (mp) { 781 mp->dev_dmat = dev_dmat; 782 if (!bus_dma_tag_create(dev_dmat, 1, MEMO_CLUSTER_SIZE, 783 BUS_SPACE_MAXADDR_32BIT, 784 BUS_SPACE_MAXADDR_32BIT, 785 NULL, NULL, MEMO_CLUSTER_SIZE, 1, 786 MEMO_CLUSTER_SIZE, 0, &mp->dmat)) { 787 mp->getp = ___dma_getp; 788 #ifdef MEMO_FREE_UNUSED 789 mp->freep = ___dma_freep; 790 #endif 791 mp->next = mp0.next; 792 mp0.next = mp; 793 return mp; 794 } 795 } 796 if (mp) 797 __sym_mfree(&mp0, mp, sizeof(*mp), "MPOOL"); 798 return 0; 799 } 800 801 #ifdef MEMO_FREE_UNUSED 802 static void ___del_dma_pool(m_pool_s *p) 803 { 804 struct m_pool **pp = &mp0.next; 805 806 while (*pp && *pp != p) 807 pp = &(*pp)->next; 808 if (*pp) { 809 *pp = (*pp)->next; 810 bus_dma_tag_destroy(p->dmat); 811 __sym_mfree(&mp0, p, sizeof(*p), "MPOOL"); 812 } 813 } 814 #endif 815 816 static void *__sym_calloc_dma(bus_dma_tag_t dev_dmat, int size, char *name) 817 { 818 struct m_pool *mp; 819 void *m = 0; 820 821 /* Lock */ 822 mp = ___get_dma_pool(dev_dmat); 823 if (!mp) 824 mp = ___cre_dma_pool(dev_dmat); 825 if (mp) 826 m = __sym_calloc(mp, size, name); 827 #ifdef MEMO_FREE_UNUSED 828 if (mp && !mp->nump) 829 ___del_dma_pool(mp); 830 #endif 831 /* Unlock */ 832 833 return m; 834 } 835 836 static void 837 __sym_mfree_dma(bus_dma_tag_t dev_dmat, void *m, int size, char *name) 838 { 839 struct m_pool *mp; 840 841 /* Lock */ 842 mp = ___get_dma_pool(dev_dmat); 843 if (mp) 844 __sym_mfree(mp, m, size, name); 845 #ifdef MEMO_FREE_UNUSED 846 if (mp && !mp->nump) 847 ___del_dma_pool(mp); 848 #endif 849 /* Unlock */ 850 } 851 852 static m_addr_t __vtobus(bus_dma_tag_t dev_dmat, void *m) 853 { 854 m_pool_s *mp; 855 int hc = VTOB_HASH_CODE(m); 856 m_vtob_s *vp = 0; 857 m_addr_t a = ((m_addr_t) m) & ~MEMO_CLUSTER_MASK; 858 859 /* Lock */ 860 mp = ___get_dma_pool(dev_dmat); 861 if (mp) { 862 vp = mp->vtob[hc]; 863 while (vp && (m_addr_t) vp->vaddr != a) 864 vp = vp->next; 865 } 866 /* Unlock */ 867 if (!vp) 868 panic("sym: VTOBUS FAILED!\n"); 869 return vp ? vp->baddr + (((m_addr_t) m) - a) : 0; 870 } 871 872 #endif /* FreeBSD_Bus_Dma_Abstraction */ 873 874 /* 875 * Verbs for DMAable memory handling. 876 * The _uvptv_ macro avoids a nasty warning about pointer to volatile 877 * being discarded. 878 */ 879 #define _uvptv_(p) ((void *)((vm_offset_t)(p))) 880 #define _sym_calloc_dma(np, s, n) __sym_calloc_dma(np->bus_dmat, s, n) 881 #define _sym_mfree_dma(np, p, s, n) \ 882 __sym_mfree_dma(np->bus_dmat, _uvptv_(p), s, n) 883 #define sym_calloc_dma(s, n) _sym_calloc_dma(np, s, n) 884 #define sym_mfree_dma(p, s, n) _sym_mfree_dma(np, p, s, n) 885 #define _vtobus(np, p) __vtobus(np->bus_dmat, _uvptv_(p)) 886 #define vtobus(p) _vtobus(np, p) 887 888 889 /* 890 * Print a buffer in hexadecimal format. 891 */ 892 static void sym_printb_hex (u_char *p, int n) 893 { 894 while (n-- > 0) 895 printf (" %x", *p++); 896 } 897 898 /* 899 * Same with a label at beginning and .\n at end. 900 */ 901 static void sym_printl_hex (char *label, u_char *p, int n) 902 { 903 printf ("%s", label); 904 sym_printb_hex (p, n); 905 printf (".\n"); 906 } 907 908 /* 909 * Return a string for SCSI BUS mode. 910 */ 911 static char *sym_scsi_bus_mode(int mode) 912 { 913 switch(mode) { 914 case SMODE_HVD: return "HVD"; 915 case SMODE_SE: return "SE"; 916 case SMODE_LVD: return "LVD"; 917 } 918 return "??"; 919 } 920 921 /* 922 * Some poor and bogus sync table that refers to Tekram NVRAM layout. 923 */ 924 #ifdef SYM_CONF_NVRAM_SUPPORT 925 static u_char Tekram_sync[16] = 926 {25,31,37,43, 50,62,75,125, 12,15,18,21, 6,7,9,10}; 927 #endif 928 929 /* 930 * Union of supported NVRAM formats. 931 */ 932 struct sym_nvram { 933 int type; 934 #define SYM_SYMBIOS_NVRAM (1) 935 #define SYM_TEKRAM_NVRAM (2) 936 #ifdef SYM_CONF_NVRAM_SUPPORT 937 union { 938 Symbios_nvram Symbios; 939 Tekram_nvram Tekram; 940 } data; 941 #endif 942 }; 943 944 /* 945 * This one is hopefully useless, but actually useful. :-) 946 */ 947 #ifndef assert 948 #define assert(expression) { \ 949 if (!(expression)) { \ 950 (void)panic( \ 951 "assertion \"%s\" failed: file \"%s\", line %d\n", \ 952 #expression, \ 953 __FILE__, __LINE__); \ 954 } \ 955 } 956 #endif 957 958 /* 959 * Some provision for a possible big endian mode supported by 960 * Symbios chips (never seen, by the way). 961 * For now, this stuff does not deserve any comments. :) 962 */ 963 964 #define sym_offb(o) (o) 965 #define sym_offw(o) (o) 966 967 /* 968 * Some provision for support for BIG ENDIAN CPU. 969 * Btw, FreeBSD does not seem to be ready yet for big endian. 970 */ 971 972 #if BYTE_ORDER == BIG_ENDIAN 973 #define cpu_to_scr(dw) _htole32(dw) 974 #define scr_to_cpu(dw) _le32toh(dw) 975 #else 976 #define cpu_to_scr(dw) (dw) 977 #define scr_to_cpu(dw) (dw) 978 #endif 979 980 /* 981 * Access to the chip IO registers and on-chip RAM. 982 * We use the `bus space' interface under FreeBSD-4 and 983 * later kernel versions. 984 */ 985 986 #ifdef FreeBSD_Bus_Space_Abstraction 987 988 #if defined(SYM_CONF_IOMAPPED) 989 990 #define INB_OFF(o) bus_space_read_1(np->io_tag, np->io_bsh, o) 991 #define INW_OFF(o) bus_space_read_2(np->io_tag, np->io_bsh, o) 992 #define INL_OFF(o) bus_space_read_4(np->io_tag, np->io_bsh, o) 993 994 #define OUTB_OFF(o, v) bus_space_write_1(np->io_tag, np->io_bsh, o, (v)) 995 #define OUTW_OFF(o, v) bus_space_write_2(np->io_tag, np->io_bsh, o, (v)) 996 #define OUTL_OFF(o, v) bus_space_write_4(np->io_tag, np->io_bsh, o, (v)) 997 998 #else /* Memory mapped IO */ 999 1000 #define INB_OFF(o) bus_space_read_1(np->mmio_tag, np->mmio_bsh, o) 1001 #define INW_OFF(o) bus_space_read_2(np->mmio_tag, np->mmio_bsh, o) 1002 #define INL_OFF(o) bus_space_read_4(np->mmio_tag, np->mmio_bsh, o) 1003 1004 #define OUTB_OFF(o, v) bus_space_write_1(np->mmio_tag, np->mmio_bsh, o, (v)) 1005 #define OUTW_OFF(o, v) bus_space_write_2(np->mmio_tag, np->mmio_bsh, o, (v)) 1006 #define OUTL_OFF(o, v) bus_space_write_4(np->mmio_tag, np->mmio_bsh, o, (v)) 1007 1008 #endif /* SYM_CONF_IOMAPPED */ 1009 1010 #define OUTRAM_OFF(o, a, l) \ 1011 bus_space_write_region_1(np->ram_tag, np->ram_bsh, o, (a), (l)) 1012 1013 #else /* not defined FreeBSD_Bus_Space_Abstraction */ 1014 1015 #if BYTE_ORDER == BIG_ENDIAN 1016 #error "BIG ENDIAN support requires bus space kernel interface" 1017 #endif 1018 1019 /* 1020 * Access to the chip IO registers and on-chip RAM. 1021 * We use legacy MMIO and IO interface for FreeBSD 3.X versions. 1022 */ 1023 1024 /* 1025 * Define some understable verbs for IO and MMIO. 1026 */ 1027 #define io_read8(p) scr_to_cpu(inb((p))) 1028 #define io_read16(p) scr_to_cpu(inw((p))) 1029 #define io_read32(p) scr_to_cpu(inl((p))) 1030 #define io_write8(p, v) outb((p), cpu_to_scr(v)) 1031 #define io_write16(p, v) outw((p), cpu_to_scr(v)) 1032 #define io_write32(p, v) outl((p), cpu_to_scr(v)) 1033 1034 #ifdef __alpha__ 1035 1036 #define mmio_read8(a) readb(a) 1037 #define mmio_read16(a) readw(a) 1038 #define mmio_read32(a) readl(a) 1039 #define mmio_write8(a, b) writeb(a, b) 1040 #define mmio_write16(a, b) writew(a, b) 1041 #define mmio_write32(a, b) writel(a, b) 1042 #define memcpy_to_pci(d, s, n) memcpy_toio((u32)(d), (void *)(s), (n)) 1043 1044 #else /*__i386__, __sparc64__*/ 1045 1046 #define mmio_read8(a) scr_to_cpu((*(volatile unsigned char *) (a))) 1047 #define mmio_read16(a) scr_to_cpu((*(volatile unsigned short *) (a))) 1048 #define mmio_read32(a) scr_to_cpu((*(volatile unsigned int *) (a))) 1049 #define mmio_write8(a, b) (*(volatile unsigned char *) (a)) = cpu_to_scr(b) 1050 #define mmio_write16(a, b) (*(volatile unsigned short *) (a)) = cpu_to_scr(b) 1051 #define mmio_write32(a, b) (*(volatile unsigned int *) (a)) = cpu_to_scr(b) 1052 #define memcpy_to_pci(d, s, n) bcopy((s), (void *)(d), (n)) 1053 1054 #endif 1055 1056 /* 1057 * Normal IO 1058 */ 1059 #if defined(SYM_CONF_IOMAPPED) 1060 1061 #define INB_OFF(o) io_read8(np->io_port + sym_offb(o)) 1062 #define OUTB_OFF(o, v) io_write8(np->io_port + sym_offb(o), (v)) 1063 1064 #define INW_OFF(o) io_read16(np->io_port + sym_offw(o)) 1065 #define OUTW_OFF(o, v) io_write16(np->io_port + sym_offw(o), (v)) 1066 1067 #define INL_OFF(o) io_read32(np->io_port + (o)) 1068 #define OUTL_OFF(o, v) io_write32(np->io_port + (o), (v)) 1069 1070 #else /* Memory mapped IO */ 1071 1072 #define INB_OFF(o) mmio_read8(np->mmio_va + sym_offb(o)) 1073 #define OUTB_OFF(o, v) mmio_write8(np->mmio_va + sym_offb(o), (v)) 1074 1075 #define INW_OFF(o) mmio_read16(np->mmio_va + sym_offw(o)) 1076 #define OUTW_OFF(o, v) mmio_write16(np->mmio_va + sym_offw(o), (v)) 1077 1078 #define INL_OFF(o) mmio_read32(np->mmio_va + (o)) 1079 #define OUTL_OFF(o, v) mmio_write32(np->mmio_va + (o), (v)) 1080 1081 #endif 1082 1083 #define OUTRAM_OFF(o, a, l) memcpy_to_pci(np->ram_va + (o), (a), (l)) 1084 1085 #endif /* FreeBSD_Bus_Space_Abstraction */ 1086 1087 /* 1088 * Common definitions for both bus space and legacy IO methods. 1089 */ 1090 #define INB(r) INB_OFF(offsetof(struct sym_reg,r)) 1091 #define INW(r) INW_OFF(offsetof(struct sym_reg,r)) 1092 #define INL(r) INL_OFF(offsetof(struct sym_reg,r)) 1093 1094 #define OUTB(r, v) OUTB_OFF(offsetof(struct sym_reg,r), (v)) 1095 #define OUTW(r, v) OUTW_OFF(offsetof(struct sym_reg,r), (v)) 1096 #define OUTL(r, v) OUTL_OFF(offsetof(struct sym_reg,r), (v)) 1097 1098 #define OUTONB(r, m) OUTB(r, INB(r) | (m)) 1099 #define OUTOFFB(r, m) OUTB(r, INB(r) & ~(m)) 1100 #define OUTONW(r, m) OUTW(r, INW(r) | (m)) 1101 #define OUTOFFW(r, m) OUTW(r, INW(r) & ~(m)) 1102 #define OUTONL(r, m) OUTL(r, INL(r) | (m)) 1103 #define OUTOFFL(r, m) OUTL(r, INL(r) & ~(m)) 1104 1105 /* 1106 * We normally want the chip to have a consistent view 1107 * of driver internal data structures when we restart it. 1108 * Thus these macros. 1109 */ 1110 #define OUTL_DSP(v) \ 1111 do { \ 1112 MEMORY_BARRIER(); \ 1113 OUTL (nc_dsp, (v)); \ 1114 } while (0) 1115 1116 #define OUTONB_STD() \ 1117 do { \ 1118 MEMORY_BARRIER(); \ 1119 OUTONB (nc_dcntl, (STD|NOCOM)); \ 1120 } while (0) 1121 1122 /* 1123 * Command control block states. 1124 */ 1125 #define HS_IDLE (0) 1126 #define HS_BUSY (1) 1127 #define HS_NEGOTIATE (2) /* sync/wide data transfer*/ 1128 #define HS_DISCONNECT (3) /* Disconnected by target */ 1129 #define HS_WAIT (4) /* waiting for resource */ 1130 1131 #define HS_DONEMASK (0x80) 1132 #define HS_COMPLETE (4|HS_DONEMASK) 1133 #define HS_SEL_TIMEOUT (5|HS_DONEMASK) /* Selection timeout */ 1134 #define HS_UNEXPECTED (6|HS_DONEMASK) /* Unexpected disconnect */ 1135 #define HS_COMP_ERR (7|HS_DONEMASK) /* Completed with error */ 1136 1137 /* 1138 * Software Interrupt Codes 1139 */ 1140 #define SIR_BAD_SCSI_STATUS (1) 1141 #define SIR_SEL_ATN_NO_MSG_OUT (2) 1142 #define SIR_MSG_RECEIVED (3) 1143 #define SIR_MSG_WEIRD (4) 1144 #define SIR_NEGO_FAILED (5) 1145 #define SIR_NEGO_PROTO (6) 1146 #define SIR_SCRIPT_STOPPED (7) 1147 #define SIR_REJECT_TO_SEND (8) 1148 #define SIR_SWIDE_OVERRUN (9) 1149 #define SIR_SODL_UNDERRUN (10) 1150 #define SIR_RESEL_NO_MSG_IN (11) 1151 #define SIR_RESEL_NO_IDENTIFY (12) 1152 #define SIR_RESEL_BAD_LUN (13) 1153 #define SIR_TARGET_SELECTED (14) 1154 #define SIR_RESEL_BAD_I_T_L (15) 1155 #define SIR_RESEL_BAD_I_T_L_Q (16) 1156 #define SIR_ABORT_SENT (17) 1157 #define SIR_RESEL_ABORTED (18) 1158 #define SIR_MSG_OUT_DONE (19) 1159 #define SIR_COMPLETE_ERROR (20) 1160 #define SIR_DATA_OVERRUN (21) 1161 #define SIR_BAD_PHASE (22) 1162 #define SIR_MAX (22) 1163 1164 /* 1165 * Extended error bit codes. 1166 * xerr_status field of struct sym_ccb. 1167 */ 1168 #define XE_EXTRA_DATA (1) /* unexpected data phase */ 1169 #define XE_BAD_PHASE (1<<1) /* illegal phase (4/5) */ 1170 #define XE_PARITY_ERR (1<<2) /* unrecovered SCSI parity error */ 1171 #define XE_SODL_UNRUN (1<<3) /* ODD transfer in DATA OUT phase */ 1172 #define XE_SWIDE_OVRUN (1<<4) /* ODD transfer in DATA IN phase */ 1173 1174 /* 1175 * Negotiation status. 1176 * nego_status field of struct sym_ccb. 1177 */ 1178 #define NS_SYNC (1) 1179 #define NS_WIDE (2) 1180 #define NS_PPR (3) 1181 1182 /* 1183 * A CCB hashed table is used to retrieve CCB address 1184 * from DSA value. 1185 */ 1186 #define CCB_HASH_SHIFT 8 1187 #define CCB_HASH_SIZE (1UL << CCB_HASH_SHIFT) 1188 #define CCB_HASH_MASK (CCB_HASH_SIZE-1) 1189 #define CCB_HASH_CODE(dsa) (((dsa) >> 9) & CCB_HASH_MASK) 1190 1191 /* 1192 * Device flags. 1193 */ 1194 #define SYM_DISC_ENABLED (1) 1195 #define SYM_TAGS_ENABLED (1<<1) 1196 #define SYM_SCAN_BOOT_DISABLED (1<<2) 1197 #define SYM_SCAN_LUNS_DISABLED (1<<3) 1198 1199 /* 1200 * Host adapter miscellaneous flags. 1201 */ 1202 #define SYM_AVOID_BUS_RESET (1) 1203 #define SYM_SCAN_TARGETS_HILO (1<<1) 1204 1205 /* 1206 * Device quirks. 1207 * Some devices, for example the CHEETAH 2 LVD, disconnects without 1208 * saving the DATA POINTER then reselects and terminates the IO. 1209 * On reselection, the automatic RESTORE DATA POINTER makes the 1210 * CURRENT DATA POINTER not point at the end of the IO. 1211 * This behaviour just breaks our calculation of the residual. 1212 * For now, we just force an AUTO SAVE on disconnection and will 1213 * fix that in a further driver version. 1214 */ 1215 #define SYM_QUIRK_AUTOSAVE 1 1216 1217 /* 1218 * Misc. 1219 */ 1220 #define SYM_SNOOP_TIMEOUT (10000000) 1221 #define SYM_PCI_IO PCIR_MAPS 1222 #define SYM_PCI_MMIO (PCIR_MAPS + 4) 1223 #define SYM_PCI_RAM (PCIR_MAPS + 8) 1224 #define SYM_PCI_RAM64 (PCIR_MAPS + 12) 1225 1226 /* 1227 * Back-pointer from the CAM CCB to our data structures. 1228 */ 1229 #define sym_hcb_ptr spriv_ptr0 1230 /* #define sym_ccb_ptr spriv_ptr1 */ 1231 1232 /* 1233 * We mostly have to deal with pointers. 1234 * Thus these typedef's. 1235 */ 1236 typedef struct sym_tcb *tcb_p; 1237 typedef struct sym_lcb *lcb_p; 1238 typedef struct sym_ccb *ccb_p; 1239 typedef struct sym_hcb *hcb_p; 1240 1241 /* 1242 * Gather negotiable parameters value 1243 */ 1244 struct sym_trans { 1245 #ifdef FreeBSD_New_Tran_Settings 1246 u8 scsi_version; 1247 u8 spi_version; 1248 #endif 1249 u8 period; 1250 u8 offset; 1251 u8 width; 1252 u8 options; /* PPR options */ 1253 }; 1254 1255 struct sym_tinfo { 1256 struct sym_trans current; 1257 struct sym_trans goal; 1258 struct sym_trans user; 1259 }; 1260 1261 #define BUS_8_BIT MSG_EXT_WDTR_BUS_8_BIT 1262 #define BUS_16_BIT MSG_EXT_WDTR_BUS_16_BIT 1263 1264 /* 1265 * Global TCB HEADER. 1266 * 1267 * Due to lack of indirect addressing on earlier NCR chips, 1268 * this substructure is copied from the TCB to a global 1269 * address after selection. 1270 * For SYMBIOS chips that support LOAD/STORE this copy is 1271 * not needed and thus not performed. 1272 */ 1273 struct sym_tcbh { 1274 /* 1275 * Scripts bus addresses of LUN table accessed from scripts. 1276 * LUN #0 is a special case, since multi-lun devices are rare, 1277 * and we we want to speed-up the general case and not waste 1278 * resources. 1279 */ 1280 u32 luntbl_sa; /* bus address of this table */ 1281 u32 lun0_sa; /* bus address of LCB #0 */ 1282 /* 1283 * Actual SYNC/WIDE IO registers value for this target. 1284 * 'sval', 'wval' and 'uval' are read from SCRIPTS and 1285 * so have alignment constraints. 1286 */ 1287 /*0*/ u_char uval; /* -> SCNTL4 register */ 1288 /*1*/ u_char sval; /* -> SXFER io register */ 1289 /*2*/ u_char filler1; 1290 /*3*/ u_char wval; /* -> SCNTL3 io register */ 1291 }; 1292 1293 /* 1294 * Target Control Block 1295 */ 1296 struct sym_tcb { 1297 /* 1298 * TCB header. 1299 * Assumed at offset 0. 1300 */ 1301 /*0*/ struct sym_tcbh head; 1302 1303 /* 1304 * LUN table used by the SCRIPTS processor. 1305 * An array of bus addresses is used on reselection. 1306 */ 1307 u32 *luntbl; /* LCBs bus address table */ 1308 1309 /* 1310 * LUN table used by the C code. 1311 */ 1312 lcb_p lun0p; /* LCB of LUN #0 (usual case) */ 1313 #if SYM_CONF_MAX_LUN > 1 1314 lcb_p *lunmp; /* Other LCBs [1..MAX_LUN] */ 1315 #endif 1316 1317 /* 1318 * Bitmap that tells about LUNs that succeeded at least 1319 * 1 IO and therefore assumed to be a real device. 1320 * Avoid useless allocation of the LCB structure. 1321 */ 1322 u32 lun_map[(SYM_CONF_MAX_LUN+31)/32]; 1323 1324 /* 1325 * Bitmap that tells about LUNs that haven't yet an LCB 1326 * allocated (not discovered or LCB allocation failed). 1327 */ 1328 u32 busy0_map[(SYM_CONF_MAX_LUN+31)/32]; 1329 1330 /* 1331 * Transfer capabilities (SIP) 1332 */ 1333 struct sym_tinfo tinfo; 1334 1335 /* 1336 * Keep track of the CCB used for the negotiation in order 1337 * to ensure that only 1 negotiation is queued at a time. 1338 */ 1339 ccb_p nego_cp; /* CCB used for the nego */ 1340 1341 /* 1342 * Set when we want to reset the device. 1343 */ 1344 u_char to_reset; 1345 1346 /* 1347 * Other user settable limits and options. 1348 * These limits are read from the NVRAM if present. 1349 */ 1350 u_char usrflags; 1351 u_short usrtags; 1352 }; 1353 1354 /* 1355 * Global LCB HEADER. 1356 * 1357 * Due to lack of indirect addressing on earlier NCR chips, 1358 * this substructure is copied from the LCB to a global 1359 * address after selection. 1360 * For SYMBIOS chips that support LOAD/STORE this copy is 1361 * not needed and thus not performed. 1362 */ 1363 struct sym_lcbh { 1364 /* 1365 * SCRIPTS address jumped by SCRIPTS on reselection. 1366 * For not probed logical units, this address points to 1367 * SCRIPTS that deal with bad LU handling (must be at 1368 * offset zero of the LCB for that reason). 1369 */ 1370 /*0*/ u32 resel_sa; 1371 1372 /* 1373 * Task (bus address of a CCB) read from SCRIPTS that points 1374 * to the unique ITL nexus allowed to be disconnected. 1375 */ 1376 u32 itl_task_sa; 1377 1378 /* 1379 * Task table bus address (read from SCRIPTS). 1380 */ 1381 u32 itlq_tbl_sa; 1382 }; 1383 1384 /* 1385 * Logical Unit Control Block 1386 */ 1387 struct sym_lcb { 1388 /* 1389 * TCB header. 1390 * Assumed at offset 0. 1391 */ 1392 /*0*/ struct sym_lcbh head; 1393 1394 /* 1395 * Task table read from SCRIPTS that contains pointers to 1396 * ITLQ nexuses. The bus address read from SCRIPTS is 1397 * inside the header. 1398 */ 1399 u32 *itlq_tbl; /* Kernel virtual address */ 1400 1401 /* 1402 * Busy CCBs management. 1403 */ 1404 u_short busy_itlq; /* Number of busy tagged CCBs */ 1405 u_short busy_itl; /* Number of busy untagged CCBs */ 1406 1407 /* 1408 * Circular tag allocation buffer. 1409 */ 1410 u_short ia_tag; /* Tag allocation index */ 1411 u_short if_tag; /* Tag release index */ 1412 u_char *cb_tags; /* Circular tags buffer */ 1413 1414 /* 1415 * Set when we want to clear all tasks. 1416 */ 1417 u_char to_clear; 1418 1419 /* 1420 * Capabilities. 1421 */ 1422 u_char user_flags; 1423 u_char current_flags; 1424 }; 1425 1426 /* 1427 * Action from SCRIPTS on a task. 1428 * Is part of the CCB, but is also used separately to plug 1429 * error handling action to perform from SCRIPTS. 1430 */ 1431 struct sym_actscr { 1432 u32 start; /* Jumped by SCRIPTS after selection */ 1433 u32 restart; /* Jumped by SCRIPTS on relection */ 1434 }; 1435 1436 /* 1437 * Phase mismatch context. 1438 * 1439 * It is part of the CCB and is used as parameters for the 1440 * DATA pointer. We need two contexts to handle correctly the 1441 * SAVED DATA POINTER. 1442 */ 1443 struct sym_pmc { 1444 struct sym_tblmove sg; /* Updated interrupted SG block */ 1445 u32 ret; /* SCRIPT return address */ 1446 }; 1447 1448 /* 1449 * LUN control block lookup. 1450 * We use a direct pointer for LUN #0, and a table of 1451 * pointers which is only allocated for devices that support 1452 * LUN(s) > 0. 1453 */ 1454 #if SYM_CONF_MAX_LUN <= 1 1455 #define sym_lp(np, tp, lun) (!lun) ? (tp)->lun0p : 0 1456 #else 1457 #define sym_lp(np, tp, lun) \ 1458 (!lun) ? (tp)->lun0p : (tp)->lunmp ? (tp)->lunmp[(lun)] : 0 1459 #endif 1460 1461 /* 1462 * Status are used by the host and the script processor. 1463 * 1464 * The last four bytes (status[4]) are copied to the 1465 * scratchb register (declared as scr0..scr3) just after the 1466 * select/reselect, and copied back just after disconnecting. 1467 * Inside the script the XX_REG are used. 1468 */ 1469 1470 /* 1471 * Last four bytes (script) 1472 */ 1473 #define QU_REG scr0 1474 #define HS_REG scr1 1475 #define HS_PRT nc_scr1 1476 #define SS_REG scr2 1477 #define SS_PRT nc_scr2 1478 #define HF_REG scr3 1479 #define HF_PRT nc_scr3 1480 1481 /* 1482 * Last four bytes (host) 1483 */ 1484 #define actualquirks phys.head.status[0] 1485 #define host_status phys.head.status[1] 1486 #define ssss_status phys.head.status[2] 1487 #define host_flags phys.head.status[3] 1488 1489 /* 1490 * Host flags 1491 */ 1492 #define HF_IN_PM0 1u 1493 #define HF_IN_PM1 (1u<<1) 1494 #define HF_ACT_PM (1u<<2) 1495 #define HF_DP_SAVED (1u<<3) 1496 #define HF_SENSE (1u<<4) 1497 #define HF_EXT_ERR (1u<<5) 1498 #define HF_DATA_IN (1u<<6) 1499 #ifdef SYM_CONF_IARB_SUPPORT 1500 #define HF_HINT_IARB (1u<<7) 1501 #endif 1502 1503 /* 1504 * Global CCB HEADER. 1505 * 1506 * Due to lack of indirect addressing on earlier NCR chips, 1507 * this substructure is copied from the ccb to a global 1508 * address after selection (or reselection) and copied back 1509 * before disconnect. 1510 * For SYMBIOS chips that support LOAD/STORE this copy is 1511 * not needed and thus not performed. 1512 */ 1513 1514 struct sym_ccbh { 1515 /* 1516 * Start and restart SCRIPTS addresses (must be at 0). 1517 */ 1518 /*0*/ struct sym_actscr go; 1519 1520 /* 1521 * SCRIPTS jump address that deal with data pointers. 1522 * 'savep' points to the position in the script responsible 1523 * for the actual transfer of data. 1524 * It's written on reception of a SAVE_DATA_POINTER message. 1525 */ 1526 u32 savep; /* Jump address to saved data pointer */ 1527 u32 lastp; /* SCRIPTS address at end of data */ 1528 u32 goalp; /* Not accessed for now from SCRIPTS */ 1529 1530 /* 1531 * Status fields. 1532 */ 1533 u8 status[4]; 1534 }; 1535 1536 /* 1537 * Data Structure Block 1538 * 1539 * During execution of a ccb by the script processor, the 1540 * DSA (data structure address) register points to this 1541 * substructure of the ccb. 1542 */ 1543 struct sym_dsb { 1544 /* 1545 * CCB header. 1546 * Also assumed at offset 0 of the sym_ccb structure. 1547 */ 1548 /*0*/ struct sym_ccbh head; 1549 1550 /* 1551 * Phase mismatch contexts. 1552 * We need two to handle correctly the SAVED DATA POINTER. 1553 * MUST BOTH BE AT OFFSET < 256, due to using 8 bit arithmetic 1554 * for address calculation from SCRIPTS. 1555 */ 1556 struct sym_pmc pm0; 1557 struct sym_pmc pm1; 1558 1559 /* 1560 * Table data for Script 1561 */ 1562 struct sym_tblsel select; 1563 struct sym_tblmove smsg; 1564 struct sym_tblmove smsg_ext; 1565 struct sym_tblmove cmd; 1566 struct sym_tblmove sense; 1567 struct sym_tblmove wresid; 1568 struct sym_tblmove data [SYM_CONF_MAX_SG]; 1569 }; 1570 1571 /* 1572 * Our Command Control Block 1573 */ 1574 struct sym_ccb { 1575 /* 1576 * This is the data structure which is pointed by the DSA 1577 * register when it is executed by the script processor. 1578 * It must be the first entry. 1579 */ 1580 struct sym_dsb phys; 1581 1582 /* 1583 * Pointer to CAM ccb and related stuff. 1584 */ 1585 union ccb *cam_ccb; /* CAM scsiio ccb */ 1586 u8 cdb_buf[16]; /* Copy of CDB */ 1587 u8 *sns_bbuf; /* Bounce buffer for sense data */ 1588 #define SYM_SNS_BBUF_LEN sizeof(struct scsi_sense_data) 1589 int data_len; /* Total data length */ 1590 int segments; /* Number of SG segments */ 1591 1592 /* 1593 * Miscellaneous status'. 1594 */ 1595 u_char nego_status; /* Negotiation status */ 1596 u_char xerr_status; /* Extended error flags */ 1597 u32 extra_bytes; /* Extraneous bytes transferred */ 1598 1599 /* 1600 * Message areas. 1601 * We prepare a message to be sent after selection. 1602 * We may use a second one if the command is rescheduled 1603 * due to CHECK_CONDITION or COMMAND TERMINATED. 1604 * Contents are IDENTIFY and SIMPLE_TAG. 1605 * While negotiating sync or wide transfer, 1606 * a SDTR or WDTR message is appended. 1607 */ 1608 u_char scsi_smsg [12]; 1609 u_char scsi_smsg2[12]; 1610 1611 /* 1612 * Auto request sense related fields. 1613 */ 1614 u_char sensecmd[6]; /* Request Sense command */ 1615 u_char sv_scsi_status; /* Saved SCSI status */ 1616 u_char sv_xerr_status; /* Saved extended status */ 1617 int sv_resid; /* Saved residual */ 1618 1619 /* 1620 * Map for the DMA of user data. 1621 */ 1622 #ifdef FreeBSD_Bus_Dma_Abstraction 1623 void *arg; /* Argument for some callback */ 1624 bus_dmamap_t dmamap; /* DMA map for user data */ 1625 u_char dmamapped; 1626 #define SYM_DMA_NONE 0 1627 #define SYM_DMA_READ 1 1628 #define SYM_DMA_WRITE 2 1629 #endif 1630 /* 1631 * Other fields. 1632 */ 1633 u32 ccb_ba; /* BUS address of this CCB */ 1634 u_short tag; /* Tag for this transfer */ 1635 /* NO_TAG means no tag */ 1636 u_char target; 1637 u_char lun; 1638 ccb_p link_ccbh; /* Host adapter CCB hash chain */ 1639 SYM_QUEHEAD 1640 link_ccbq; /* Link to free/busy CCB queue */ 1641 u32 startp; /* Initial data pointer */ 1642 int ext_sg; /* Extreme data pointer, used */ 1643 int ext_ofs; /* to calculate the residual. */ 1644 u_char to_abort; /* Want this IO to be aborted */ 1645 }; 1646 1647 #define CCB_BA(cp,lbl) (cp->ccb_ba + offsetof(struct sym_ccb, lbl)) 1648 1649 /* 1650 * Host Control Block 1651 */ 1652 struct sym_hcb { 1653 /* 1654 * Global headers. 1655 * Due to poorness of addressing capabilities, earlier 1656 * chips (810, 815, 825) copy part of the data structures 1657 * (CCB, TCB and LCB) in fixed areas. 1658 */ 1659 #ifdef SYM_CONF_GENERIC_SUPPORT 1660 struct sym_ccbh ccb_head; 1661 struct sym_tcbh tcb_head; 1662 struct sym_lcbh lcb_head; 1663 #endif 1664 /* 1665 * Idle task and invalid task actions and 1666 * their bus addresses. 1667 */ 1668 struct sym_actscr idletask, notask, bad_itl, bad_itlq; 1669 vm_offset_t idletask_ba, notask_ba, bad_itl_ba, bad_itlq_ba; 1670 1671 /* 1672 * Dummy lun table to protect us against target 1673 * returning bad lun number on reselection. 1674 */ 1675 u32 *badluntbl; /* Table physical address */ 1676 u32 badlun_sa; /* SCRIPT handler BUS address */ 1677 1678 /* 1679 * Bus address of this host control block. 1680 */ 1681 u32 hcb_ba; 1682 1683 /* 1684 * Bit 32-63 of the on-chip RAM bus address in LE format. 1685 * The START_RAM64 script loads the MMRS and MMWS from this 1686 * field. 1687 */ 1688 u32 scr_ram_seg; 1689 1690 /* 1691 * Chip and controller indentification. 1692 */ 1693 #ifdef FreeBSD_Bus_Io_Abstraction 1694 device_t device; 1695 #else 1696 pcici_t pci_tag; 1697 #endif 1698 int unit; 1699 char inst_name[8]; 1700 1701 /* 1702 * Initial value of some IO register bits. 1703 * These values are assumed to have been set by BIOS, and may 1704 * be used to probe adapter implementation differences. 1705 */ 1706 u_char sv_scntl0, sv_scntl3, sv_dmode, sv_dcntl, sv_ctest3, sv_ctest4, 1707 sv_ctest5, sv_gpcntl, sv_stest2, sv_stest4, sv_scntl4, 1708 sv_stest1; 1709 1710 /* 1711 * Actual initial value of IO register bits used by the 1712 * driver. They are loaded at initialisation according to 1713 * features that are to be enabled/disabled. 1714 */ 1715 u_char rv_scntl0, rv_scntl3, rv_dmode, rv_dcntl, rv_ctest3, rv_ctest4, 1716 rv_ctest5, rv_stest2, rv_ccntl0, rv_ccntl1, rv_scntl4; 1717 1718 /* 1719 * Target data. 1720 */ 1721 struct sym_tcb target[SYM_CONF_MAX_TARGET]; 1722 1723 /* 1724 * Target control block bus address array used by the SCRIPT 1725 * on reselection. 1726 */ 1727 u32 *targtbl; 1728 u32 targtbl_ba; 1729 1730 /* 1731 * CAM SIM information for this instance. 1732 */ 1733 struct cam_sim *sim; 1734 struct cam_path *path; 1735 1736 /* 1737 * Allocated hardware resources. 1738 */ 1739 #ifdef FreeBSD_Bus_Io_Abstraction 1740 struct resource *irq_res; 1741 struct resource *io_res; 1742 struct resource *mmio_res; 1743 struct resource *ram_res; 1744 int ram_id; 1745 void *intr; 1746 #endif 1747 1748 /* 1749 * Bus stuff. 1750 * 1751 * My understanding of PCI is that all agents must share the 1752 * same addressing range and model. 1753 * But some hardware architecture guys provide complex and 1754 * brain-deaded stuff that makes shit. 1755 * This driver only support PCI compliant implementations and 1756 * deals with part of the BUS stuff complexity only to fit O/S 1757 * requirements. 1758 */ 1759 #ifdef FreeBSD_Bus_Io_Abstraction 1760 bus_space_handle_t io_bsh; 1761 bus_space_tag_t io_tag; 1762 bus_space_handle_t mmio_bsh; 1763 bus_space_tag_t mmio_tag; 1764 bus_space_handle_t ram_bsh; 1765 bus_space_tag_t ram_tag; 1766 #endif 1767 1768 /* 1769 * DMA stuff. 1770 */ 1771 #ifdef FreeBSD_Bus_Dma_Abstraction 1772 bus_dma_tag_t bus_dmat; /* DMA tag from parent BUS */ 1773 bus_dma_tag_t data_dmat; /* DMA tag for user data */ 1774 #endif 1775 /* 1776 * Virtual and physical bus addresses of the chip. 1777 */ 1778 vm_offset_t mmio_va; /* MMIO kernel virtual address */ 1779 vm_offset_t mmio_pa; /* MMIO CPU physical address */ 1780 vm_offset_t mmio_ba; /* MMIO BUS address */ 1781 int mmio_ws; /* MMIO Window size */ 1782 1783 vm_offset_t ram_va; /* RAM kernel virtual address */ 1784 vm_offset_t ram_pa; /* RAM CPU physical address */ 1785 vm_offset_t ram_ba; /* RAM BUS address */ 1786 int ram_ws; /* RAM window size */ 1787 u32 io_port; /* IO port address */ 1788 1789 /* 1790 * SCRIPTS virtual and physical bus addresses. 1791 * 'script' is loaded in the on-chip RAM if present. 1792 * 'scripth' stays in main memory for all chips except the 1793 * 53C895A, 53C896 and 53C1010 that provide 8K on-chip RAM. 1794 */ 1795 u_char *scripta0; /* Copies of script and scripth */ 1796 u_char *scriptb0; /* Copies of script and scripth */ 1797 vm_offset_t scripta_ba; /* Actual script and scripth */ 1798 vm_offset_t scriptb_ba; /* bus addresses. */ 1799 vm_offset_t scriptb0_ba; 1800 u_short scripta_sz; /* Actual size of script A */ 1801 u_short scriptb_sz; /* Actual size of script B */ 1802 1803 /* 1804 * Bus addresses, setup and patch methods for 1805 * the selected firmware. 1806 */ 1807 struct sym_fwa_ba fwa_bas; /* Useful SCRIPTA bus addresses */ 1808 struct sym_fwb_ba fwb_bas; /* Useful SCRIPTB bus addresses */ 1809 void (*fw_setup)(hcb_p np, struct sym_fw *fw); 1810 void (*fw_patch)(hcb_p np); 1811 char *fw_name; 1812 1813 /* 1814 * General controller parameters and configuration. 1815 */ 1816 u_short device_id; /* PCI device id */ 1817 u_char revision_id; /* PCI device revision id */ 1818 u_int features; /* Chip features map */ 1819 u_char myaddr; /* SCSI id of the adapter */ 1820 u_char maxburst; /* log base 2 of dwords burst */ 1821 u_char maxwide; /* Maximum transfer width */ 1822 u_char minsync; /* Min sync period factor (ST) */ 1823 u_char maxsync; /* Max sync period factor (ST) */ 1824 u_char maxoffs; /* Max scsi offset (ST) */ 1825 u_char minsync_dt; /* Min sync period factor (DT) */ 1826 u_char maxsync_dt; /* Max sync period factor (DT) */ 1827 u_char maxoffs_dt; /* Max scsi offset (DT) */ 1828 u_char multiplier; /* Clock multiplier (1,2,4) */ 1829 u_char clock_divn; /* Number of clock divisors */ 1830 u32 clock_khz; /* SCSI clock frequency in KHz */ 1831 u32 pciclk_khz; /* Estimated PCI clock in KHz */ 1832 /* 1833 * Start queue management. 1834 * It is filled up by the host processor and accessed by the 1835 * SCRIPTS processor in order to start SCSI commands. 1836 */ 1837 volatile /* Prevent code optimizations */ 1838 u32 *squeue; /* Start queue virtual address */ 1839 u32 squeue_ba; /* Start queue BUS address */ 1840 u_short squeueput; /* Next free slot of the queue */ 1841 u_short actccbs; /* Number of allocated CCBs */ 1842 1843 /* 1844 * Command completion queue. 1845 * It is the same size as the start queue to avoid overflow. 1846 */ 1847 u_short dqueueget; /* Next position to scan */ 1848 volatile /* Prevent code optimizations */ 1849 u32 *dqueue; /* Completion (done) queue */ 1850 u32 dqueue_ba; /* Done queue BUS address */ 1851 1852 /* 1853 * Miscellaneous buffers accessed by the scripts-processor. 1854 * They shall be DWORD aligned, because they may be read or 1855 * written with a script command. 1856 */ 1857 u_char msgout[8]; /* Buffer for MESSAGE OUT */ 1858 u_char msgin [8]; /* Buffer for MESSAGE IN */ 1859 u32 lastmsg; /* Last SCSI message sent */ 1860 u_char scratch; /* Scratch for SCSI receive */ 1861 1862 /* 1863 * Miscellaneous configuration and status parameters. 1864 */ 1865 u_char usrflags; /* Miscellaneous user flags */ 1866 u_char scsi_mode; /* Current SCSI BUS mode */ 1867 u_char verbose; /* Verbosity for this controller*/ 1868 u32 cache; /* Used for cache test at init. */ 1869 1870 /* 1871 * CCB lists and queue. 1872 */ 1873 ccb_p ccbh[CCB_HASH_SIZE]; /* CCB hashed by DSA value */ 1874 SYM_QUEHEAD free_ccbq; /* Queue of available CCBs */ 1875 SYM_QUEHEAD busy_ccbq; /* Queue of busy CCBs */ 1876 1877 /* 1878 * During error handling and/or recovery, 1879 * active CCBs that are to be completed with 1880 * error or requeued are moved from the busy_ccbq 1881 * to the comp_ccbq prior to completion. 1882 */ 1883 SYM_QUEHEAD comp_ccbq; 1884 1885 /* 1886 * CAM CCB pending queue. 1887 */ 1888 SYM_QUEHEAD cam_ccbq; 1889 1890 /* 1891 * IMMEDIATE ARBITRATION (IARB) control. 1892 * 1893 * We keep track in 'last_cp' of the last CCB that has been 1894 * queued to the SCRIPTS processor and clear 'last_cp' when 1895 * this CCB completes. If last_cp is not zero at the moment 1896 * we queue a new CCB, we set a flag in 'last_cp' that is 1897 * used by the SCRIPTS as a hint for setting IARB. 1898 * We donnot set more than 'iarb_max' consecutive hints for 1899 * IARB in order to leave devices a chance to reselect. 1900 * By the way, any non zero value of 'iarb_max' is unfair. :) 1901 */ 1902 #ifdef SYM_CONF_IARB_SUPPORT 1903 u_short iarb_max; /* Max. # consecutive IARB hints*/ 1904 u_short iarb_count; /* Actual # of these hints */ 1905 ccb_p last_cp; 1906 #endif 1907 1908 /* 1909 * Command abort handling. 1910 * We need to synchronize tightly with the SCRIPTS 1911 * processor in order to handle things correctly. 1912 */ 1913 u_char abrt_msg[4]; /* Message to send buffer */ 1914 struct sym_tblmove abrt_tbl; /* Table for the MOV of it */ 1915 struct sym_tblsel abrt_sel; /* Sync params for selection */ 1916 u_char istat_sem; /* Tells the chip to stop (SEM) */ 1917 }; 1918 1919 #define HCB_BA(np, lbl) (np->hcb_ba + offsetof(struct sym_hcb, lbl)) 1920 1921 /* 1922 * Return the name of the controller. 1923 */ 1924 static __inline char *sym_name(hcb_p np) 1925 { 1926 return np->inst_name; 1927 } 1928 1929 /*--------------------------------------------------------------------------*/ 1930 /*------------------------------ FIRMWARES ---------------------------------*/ 1931 /*--------------------------------------------------------------------------*/ 1932 1933 /* 1934 * This stuff will be moved to a separate source file when 1935 * the driver will be broken into several source modules. 1936 */ 1937 1938 /* 1939 * Macros used for all firmwares. 1940 */ 1941 #define SYM_GEN_A(s, label) ((short) offsetof(s, label)), 1942 #define SYM_GEN_B(s, label) ((short) offsetof(s, label)), 1943 #define PADDR_A(label) SYM_GEN_PADDR_A(struct SYM_FWA_SCR, label) 1944 #define PADDR_B(label) SYM_GEN_PADDR_B(struct SYM_FWB_SCR, label) 1945 1946 1947 #ifdef SYM_CONF_GENERIC_SUPPORT 1948 /* 1949 * Allocate firmware #1 script area. 1950 */ 1951 #define SYM_FWA_SCR sym_fw1a_scr 1952 #define SYM_FWB_SCR sym_fw1b_scr 1953 #include <dev/sym/sym_fw1.h> 1954 struct sym_fwa_ofs sym_fw1a_ofs = { 1955 SYM_GEN_FW_A(struct SYM_FWA_SCR) 1956 }; 1957 struct sym_fwb_ofs sym_fw1b_ofs = { 1958 SYM_GEN_FW_B(struct SYM_FWB_SCR) 1959 }; 1960 #undef SYM_FWA_SCR 1961 #undef SYM_FWB_SCR 1962 #endif /* SYM_CONF_GENERIC_SUPPORT */ 1963 1964 /* 1965 * Allocate firmware #2 script area. 1966 */ 1967 #define SYM_FWA_SCR sym_fw2a_scr 1968 #define SYM_FWB_SCR sym_fw2b_scr 1969 #include <dev/sym/sym_fw2.h> 1970 struct sym_fwa_ofs sym_fw2a_ofs = { 1971 SYM_GEN_FW_A(struct SYM_FWA_SCR) 1972 }; 1973 struct sym_fwb_ofs sym_fw2b_ofs = { 1974 SYM_GEN_FW_B(struct SYM_FWB_SCR) 1975 SYM_GEN_B(struct SYM_FWB_SCR, start64) 1976 SYM_GEN_B(struct SYM_FWB_SCR, pm_handle) 1977 }; 1978 #undef SYM_FWA_SCR 1979 #undef SYM_FWB_SCR 1980 1981 #undef SYM_GEN_A 1982 #undef SYM_GEN_B 1983 #undef PADDR_A 1984 #undef PADDR_B 1985 1986 #ifdef SYM_CONF_GENERIC_SUPPORT 1987 /* 1988 * Patch routine for firmware #1. 1989 */ 1990 static void 1991 sym_fw1_patch(hcb_p np) 1992 { 1993 struct sym_fw1a_scr *scripta0; 1994 struct sym_fw1b_scr *scriptb0; 1995 1996 scripta0 = (struct sym_fw1a_scr *) np->scripta0; 1997 scriptb0 = (struct sym_fw1b_scr *) np->scriptb0; 1998 1999 /* 2000 * Remove LED support if not needed. 2001 */ 2002 if (!(np->features & FE_LED0)) { 2003 scripta0->idle[0] = cpu_to_scr(SCR_NO_OP); 2004 scripta0->reselected[0] = cpu_to_scr(SCR_NO_OP); 2005 scripta0->start[0] = cpu_to_scr(SCR_NO_OP); 2006 } 2007 2008 #ifdef SYM_CONF_IARB_SUPPORT 2009 /* 2010 * If user does not want to use IMMEDIATE ARBITRATION 2011 * when we are reselected while attempting to arbitrate, 2012 * patch the SCRIPTS accordingly with a SCRIPT NO_OP. 2013 */ 2014 if (!SYM_CONF_SET_IARB_ON_ARB_LOST) 2015 scripta0->ungetjob[0] = cpu_to_scr(SCR_NO_OP); 2016 #endif 2017 /* 2018 * Patch some data in SCRIPTS. 2019 * - start and done queue initial bus address. 2020 * - target bus address table bus address. 2021 */ 2022 scriptb0->startpos[0] = cpu_to_scr(np->squeue_ba); 2023 scriptb0->done_pos[0] = cpu_to_scr(np->dqueue_ba); 2024 scriptb0->targtbl[0] = cpu_to_scr(np->targtbl_ba); 2025 } 2026 #endif /* SYM_CONF_GENERIC_SUPPORT */ 2027 2028 /* 2029 * Patch routine for firmware #2. 2030 */ 2031 static void 2032 sym_fw2_patch(hcb_p np) 2033 { 2034 struct sym_fw2a_scr *scripta0; 2035 struct sym_fw2b_scr *scriptb0; 2036 2037 scripta0 = (struct sym_fw2a_scr *) np->scripta0; 2038 scriptb0 = (struct sym_fw2b_scr *) np->scriptb0; 2039 2040 /* 2041 * Remove LED support if not needed. 2042 */ 2043 if (!(np->features & FE_LED0)) { 2044 scripta0->idle[0] = cpu_to_scr(SCR_NO_OP); 2045 scripta0->reselected[0] = cpu_to_scr(SCR_NO_OP); 2046 scripta0->start[0] = cpu_to_scr(SCR_NO_OP); 2047 } 2048 2049 #ifdef SYM_CONF_IARB_SUPPORT 2050 /* 2051 * If user does not want to use IMMEDIATE ARBITRATION 2052 * when we are reselected while attempting to arbitrate, 2053 * patch the SCRIPTS accordingly with a SCRIPT NO_OP. 2054 */ 2055 if (!SYM_CONF_SET_IARB_ON_ARB_LOST) 2056 scripta0->ungetjob[0] = cpu_to_scr(SCR_NO_OP); 2057 #endif 2058 /* 2059 * Patch some variable in SCRIPTS. 2060 * - start and done queue initial bus address. 2061 * - target bus address table bus address. 2062 */ 2063 scriptb0->startpos[0] = cpu_to_scr(np->squeue_ba); 2064 scriptb0->done_pos[0] = cpu_to_scr(np->dqueue_ba); 2065 scriptb0->targtbl[0] = cpu_to_scr(np->targtbl_ba); 2066 2067 /* 2068 * Remove the load of SCNTL4 on reselection if not a C10. 2069 */ 2070 if (!(np->features & FE_C10)) { 2071 scripta0->resel_scntl4[0] = cpu_to_scr(SCR_NO_OP); 2072 scripta0->resel_scntl4[1] = cpu_to_scr(0); 2073 } 2074 2075 /* 2076 * Remove a couple of work-arounds specific to C1010 if 2077 * they are not desirable. See `sym_fw2.h' for more details. 2078 */ 2079 if (!(np->device_id == PCI_ID_LSI53C1010_2 && 2080 np->revision_id < 0x1 && 2081 np->pciclk_khz < 60000)) { 2082 scripta0->datao_phase[0] = cpu_to_scr(SCR_NO_OP); 2083 scripta0->datao_phase[1] = cpu_to_scr(0); 2084 } 2085 if (!(np->device_id == PCI_ID_LSI53C1010 && 2086 /* np->revision_id < 0xff */ 1)) { 2087 scripta0->sel_done[0] = cpu_to_scr(SCR_NO_OP); 2088 scripta0->sel_done[1] = cpu_to_scr(0); 2089 } 2090 2091 /* 2092 * Patch some other variables in SCRIPTS. 2093 * These ones are loaded by the SCRIPTS processor. 2094 */ 2095 scriptb0->pm0_data_addr[0] = 2096 cpu_to_scr(np->scripta_ba + 2097 offsetof(struct sym_fw2a_scr, pm0_data)); 2098 scriptb0->pm1_data_addr[0] = 2099 cpu_to_scr(np->scripta_ba + 2100 offsetof(struct sym_fw2a_scr, pm1_data)); 2101 } 2102 2103 /* 2104 * Fill the data area in scripts. 2105 * To be done for all firmwares. 2106 */ 2107 static void 2108 sym_fw_fill_data (u32 *in, u32 *out) 2109 { 2110 int i; 2111 2112 for (i = 0; i < SYM_CONF_MAX_SG; i++) { 2113 *in++ = SCR_CHMOV_TBL ^ SCR_DATA_IN; 2114 *in++ = offsetof (struct sym_dsb, data[i]); 2115 *out++ = SCR_CHMOV_TBL ^ SCR_DATA_OUT; 2116 *out++ = offsetof (struct sym_dsb, data[i]); 2117 } 2118 } 2119 2120 /* 2121 * Setup useful script bus addresses. 2122 * To be done for all firmwares. 2123 */ 2124 static void 2125 sym_fw_setup_bus_addresses(hcb_p np, struct sym_fw *fw) 2126 { 2127 u32 *pa; 2128 u_short *po; 2129 int i; 2130 2131 /* 2132 * Build the bus address table for script A 2133 * from the script A offset table. 2134 */ 2135 po = (u_short *) fw->a_ofs; 2136 pa = (u32 *) &np->fwa_bas; 2137 for (i = 0 ; i < sizeof(np->fwa_bas)/sizeof(u32) ; i++) 2138 pa[i] = np->scripta_ba + po[i]; 2139 2140 /* 2141 * Same for script B. 2142 */ 2143 po = (u_short *) fw->b_ofs; 2144 pa = (u32 *) &np->fwb_bas; 2145 for (i = 0 ; i < sizeof(np->fwb_bas)/sizeof(u32) ; i++) 2146 pa[i] = np->scriptb_ba + po[i]; 2147 } 2148 2149 #ifdef SYM_CONF_GENERIC_SUPPORT 2150 /* 2151 * Setup routine for firmware #1. 2152 */ 2153 static void 2154 sym_fw1_setup(hcb_p np, struct sym_fw *fw) 2155 { 2156 struct sym_fw1a_scr *scripta0; 2157 struct sym_fw1b_scr *scriptb0; 2158 2159 scripta0 = (struct sym_fw1a_scr *) np->scripta0; 2160 scriptb0 = (struct sym_fw1b_scr *) np->scriptb0; 2161 2162 /* 2163 * Fill variable parts in scripts. 2164 */ 2165 sym_fw_fill_data(scripta0->data_in, scripta0->data_out); 2166 2167 /* 2168 * Setup bus addresses used from the C code.. 2169 */ 2170 sym_fw_setup_bus_addresses(np, fw); 2171 } 2172 #endif /* SYM_CONF_GENERIC_SUPPORT */ 2173 2174 /* 2175 * Setup routine for firmware #2. 2176 */ 2177 static void 2178 sym_fw2_setup(hcb_p np, struct sym_fw *fw) 2179 { 2180 struct sym_fw2a_scr *scripta0; 2181 struct sym_fw2b_scr *scriptb0; 2182 2183 scripta0 = (struct sym_fw2a_scr *) np->scripta0; 2184 scriptb0 = (struct sym_fw2b_scr *) np->scriptb0; 2185 2186 /* 2187 * Fill variable parts in scripts. 2188 */ 2189 sym_fw_fill_data(scripta0->data_in, scripta0->data_out); 2190 2191 /* 2192 * Setup bus addresses used from the C code.. 2193 */ 2194 sym_fw_setup_bus_addresses(np, fw); 2195 } 2196 2197 /* 2198 * Allocate firmware descriptors. 2199 */ 2200 #ifdef SYM_CONF_GENERIC_SUPPORT 2201 static struct sym_fw sym_fw1 = SYM_FW_ENTRY(sym_fw1, "NCR-generic"); 2202 #endif /* SYM_CONF_GENERIC_SUPPORT */ 2203 static struct sym_fw sym_fw2 = SYM_FW_ENTRY(sym_fw2, "LOAD/STORE-based"); 2204 2205 /* 2206 * Find the most appropriate firmware for a chip. 2207 */ 2208 static struct sym_fw * 2209 sym_find_firmware(struct sym_pci_chip *chip) 2210 { 2211 if (chip->features & FE_LDSTR) 2212 return &sym_fw2; 2213 #ifdef SYM_CONF_GENERIC_SUPPORT 2214 else if (!(chip->features & (FE_PFEN|FE_NOPM|FE_DAC))) 2215 return &sym_fw1; 2216 #endif 2217 else 2218 return 0; 2219 } 2220 2221 /* 2222 * Bind a script to physical addresses. 2223 */ 2224 static void sym_fw_bind_script (hcb_p np, u32 *start, int len) 2225 { 2226 u32 opcode, new, old, tmp1, tmp2; 2227 u32 *end, *cur; 2228 int relocs; 2229 2230 cur = start; 2231 end = start + len/4; 2232 2233 while (cur < end) { 2234 2235 opcode = *cur; 2236 2237 /* 2238 * If we forget to change the length 2239 * in scripts, a field will be 2240 * padded with 0. This is an illegal 2241 * command. 2242 */ 2243 if (opcode == 0) { 2244 printf ("%s: ERROR0 IN SCRIPT at %d.\n", 2245 sym_name(np), (int) (cur-start)); 2246 MDELAY (10000); 2247 ++cur; 2248 continue; 2249 }; 2250 2251 /* 2252 * We use the bogus value 0xf00ff00f ;-) 2253 * to reserve data area in SCRIPTS. 2254 */ 2255 if (opcode == SCR_DATA_ZERO) { 2256 *cur++ = 0; 2257 continue; 2258 } 2259 2260 if (DEBUG_FLAGS & DEBUG_SCRIPT) 2261 printf ("%d: <%x>\n", (int) (cur-start), 2262 (unsigned)opcode); 2263 2264 /* 2265 * We don't have to decode ALL commands 2266 */ 2267 switch (opcode >> 28) { 2268 case 0xf: 2269 /* 2270 * LOAD / STORE DSA relative, don't relocate. 2271 */ 2272 relocs = 0; 2273 break; 2274 case 0xe: 2275 /* 2276 * LOAD / STORE absolute. 2277 */ 2278 relocs = 1; 2279 break; 2280 case 0xc: 2281 /* 2282 * COPY has TWO arguments. 2283 */ 2284 relocs = 2; 2285 tmp1 = cur[1]; 2286 tmp2 = cur[2]; 2287 if ((tmp1 ^ tmp2) & 3) { 2288 printf ("%s: ERROR1 IN SCRIPT at %d.\n", 2289 sym_name(np), (int) (cur-start)); 2290 MDELAY (10000); 2291 } 2292 /* 2293 * If PREFETCH feature not enabled, remove 2294 * the NO FLUSH bit if present. 2295 */ 2296 if ((opcode & SCR_NO_FLUSH) && 2297 !(np->features & FE_PFEN)) { 2298 opcode = (opcode & ~SCR_NO_FLUSH); 2299 } 2300 break; 2301 case 0x0: 2302 /* 2303 * MOVE/CHMOV (absolute address) 2304 */ 2305 if (!(np->features & FE_WIDE)) 2306 opcode = (opcode | OPC_MOVE); 2307 relocs = 1; 2308 break; 2309 case 0x1: 2310 /* 2311 * MOVE/CHMOV (table indirect) 2312 */ 2313 if (!(np->features & FE_WIDE)) 2314 opcode = (opcode | OPC_MOVE); 2315 relocs = 0; 2316 break; 2317 case 0x8: 2318 /* 2319 * JUMP / CALL 2320 * dont't relocate if relative :-) 2321 */ 2322 if (opcode & 0x00800000) 2323 relocs = 0; 2324 else if ((opcode & 0xf8400000) == 0x80400000)/*JUMP64*/ 2325 relocs = 2; 2326 else 2327 relocs = 1; 2328 break; 2329 case 0x4: 2330 case 0x5: 2331 case 0x6: 2332 case 0x7: 2333 relocs = 1; 2334 break; 2335 default: 2336 relocs = 0; 2337 break; 2338 }; 2339 2340 /* 2341 * Scriptify:) the opcode. 2342 */ 2343 *cur++ = cpu_to_scr(opcode); 2344 2345 /* 2346 * If no relocation, assume 1 argument 2347 * and just scriptize:) it. 2348 */ 2349 if (!relocs) { 2350 *cur = cpu_to_scr(*cur); 2351 ++cur; 2352 continue; 2353 } 2354 2355 /* 2356 * Otherwise performs all needed relocations. 2357 */ 2358 while (relocs--) { 2359 old = *cur; 2360 2361 switch (old & RELOC_MASK) { 2362 case RELOC_REGISTER: 2363 new = (old & ~RELOC_MASK) + np->mmio_ba; 2364 break; 2365 case RELOC_LABEL_A: 2366 new = (old & ~RELOC_MASK) + np->scripta_ba; 2367 break; 2368 case RELOC_LABEL_B: 2369 new = (old & ~RELOC_MASK) + np->scriptb_ba; 2370 break; 2371 case RELOC_SOFTC: 2372 new = (old & ~RELOC_MASK) + np->hcb_ba; 2373 break; 2374 case 0: 2375 /* 2376 * Don't relocate a 0 address. 2377 * They are mostly used for patched or 2378 * script self-modified areas. 2379 */ 2380 if (old == 0) { 2381 new = old; 2382 break; 2383 } 2384 /* fall through */ 2385 default: 2386 new = 0; 2387 panic("sym_fw_bind_script: " 2388 "weird relocation %x\n", old); 2389 break; 2390 } 2391 2392 *cur++ = cpu_to_scr(new); 2393 } 2394 }; 2395 } 2396 2397 /*--------------------------------------------------------------------------*/ 2398 /*--------------------------- END OF FIRMARES -----------------------------*/ 2399 /*--------------------------------------------------------------------------*/ 2400 2401 /* 2402 * Function prototypes. 2403 */ 2404 static void sym_save_initial_setting (hcb_p np); 2405 static int sym_prepare_setting (hcb_p np, struct sym_nvram *nvram); 2406 static int sym_prepare_nego (hcb_p np, ccb_p cp, int nego, u_char *msgptr); 2407 static void sym_put_start_queue (hcb_p np, ccb_p cp); 2408 static void sym_chip_reset (hcb_p np); 2409 static void sym_soft_reset (hcb_p np); 2410 static void sym_start_reset (hcb_p np); 2411 static int sym_reset_scsi_bus (hcb_p np, int enab_int); 2412 static int sym_wakeup_done (hcb_p np); 2413 static void sym_flush_busy_queue (hcb_p np, int cam_status); 2414 static void sym_flush_comp_queue (hcb_p np, int cam_status); 2415 static void sym_init (hcb_p np, int reason); 2416 static int sym_getsync(hcb_p np, u_char dt, u_char sfac, u_char *divp, 2417 u_char *fakp); 2418 static void sym_setsync (hcb_p np, ccb_p cp, u_char ofs, u_char per, 2419 u_char div, u_char fak); 2420 static void sym_setwide (hcb_p np, ccb_p cp, u_char wide); 2421 static void sym_setpprot(hcb_p np, ccb_p cp, u_char dt, u_char ofs, 2422 u_char per, u_char wide, u_char div, u_char fak); 2423 static void sym_settrans(hcb_p np, ccb_p cp, u_char dt, u_char ofs, 2424 u_char per, u_char wide, u_char div, u_char fak); 2425 static void sym_log_hard_error (hcb_p np, u_short sist, u_char dstat); 2426 static void sym_intr (void *arg); 2427 static void sym_poll (struct cam_sim *sim); 2428 static void sym_recover_scsi_int (hcb_p np, u_char hsts); 2429 static void sym_int_sto (hcb_p np); 2430 static void sym_int_udc (hcb_p np); 2431 static void sym_int_sbmc (hcb_p np); 2432 static void sym_int_par (hcb_p np, u_short sist); 2433 static void sym_int_ma (hcb_p np); 2434 static int sym_dequeue_from_squeue(hcb_p np, int i, int target, int lun, 2435 int task); 2436 static void sym_sir_bad_scsi_status (hcb_p np, int num, ccb_p cp); 2437 static int sym_clear_tasks (hcb_p np, int status, int targ, int lun, int task); 2438 static void sym_sir_task_recovery (hcb_p np, int num); 2439 static int sym_evaluate_dp (hcb_p np, ccb_p cp, u32 scr, int *ofs); 2440 static void sym_modify_dp (hcb_p np, tcb_p tp, ccb_p cp, int ofs); 2441 static int sym_compute_residual (hcb_p np, ccb_p cp); 2442 static int sym_show_msg (u_char * msg); 2443 static void sym_print_msg (ccb_p cp, char *label, u_char *msg); 2444 static void sym_sync_nego (hcb_p np, tcb_p tp, ccb_p cp); 2445 static void sym_ppr_nego (hcb_p np, tcb_p tp, ccb_p cp); 2446 static void sym_wide_nego (hcb_p np, tcb_p tp, ccb_p cp); 2447 static void sym_nego_default (hcb_p np, tcb_p tp, ccb_p cp); 2448 static void sym_nego_rejected (hcb_p np, tcb_p tp, ccb_p cp); 2449 static void sym_int_sir (hcb_p np); 2450 static void sym_free_ccb (hcb_p np, ccb_p cp); 2451 static ccb_p sym_get_ccb (hcb_p np, u_char tn, u_char ln, u_char tag_order); 2452 static ccb_p sym_alloc_ccb (hcb_p np); 2453 static ccb_p sym_ccb_from_dsa (hcb_p np, u32 dsa); 2454 static lcb_p sym_alloc_lcb (hcb_p np, u_char tn, u_char ln); 2455 static void sym_alloc_lcb_tags (hcb_p np, u_char tn, u_char ln); 2456 static int sym_snooptest (hcb_p np); 2457 static void sym_selectclock(hcb_p np, u_char scntl3); 2458 static void sym_getclock (hcb_p np, int mult); 2459 static int sym_getpciclock (hcb_p np); 2460 static void sym_complete_ok (hcb_p np, ccb_p cp); 2461 static void sym_complete_error (hcb_p np, ccb_p cp); 2462 static void sym_timeout (void *arg); 2463 static int sym_abort_scsiio (hcb_p np, union ccb *ccb, int timed_out); 2464 static void sym_reset_dev (hcb_p np, union ccb *ccb); 2465 static void sym_action (struct cam_sim *sim, union ccb *ccb); 2466 static void sym_action1 (struct cam_sim *sim, union ccb *ccb); 2467 static int sym_setup_cdb (hcb_p np, struct ccb_scsiio *csio, ccb_p cp); 2468 static void sym_setup_data_and_start (hcb_p np, struct ccb_scsiio *csio, 2469 ccb_p cp); 2470 #ifdef FreeBSD_Bus_Dma_Abstraction 2471 static int sym_fast_scatter_sg_physical(hcb_p np, ccb_p cp, 2472 bus_dma_segment_t *psegs, int nsegs); 2473 #else 2474 static int sym_scatter_virtual (hcb_p np, ccb_p cp, vm_offset_t vaddr, 2475 vm_size_t len); 2476 static int sym_scatter_sg_virtual (hcb_p np, ccb_p cp, 2477 bus_dma_segment_t *psegs, int nsegs); 2478 static int sym_scatter_physical (hcb_p np, ccb_p cp, vm_offset_t paddr, 2479 vm_size_t len); 2480 #endif 2481 static int sym_scatter_sg_physical (hcb_p np, ccb_p cp, 2482 bus_dma_segment_t *psegs, int nsegs); 2483 static void sym_action2 (struct cam_sim *sim, union ccb *ccb); 2484 static void sym_update_trans (hcb_p np, tcb_p tp, struct sym_trans *tip, 2485 struct ccb_trans_settings *cts); 2486 static void sym_update_dflags(hcb_p np, u_char *flags, 2487 struct ccb_trans_settings *cts); 2488 2489 #ifdef FreeBSD_Bus_Io_Abstraction 2490 static struct sym_pci_chip *sym_find_pci_chip (device_t dev); 2491 static int sym_pci_probe (device_t dev); 2492 static int sym_pci_attach (device_t dev); 2493 #else 2494 static struct sym_pci_chip *sym_find_pci_chip (pcici_t tag); 2495 static const char *sym_pci_probe (pcici_t tag, pcidi_t type); 2496 static void sym_pci_attach (pcici_t tag, int unit); 2497 static int sym_pci_attach2 (pcici_t tag, int unit); 2498 #endif 2499 2500 static void sym_pci_free (hcb_p np); 2501 static int sym_cam_attach (hcb_p np); 2502 static void sym_cam_free (hcb_p np); 2503 2504 static void sym_nvram_setup_host (hcb_p np, struct sym_nvram *nvram); 2505 static void sym_nvram_setup_target (hcb_p np, int targ, struct sym_nvram *nvp); 2506 static int sym_read_nvram (hcb_p np, struct sym_nvram *nvp); 2507 2508 /* 2509 * Print something which allows to retrieve the controler type, 2510 * unit, target, lun concerned by a kernel message. 2511 */ 2512 static void PRINT_TARGET (hcb_p np, int target) 2513 { 2514 printf ("%s:%d:", sym_name(np), target); 2515 } 2516 2517 static void PRINT_LUN(hcb_p np, int target, int lun) 2518 { 2519 printf ("%s:%d:%d:", sym_name(np), target, lun); 2520 } 2521 2522 static void PRINT_ADDR (ccb_p cp) 2523 { 2524 if (cp && cp->cam_ccb) 2525 xpt_print_path(cp->cam_ccb->ccb_h.path); 2526 } 2527 2528 /* 2529 * Take into account this ccb in the freeze count. 2530 */ 2531 static void sym_freeze_cam_ccb(union ccb *ccb) 2532 { 2533 if (!(ccb->ccb_h.flags & CAM_DEV_QFRZDIS)) { 2534 if (!(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 2535 ccb->ccb_h.status |= CAM_DEV_QFRZN; 2536 xpt_freeze_devq(ccb->ccb_h.path, 1); 2537 } 2538 } 2539 } 2540 2541 /* 2542 * Set the status field of a CAM CCB. 2543 */ 2544 static __inline void sym_set_cam_status(union ccb *ccb, cam_status status) 2545 { 2546 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2547 ccb->ccb_h.status |= status; 2548 } 2549 2550 /* 2551 * Get the status field of a CAM CCB. 2552 */ 2553 static __inline int sym_get_cam_status(union ccb *ccb) 2554 { 2555 return ccb->ccb_h.status & CAM_STATUS_MASK; 2556 } 2557 2558 /* 2559 * Enqueue a CAM CCB. 2560 */ 2561 static void sym_enqueue_cam_ccb(hcb_p np, union ccb *ccb) 2562 { 2563 assert(!(ccb->ccb_h.status & CAM_SIM_QUEUED)); 2564 ccb->ccb_h.status = CAM_REQ_INPROG; 2565 2566 ccb->ccb_h.timeout_ch = timeout(sym_timeout, (caddr_t) ccb, 2567 ccb->ccb_h.timeout*hz/1000); 2568 ccb->ccb_h.status |= CAM_SIM_QUEUED; 2569 ccb->ccb_h.sym_hcb_ptr = np; 2570 2571 sym_insque_tail(sym_qptr(&ccb->ccb_h.sim_links), &np->cam_ccbq); 2572 } 2573 2574 /* 2575 * Complete a pending CAM CCB. 2576 */ 2577 static void sym_xpt_done(hcb_p np, union ccb *ccb) 2578 { 2579 if (ccb->ccb_h.status & CAM_SIM_QUEUED) { 2580 untimeout(sym_timeout, (caddr_t) ccb, ccb->ccb_h.timeout_ch); 2581 sym_remque(sym_qptr(&ccb->ccb_h.sim_links)); 2582 ccb->ccb_h.status &= ~CAM_SIM_QUEUED; 2583 ccb->ccb_h.sym_hcb_ptr = 0; 2584 } 2585 if (ccb->ccb_h.flags & CAM_DEV_QFREEZE) 2586 sym_freeze_cam_ccb(ccb); 2587 xpt_done(ccb); 2588 } 2589 2590 static void sym_xpt_done2(hcb_p np, union ccb *ccb, int cam_status) 2591 { 2592 sym_set_cam_status(ccb, cam_status); 2593 sym_xpt_done(np, ccb); 2594 } 2595 2596 /* 2597 * SYMBIOS chip clock divisor table. 2598 * 2599 * Divisors are multiplied by 10,000,000 in order to make 2600 * calculations more simple. 2601 */ 2602 #define _5M 5000000 2603 static u32 div_10M[] = {2*_5M, 3*_5M, 4*_5M, 6*_5M, 8*_5M, 12*_5M, 16*_5M}; 2604 2605 /* 2606 * SYMBIOS chips allow burst lengths of 2, 4, 8, 16, 32, 64, 2607 * 128 transfers. All chips support at least 16 transfers 2608 * bursts. The 825A, 875 and 895 chips support bursts of up 2609 * to 128 transfers and the 895A and 896 support bursts of up 2610 * to 64 transfers. All other chips support up to 16 2611 * transfers bursts. 2612 * 2613 * For PCI 32 bit data transfers each transfer is a DWORD. 2614 * It is a QUADWORD (8 bytes) for PCI 64 bit data transfers. 2615 * 2616 * We use log base 2 (burst length) as internal code, with 2617 * value 0 meaning "burst disabled". 2618 */ 2619 2620 /* 2621 * Burst length from burst code. 2622 */ 2623 #define burst_length(bc) (!(bc))? 0 : 1 << (bc) 2624 2625 /* 2626 * Burst code from io register bits. 2627 */ 2628 #define burst_code(dmode, ctest4, ctest5) \ 2629 (ctest4) & 0x80? 0 : (((dmode) & 0xc0) >> 6) + ((ctest5) & 0x04) + 1 2630 2631 /* 2632 * Set initial io register bits from burst code. 2633 */ 2634 static __inline void sym_init_burst(hcb_p np, u_char bc) 2635 { 2636 np->rv_ctest4 &= ~0x80; 2637 np->rv_dmode &= ~(0x3 << 6); 2638 np->rv_ctest5 &= ~0x4; 2639 2640 if (!bc) { 2641 np->rv_ctest4 |= 0x80; 2642 } 2643 else { 2644 --bc; 2645 np->rv_dmode |= ((bc & 0x3) << 6); 2646 np->rv_ctest5 |= (bc & 0x4); 2647 } 2648 } 2649 2650 2651 /* 2652 * Print out the list of targets that have some flag disabled by user. 2653 */ 2654 static void sym_print_targets_flag(hcb_p np, int mask, char *msg) 2655 { 2656 int cnt; 2657 int i; 2658 2659 for (cnt = 0, i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) { 2660 if (i == np->myaddr) 2661 continue; 2662 if (np->target[i].usrflags & mask) { 2663 if (!cnt++) 2664 printf("%s: %s disabled for targets", 2665 sym_name(np), msg); 2666 printf(" %d", i); 2667 } 2668 } 2669 if (cnt) 2670 printf(".\n"); 2671 } 2672 2673 /* 2674 * Save initial settings of some IO registers. 2675 * Assumed to have been set by BIOS. 2676 * We cannot reset the chip prior to reading the 2677 * IO registers, since informations will be lost. 2678 * Since the SCRIPTS processor may be running, this 2679 * is not safe on paper, but it seems to work quite 2680 * well. :) 2681 */ 2682 static void sym_save_initial_setting (hcb_p np) 2683 { 2684 np->sv_scntl0 = INB(nc_scntl0) & 0x0a; 2685 np->sv_scntl3 = INB(nc_scntl3) & 0x07; 2686 np->sv_dmode = INB(nc_dmode) & 0xce; 2687 np->sv_dcntl = INB(nc_dcntl) & 0xa8; 2688 np->sv_ctest3 = INB(nc_ctest3) & 0x01; 2689 np->sv_ctest4 = INB(nc_ctest4) & 0x80; 2690 np->sv_gpcntl = INB(nc_gpcntl); 2691 np->sv_stest1 = INB(nc_stest1); 2692 np->sv_stest2 = INB(nc_stest2) & 0x20; 2693 np->sv_stest4 = INB(nc_stest4); 2694 if (np->features & FE_C10) { /* Always large DMA fifo + ultra3 */ 2695 np->sv_scntl4 = INB(nc_scntl4); 2696 np->sv_ctest5 = INB(nc_ctest5) & 0x04; 2697 } 2698 else 2699 np->sv_ctest5 = INB(nc_ctest5) & 0x24; 2700 } 2701 2702 /* 2703 * Prepare io register values used by sym_init() according 2704 * to selected and supported features. 2705 */ 2706 static int sym_prepare_setting(hcb_p np, struct sym_nvram *nvram) 2707 { 2708 u_char burst_max; 2709 u32 period; 2710 int i; 2711 2712 /* 2713 * Wide ? 2714 */ 2715 np->maxwide = (np->features & FE_WIDE)? 1 : 0; 2716 2717 /* 2718 * Get the frequency of the chip's clock. 2719 */ 2720 if (np->features & FE_QUAD) 2721 np->multiplier = 4; 2722 else if (np->features & FE_DBLR) 2723 np->multiplier = 2; 2724 else 2725 np->multiplier = 1; 2726 2727 np->clock_khz = (np->features & FE_CLK80)? 80000 : 40000; 2728 np->clock_khz *= np->multiplier; 2729 2730 if (np->clock_khz != 40000) 2731 sym_getclock(np, np->multiplier); 2732 2733 /* 2734 * Divisor to be used for async (timer pre-scaler). 2735 */ 2736 i = np->clock_divn - 1; 2737 while (--i >= 0) { 2738 if (10ul * SYM_CONF_MIN_ASYNC * np->clock_khz > div_10M[i]) { 2739 ++i; 2740 break; 2741 } 2742 } 2743 np->rv_scntl3 = i+1; 2744 2745 /* 2746 * The C1010 uses hardwired divisors for async. 2747 * So, we just throw away, the async. divisor.:-) 2748 */ 2749 if (np->features & FE_C10) 2750 np->rv_scntl3 = 0; 2751 2752 /* 2753 * Minimum synchronous period factor supported by the chip. 2754 * Btw, 'period' is in tenths of nanoseconds. 2755 */ 2756 period = (4 * div_10M[0] + np->clock_khz - 1) / np->clock_khz; 2757 if (period <= 250) np->minsync = 10; 2758 else if (period <= 303) np->minsync = 11; 2759 else if (period <= 500) np->minsync = 12; 2760 else np->minsync = (period + 40 - 1) / 40; 2761 2762 /* 2763 * Check against chip SCSI standard support (SCSI-2,ULTRA,ULTRA2). 2764 */ 2765 if (np->minsync < 25 && 2766 !(np->features & (FE_ULTRA|FE_ULTRA2|FE_ULTRA3))) 2767 np->minsync = 25; 2768 else if (np->minsync < 12 && 2769 !(np->features & (FE_ULTRA2|FE_ULTRA3))) 2770 np->minsync = 12; 2771 2772 /* 2773 * Maximum synchronous period factor supported by the chip. 2774 */ 2775 period = (11 * div_10M[np->clock_divn - 1]) / (4 * np->clock_khz); 2776 np->maxsync = period > 2540 ? 254 : period / 10; 2777 2778 /* 2779 * If chip is a C1010, guess the sync limits in DT mode. 2780 */ 2781 if ((np->features & (FE_C10|FE_ULTRA3)) == (FE_C10|FE_ULTRA3)) { 2782 if (np->clock_khz == 160000) { 2783 np->minsync_dt = 9; 2784 np->maxsync_dt = 50; 2785 np->maxoffs_dt = 62; 2786 } 2787 } 2788 2789 /* 2790 * 64 bit addressing (895A/896/1010) ? 2791 */ 2792 if (np->features & FE_DAC) 2793 #if BITS_PER_LONG > 32 2794 np->rv_ccntl1 |= (XTIMOD | EXTIBMV); 2795 #else 2796 np->rv_ccntl1 |= (DDAC); 2797 #endif 2798 2799 /* 2800 * Phase mismatch handled by SCRIPTS (895A/896/1010) ? 2801 */ 2802 if (np->features & FE_NOPM) 2803 np->rv_ccntl0 |= (ENPMJ); 2804 2805 /* 2806 * C1010 Errata. 2807 * In dual channel mode, contention occurs if internal cycles 2808 * are used. Disable internal cycles. 2809 */ 2810 if (np->device_id == PCI_ID_LSI53C1010 && 2811 np->revision_id < 0x2) 2812 np->rv_ccntl0 |= DILS; 2813 2814 /* 2815 * Select burst length (dwords) 2816 */ 2817 burst_max = SYM_SETUP_BURST_ORDER; 2818 if (burst_max == 255) 2819 burst_max = burst_code(np->sv_dmode, np->sv_ctest4, 2820 np->sv_ctest5); 2821 if (burst_max > 7) 2822 burst_max = 7; 2823 if (burst_max > np->maxburst) 2824 burst_max = np->maxburst; 2825 2826 /* 2827 * DEL 352 - 53C810 Rev x11 - Part Number 609-0392140 - ITEM 2. 2828 * This chip and the 860 Rev 1 may wrongly use PCI cache line 2829 * based transactions on LOAD/STORE instructions. So we have 2830 * to prevent these chips from using such PCI transactions in 2831 * this driver. The generic ncr driver that does not use 2832 * LOAD/STORE instructions does not need this work-around. 2833 */ 2834 if ((np->device_id == PCI_ID_SYM53C810 && 2835 np->revision_id >= 0x10 && np->revision_id <= 0x11) || 2836 (np->device_id == PCI_ID_SYM53C860 && 2837 np->revision_id <= 0x1)) 2838 np->features &= ~(FE_WRIE|FE_ERL|FE_ERMP); 2839 2840 /* 2841 * Select all supported special features. 2842 * If we are using on-board RAM for scripts, prefetch (PFEN) 2843 * does not help, but burst op fetch (BOF) does. 2844 * Disabling PFEN makes sure BOF will be used. 2845 */ 2846 if (np->features & FE_ERL) 2847 np->rv_dmode |= ERL; /* Enable Read Line */ 2848 if (np->features & FE_BOF) 2849 np->rv_dmode |= BOF; /* Burst Opcode Fetch */ 2850 if (np->features & FE_ERMP) 2851 np->rv_dmode |= ERMP; /* Enable Read Multiple */ 2852 #if 1 2853 if ((np->features & FE_PFEN) && !np->ram_ba) 2854 #else 2855 if (np->features & FE_PFEN) 2856 #endif 2857 np->rv_dcntl |= PFEN; /* Prefetch Enable */ 2858 if (np->features & FE_CLSE) 2859 np->rv_dcntl |= CLSE; /* Cache Line Size Enable */ 2860 if (np->features & FE_WRIE) 2861 np->rv_ctest3 |= WRIE; /* Write and Invalidate */ 2862 if (np->features & FE_DFS) 2863 np->rv_ctest5 |= DFS; /* Dma Fifo Size */ 2864 2865 /* 2866 * Select some other 2867 */ 2868 if (SYM_SETUP_PCI_PARITY) 2869 np->rv_ctest4 |= MPEE; /* Master parity checking */ 2870 if (SYM_SETUP_SCSI_PARITY) 2871 np->rv_scntl0 |= 0x0a; /* full arb., ena parity, par->ATN */ 2872 2873 /* 2874 * Get parity checking, host ID and verbose mode from NVRAM 2875 */ 2876 np->myaddr = 255; 2877 sym_nvram_setup_host (np, nvram); 2878 2879 /* 2880 * Get SCSI addr of host adapter (set by bios?). 2881 */ 2882 if (np->myaddr == 255) { 2883 np->myaddr = INB(nc_scid) & 0x07; 2884 if (!np->myaddr) 2885 np->myaddr = SYM_SETUP_HOST_ID; 2886 } 2887 2888 /* 2889 * Prepare initial io register bits for burst length 2890 */ 2891 sym_init_burst(np, burst_max); 2892 2893 /* 2894 * Set SCSI BUS mode. 2895 * - LVD capable chips (895/895A/896/1010) report the 2896 * current BUS mode through the STEST4 IO register. 2897 * - For previous generation chips (825/825A/875), 2898 * user has to tell us how to check against HVD, 2899 * since a 100% safe algorithm is not possible. 2900 */ 2901 np->scsi_mode = SMODE_SE; 2902 if (np->features & (FE_ULTRA2|FE_ULTRA3)) 2903 np->scsi_mode = (np->sv_stest4 & SMODE); 2904 else if (np->features & FE_DIFF) { 2905 if (SYM_SETUP_SCSI_DIFF == 1) { 2906 if (np->sv_scntl3) { 2907 if (np->sv_stest2 & 0x20) 2908 np->scsi_mode = SMODE_HVD; 2909 } 2910 else if (nvram->type == SYM_SYMBIOS_NVRAM) { 2911 if (!(INB(nc_gpreg) & 0x08)) 2912 np->scsi_mode = SMODE_HVD; 2913 } 2914 } 2915 else if (SYM_SETUP_SCSI_DIFF == 2) 2916 np->scsi_mode = SMODE_HVD; 2917 } 2918 if (np->scsi_mode == SMODE_HVD) 2919 np->rv_stest2 |= 0x20; 2920 2921 /* 2922 * Set LED support from SCRIPTS. 2923 * Ignore this feature for boards known to use a 2924 * specific GPIO wiring and for the 895A, 896 2925 * and 1010 that drive the LED directly. 2926 */ 2927 if ((SYM_SETUP_SCSI_LED || 2928 (nvram->type == SYM_SYMBIOS_NVRAM || 2929 (nvram->type == SYM_TEKRAM_NVRAM && 2930 np->device_id == PCI_ID_SYM53C895))) && 2931 !(np->features & FE_LEDC) && !(np->sv_gpcntl & 0x01)) 2932 np->features |= FE_LED0; 2933 2934 /* 2935 * Set irq mode. 2936 */ 2937 switch(SYM_SETUP_IRQ_MODE & 3) { 2938 case 2: 2939 np->rv_dcntl |= IRQM; 2940 break; 2941 case 1: 2942 np->rv_dcntl |= (np->sv_dcntl & IRQM); 2943 break; 2944 default: 2945 break; 2946 } 2947 2948 /* 2949 * Configure targets according to driver setup. 2950 * If NVRAM present get targets setup from NVRAM. 2951 */ 2952 for (i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) { 2953 tcb_p tp = &np->target[i]; 2954 2955 #ifdef FreeBSD_New_Tran_Settings 2956 tp->tinfo.user.scsi_version = tp->tinfo.current.scsi_version= 2; 2957 tp->tinfo.user.spi_version = tp->tinfo.current.spi_version = 2; 2958 #endif 2959 tp->tinfo.user.period = np->minsync; 2960 tp->tinfo.user.offset = np->maxoffs; 2961 tp->tinfo.user.width = np->maxwide ? BUS_16_BIT : BUS_8_BIT; 2962 tp->usrflags |= (SYM_DISC_ENABLED | SYM_TAGS_ENABLED); 2963 tp->usrtags = SYM_SETUP_MAX_TAG; 2964 2965 sym_nvram_setup_target (np, i, nvram); 2966 2967 /* 2968 * For now, guess PPR/DT support from the period 2969 * and BUS width. 2970 */ 2971 if (np->features & FE_ULTRA3) { 2972 if (tp->tinfo.user.period <= 9 && 2973 tp->tinfo.user.width == BUS_16_BIT) { 2974 tp->tinfo.user.options |= PPR_OPT_DT; 2975 tp->tinfo.user.offset = np->maxoffs_dt; 2976 #ifdef FreeBSD_New_Tran_Settings 2977 tp->tinfo.user.spi_version = 3; 2978 #endif 2979 } 2980 } 2981 2982 if (!tp->usrtags) 2983 tp->usrflags &= ~SYM_TAGS_ENABLED; 2984 } 2985 2986 /* 2987 * Let user know about the settings. 2988 */ 2989 i = nvram->type; 2990 printf("%s: %s NVRAM, ID %d, Fast-%d, %s, %s\n", sym_name(np), 2991 i == SYM_SYMBIOS_NVRAM ? "Symbios" : 2992 (i == SYM_TEKRAM_NVRAM ? "Tekram" : "No"), 2993 np->myaddr, 2994 (np->features & FE_ULTRA3) ? 80 : 2995 (np->features & FE_ULTRA2) ? 40 : 2996 (np->features & FE_ULTRA) ? 20 : 10, 2997 sym_scsi_bus_mode(np->scsi_mode), 2998 (np->rv_scntl0 & 0xa) ? "parity checking" : "NO parity"); 2999 /* 3000 * Tell him more on demand. 3001 */ 3002 if (sym_verbose) { 3003 printf("%s: %s IRQ line driver%s\n", 3004 sym_name(np), 3005 np->rv_dcntl & IRQM ? "totem pole" : "open drain", 3006 np->ram_ba ? ", using on-chip SRAM" : ""); 3007 printf("%s: using %s firmware.\n", sym_name(np), np->fw_name); 3008 if (np->features & FE_NOPM) 3009 printf("%s: handling phase mismatch from SCRIPTS.\n", 3010 sym_name(np)); 3011 } 3012 /* 3013 * And still more. 3014 */ 3015 if (sym_verbose > 1) { 3016 printf ("%s: initial SCNTL3/DMODE/DCNTL/CTEST3/4/5 = " 3017 "(hex) %02x/%02x/%02x/%02x/%02x/%02x\n", 3018 sym_name(np), np->sv_scntl3, np->sv_dmode, np->sv_dcntl, 3019 np->sv_ctest3, np->sv_ctest4, np->sv_ctest5); 3020 3021 printf ("%s: final SCNTL3/DMODE/DCNTL/CTEST3/4/5 = " 3022 "(hex) %02x/%02x/%02x/%02x/%02x/%02x\n", 3023 sym_name(np), np->rv_scntl3, np->rv_dmode, np->rv_dcntl, 3024 np->rv_ctest3, np->rv_ctest4, np->rv_ctest5); 3025 } 3026 /* 3027 * Let user be aware of targets that have some disable flags set. 3028 */ 3029 sym_print_targets_flag(np, SYM_SCAN_BOOT_DISABLED, "SCAN AT BOOT"); 3030 if (sym_verbose) 3031 sym_print_targets_flag(np, SYM_SCAN_LUNS_DISABLED, 3032 "SCAN FOR LUNS"); 3033 3034 return 0; 3035 } 3036 3037 /* 3038 * Prepare the next negotiation message if needed. 3039 * 3040 * Fill in the part of message buffer that contains the 3041 * negotiation and the nego_status field of the CCB. 3042 * Returns the size of the message in bytes. 3043 */ 3044 3045 static int sym_prepare_nego(hcb_p np, ccb_p cp, int nego, u_char *msgptr) 3046 { 3047 tcb_p tp = &np->target[cp->target]; 3048 int msglen = 0; 3049 3050 /* 3051 * Early C1010 chips need a work-around for DT 3052 * data transfer to work. 3053 */ 3054 if (!(np->features & FE_U3EN)) 3055 tp->tinfo.goal.options = 0; 3056 /* 3057 * negotiate using PPR ? 3058 */ 3059 if (tp->tinfo.goal.options & PPR_OPT_MASK) 3060 nego = NS_PPR; 3061 /* 3062 * negotiate wide transfers ? 3063 */ 3064 else if (tp->tinfo.current.width != tp->tinfo.goal.width) 3065 nego = NS_WIDE; 3066 /* 3067 * negotiate synchronous transfers? 3068 */ 3069 else if (tp->tinfo.current.period != tp->tinfo.goal.period || 3070 tp->tinfo.current.offset != tp->tinfo.goal.offset) 3071 nego = NS_SYNC; 3072 3073 switch (nego) { 3074 case NS_SYNC: 3075 msgptr[msglen++] = M_EXTENDED; 3076 msgptr[msglen++] = 3; 3077 msgptr[msglen++] = M_X_SYNC_REQ; 3078 msgptr[msglen++] = tp->tinfo.goal.period; 3079 msgptr[msglen++] = tp->tinfo.goal.offset; 3080 break; 3081 case NS_WIDE: 3082 msgptr[msglen++] = M_EXTENDED; 3083 msgptr[msglen++] = 2; 3084 msgptr[msglen++] = M_X_WIDE_REQ; 3085 msgptr[msglen++] = tp->tinfo.goal.width; 3086 break; 3087 case NS_PPR: 3088 msgptr[msglen++] = M_EXTENDED; 3089 msgptr[msglen++] = 6; 3090 msgptr[msglen++] = M_X_PPR_REQ; 3091 msgptr[msglen++] = tp->tinfo.goal.period; 3092 msgptr[msglen++] = 0; 3093 msgptr[msglen++] = tp->tinfo.goal.offset; 3094 msgptr[msglen++] = tp->tinfo.goal.width; 3095 msgptr[msglen++] = tp->tinfo.goal.options & PPR_OPT_DT; 3096 break; 3097 }; 3098 3099 cp->nego_status = nego; 3100 3101 if (nego) { 3102 tp->nego_cp = cp; /* Keep track a nego will be performed */ 3103 if (DEBUG_FLAGS & DEBUG_NEGO) { 3104 sym_print_msg(cp, nego == NS_SYNC ? "sync msgout" : 3105 nego == NS_WIDE ? "wide msgout" : 3106 "ppr msgout", msgptr); 3107 }; 3108 }; 3109 3110 return msglen; 3111 } 3112 3113 /* 3114 * Insert a job into the start queue. 3115 */ 3116 static void sym_put_start_queue(hcb_p np, ccb_p cp) 3117 { 3118 u_short qidx; 3119 3120 #ifdef SYM_CONF_IARB_SUPPORT 3121 /* 3122 * If the previously queued CCB is not yet done, 3123 * set the IARB hint. The SCRIPTS will go with IARB 3124 * for this job when starting the previous one. 3125 * We leave devices a chance to win arbitration by 3126 * not using more than 'iarb_max' consecutive 3127 * immediate arbitrations. 3128 */ 3129 if (np->last_cp && np->iarb_count < np->iarb_max) { 3130 np->last_cp->host_flags |= HF_HINT_IARB; 3131 ++np->iarb_count; 3132 } 3133 else 3134 np->iarb_count = 0; 3135 np->last_cp = cp; 3136 #endif 3137 3138 /* 3139 * Insert first the idle task and then our job. 3140 * The MB should ensure proper ordering. 3141 */ 3142 qidx = np->squeueput + 2; 3143 if (qidx >= MAX_QUEUE*2) qidx = 0; 3144 3145 np->squeue [qidx] = cpu_to_scr(np->idletask_ba); 3146 MEMORY_BARRIER(); 3147 np->squeue [np->squeueput] = cpu_to_scr(cp->ccb_ba); 3148 3149 np->squeueput = qidx; 3150 3151 if (DEBUG_FLAGS & DEBUG_QUEUE) 3152 printf ("%s: queuepos=%d.\n", sym_name (np), np->squeueput); 3153 3154 /* 3155 * Script processor may be waiting for reselect. 3156 * Wake it up. 3157 */ 3158 MEMORY_BARRIER(); 3159 OUTB (nc_istat, SIGP|np->istat_sem); 3160 } 3161 3162 3163 /* 3164 * Soft reset the chip. 3165 * 3166 * Raising SRST when the chip is running may cause 3167 * problems on dual function chips (see below). 3168 * On the other hand, LVD devices need some delay 3169 * to settle and report actual BUS mode in STEST4. 3170 */ 3171 static void sym_chip_reset (hcb_p np) 3172 { 3173 OUTB (nc_istat, SRST); 3174 UDELAY (10); 3175 OUTB (nc_istat, 0); 3176 UDELAY(2000); /* For BUS MODE to settle */ 3177 } 3178 3179 /* 3180 * Soft reset the chip. 3181 * 3182 * Some 896 and 876 chip revisions may hang-up if we set 3183 * the SRST (soft reset) bit at the wrong time when SCRIPTS 3184 * are running. 3185 * So, we need to abort the current operation prior to 3186 * soft resetting the chip. 3187 */ 3188 static void sym_soft_reset (hcb_p np) 3189 { 3190 u_char istat; 3191 int i; 3192 3193 OUTB (nc_istat, CABRT); 3194 for (i = 1000000 ; i ; --i) { 3195 istat = INB (nc_istat); 3196 if (istat & SIP) { 3197 INW (nc_sist); 3198 continue; 3199 } 3200 if (istat & DIP) { 3201 OUTB (nc_istat, 0); 3202 INB (nc_dstat); 3203 break; 3204 } 3205 } 3206 if (!i) 3207 printf("%s: unable to abort current chip operation.\n", 3208 sym_name(np)); 3209 sym_chip_reset (np); 3210 } 3211 3212 /* 3213 * Start reset process. 3214 * 3215 * The interrupt handler will reinitialize the chip. 3216 */ 3217 static void sym_start_reset(hcb_p np) 3218 { 3219 (void) sym_reset_scsi_bus(np, 1); 3220 } 3221 3222 static int sym_reset_scsi_bus(hcb_p np, int enab_int) 3223 { 3224 u32 term; 3225 int retv = 0; 3226 3227 sym_soft_reset(np); /* Soft reset the chip */ 3228 if (enab_int) 3229 OUTW (nc_sien, RST); 3230 /* 3231 * Enable Tolerant, reset IRQD if present and 3232 * properly set IRQ mode, prior to resetting the bus. 3233 */ 3234 OUTB (nc_stest3, TE); 3235 OUTB (nc_dcntl, (np->rv_dcntl & IRQM)); 3236 OUTB (nc_scntl1, CRST); 3237 UDELAY (200); 3238 3239 if (!SYM_SETUP_SCSI_BUS_CHECK) 3240 goto out; 3241 /* 3242 * Check for no terminators or SCSI bus shorts to ground. 3243 * Read SCSI data bus, data parity bits and control signals. 3244 * We are expecting RESET to be TRUE and other signals to be 3245 * FALSE. 3246 */ 3247 term = INB(nc_sstat0); 3248 term = ((term & 2) << 7) + ((term & 1) << 17); /* rst sdp0 */ 3249 term |= ((INB(nc_sstat2) & 0x01) << 26) | /* sdp1 */ 3250 ((INW(nc_sbdl) & 0xff) << 9) | /* d7-0 */ 3251 ((INW(nc_sbdl) & 0xff00) << 10) | /* d15-8 */ 3252 INB(nc_sbcl); /* req ack bsy sel atn msg cd io */ 3253 3254 if (!(np->features & FE_WIDE)) 3255 term &= 0x3ffff; 3256 3257 if (term != (2<<7)) { 3258 printf("%s: suspicious SCSI data while resetting the BUS.\n", 3259 sym_name(np)); 3260 printf("%s: %sdp0,d7-0,rst,req,ack,bsy,sel,atn,msg,c/d,i/o = " 3261 "0x%lx, expecting 0x%lx\n", 3262 sym_name(np), 3263 (np->features & FE_WIDE) ? "dp1,d15-8," : "", 3264 (u_long)term, (u_long)(2<<7)); 3265 if (SYM_SETUP_SCSI_BUS_CHECK == 1) 3266 retv = 1; 3267 } 3268 out: 3269 OUTB (nc_scntl1, 0); 3270 /* MDELAY(100); */ 3271 return retv; 3272 } 3273 3274 /* 3275 * The chip may have completed jobs. Look at the DONE QUEUE. 3276 * 3277 * On architectures that may reorder LOAD/STORE operations, 3278 * a memory barrier may be needed after the reading of the 3279 * so-called `flag' and prior to dealing with the data. 3280 */ 3281 static int sym_wakeup_done (hcb_p np) 3282 { 3283 ccb_p cp; 3284 int i, n; 3285 u32 dsa; 3286 3287 n = 0; 3288 i = np->dqueueget; 3289 while (1) { 3290 dsa = scr_to_cpu(np->dqueue[i]); 3291 if (!dsa) 3292 break; 3293 np->dqueue[i] = 0; 3294 if ((i = i+2) >= MAX_QUEUE*2) 3295 i = 0; 3296 3297 cp = sym_ccb_from_dsa(np, dsa); 3298 if (cp) { 3299 MEMORY_BARRIER(); 3300 sym_complete_ok (np, cp); 3301 ++n; 3302 } 3303 else 3304 printf ("%s: bad DSA (%x) in done queue.\n", 3305 sym_name(np), (u_int) dsa); 3306 } 3307 np->dqueueget = i; 3308 3309 return n; 3310 } 3311 3312 /* 3313 * Complete all active CCBs with error. 3314 * Used on CHIP/SCSI RESET. 3315 */ 3316 static void sym_flush_busy_queue (hcb_p np, int cam_status) 3317 { 3318 /* 3319 * Move all active CCBs to the COMP queue 3320 * and flush this queue. 3321 */ 3322 sym_que_splice(&np->busy_ccbq, &np->comp_ccbq); 3323 sym_que_init(&np->busy_ccbq); 3324 sym_flush_comp_queue(np, cam_status); 3325 } 3326 3327 /* 3328 * Start chip. 3329 * 3330 * 'reason' means: 3331 * 0: initialisation. 3332 * 1: SCSI BUS RESET delivered or received. 3333 * 2: SCSI BUS MODE changed. 3334 */ 3335 static void sym_init (hcb_p np, int reason) 3336 { 3337 int i; 3338 u32 phys; 3339 3340 /* 3341 * Reset chip if asked, otherwise just clear fifos. 3342 */ 3343 if (reason == 1) 3344 sym_soft_reset(np); 3345 else { 3346 OUTB (nc_stest3, TE|CSF); 3347 OUTONB (nc_ctest3, CLF); 3348 } 3349 3350 /* 3351 * Clear Start Queue 3352 */ 3353 phys = np->squeue_ba; 3354 for (i = 0; i < MAX_QUEUE*2; i += 2) { 3355 np->squeue[i] = cpu_to_scr(np->idletask_ba); 3356 np->squeue[i+1] = cpu_to_scr(phys + (i+2)*4); 3357 } 3358 np->squeue[MAX_QUEUE*2-1] = cpu_to_scr(phys); 3359 3360 /* 3361 * Start at first entry. 3362 */ 3363 np->squeueput = 0; 3364 3365 /* 3366 * Clear Done Queue 3367 */ 3368 phys = np->dqueue_ba; 3369 for (i = 0; i < MAX_QUEUE*2; i += 2) { 3370 np->dqueue[i] = 0; 3371 np->dqueue[i+1] = cpu_to_scr(phys + (i+2)*4); 3372 } 3373 np->dqueue[MAX_QUEUE*2-1] = cpu_to_scr(phys); 3374 3375 /* 3376 * Start at first entry. 3377 */ 3378 np->dqueueget = 0; 3379 3380 /* 3381 * Install patches in scripts. 3382 * This also let point to first position the start 3383 * and done queue pointers used from SCRIPTS. 3384 */ 3385 np->fw_patch(np); 3386 3387 /* 3388 * Wakeup all pending jobs. 3389 */ 3390 sym_flush_busy_queue(np, CAM_SCSI_BUS_RESET); 3391 3392 /* 3393 * Init chip. 3394 */ 3395 OUTB (nc_istat, 0x00 ); /* Remove Reset, abort */ 3396 UDELAY (2000); /* The 895 needs time for the bus mode to settle */ 3397 3398 OUTB (nc_scntl0, np->rv_scntl0 | 0xc0); 3399 /* full arb., ena parity, par->ATN */ 3400 OUTB (nc_scntl1, 0x00); /* odd parity, and remove CRST!! */ 3401 3402 sym_selectclock(np, np->rv_scntl3); /* Select SCSI clock */ 3403 3404 OUTB (nc_scid , RRE|np->myaddr); /* Adapter SCSI address */ 3405 OUTW (nc_respid, 1ul<<np->myaddr); /* Id to respond to */ 3406 OUTB (nc_istat , SIGP ); /* Signal Process */ 3407 OUTB (nc_dmode , np->rv_dmode); /* Burst length, dma mode */ 3408 OUTB (nc_ctest5, np->rv_ctest5); /* Large fifo + large burst */ 3409 3410 OUTB (nc_dcntl , NOCOM|np->rv_dcntl); /* Protect SFBR */ 3411 OUTB (nc_ctest3, np->rv_ctest3); /* Write and invalidate */ 3412 OUTB (nc_ctest4, np->rv_ctest4); /* Master parity checking */ 3413 3414 /* Extended Sreq/Sack filtering not supported on the C10 */ 3415 if (np->features & FE_C10) 3416 OUTB (nc_stest2, np->rv_stest2); 3417 else 3418 OUTB (nc_stest2, EXT|np->rv_stest2); 3419 3420 OUTB (nc_stest3, TE); /* TolerANT enable */ 3421 OUTB (nc_stime0, 0x0c); /* HTH disabled STO 0.25 sec */ 3422 3423 /* 3424 * For now, disable AIP generation on C1010-66. 3425 */ 3426 if (np->device_id == PCI_ID_LSI53C1010_2) 3427 OUTB (nc_aipcntl1, DISAIP); 3428 3429 /* 3430 * C10101 Errata. 3431 * Errant SGE's when in narrow. Write bits 4 & 5 of 3432 * STEST1 register to disable SGE. We probably should do 3433 * that from SCRIPTS for each selection/reselection, but 3434 * I just don't want. :) 3435 */ 3436 if (np->device_id == PCI_ID_LSI53C1010 && 3437 /* np->revision_id < 0xff */ 1) 3438 OUTB (nc_stest1, INB(nc_stest1) | 0x30); 3439 3440 /* 3441 * DEL 441 - 53C876 Rev 5 - Part Number 609-0392787/2788 - ITEM 2. 3442 * Disable overlapped arbitration for some dual function devices, 3443 * regardless revision id (kind of post-chip-design feature. ;-)) 3444 */ 3445 if (np->device_id == PCI_ID_SYM53C875) 3446 OUTB (nc_ctest0, (1<<5)); 3447 else if (np->device_id == PCI_ID_SYM53C896) 3448 np->rv_ccntl0 |= DPR; 3449 3450 /* 3451 * Write CCNTL0/CCNTL1 for chips capable of 64 bit addressing 3452 * and/or hardware phase mismatch, since only such chips 3453 * seem to support those IO registers. 3454 */ 3455 if (np->features & (FE_DAC|FE_NOPM)) { 3456 OUTB (nc_ccntl0, np->rv_ccntl0); 3457 OUTB (nc_ccntl1, np->rv_ccntl1); 3458 } 3459 3460 /* 3461 * If phase mismatch handled by scripts (895A/896/1010), 3462 * set PM jump addresses. 3463 */ 3464 if (np->features & FE_NOPM) { 3465 OUTL (nc_pmjad1, SCRIPTB_BA (np, pm_handle)); 3466 OUTL (nc_pmjad2, SCRIPTB_BA (np, pm_handle)); 3467 } 3468 3469 /* 3470 * Enable GPIO0 pin for writing if LED support from SCRIPTS. 3471 * Also set GPIO5 and clear GPIO6 if hardware LED control. 3472 */ 3473 if (np->features & FE_LED0) 3474 OUTB(nc_gpcntl, INB(nc_gpcntl) & ~0x01); 3475 else if (np->features & FE_LEDC) 3476 OUTB(nc_gpcntl, (INB(nc_gpcntl) & ~0x41) | 0x20); 3477 3478 /* 3479 * enable ints 3480 */ 3481 OUTW (nc_sien , STO|HTH|MA|SGE|UDC|RST|PAR); 3482 OUTB (nc_dien , MDPE|BF|SSI|SIR|IID); 3483 3484 /* 3485 * For 895/6 enable SBMC interrupt and save current SCSI bus mode. 3486 * Try to eat the spurious SBMC interrupt that may occur when 3487 * we reset the chip but not the SCSI BUS (at initialization). 3488 */ 3489 if (np->features & (FE_ULTRA2|FE_ULTRA3)) { 3490 OUTONW (nc_sien, SBMC); 3491 if (reason == 0) { 3492 MDELAY(100); 3493 INW (nc_sist); 3494 } 3495 np->scsi_mode = INB (nc_stest4) & SMODE; 3496 } 3497 3498 /* 3499 * Fill in target structure. 3500 * Reinitialize usrsync. 3501 * Reinitialize usrwide. 3502 * Prepare sync negotiation according to actual SCSI bus mode. 3503 */ 3504 for (i=0;i<SYM_CONF_MAX_TARGET;i++) { 3505 tcb_p tp = &np->target[i]; 3506 3507 tp->to_reset = 0; 3508 tp->head.sval = 0; 3509 tp->head.wval = np->rv_scntl3; 3510 tp->head.uval = 0; 3511 3512 tp->tinfo.current.period = 0; 3513 tp->tinfo.current.offset = 0; 3514 tp->tinfo.current.width = BUS_8_BIT; 3515 tp->tinfo.current.options = 0; 3516 } 3517 3518 /* 3519 * Download SCSI SCRIPTS to on-chip RAM if present, 3520 * and start script processor. 3521 */ 3522 if (np->ram_ba) { 3523 if (sym_verbose > 1) 3524 printf ("%s: Downloading SCSI SCRIPTS.\n", 3525 sym_name(np)); 3526 if (np->ram_ws == 8192) { 3527 OUTRAM_OFF(4096, np->scriptb0, np->scriptb_sz); 3528 OUTL (nc_mmws, np->scr_ram_seg); 3529 OUTL (nc_mmrs, np->scr_ram_seg); 3530 OUTL (nc_sfs, np->scr_ram_seg); 3531 phys = SCRIPTB_BA (np, start64); 3532 } 3533 else 3534 phys = SCRIPTA_BA (np, init); 3535 OUTRAM_OFF(0, np->scripta0, np->scripta_sz); 3536 } 3537 else 3538 phys = SCRIPTA_BA (np, init); 3539 3540 np->istat_sem = 0; 3541 3542 OUTL (nc_dsa, np->hcb_ba); 3543 OUTL_DSP (phys); 3544 3545 /* 3546 * Notify the XPT about the RESET condition. 3547 */ 3548 if (reason != 0) 3549 xpt_async(AC_BUS_RESET, np->path, NULL); 3550 } 3551 3552 /* 3553 * Get clock factor and sync divisor for a given 3554 * synchronous factor period. 3555 */ 3556 static int 3557 sym_getsync(hcb_p np, u_char dt, u_char sfac, u_char *divp, u_char *fakp) 3558 { 3559 u32 clk = np->clock_khz; /* SCSI clock frequency in kHz */ 3560 int div = np->clock_divn; /* Number of divisors supported */ 3561 u32 fak; /* Sync factor in sxfer */ 3562 u32 per; /* Period in tenths of ns */ 3563 u32 kpc; /* (per * clk) */ 3564 int ret; 3565 3566 /* 3567 * Compute the synchronous period in tenths of nano-seconds 3568 */ 3569 if (dt && sfac <= 9) per = 125; 3570 else if (sfac <= 10) per = 250; 3571 else if (sfac == 11) per = 303; 3572 else if (sfac == 12) per = 500; 3573 else per = 40 * sfac; 3574 ret = per; 3575 3576 kpc = per * clk; 3577 if (dt) 3578 kpc <<= 1; 3579 3580 /* 3581 * For earliest C10 revision 0, we cannot use extra 3582 * clocks for the setting of the SCSI clocking. 3583 * Note that this limits the lowest sync data transfer 3584 * to 5 Mega-transfers per second and may result in 3585 * using higher clock divisors. 3586 */ 3587 #if 1 3588 if ((np->features & (FE_C10|FE_U3EN)) == FE_C10) { 3589 /* 3590 * Look for the lowest clock divisor that allows an 3591 * output speed not faster than the period. 3592 */ 3593 while (div > 0) { 3594 --div; 3595 if (kpc > (div_10M[div] << 2)) { 3596 ++div; 3597 break; 3598 } 3599 } 3600 fak = 0; /* No extra clocks */ 3601 if (div == np->clock_divn) { /* Are we too fast ? */ 3602 ret = -1; 3603 } 3604 *divp = div; 3605 *fakp = fak; 3606 return ret; 3607 } 3608 #endif 3609 3610 /* 3611 * Look for the greatest clock divisor that allows an 3612 * input speed faster than the period. 3613 */ 3614 while (div-- > 0) 3615 if (kpc >= (div_10M[div] << 2)) break; 3616 3617 /* 3618 * Calculate the lowest clock factor that allows an output 3619 * speed not faster than the period, and the max output speed. 3620 * If fak >= 1 we will set both XCLKH_ST and XCLKH_DT. 3621 * If fak >= 2 we will also set XCLKS_ST and XCLKS_DT. 3622 */ 3623 if (dt) { 3624 fak = (kpc - 1) / (div_10M[div] << 1) + 1 - 2; 3625 /* ret = ((2+fak)*div_10M[div])/np->clock_khz; */ 3626 } 3627 else { 3628 fak = (kpc - 1) / div_10M[div] + 1 - 4; 3629 /* ret = ((4+fak)*div_10M[div])/np->clock_khz; */ 3630 } 3631 3632 /* 3633 * Check against our hardware limits, or bugs :). 3634 */ 3635 if (fak < 0) {fak = 0; ret = -1;} 3636 if (fak > 2) {fak = 2; ret = -1;} 3637 3638 /* 3639 * Compute and return sync parameters. 3640 */ 3641 *divp = div; 3642 *fakp = fak; 3643 3644 return ret; 3645 } 3646 3647 /* 3648 * Tell the SCSI layer about the new transfer parameters. 3649 */ 3650 static void 3651 sym_xpt_async_transfer_neg(hcb_p np, int target, u_int spi_valid) 3652 { 3653 struct ccb_trans_settings cts; 3654 struct cam_path *path; 3655 int sts; 3656 tcb_p tp = &np->target[target]; 3657 3658 sts = xpt_create_path(&path, NULL, cam_sim_path(np->sim), target, 3659 CAM_LUN_WILDCARD); 3660 if (sts != CAM_REQ_CMP) 3661 return; 3662 3663 bzero(&cts, sizeof(cts)); 3664 3665 #ifdef FreeBSD_New_Tran_Settings 3666 #define cts__scsi (cts.proto_specific.scsi) 3667 #define cts__spi (cts.xport_specific.spi) 3668 3669 cts.type = CTS_TYPE_CURRENT_SETTINGS; 3670 cts.protocol = PROTO_SCSI; 3671 cts.transport = XPORT_SPI; 3672 cts.protocol_version = tp->tinfo.current.scsi_version; 3673 cts.transport_version = tp->tinfo.current.spi_version; 3674 3675 cts__spi.valid = spi_valid; 3676 if (spi_valid & CTS_SPI_VALID_SYNC_RATE) 3677 cts__spi.sync_period = tp->tinfo.current.period; 3678 if (spi_valid & CTS_SPI_VALID_SYNC_OFFSET) 3679 cts__spi.sync_offset = tp->tinfo.current.offset; 3680 if (spi_valid & CTS_SPI_VALID_BUS_WIDTH) 3681 cts__spi.bus_width = tp->tinfo.current.width; 3682 if (spi_valid & CTS_SPI_VALID_PPR_OPTIONS) 3683 cts__spi.ppr_options = tp->tinfo.current.options; 3684 #undef cts__spi 3685 #undef cts__scsi 3686 #else 3687 cts.valid = spi_valid; 3688 if (spi_valid & CCB_TRANS_SYNC_RATE_VALID) 3689 cts.sync_period = tp->tinfo.current.period; 3690 if (spi_valid & CCB_TRANS_SYNC_OFFSET_VALID) 3691 cts.sync_offset = tp->tinfo.current.offset; 3692 if (spi_valid & CCB_TRANS_BUS_WIDTH_VALID) 3693 cts.bus_width = tp->tinfo.current.width; 3694 #endif 3695 xpt_setup_ccb(&cts.ccb_h, path, /*priority*/1); 3696 xpt_async(AC_TRANSFER_NEG, path, &cts); 3697 xpt_free_path(path); 3698 } 3699 3700 #ifdef FreeBSD_New_Tran_Settings 3701 #define SYM_SPI_VALID_WDTR \ 3702 CTS_SPI_VALID_BUS_WIDTH | \ 3703 CTS_SPI_VALID_SYNC_RATE | \ 3704 CTS_SPI_VALID_SYNC_OFFSET 3705 #define SYM_SPI_VALID_SDTR \ 3706 CTS_SPI_VALID_SYNC_RATE | \ 3707 CTS_SPI_VALID_SYNC_OFFSET 3708 #define SYM_SPI_VALID_PPR \ 3709 CTS_SPI_VALID_PPR_OPTIONS | \ 3710 CTS_SPI_VALID_BUS_WIDTH | \ 3711 CTS_SPI_VALID_SYNC_RATE | \ 3712 CTS_SPI_VALID_SYNC_OFFSET 3713 #else 3714 #define SYM_SPI_VALID_WDTR \ 3715 CCB_TRANS_BUS_WIDTH_VALID | \ 3716 CCB_TRANS_SYNC_RATE_VALID | \ 3717 CCB_TRANS_SYNC_OFFSET_VALID 3718 #define SYM_SPI_VALID_SDTR \ 3719 CCB_TRANS_SYNC_RATE_VALID | \ 3720 CCB_TRANS_SYNC_OFFSET_VALID 3721 #define SYM_SPI_VALID_PPR \ 3722 CCB_TRANS_BUS_WIDTH_VALID | \ 3723 CCB_TRANS_SYNC_RATE_VALID | \ 3724 CCB_TRANS_SYNC_OFFSET_VALID 3725 #endif 3726 3727 /* 3728 * We received a WDTR. 3729 * Let everything be aware of the changes. 3730 */ 3731 static void sym_setwide(hcb_p np, ccb_p cp, u_char wide) 3732 { 3733 tcb_p tp = &np->target[cp->target]; 3734 3735 sym_settrans(np, cp, 0, 0, 0, wide, 0, 0); 3736 3737 /* 3738 * Tell the SCSI layer about the new transfer parameters. 3739 */ 3740 tp->tinfo.goal.width = tp->tinfo.current.width = wide; 3741 tp->tinfo.current.offset = 0; 3742 tp->tinfo.current.period = 0; 3743 tp->tinfo.current.options = 0; 3744 3745 sym_xpt_async_transfer_neg(np, cp->target, SYM_SPI_VALID_WDTR); 3746 } 3747 3748 /* 3749 * We received a SDTR. 3750 * Let everything be aware of the changes. 3751 */ 3752 static void 3753 sym_setsync(hcb_p np, ccb_p cp, u_char ofs, u_char per, u_char div, u_char fak) 3754 { 3755 tcb_p tp = &np->target[cp->target]; 3756 u_char wide = (cp->phys.select.sel_scntl3 & EWS) ? 1 : 0; 3757 3758 sym_settrans(np, cp, 0, ofs, per, wide, div, fak); 3759 3760 /* 3761 * Tell the SCSI layer about the new transfer parameters. 3762 */ 3763 tp->tinfo.goal.period = tp->tinfo.current.period = per; 3764 tp->tinfo.goal.offset = tp->tinfo.current.offset = ofs; 3765 tp->tinfo.goal.options = tp->tinfo.current.options = 0; 3766 3767 sym_xpt_async_transfer_neg(np, cp->target, SYM_SPI_VALID_SDTR); 3768 } 3769 3770 /* 3771 * We received a PPR. 3772 * Let everything be aware of the changes. 3773 */ 3774 static void sym_setpprot(hcb_p np, ccb_p cp, u_char dt, u_char ofs, 3775 u_char per, u_char wide, u_char div, u_char fak) 3776 { 3777 tcb_p tp = &np->target[cp->target]; 3778 3779 sym_settrans(np, cp, dt, ofs, per, wide, div, fak); 3780 3781 /* 3782 * Tell the SCSI layer about the new transfer parameters. 3783 */ 3784 tp->tinfo.goal.width = tp->tinfo.current.width = wide; 3785 tp->tinfo.goal.period = tp->tinfo.current.period = per; 3786 tp->tinfo.goal.offset = tp->tinfo.current.offset = ofs; 3787 tp->tinfo.goal.options = tp->tinfo.current.options = dt; 3788 3789 sym_xpt_async_transfer_neg(np, cp->target, SYM_SPI_VALID_PPR); 3790 } 3791 3792 /* 3793 * Switch trans mode for current job and it's target. 3794 */ 3795 static void sym_settrans(hcb_p np, ccb_p cp, u_char dt, u_char ofs, 3796 u_char per, u_char wide, u_char div, u_char fak) 3797 { 3798 SYM_QUEHEAD *qp; 3799 union ccb *ccb; 3800 tcb_p tp; 3801 u_char target = INB (nc_sdid) & 0x0f; 3802 u_char sval, wval, uval; 3803 3804 assert (cp); 3805 if (!cp) return; 3806 ccb = cp->cam_ccb; 3807 assert (ccb); 3808 if (!ccb) return; 3809 assert (target == (cp->target & 0xf)); 3810 tp = &np->target[target]; 3811 3812 sval = tp->head.sval; 3813 wval = tp->head.wval; 3814 uval = tp->head.uval; 3815 3816 #if 0 3817 printf("XXXX sval=%x wval=%x uval=%x (%x)\n", 3818 sval, wval, uval, np->rv_scntl3); 3819 #endif 3820 /* 3821 * Set the offset. 3822 */ 3823 if (!(np->features & FE_C10)) 3824 sval = (sval & ~0x1f) | ofs; 3825 else 3826 sval = (sval & ~0x3f) | ofs; 3827 3828 /* 3829 * Set the sync divisor and extra clock factor. 3830 */ 3831 if (ofs != 0) { 3832 wval = (wval & ~0x70) | ((div+1) << 4); 3833 if (!(np->features & FE_C10)) 3834 sval = (sval & ~0xe0) | (fak << 5); 3835 else { 3836 uval = uval & ~(XCLKH_ST|XCLKH_DT|XCLKS_ST|XCLKS_DT); 3837 if (fak >= 1) uval |= (XCLKH_ST|XCLKH_DT); 3838 if (fak >= 2) uval |= (XCLKS_ST|XCLKS_DT); 3839 } 3840 } 3841 3842 /* 3843 * Set the bus width. 3844 */ 3845 wval = wval & ~EWS; 3846 if (wide != 0) 3847 wval |= EWS; 3848 3849 /* 3850 * Set misc. ultra enable bits. 3851 */ 3852 if (np->features & FE_C10) { 3853 uval = uval & ~(U3EN|AIPCKEN); 3854 if (dt) { 3855 assert(np->features & FE_U3EN); 3856 uval |= U3EN; 3857 } 3858 } 3859 else { 3860 wval = wval & ~ULTRA; 3861 if (per <= 12) wval |= ULTRA; 3862 } 3863 3864 /* 3865 * Stop there if sync parameters are unchanged. 3866 */ 3867 if (tp->head.sval == sval && 3868 tp->head.wval == wval && 3869 tp->head.uval == uval) 3870 return; 3871 tp->head.sval = sval; 3872 tp->head.wval = wval; 3873 tp->head.uval = uval; 3874 3875 /* 3876 * Disable extended Sreq/Sack filtering if per < 50. 3877 * Not supported on the C1010. 3878 */ 3879 if (per < 50 && !(np->features & FE_C10)) 3880 OUTOFFB (nc_stest2, EXT); 3881 3882 /* 3883 * set actual value and sync_status 3884 */ 3885 OUTB (nc_sxfer, tp->head.sval); 3886 OUTB (nc_scntl3, tp->head.wval); 3887 3888 if (np->features & FE_C10) { 3889 OUTB (nc_scntl4, tp->head.uval); 3890 } 3891 3892 /* 3893 * patch ALL busy ccbs of this target. 3894 */ 3895 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) { 3896 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 3897 if (cp->target != target) 3898 continue; 3899 cp->phys.select.sel_scntl3 = tp->head.wval; 3900 cp->phys.select.sel_sxfer = tp->head.sval; 3901 if (np->features & FE_C10) { 3902 cp->phys.select.sel_scntl4 = tp->head.uval; 3903 } 3904 } 3905 } 3906 3907 /* 3908 * log message for real hard errors 3909 * 3910 * sym0 targ 0?: ERROR (ds:si) (so-si-sd) (sxfer/scntl3) @ name (dsp:dbc). 3911 * reg: r0 r1 r2 r3 r4 r5 r6 ..... rf. 3912 * 3913 * exception register: 3914 * ds: dstat 3915 * si: sist 3916 * 3917 * SCSI bus lines: 3918 * so: control lines as driven by chip. 3919 * si: control lines as seen by chip. 3920 * sd: scsi data lines as seen by chip. 3921 * 3922 * wide/fastmode: 3923 * sxfer: (see the manual) 3924 * scntl3: (see the manual) 3925 * 3926 * current script command: 3927 * dsp: script address (relative to start of script). 3928 * dbc: first word of script command. 3929 * 3930 * First 24 register of the chip: 3931 * r0..rf 3932 */ 3933 static void sym_log_hard_error(hcb_p np, u_short sist, u_char dstat) 3934 { 3935 u32 dsp; 3936 int script_ofs; 3937 int script_size; 3938 char *script_name; 3939 u_char *script_base; 3940 int i; 3941 3942 dsp = INL (nc_dsp); 3943 3944 if (dsp > np->scripta_ba && 3945 dsp <= np->scripta_ba + np->scripta_sz) { 3946 script_ofs = dsp - np->scripta_ba; 3947 script_size = np->scripta_sz; 3948 script_base = (u_char *) np->scripta0; 3949 script_name = "scripta"; 3950 } 3951 else if (np->scriptb_ba < dsp && 3952 dsp <= np->scriptb_ba + np->scriptb_sz) { 3953 script_ofs = dsp - np->scriptb_ba; 3954 script_size = np->scriptb_sz; 3955 script_base = (u_char *) np->scriptb0; 3956 script_name = "scriptb"; 3957 } else { 3958 script_ofs = dsp; 3959 script_size = 0; 3960 script_base = 0; 3961 script_name = "mem"; 3962 } 3963 3964 printf ("%s:%d: ERROR (%x:%x) (%x-%x-%x) (%x/%x) @ (%s %x:%08x).\n", 3965 sym_name (np), (unsigned)INB (nc_sdid)&0x0f, dstat, sist, 3966 (unsigned)INB (nc_socl), (unsigned)INB (nc_sbcl), 3967 (unsigned)INB (nc_sbdl), (unsigned)INB (nc_sxfer), 3968 (unsigned)INB (nc_scntl3), script_name, script_ofs, 3969 (unsigned)INL (nc_dbc)); 3970 3971 if (((script_ofs & 3) == 0) && 3972 (unsigned)script_ofs < script_size) { 3973 printf ("%s: script cmd = %08x\n", sym_name(np), 3974 scr_to_cpu((int) *(u32 *)(script_base + script_ofs))); 3975 } 3976 3977 printf ("%s: regdump:", sym_name(np)); 3978 for (i=0; i<24;i++) 3979 printf (" %02x", (unsigned)INB_OFF(i)); 3980 printf (".\n"); 3981 3982 /* 3983 * PCI BUS error, read the PCI ststus register. 3984 */ 3985 if (dstat & (MDPE|BF)) { 3986 u_short pci_sts; 3987 #ifdef FreeBSD_Bus_Io_Abstraction 3988 pci_sts = pci_read_config(np->device, PCIR_STATUS, 2); 3989 #else 3990 pci_sts = pci_cfgread(np->pci_tag, PCIR_STATUS, 2); 3991 #endif 3992 if (pci_sts & 0xf900) { 3993 #ifdef FreeBSD_Bus_Io_Abstraction 3994 pci_write_config(np->device, PCIR_STATUS, pci_sts, 2); 3995 #else 3996 pci_cfgwrite(np->pci_tag, PCIR_STATUS, pci_sts, 2); 3997 #endif 3998 printf("%s: PCI STATUS = 0x%04x\n", 3999 sym_name(np), pci_sts & 0xf900); 4000 } 4001 } 4002 } 4003 4004 /* 4005 * chip interrupt handler 4006 * 4007 * In normal situations, interrupt conditions occur one at 4008 * a time. But when something bad happens on the SCSI BUS, 4009 * the chip may raise several interrupt flags before 4010 * stopping and interrupting the CPU. The additionnal 4011 * interrupt flags are stacked in some extra registers 4012 * after the SIP and/or DIP flag has been raised in the 4013 * ISTAT. After the CPU has read the interrupt condition 4014 * flag from SIST or DSTAT, the chip unstacks the other 4015 * interrupt flags and sets the corresponding bits in 4016 * SIST or DSTAT. Since the chip starts stacking once the 4017 * SIP or DIP flag is set, there is a small window of time 4018 * where the stacking does not occur. 4019 * 4020 * Typically, multiple interrupt conditions may happen in 4021 * the following situations: 4022 * 4023 * - SCSI parity error + Phase mismatch (PAR|MA) 4024 * When a parity error is detected in input phase 4025 * and the device switches to msg-in phase inside a 4026 * block MOV. 4027 * - SCSI parity error + Unexpected disconnect (PAR|UDC) 4028 * When a stupid device does not want to handle the 4029 * recovery of an SCSI parity error. 4030 * - Some combinations of STO, PAR, UDC, ... 4031 * When using non compliant SCSI stuff, when user is 4032 * doing non compliant hot tampering on the BUS, when 4033 * something really bad happens to a device, etc ... 4034 * 4035 * The heuristic suggested by SYMBIOS to handle 4036 * multiple interrupts is to try unstacking all 4037 * interrupts conditions and to handle them on some 4038 * priority based on error severity. 4039 * This will work when the unstacking has been 4040 * successful, but we cannot be 100 % sure of that, 4041 * since the CPU may have been faster to unstack than 4042 * the chip is able to stack. Hmmm ... But it seems that 4043 * such a situation is very unlikely to happen. 4044 * 4045 * If this happen, for example STO caught by the CPU 4046 * then UDC happenning before the CPU have restarted 4047 * the SCRIPTS, the driver may wrongly complete the 4048 * same command on UDC, since the SCRIPTS didn't restart 4049 * and the DSA still points to the same command. 4050 * We avoid this situation by setting the DSA to an 4051 * invalid value when the CCB is completed and before 4052 * restarting the SCRIPTS. 4053 * 4054 * Another issue is that we need some section of our 4055 * recovery procedures to be somehow uninterruptible but 4056 * the SCRIPTS processor does not provides such a 4057 * feature. For this reason, we handle recovery preferently 4058 * from the C code and check against some SCRIPTS critical 4059 * sections from the C code. 4060 * 4061 * Hopefully, the interrupt handling of the driver is now 4062 * able to resist to weird BUS error conditions, but donnot 4063 * ask me for any guarantee that it will never fail. :-) 4064 * Use at your own decision and risk. 4065 */ 4066 4067 static void sym_intr1 (hcb_p np) 4068 { 4069 u_char istat, istatc; 4070 u_char dstat; 4071 u_short sist; 4072 4073 /* 4074 * interrupt on the fly ? 4075 * 4076 * A `dummy read' is needed to ensure that the 4077 * clear of the INTF flag reaches the device 4078 * before the scanning of the DONE queue. 4079 */ 4080 istat = INB (nc_istat); 4081 if (istat & INTF) { 4082 OUTB (nc_istat, (istat & SIGP) | INTF | np->istat_sem); 4083 istat = INB (nc_istat); /* DUMMY READ */ 4084 if (DEBUG_FLAGS & DEBUG_TINY) printf ("F "); 4085 (void)sym_wakeup_done (np); 4086 }; 4087 4088 if (!(istat & (SIP|DIP))) 4089 return; 4090 4091 #if 0 /* We should never get this one */ 4092 if (istat & CABRT) 4093 OUTB (nc_istat, CABRT); 4094 #endif 4095 4096 /* 4097 * PAR and MA interrupts may occur at the same time, 4098 * and we need to know of both in order to handle 4099 * this situation properly. We try to unstack SCSI 4100 * interrupts for that reason. BTW, I dislike a LOT 4101 * such a loop inside the interrupt routine. 4102 * Even if DMA interrupt stacking is very unlikely to 4103 * happen, we also try unstacking these ones, since 4104 * this has no performance impact. 4105 */ 4106 sist = 0; 4107 dstat = 0; 4108 istatc = istat; 4109 do { 4110 if (istatc & SIP) 4111 sist |= INW (nc_sist); 4112 if (istatc & DIP) 4113 dstat |= INB (nc_dstat); 4114 istatc = INB (nc_istat); 4115 istat |= istatc; 4116 } while (istatc & (SIP|DIP)); 4117 4118 if (DEBUG_FLAGS & DEBUG_TINY) 4119 printf ("<%d|%x:%x|%x:%x>", 4120 (int)INB(nc_scr0), 4121 dstat,sist, 4122 (unsigned)INL(nc_dsp), 4123 (unsigned)INL(nc_dbc)); 4124 /* 4125 * On paper, a memory barrier may be needed here. 4126 * And since we are paranoid ... :) 4127 */ 4128 MEMORY_BARRIER(); 4129 4130 /* 4131 * First, interrupts we want to service cleanly. 4132 * 4133 * Phase mismatch (MA) is the most frequent interrupt 4134 * for chip earlier than the 896 and so we have to service 4135 * it as quickly as possible. 4136 * A SCSI parity error (PAR) may be combined with a phase 4137 * mismatch condition (MA). 4138 * Programmed interrupts (SIR) are used to call the C code 4139 * from SCRIPTS. 4140 * The single step interrupt (SSI) is not used in this 4141 * driver. 4142 */ 4143 if (!(sist & (STO|GEN|HTH|SGE|UDC|SBMC|RST)) && 4144 !(dstat & (MDPE|BF|ABRT|IID))) { 4145 if (sist & PAR) sym_int_par (np, sist); 4146 else if (sist & MA) sym_int_ma (np); 4147 else if (dstat & SIR) sym_int_sir (np); 4148 else if (dstat & SSI) OUTONB_STD (); 4149 else goto unknown_int; 4150 return; 4151 }; 4152 4153 /* 4154 * Now, interrupts that donnot happen in normal 4155 * situations and that we may need to recover from. 4156 * 4157 * On SCSI RESET (RST), we reset everything. 4158 * On SCSI BUS MODE CHANGE (SBMC), we complete all 4159 * active CCBs with RESET status, prepare all devices 4160 * for negotiating again and restart the SCRIPTS. 4161 * On STO and UDC, we complete the CCB with the corres- 4162 * ponding status and restart the SCRIPTS. 4163 */ 4164 if (sist & RST) { 4165 xpt_print_path(np->path); 4166 printf("SCSI BUS reset detected.\n"); 4167 sym_init (np, 1); 4168 return; 4169 }; 4170 4171 OUTB (nc_ctest3, np->rv_ctest3 | CLF); /* clear dma fifo */ 4172 OUTB (nc_stest3, TE|CSF); /* clear scsi fifo */ 4173 4174 if (!(sist & (GEN|HTH|SGE)) && 4175 !(dstat & (MDPE|BF|ABRT|IID))) { 4176 if (sist & SBMC) sym_int_sbmc (np); 4177 else if (sist & STO) sym_int_sto (np); 4178 else if (sist & UDC) sym_int_udc (np); 4179 else goto unknown_int; 4180 return; 4181 }; 4182 4183 /* 4184 * Now, interrupts we are not able to recover cleanly. 4185 * 4186 * Log message for hard errors. 4187 * Reset everything. 4188 */ 4189 4190 sym_log_hard_error(np, sist, dstat); 4191 4192 if ((sist & (GEN|HTH|SGE)) || 4193 (dstat & (MDPE|BF|ABRT|IID))) { 4194 sym_start_reset(np); 4195 return; 4196 }; 4197 4198 unknown_int: 4199 /* 4200 * We just miss the cause of the interrupt. :( 4201 * Print a message. The timeout will do the real work. 4202 */ 4203 printf( "%s: unknown interrupt(s) ignored, " 4204 "ISTAT=0x%x DSTAT=0x%x SIST=0x%x\n", 4205 sym_name(np), istat, dstat, sist); 4206 } 4207 4208 static void sym_intr(void *arg) 4209 { 4210 if (DEBUG_FLAGS & DEBUG_TINY) printf ("["); 4211 sym_intr1((hcb_p) arg); 4212 if (DEBUG_FLAGS & DEBUG_TINY) printf ("]"); 4213 return; 4214 } 4215 4216 static void sym_poll(struct cam_sim *sim) 4217 { 4218 int s = splcam(); 4219 sym_intr(cam_sim_softc(sim)); 4220 splx(s); 4221 } 4222 4223 4224 /* 4225 * generic recovery from scsi interrupt 4226 * 4227 * The doc says that when the chip gets an SCSI interrupt, 4228 * it tries to stop in an orderly fashion, by completing 4229 * an instruction fetch that had started or by flushing 4230 * the DMA fifo for a write to memory that was executing. 4231 * Such a fashion is not enough to know if the instruction 4232 * that was just before the current DSP value has been 4233 * executed or not. 4234 * 4235 * There are some small SCRIPTS sections that deal with 4236 * the start queue and the done queue that may break any 4237 * assomption from the C code if we are interrupted 4238 * inside, so we reset if this happens. Btw, since these 4239 * SCRIPTS sections are executed while the SCRIPTS hasn't 4240 * started SCSI operations, it is very unlikely to happen. 4241 * 4242 * All the driver data structures are supposed to be 4243 * allocated from the same 4 GB memory window, so there 4244 * is a 1 to 1 relationship between DSA and driver data 4245 * structures. Since we are careful :) to invalidate the 4246 * DSA when we complete a command or when the SCRIPTS 4247 * pushes a DSA into a queue, we can trust it when it 4248 * points to a CCB. 4249 */ 4250 static void sym_recover_scsi_int (hcb_p np, u_char hsts) 4251 { 4252 u32 dsp = INL (nc_dsp); 4253 u32 dsa = INL (nc_dsa); 4254 ccb_p cp = sym_ccb_from_dsa(np, dsa); 4255 4256 /* 4257 * If we haven't been interrupted inside the SCRIPTS 4258 * critical pathes, we can safely restart the SCRIPTS 4259 * and trust the DSA value if it matches a CCB. 4260 */ 4261 if ((!(dsp > SCRIPTA_BA (np, getjob_begin) && 4262 dsp < SCRIPTA_BA (np, getjob_end) + 1)) && 4263 (!(dsp > SCRIPTA_BA (np, ungetjob) && 4264 dsp < SCRIPTA_BA (np, reselect) + 1)) && 4265 (!(dsp > SCRIPTB_BA (np, sel_for_abort) && 4266 dsp < SCRIPTB_BA (np, sel_for_abort_1) + 1)) && 4267 (!(dsp > SCRIPTA_BA (np, done) && 4268 dsp < SCRIPTA_BA (np, done_end) + 1))) { 4269 OUTB (nc_ctest3, np->rv_ctest3 | CLF); /* clear dma fifo */ 4270 OUTB (nc_stest3, TE|CSF); /* clear scsi fifo */ 4271 /* 4272 * If we have a CCB, let the SCRIPTS call us back for 4273 * the handling of the error with SCRATCHA filled with 4274 * STARTPOS. This way, we will be able to freeze the 4275 * device queue and requeue awaiting IOs. 4276 */ 4277 if (cp) { 4278 cp->host_status = hsts; 4279 OUTL_DSP (SCRIPTA_BA (np, complete_error)); 4280 } 4281 /* 4282 * Otherwise just restart the SCRIPTS. 4283 */ 4284 else { 4285 OUTL (nc_dsa, 0xffffff); 4286 OUTL_DSP (SCRIPTA_BA (np, start)); 4287 } 4288 } 4289 else 4290 goto reset_all; 4291 4292 return; 4293 4294 reset_all: 4295 sym_start_reset(np); 4296 } 4297 4298 /* 4299 * chip exception handler for selection timeout 4300 */ 4301 static void sym_int_sto (hcb_p np) 4302 { 4303 u32 dsp = INL (nc_dsp); 4304 4305 if (DEBUG_FLAGS & DEBUG_TINY) printf ("T"); 4306 4307 if (dsp == SCRIPTA_BA (np, wf_sel_done) + 8) 4308 sym_recover_scsi_int(np, HS_SEL_TIMEOUT); 4309 else 4310 sym_start_reset(np); 4311 } 4312 4313 /* 4314 * chip exception handler for unexpected disconnect 4315 */ 4316 static void sym_int_udc (hcb_p np) 4317 { 4318 printf ("%s: unexpected disconnect\n", sym_name(np)); 4319 sym_recover_scsi_int(np, HS_UNEXPECTED); 4320 } 4321 4322 /* 4323 * chip exception handler for SCSI bus mode change 4324 * 4325 * spi2-r12 11.2.3 says a transceiver mode change must 4326 * generate a reset event and a device that detects a reset 4327 * event shall initiate a hard reset. It says also that a 4328 * device that detects a mode change shall set data transfer 4329 * mode to eight bit asynchronous, etc... 4330 * So, just reinitializing all except chip should be enough. 4331 */ 4332 static void sym_int_sbmc (hcb_p np) 4333 { 4334 u_char scsi_mode = INB (nc_stest4) & SMODE; 4335 4336 /* 4337 * Notify user. 4338 */ 4339 xpt_print_path(np->path); 4340 printf("SCSI BUS mode change from %s to %s.\n", 4341 sym_scsi_bus_mode(np->scsi_mode), sym_scsi_bus_mode(scsi_mode)); 4342 4343 /* 4344 * Should suspend command processing for a few seconds and 4345 * reinitialize all except the chip. 4346 */ 4347 sym_init (np, 2); 4348 } 4349 4350 /* 4351 * chip exception handler for SCSI parity error. 4352 * 4353 * When the chip detects a SCSI parity error and is 4354 * currently executing a (CH)MOV instruction, it does 4355 * not interrupt immediately, but tries to finish the 4356 * transfer of the current scatter entry before 4357 * interrupting. The following situations may occur: 4358 * 4359 * - The complete scatter entry has been transferred 4360 * without the device having changed phase. 4361 * The chip will then interrupt with the DSP pointing 4362 * to the instruction that follows the MOV. 4363 * 4364 * - A phase mismatch occurs before the MOV finished 4365 * and phase errors are to be handled by the C code. 4366 * The chip will then interrupt with both PAR and MA 4367 * conditions set. 4368 * 4369 * - A phase mismatch occurs before the MOV finished and 4370 * phase errors are to be handled by SCRIPTS. 4371 * The chip will load the DSP with the phase mismatch 4372 * JUMP address and interrupt the host processor. 4373 */ 4374 static void sym_int_par (hcb_p np, u_short sist) 4375 { 4376 u_char hsts = INB (HS_PRT); 4377 u32 dsp = INL (nc_dsp); 4378 u32 dbc = INL (nc_dbc); 4379 u32 dsa = INL (nc_dsa); 4380 u_char sbcl = INB (nc_sbcl); 4381 u_char cmd = dbc >> 24; 4382 int phase = cmd & 7; 4383 ccb_p cp = sym_ccb_from_dsa(np, dsa); 4384 4385 printf("%s: SCSI parity error detected: SCR1=%d DBC=%x SBCL=%x\n", 4386 sym_name(np), hsts, dbc, sbcl); 4387 4388 /* 4389 * Check that the chip is connected to the SCSI BUS. 4390 */ 4391 if (!(INB (nc_scntl1) & ISCON)) { 4392 sym_recover_scsi_int(np, HS_UNEXPECTED); 4393 return; 4394 } 4395 4396 /* 4397 * If the nexus is not clearly identified, reset the bus. 4398 * We will try to do better later. 4399 */ 4400 if (!cp) 4401 goto reset_all; 4402 4403 /* 4404 * Check instruction was a MOV, direction was INPUT and 4405 * ATN is asserted. 4406 */ 4407 if ((cmd & 0xc0) || !(phase & 1) || !(sbcl & 0x8)) 4408 goto reset_all; 4409 4410 /* 4411 * Keep track of the parity error. 4412 */ 4413 OUTONB (HF_PRT, HF_EXT_ERR); 4414 cp->xerr_status |= XE_PARITY_ERR; 4415 4416 /* 4417 * Prepare the message to send to the device. 4418 */ 4419 np->msgout[0] = (phase == 7) ? M_PARITY : M_ID_ERROR; 4420 4421 /* 4422 * If the old phase was DATA IN phase, we have to deal with 4423 * the 3 situations described above. 4424 * For other input phases (MSG IN and STATUS), the device 4425 * must resend the whole thing that failed parity checking 4426 * or signal error. So, jumping to dispatcher should be OK. 4427 */ 4428 if (phase == 1 || phase == 5) { 4429 /* Phase mismatch handled by SCRIPTS */ 4430 if (dsp == SCRIPTB_BA (np, pm_handle)) 4431 OUTL_DSP (dsp); 4432 /* Phase mismatch handled by the C code */ 4433 else if (sist & MA) 4434 sym_int_ma (np); 4435 /* No phase mismatch occurred */ 4436 else { 4437 OUTL (nc_temp, dsp); 4438 OUTL_DSP (SCRIPTA_BA (np, dispatch)); 4439 } 4440 } 4441 else 4442 OUTL_DSP (SCRIPTA_BA (np, clrack)); 4443 return; 4444 4445 reset_all: 4446 sym_start_reset(np); 4447 return; 4448 } 4449 4450 /* 4451 * chip exception handler for phase errors. 4452 * 4453 * We have to construct a new transfer descriptor, 4454 * to transfer the rest of the current block. 4455 */ 4456 static void sym_int_ma (hcb_p np) 4457 { 4458 u32 dbc; 4459 u32 rest; 4460 u32 dsp; 4461 u32 dsa; 4462 u32 nxtdsp; 4463 u32 *vdsp; 4464 u32 oadr, olen; 4465 u32 *tblp; 4466 u32 newcmd; 4467 u_int delta; 4468 u_char cmd; 4469 u_char hflags, hflags0; 4470 struct sym_pmc *pm; 4471 ccb_p cp; 4472 4473 dsp = INL (nc_dsp); 4474 dbc = INL (nc_dbc); 4475 dsa = INL (nc_dsa); 4476 4477 cmd = dbc >> 24; 4478 rest = dbc & 0xffffff; 4479 delta = 0; 4480 4481 /* 4482 * locate matching cp if any. 4483 */ 4484 cp = sym_ccb_from_dsa(np, dsa); 4485 4486 /* 4487 * Donnot take into account dma fifo and various buffers in 4488 * INPUT phase since the chip flushes everything before 4489 * raising the MA interrupt for interrupted INPUT phases. 4490 * For DATA IN phase, we will check for the SWIDE later. 4491 */ 4492 if ((cmd & 7) != 1 && (cmd & 7) != 5) { 4493 u_char ss0, ss2; 4494 4495 if (np->features & FE_DFBC) 4496 delta = INW (nc_dfbc); 4497 else { 4498 u32 dfifo; 4499 4500 /* 4501 * Read DFIFO, CTEST[4-6] using 1 PCI bus ownership. 4502 */ 4503 dfifo = INL(nc_dfifo); 4504 4505 /* 4506 * Calculate remaining bytes in DMA fifo. 4507 * (CTEST5 = dfifo >> 16) 4508 */ 4509 if (dfifo & (DFS << 16)) 4510 delta = ((((dfifo >> 8) & 0x300) | 4511 (dfifo & 0xff)) - rest) & 0x3ff; 4512 else 4513 delta = ((dfifo & 0xff) - rest) & 0x7f; 4514 } 4515 4516 /* 4517 * The data in the dma fifo has not been transfered to 4518 * the target -> add the amount to the rest 4519 * and clear the data. 4520 * Check the sstat2 register in case of wide transfer. 4521 */ 4522 rest += delta; 4523 ss0 = INB (nc_sstat0); 4524 if (ss0 & OLF) rest++; 4525 if (!(np->features & FE_C10)) 4526 if (ss0 & ORF) rest++; 4527 if (cp && (cp->phys.select.sel_scntl3 & EWS)) { 4528 ss2 = INB (nc_sstat2); 4529 if (ss2 & OLF1) rest++; 4530 if (!(np->features & FE_C10)) 4531 if (ss2 & ORF1) rest++; 4532 }; 4533 4534 /* 4535 * Clear fifos. 4536 */ 4537 OUTB (nc_ctest3, np->rv_ctest3 | CLF); /* dma fifo */ 4538 OUTB (nc_stest3, TE|CSF); /* scsi fifo */ 4539 } 4540 4541 /* 4542 * log the information 4543 */ 4544 if (DEBUG_FLAGS & (DEBUG_TINY|DEBUG_PHASE)) 4545 printf ("P%x%x RL=%d D=%d ", cmd&7, INB(nc_sbcl)&7, 4546 (unsigned) rest, (unsigned) delta); 4547 4548 /* 4549 * try to find the interrupted script command, 4550 * and the address at which to continue. 4551 */ 4552 vdsp = 0; 4553 nxtdsp = 0; 4554 if (dsp > np->scripta_ba && 4555 dsp <= np->scripta_ba + np->scripta_sz) { 4556 vdsp = (u32 *)((char*)np->scripta0 + (dsp-np->scripta_ba-8)); 4557 nxtdsp = dsp; 4558 } 4559 else if (dsp > np->scriptb_ba && 4560 dsp <= np->scriptb_ba + np->scriptb_sz) { 4561 vdsp = (u32 *)((char*)np->scriptb0 + (dsp-np->scriptb_ba-8)); 4562 nxtdsp = dsp; 4563 } 4564 4565 /* 4566 * log the information 4567 */ 4568 if (DEBUG_FLAGS & DEBUG_PHASE) { 4569 printf ("\nCP=%p DSP=%x NXT=%x VDSP=%p CMD=%x ", 4570 cp, (unsigned)dsp, (unsigned)nxtdsp, vdsp, cmd); 4571 }; 4572 4573 if (!vdsp) { 4574 printf ("%s: interrupted SCRIPT address not found.\n", 4575 sym_name (np)); 4576 goto reset_all; 4577 } 4578 4579 if (!cp) { 4580 printf ("%s: SCSI phase error fixup: CCB already dequeued.\n", 4581 sym_name (np)); 4582 goto reset_all; 4583 } 4584 4585 /* 4586 * get old startaddress and old length. 4587 */ 4588 oadr = scr_to_cpu(vdsp[1]); 4589 4590 if (cmd & 0x10) { /* Table indirect */ 4591 tblp = (u32 *) ((char*) &cp->phys + oadr); 4592 olen = scr_to_cpu(tblp[0]); 4593 oadr = scr_to_cpu(tblp[1]); 4594 } else { 4595 tblp = (u32 *) 0; 4596 olen = scr_to_cpu(vdsp[0]) & 0xffffff; 4597 }; 4598 4599 if (DEBUG_FLAGS & DEBUG_PHASE) { 4600 printf ("OCMD=%x\nTBLP=%p OLEN=%x OADR=%x\n", 4601 (unsigned) (scr_to_cpu(vdsp[0]) >> 24), 4602 tblp, 4603 (unsigned) olen, 4604 (unsigned) oadr); 4605 }; 4606 4607 /* 4608 * check cmd against assumed interrupted script command. 4609 * If dt data phase, the MOVE instruction hasn't bit 4 of 4610 * the phase. 4611 */ 4612 if (((cmd & 2) ? cmd : (cmd & ~4)) != (scr_to_cpu(vdsp[0]) >> 24)) { 4613 PRINT_ADDR(cp); 4614 printf ("internal error: cmd=%02x != %02x=(vdsp[0] >> 24)\n", 4615 (unsigned)cmd, (unsigned)scr_to_cpu(vdsp[0]) >> 24); 4616 4617 goto reset_all; 4618 }; 4619 4620 /* 4621 * if old phase not dataphase, leave here. 4622 */ 4623 if (cmd & 2) { 4624 PRINT_ADDR(cp); 4625 printf ("phase change %x-%x %d@%08x resid=%d.\n", 4626 cmd&7, INB(nc_sbcl)&7, (unsigned)olen, 4627 (unsigned)oadr, (unsigned)rest); 4628 goto unexpected_phase; 4629 }; 4630 4631 /* 4632 * Choose the correct PM save area. 4633 * 4634 * Look at the PM_SAVE SCRIPT if you want to understand 4635 * this stuff. The equivalent code is implemented in 4636 * SCRIPTS for the 895A, 896 and 1010 that are able to 4637 * handle PM from the SCRIPTS processor. 4638 */ 4639 hflags0 = INB (HF_PRT); 4640 hflags = hflags0; 4641 4642 if (hflags & (HF_IN_PM0 | HF_IN_PM1 | HF_DP_SAVED)) { 4643 if (hflags & HF_IN_PM0) 4644 nxtdsp = scr_to_cpu(cp->phys.pm0.ret); 4645 else if (hflags & HF_IN_PM1) 4646 nxtdsp = scr_to_cpu(cp->phys.pm1.ret); 4647 4648 if (hflags & HF_DP_SAVED) 4649 hflags ^= HF_ACT_PM; 4650 } 4651 4652 if (!(hflags & HF_ACT_PM)) { 4653 pm = &cp->phys.pm0; 4654 newcmd = SCRIPTA_BA (np, pm0_data); 4655 } 4656 else { 4657 pm = &cp->phys.pm1; 4658 newcmd = SCRIPTA_BA (np, pm1_data); 4659 } 4660 4661 hflags &= ~(HF_IN_PM0 | HF_IN_PM1 | HF_DP_SAVED); 4662 if (hflags != hflags0) 4663 OUTB (HF_PRT, hflags); 4664 4665 /* 4666 * fillin the phase mismatch context 4667 */ 4668 pm->sg.addr = cpu_to_scr(oadr + olen - rest); 4669 pm->sg.size = cpu_to_scr(rest); 4670 pm->ret = cpu_to_scr(nxtdsp); 4671 4672 /* 4673 * If we have a SWIDE, 4674 * - prepare the address to write the SWIDE from SCRIPTS, 4675 * - compute the SCRIPTS address to restart from, 4676 * - move current data pointer context by one byte. 4677 */ 4678 nxtdsp = SCRIPTA_BA (np, dispatch); 4679 if ((cmd & 7) == 1 && cp && (cp->phys.select.sel_scntl3 & EWS) && 4680 (INB (nc_scntl2) & WSR)) { 4681 u32 tmp; 4682 4683 /* 4684 * Set up the table indirect for the MOVE 4685 * of the residual byte and adjust the data 4686 * pointer context. 4687 */ 4688 tmp = scr_to_cpu(pm->sg.addr); 4689 cp->phys.wresid.addr = cpu_to_scr(tmp); 4690 pm->sg.addr = cpu_to_scr(tmp + 1); 4691 tmp = scr_to_cpu(pm->sg.size); 4692 cp->phys.wresid.size = cpu_to_scr((tmp&0xff000000) | 1); 4693 pm->sg.size = cpu_to_scr(tmp - 1); 4694 4695 /* 4696 * If only the residual byte is to be moved, 4697 * no PM context is needed. 4698 */ 4699 if ((tmp&0xffffff) == 1) 4700 newcmd = pm->ret; 4701 4702 /* 4703 * Prepare the address of SCRIPTS that will 4704 * move the residual byte to memory. 4705 */ 4706 nxtdsp = SCRIPTB_BA (np, wsr_ma_helper); 4707 } 4708 4709 if (DEBUG_FLAGS & DEBUG_PHASE) { 4710 PRINT_ADDR(cp); 4711 printf ("PM %x %x %x / %x %x %x.\n", 4712 hflags0, hflags, newcmd, 4713 (unsigned)scr_to_cpu(pm->sg.addr), 4714 (unsigned)scr_to_cpu(pm->sg.size), 4715 (unsigned)scr_to_cpu(pm->ret)); 4716 } 4717 4718 /* 4719 * Restart the SCRIPTS processor. 4720 */ 4721 OUTL (nc_temp, newcmd); 4722 OUTL_DSP (nxtdsp); 4723 return; 4724 4725 /* 4726 * Unexpected phase changes that occurs when the current phase 4727 * is not a DATA IN or DATA OUT phase are due to error conditions. 4728 * Such event may only happen when the SCRIPTS is using a 4729 * multibyte SCSI MOVE. 4730 * 4731 * Phase change Some possible cause 4732 * 4733 * COMMAND --> MSG IN SCSI parity error detected by target. 4734 * COMMAND --> STATUS Bad command or refused by target. 4735 * MSG OUT --> MSG IN Message rejected by target. 4736 * MSG OUT --> COMMAND Bogus target that discards extended 4737 * negotiation messages. 4738 * 4739 * The code below does not care of the new phase and so 4740 * trusts the target. Why to annoy it ? 4741 * If the interrupted phase is COMMAND phase, we restart at 4742 * dispatcher. 4743 * If a target does not get all the messages after selection, 4744 * the code assumes blindly that the target discards extended 4745 * messages and clears the negotiation status. 4746 * If the target does not want all our response to negotiation, 4747 * we force a SIR_NEGO_PROTO interrupt (it is a hack that avoids 4748 * bloat for such a should_not_happen situation). 4749 * In all other situation, we reset the BUS. 4750 * Are these assumptions reasonnable ? (Wait and see ...) 4751 */ 4752 unexpected_phase: 4753 dsp -= 8; 4754 nxtdsp = 0; 4755 4756 switch (cmd & 7) { 4757 case 2: /* COMMAND phase */ 4758 nxtdsp = SCRIPTA_BA (np, dispatch); 4759 break; 4760 #if 0 4761 case 3: /* STATUS phase */ 4762 nxtdsp = SCRIPTA_BA (np, dispatch); 4763 break; 4764 #endif 4765 case 6: /* MSG OUT phase */ 4766 /* 4767 * If the device may want to use untagged when we want 4768 * tagged, we prepare an IDENTIFY without disc. granted, 4769 * since we will not be able to handle reselect. 4770 * Otherwise, we just don't care. 4771 */ 4772 if (dsp == SCRIPTA_BA (np, send_ident)) { 4773 if (cp->tag != NO_TAG && olen - rest <= 3) { 4774 cp->host_status = HS_BUSY; 4775 np->msgout[0] = M_IDENTIFY | cp->lun; 4776 nxtdsp = SCRIPTB_BA (np, ident_break_atn); 4777 } 4778 else 4779 nxtdsp = SCRIPTB_BA (np, ident_break); 4780 } 4781 else if (dsp == SCRIPTB_BA (np, send_wdtr) || 4782 dsp == SCRIPTB_BA (np, send_sdtr) || 4783 dsp == SCRIPTB_BA (np, send_ppr)) { 4784 nxtdsp = SCRIPTB_BA (np, nego_bad_phase); 4785 } 4786 break; 4787 #if 0 4788 case 7: /* MSG IN phase */ 4789 nxtdsp = SCRIPTA_BA (np, clrack); 4790 break; 4791 #endif 4792 } 4793 4794 if (nxtdsp) { 4795 OUTL_DSP (nxtdsp); 4796 return; 4797 } 4798 4799 reset_all: 4800 sym_start_reset(np); 4801 } 4802 4803 /* 4804 * Dequeue from the START queue all CCBs that match 4805 * a given target/lun/task condition (-1 means all), 4806 * and move them from the BUSY queue to the COMP queue 4807 * with CAM_REQUEUE_REQ status condition. 4808 * This function is used during error handling/recovery. 4809 * It is called with SCRIPTS not running. 4810 */ 4811 static int 4812 sym_dequeue_from_squeue(hcb_p np, int i, int target, int lun, int task) 4813 { 4814 int j; 4815 ccb_p cp; 4816 4817 /* 4818 * Make sure the starting index is within range. 4819 */ 4820 assert((i >= 0) && (i < 2*MAX_QUEUE)); 4821 4822 /* 4823 * Walk until end of START queue and dequeue every job 4824 * that matches the target/lun/task condition. 4825 */ 4826 j = i; 4827 while (i != np->squeueput) { 4828 cp = sym_ccb_from_dsa(np, scr_to_cpu(np->squeue[i])); 4829 assert(cp); 4830 #ifdef SYM_CONF_IARB_SUPPORT 4831 /* Forget hints for IARB, they may be no longer relevant */ 4832 cp->host_flags &= ~HF_HINT_IARB; 4833 #endif 4834 if ((target == -1 || cp->target == target) && 4835 (lun == -1 || cp->lun == lun) && 4836 (task == -1 || cp->tag == task)) { 4837 sym_set_cam_status(cp->cam_ccb, CAM_REQUEUE_REQ); 4838 sym_remque(&cp->link_ccbq); 4839 sym_insque_tail(&cp->link_ccbq, &np->comp_ccbq); 4840 } 4841 else { 4842 if (i != j) 4843 np->squeue[j] = np->squeue[i]; 4844 if ((j += 2) >= MAX_QUEUE*2) j = 0; 4845 } 4846 if ((i += 2) >= MAX_QUEUE*2) i = 0; 4847 } 4848 if (i != j) /* Copy back the idle task if needed */ 4849 np->squeue[j] = np->squeue[i]; 4850 np->squeueput = j; /* Update our current start queue pointer */ 4851 4852 return (i - j) / 2; 4853 } 4854 4855 /* 4856 * Complete all CCBs queued to the COMP queue. 4857 * 4858 * These CCBs are assumed: 4859 * - Not to be referenced either by devices or 4860 * SCRIPTS-related queues and datas. 4861 * - To have to be completed with an error condition 4862 * or requeued. 4863 * 4864 * The device queue freeze count is incremented 4865 * for each CCB that does not prevent this. 4866 * This function is called when all CCBs involved 4867 * in error handling/recovery have been reaped. 4868 */ 4869 static void 4870 sym_flush_comp_queue(hcb_p np, int cam_status) 4871 { 4872 SYM_QUEHEAD *qp; 4873 ccb_p cp; 4874 4875 while ((qp = sym_remque_head(&np->comp_ccbq)) != 0) { 4876 union ccb *ccb; 4877 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 4878 sym_insque_tail(&cp->link_ccbq, &np->busy_ccbq); 4879 /* Leave quiet CCBs waiting for resources */ 4880 if (cp->host_status == HS_WAIT) 4881 continue; 4882 ccb = cp->cam_ccb; 4883 if (cam_status) 4884 sym_set_cam_status(ccb, cam_status); 4885 sym_free_ccb(np, cp); 4886 sym_freeze_cam_ccb(ccb); 4887 sym_xpt_done(np, ccb); 4888 } 4889 } 4890 4891 /* 4892 * chip handler for bad SCSI status condition 4893 * 4894 * In case of bad SCSI status, we unqueue all the tasks 4895 * currently queued to the controller but not yet started 4896 * and then restart the SCRIPTS processor immediately. 4897 * 4898 * QUEUE FULL and BUSY conditions are handled the same way. 4899 * Basically all the not yet started tasks are requeued in 4900 * device queue and the queue is frozen until a completion. 4901 * 4902 * For CHECK CONDITION and COMMAND TERMINATED status, we use 4903 * the CCB of the failed command to prepare a REQUEST SENSE 4904 * SCSI command and queue it to the controller queue. 4905 * 4906 * SCRATCHA is assumed to have been loaded with STARTPOS 4907 * before the SCRIPTS called the C code. 4908 */ 4909 static void sym_sir_bad_scsi_status(hcb_p np, int num, ccb_p cp) 4910 { 4911 tcb_p tp = &np->target[cp->target]; 4912 u32 startp; 4913 u_char s_status = cp->ssss_status; 4914 u_char h_flags = cp->host_flags; 4915 int msglen; 4916 int nego; 4917 int i; 4918 4919 /* 4920 * Compute the index of the next job to start from SCRIPTS. 4921 */ 4922 i = (INL (nc_scratcha) - np->squeue_ba) / 4; 4923 4924 /* 4925 * The last CCB queued used for IARB hint may be 4926 * no longer relevant. Forget it. 4927 */ 4928 #ifdef SYM_CONF_IARB_SUPPORT 4929 if (np->last_cp) 4930 np->last_cp = 0; 4931 #endif 4932 4933 /* 4934 * Now deal with the SCSI status. 4935 */ 4936 switch(s_status) { 4937 case S_BUSY: 4938 case S_QUEUE_FULL: 4939 if (sym_verbose >= 2) { 4940 PRINT_ADDR(cp); 4941 printf (s_status == S_BUSY ? "BUSY" : "QUEUE FULL\n"); 4942 } 4943 default: /* S_INT, S_INT_COND_MET, S_CONFLICT */ 4944 sym_complete_error (np, cp); 4945 break; 4946 case S_TERMINATED: 4947 case S_CHECK_COND: 4948 /* 4949 * If we get an SCSI error when requesting sense, give up. 4950 */ 4951 if (h_flags & HF_SENSE) { 4952 sym_complete_error (np, cp); 4953 break; 4954 } 4955 4956 /* 4957 * Dequeue all queued CCBs for that device not yet started, 4958 * and restart the SCRIPTS processor immediately. 4959 */ 4960 (void) sym_dequeue_from_squeue(np, i, cp->target, cp->lun, -1); 4961 OUTL_DSP (SCRIPTA_BA (np, start)); 4962 4963 /* 4964 * Save some info of the actual IO. 4965 * Compute the data residual. 4966 */ 4967 cp->sv_scsi_status = cp->ssss_status; 4968 cp->sv_xerr_status = cp->xerr_status; 4969 cp->sv_resid = sym_compute_residual(np, cp); 4970 4971 /* 4972 * Prepare all needed data structures for 4973 * requesting sense data. 4974 */ 4975 4976 /* 4977 * identify message 4978 */ 4979 cp->scsi_smsg2[0] = M_IDENTIFY | cp->lun; 4980 msglen = 1; 4981 4982 /* 4983 * If we are currently using anything different from 4984 * async. 8 bit data transfers with that target, 4985 * start a negotiation, since the device may want 4986 * to report us a UNIT ATTENTION condition due to 4987 * a cause we currently ignore, and we donnot want 4988 * to be stuck with WIDE and/or SYNC data transfer. 4989 * 4990 * cp->nego_status is filled by sym_prepare_nego(). 4991 */ 4992 cp->nego_status = 0; 4993 nego = 0; 4994 if (tp->tinfo.current.options & PPR_OPT_MASK) 4995 nego = NS_PPR; 4996 else if (tp->tinfo.current.width != BUS_8_BIT) 4997 nego = NS_WIDE; 4998 else if (tp->tinfo.current.offset != 0) 4999 nego = NS_SYNC; 5000 if (nego) 5001 msglen += 5002 sym_prepare_nego (np,cp, nego, &cp->scsi_smsg2[msglen]); 5003 /* 5004 * Message table indirect structure. 5005 */ 5006 cp->phys.smsg.addr = cpu_to_scr(CCB_BA (cp, scsi_smsg2)); 5007 cp->phys.smsg.size = cpu_to_scr(msglen); 5008 5009 /* 5010 * sense command 5011 */ 5012 cp->phys.cmd.addr = cpu_to_scr(CCB_BA (cp, sensecmd)); 5013 cp->phys.cmd.size = cpu_to_scr(6); 5014 5015 /* 5016 * patch requested size into sense command 5017 */ 5018 cp->sensecmd[0] = 0x03; 5019 cp->sensecmd[1] = cp->lun << 5; 5020 #ifdef FreeBSD_New_Tran_Settings 5021 if (tp->tinfo.current.scsi_version > 2 || cp->lun > 7) 5022 cp->sensecmd[1] = 0; 5023 #endif 5024 cp->sensecmd[4] = SYM_SNS_BBUF_LEN; 5025 cp->data_len = SYM_SNS_BBUF_LEN; 5026 5027 /* 5028 * sense data 5029 */ 5030 bzero(cp->sns_bbuf, SYM_SNS_BBUF_LEN); 5031 cp->phys.sense.addr = cpu_to_scr(vtobus(cp->sns_bbuf)); 5032 cp->phys.sense.size = cpu_to_scr(SYM_SNS_BBUF_LEN); 5033 5034 /* 5035 * requeue the command. 5036 */ 5037 startp = SCRIPTB_BA (np, sdata_in); 5038 5039 cp->phys.head.savep = cpu_to_scr(startp); 5040 cp->phys.head.goalp = cpu_to_scr(startp + 16); 5041 cp->phys.head.lastp = cpu_to_scr(startp); 5042 cp->startp = cpu_to_scr(startp); 5043 5044 cp->actualquirks = SYM_QUIRK_AUTOSAVE; 5045 cp->host_status = cp->nego_status ? HS_NEGOTIATE : HS_BUSY; 5046 cp->ssss_status = S_ILLEGAL; 5047 cp->host_flags = (HF_SENSE|HF_DATA_IN); 5048 cp->xerr_status = 0; 5049 cp->extra_bytes = 0; 5050 5051 cp->phys.head.go.start = cpu_to_scr(SCRIPTA_BA (np, select)); 5052 5053 /* 5054 * Requeue the command. 5055 */ 5056 sym_put_start_queue(np, cp); 5057 5058 /* 5059 * Give back to upper layer everything we have dequeued. 5060 */ 5061 sym_flush_comp_queue(np, 0); 5062 break; 5063 } 5064 } 5065 5066 /* 5067 * After a device has accepted some management message 5068 * as BUS DEVICE RESET, ABORT TASK, etc ..., or when 5069 * a device signals a UNIT ATTENTION condition, some 5070 * tasks are thrown away by the device. We are required 5071 * to reflect that on our tasks list since the device 5072 * will never complete these tasks. 5073 * 5074 * This function move from the BUSY queue to the COMP 5075 * queue all disconnected CCBs for a given target that 5076 * match the following criteria: 5077 * - lun=-1 means any logical UNIT otherwise a given one. 5078 * - task=-1 means any task, otherwise a given one. 5079 */ 5080 static int 5081 sym_clear_tasks(hcb_p np, int cam_status, int target, int lun, int task) 5082 { 5083 SYM_QUEHEAD qtmp, *qp; 5084 int i = 0; 5085 ccb_p cp; 5086 5087 /* 5088 * Move the entire BUSY queue to our temporary queue. 5089 */ 5090 sym_que_init(&qtmp); 5091 sym_que_splice(&np->busy_ccbq, &qtmp); 5092 sym_que_init(&np->busy_ccbq); 5093 5094 /* 5095 * Put all CCBs that matches our criteria into 5096 * the COMP queue and put back other ones into 5097 * the BUSY queue. 5098 */ 5099 while ((qp = sym_remque_head(&qtmp)) != 0) { 5100 union ccb *ccb; 5101 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 5102 ccb = cp->cam_ccb; 5103 if (cp->host_status != HS_DISCONNECT || 5104 cp->target != target || 5105 (lun != -1 && cp->lun != lun) || 5106 (task != -1 && 5107 (cp->tag != NO_TAG && cp->scsi_smsg[2] != task))) { 5108 sym_insque_tail(&cp->link_ccbq, &np->busy_ccbq); 5109 continue; 5110 } 5111 sym_insque_tail(&cp->link_ccbq, &np->comp_ccbq); 5112 5113 /* Preserve the software timeout condition */ 5114 if (sym_get_cam_status(ccb) != CAM_CMD_TIMEOUT) 5115 sym_set_cam_status(ccb, cam_status); 5116 ++i; 5117 #if 0 5118 printf("XXXX TASK @%p CLEARED\n", cp); 5119 #endif 5120 } 5121 return i; 5122 } 5123 5124 /* 5125 * chip handler for TASKS recovery 5126 * 5127 * We cannot safely abort a command, while the SCRIPTS 5128 * processor is running, since we just would be in race 5129 * with it. 5130 * 5131 * As long as we have tasks to abort, we keep the SEM 5132 * bit set in the ISTAT. When this bit is set, the 5133 * SCRIPTS processor interrupts (SIR_SCRIPT_STOPPED) 5134 * each time it enters the scheduler. 5135 * 5136 * If we have to reset a target, clear tasks of a unit, 5137 * or to perform the abort of a disconnected job, we 5138 * restart the SCRIPTS for selecting the target. Once 5139 * selected, the SCRIPTS interrupts (SIR_TARGET_SELECTED). 5140 * If it loses arbitration, the SCRIPTS will interrupt again 5141 * the next time it will enter its scheduler, and so on ... 5142 * 5143 * On SIR_TARGET_SELECTED, we scan for the more 5144 * appropriate thing to do: 5145 * 5146 * - If nothing, we just sent a M_ABORT message to the 5147 * target to get rid of the useless SCSI bus ownership. 5148 * According to the specs, no tasks shall be affected. 5149 * - If the target is to be reset, we send it a M_RESET 5150 * message. 5151 * - If a logical UNIT is to be cleared , we send the 5152 * IDENTIFY(lun) + M_ABORT. 5153 * - If an untagged task is to be aborted, we send the 5154 * IDENTIFY(lun) + M_ABORT. 5155 * - If a tagged task is to be aborted, we send the 5156 * IDENTIFY(lun) + task attributes + M_ABORT_TAG. 5157 * 5158 * Once our 'kiss of death' :) message has been accepted 5159 * by the target, the SCRIPTS interrupts again 5160 * (SIR_ABORT_SENT). On this interrupt, we complete 5161 * all the CCBs that should have been aborted by the 5162 * target according to our message. 5163 */ 5164 static void sym_sir_task_recovery(hcb_p np, int num) 5165 { 5166 SYM_QUEHEAD *qp; 5167 ccb_p cp; 5168 tcb_p tp; 5169 int target=-1, lun=-1, task; 5170 int i, k; 5171 5172 switch(num) { 5173 /* 5174 * The SCRIPTS processor stopped before starting 5175 * the next command in order to allow us to perform 5176 * some task recovery. 5177 */ 5178 case SIR_SCRIPT_STOPPED: 5179 /* 5180 * Do we have any target to reset or unit to clear ? 5181 */ 5182 for (i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) { 5183 tp = &np->target[i]; 5184 if (tp->to_reset || 5185 (tp->lun0p && tp->lun0p->to_clear)) { 5186 target = i; 5187 break; 5188 } 5189 if (!tp->lunmp) 5190 continue; 5191 for (k = 1 ; k < SYM_CONF_MAX_LUN ; k++) { 5192 if (tp->lunmp[k] && tp->lunmp[k]->to_clear) { 5193 target = i; 5194 break; 5195 } 5196 } 5197 if (target != -1) 5198 break; 5199 } 5200 5201 /* 5202 * If not, walk the busy queue for any 5203 * disconnected CCB to be aborted. 5204 */ 5205 if (target == -1) { 5206 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) { 5207 cp = sym_que_entry(qp,struct sym_ccb,link_ccbq); 5208 if (cp->host_status != HS_DISCONNECT) 5209 continue; 5210 if (cp->to_abort) { 5211 target = cp->target; 5212 break; 5213 } 5214 } 5215 } 5216 5217 /* 5218 * If some target is to be selected, 5219 * prepare and start the selection. 5220 */ 5221 if (target != -1) { 5222 tp = &np->target[target]; 5223 np->abrt_sel.sel_id = target; 5224 np->abrt_sel.sel_scntl3 = tp->head.wval; 5225 np->abrt_sel.sel_sxfer = tp->head.sval; 5226 OUTL(nc_dsa, np->hcb_ba); 5227 OUTL_DSP (SCRIPTB_BA (np, sel_for_abort)); 5228 return; 5229 } 5230 5231 /* 5232 * Now look for a CCB to abort that haven't started yet. 5233 * Btw, the SCRIPTS processor is still stopped, so 5234 * we are not in race. 5235 */ 5236 i = 0; 5237 cp = 0; 5238 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) { 5239 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 5240 if (cp->host_status != HS_BUSY && 5241 cp->host_status != HS_NEGOTIATE) 5242 continue; 5243 if (!cp->to_abort) 5244 continue; 5245 #ifdef SYM_CONF_IARB_SUPPORT 5246 /* 5247 * If we are using IMMEDIATE ARBITRATION, we donnot 5248 * want to cancel the last queued CCB, since the 5249 * SCRIPTS may have anticipated the selection. 5250 */ 5251 if (cp == np->last_cp) { 5252 cp->to_abort = 0; 5253 continue; 5254 } 5255 #endif 5256 i = 1; /* Means we have found some */ 5257 break; 5258 } 5259 if (!i) { 5260 /* 5261 * We are done, so we donnot need 5262 * to synchronize with the SCRIPTS anylonger. 5263 * Remove the SEM flag from the ISTAT. 5264 */ 5265 np->istat_sem = 0; 5266 OUTB (nc_istat, SIGP); 5267 break; 5268 } 5269 /* 5270 * Compute index of next position in the start 5271 * queue the SCRIPTS intends to start and dequeue 5272 * all CCBs for that device that haven't been started. 5273 */ 5274 i = (INL (nc_scratcha) - np->squeue_ba) / 4; 5275 i = sym_dequeue_from_squeue(np, i, cp->target, cp->lun, -1); 5276 5277 /* 5278 * Make sure at least our IO to abort has been dequeued. 5279 */ 5280 assert(i && sym_get_cam_status(cp->cam_ccb) == CAM_REQUEUE_REQ); 5281 5282 /* 5283 * Keep track in cam status of the reason of the abort. 5284 */ 5285 if (cp->to_abort == 2) 5286 sym_set_cam_status(cp->cam_ccb, CAM_CMD_TIMEOUT); 5287 else 5288 sym_set_cam_status(cp->cam_ccb, CAM_REQ_ABORTED); 5289 5290 /* 5291 * Complete with error everything that we have dequeued. 5292 */ 5293 sym_flush_comp_queue(np, 0); 5294 break; 5295 /* 5296 * The SCRIPTS processor has selected a target 5297 * we may have some manual recovery to perform for. 5298 */ 5299 case SIR_TARGET_SELECTED: 5300 target = (INB (nc_sdid) & 0xf); 5301 tp = &np->target[target]; 5302 5303 np->abrt_tbl.addr = cpu_to_scr(vtobus(np->abrt_msg)); 5304 5305 /* 5306 * If the target is to be reset, prepare a 5307 * M_RESET message and clear the to_reset flag 5308 * since we donnot expect this operation to fail. 5309 */ 5310 if (tp->to_reset) { 5311 np->abrt_msg[0] = M_RESET; 5312 np->abrt_tbl.size = 1; 5313 tp->to_reset = 0; 5314 break; 5315 } 5316 5317 /* 5318 * Otherwise, look for some logical unit to be cleared. 5319 */ 5320 if (tp->lun0p && tp->lun0p->to_clear) 5321 lun = 0; 5322 else if (tp->lunmp) { 5323 for (k = 1 ; k < SYM_CONF_MAX_LUN ; k++) { 5324 if (tp->lunmp[k] && tp->lunmp[k]->to_clear) { 5325 lun = k; 5326 break; 5327 } 5328 } 5329 } 5330 5331 /* 5332 * If a logical unit is to be cleared, prepare 5333 * an IDENTIFY(lun) + ABORT MESSAGE. 5334 */ 5335 if (lun != -1) { 5336 lcb_p lp = sym_lp(np, tp, lun); 5337 lp->to_clear = 0; /* We donnot expect to fail here */ 5338 np->abrt_msg[0] = M_IDENTIFY | lun; 5339 np->abrt_msg[1] = M_ABORT; 5340 np->abrt_tbl.size = 2; 5341 break; 5342 } 5343 5344 /* 5345 * Otherwise, look for some disconnected job to 5346 * abort for this target. 5347 */ 5348 i = 0; 5349 cp = 0; 5350 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) { 5351 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 5352 if (cp->host_status != HS_DISCONNECT) 5353 continue; 5354 if (cp->target != target) 5355 continue; 5356 if (!cp->to_abort) 5357 continue; 5358 i = 1; /* Means we have some */ 5359 break; 5360 } 5361 5362 /* 5363 * If we have none, probably since the device has 5364 * completed the command before we won abitration, 5365 * send a M_ABORT message without IDENTIFY. 5366 * According to the specs, the device must just 5367 * disconnect the BUS and not abort any task. 5368 */ 5369 if (!i) { 5370 np->abrt_msg[0] = M_ABORT; 5371 np->abrt_tbl.size = 1; 5372 break; 5373 } 5374 5375 /* 5376 * We have some task to abort. 5377 * Set the IDENTIFY(lun) 5378 */ 5379 np->abrt_msg[0] = M_IDENTIFY | cp->lun; 5380 5381 /* 5382 * If we want to abort an untagged command, we 5383 * will send an IDENTIFY + M_ABORT. 5384 * Otherwise (tagged command), we will send 5385 * an IDENTIFY + task attributes + ABORT TAG. 5386 */ 5387 if (cp->tag == NO_TAG) { 5388 np->abrt_msg[1] = M_ABORT; 5389 np->abrt_tbl.size = 2; 5390 } 5391 else { 5392 np->abrt_msg[1] = cp->scsi_smsg[1]; 5393 np->abrt_msg[2] = cp->scsi_smsg[2]; 5394 np->abrt_msg[3] = M_ABORT_TAG; 5395 np->abrt_tbl.size = 4; 5396 } 5397 /* 5398 * Keep track of software timeout condition, since the 5399 * peripheral driver may not count retries on abort 5400 * conditions not due to timeout. 5401 */ 5402 if (cp->to_abort == 2) 5403 sym_set_cam_status(cp->cam_ccb, CAM_CMD_TIMEOUT); 5404 cp->to_abort = 0; /* We donnot expect to fail here */ 5405 break; 5406 5407 /* 5408 * The target has accepted our message and switched 5409 * to BUS FREE phase as we expected. 5410 */ 5411 case SIR_ABORT_SENT: 5412 target = (INB (nc_sdid) & 0xf); 5413 tp = &np->target[target]; 5414 5415 /* 5416 ** If we didn't abort anything, leave here. 5417 */ 5418 if (np->abrt_msg[0] == M_ABORT) 5419 break; 5420 5421 /* 5422 * If we sent a M_RESET, then a hardware reset has 5423 * been performed by the target. 5424 * - Reset everything to async 8 bit 5425 * - Tell ourself to negotiate next time :-) 5426 * - Prepare to clear all disconnected CCBs for 5427 * this target from our task list (lun=task=-1) 5428 */ 5429 lun = -1; 5430 task = -1; 5431 if (np->abrt_msg[0] == M_RESET) { 5432 tp->head.sval = 0; 5433 tp->head.wval = np->rv_scntl3; 5434 tp->head.uval = 0; 5435 tp->tinfo.current.period = 0; 5436 tp->tinfo.current.offset = 0; 5437 tp->tinfo.current.width = BUS_8_BIT; 5438 tp->tinfo.current.options = 0; 5439 } 5440 5441 /* 5442 * Otherwise, check for the LUN and TASK(s) 5443 * concerned by the cancelation. 5444 * If it is not ABORT_TAG then it is CLEAR_QUEUE 5445 * or an ABORT message :-) 5446 */ 5447 else { 5448 lun = np->abrt_msg[0] & 0x3f; 5449 if (np->abrt_msg[1] == M_ABORT_TAG) 5450 task = np->abrt_msg[2]; 5451 } 5452 5453 /* 5454 * Complete all the CCBs the device should have 5455 * aborted due to our 'kiss of death' message. 5456 */ 5457 i = (INL (nc_scratcha) - np->squeue_ba) / 4; 5458 (void) sym_dequeue_from_squeue(np, i, target, lun, -1); 5459 (void) sym_clear_tasks(np, CAM_REQ_ABORTED, target, lun, task); 5460 sym_flush_comp_queue(np, 0); 5461 5462 /* 5463 * If we sent a BDR, make uper layer aware of that. 5464 */ 5465 if (np->abrt_msg[0] == M_RESET) 5466 xpt_async(AC_SENT_BDR, np->path, NULL); 5467 break; 5468 } 5469 5470 /* 5471 * Print to the log the message we intend to send. 5472 */ 5473 if (num == SIR_TARGET_SELECTED) { 5474 PRINT_TARGET(np, target); 5475 sym_printl_hex("control msgout:", np->abrt_msg, 5476 np->abrt_tbl.size); 5477 np->abrt_tbl.size = cpu_to_scr(np->abrt_tbl.size); 5478 } 5479 5480 /* 5481 * Let the SCRIPTS processor continue. 5482 */ 5483 OUTONB_STD (); 5484 } 5485 5486 /* 5487 * Gerard's alchemy:) that deals with with the data 5488 * pointer for both MDP and the residual calculation. 5489 * 5490 * I didn't want to bloat the code by more than 200 5491 * lignes for the handling of both MDP and the residual. 5492 * This has been achieved by using a data pointer 5493 * representation consisting in an index in the data 5494 * array (dp_sg) and a negative offset (dp_ofs) that 5495 * have the following meaning: 5496 * 5497 * - dp_sg = SYM_CONF_MAX_SG 5498 * we are at the end of the data script. 5499 * - dp_sg < SYM_CONF_MAX_SG 5500 * dp_sg points to the next entry of the scatter array 5501 * we want to transfer. 5502 * - dp_ofs < 0 5503 * dp_ofs represents the residual of bytes of the 5504 * previous entry scatter entry we will send first. 5505 * - dp_ofs = 0 5506 * no residual to send first. 5507 * 5508 * The function sym_evaluate_dp() accepts an arbitray 5509 * offset (basically from the MDP message) and returns 5510 * the corresponding values of dp_sg and dp_ofs. 5511 */ 5512 5513 static int sym_evaluate_dp(hcb_p np, ccb_p cp, u32 scr, int *ofs) 5514 { 5515 u32 dp_scr; 5516 int dp_ofs, dp_sg, dp_sgmin; 5517 int tmp; 5518 struct sym_pmc *pm; 5519 5520 /* 5521 * Compute the resulted data pointer in term of a script 5522 * address within some DATA script and a signed byte offset. 5523 */ 5524 dp_scr = scr; 5525 dp_ofs = *ofs; 5526 if (dp_scr == SCRIPTA_BA (np, pm0_data)) 5527 pm = &cp->phys.pm0; 5528 else if (dp_scr == SCRIPTA_BA (np, pm1_data)) 5529 pm = &cp->phys.pm1; 5530 else 5531 pm = 0; 5532 5533 if (pm) { 5534 dp_scr = scr_to_cpu(pm->ret); 5535 dp_ofs -= scr_to_cpu(pm->sg.size); 5536 } 5537 5538 /* 5539 * If we are auto-sensing, then we are done. 5540 */ 5541 if (cp->host_flags & HF_SENSE) { 5542 *ofs = dp_ofs; 5543 return 0; 5544 } 5545 5546 /* 5547 * Deduce the index of the sg entry. 5548 * Keep track of the index of the first valid entry. 5549 * If result is dp_sg = SYM_CONF_MAX_SG, then we are at the 5550 * end of the data. 5551 */ 5552 tmp = scr_to_cpu(cp->phys.head.goalp); 5553 dp_sg = SYM_CONF_MAX_SG; 5554 if (dp_scr != tmp) 5555 dp_sg -= (tmp - 8 - (int)dp_scr) / (2*4); 5556 dp_sgmin = SYM_CONF_MAX_SG - cp->segments; 5557 5558 /* 5559 * Move to the sg entry the data pointer belongs to. 5560 * 5561 * If we are inside the data area, we expect result to be: 5562 * 5563 * Either, 5564 * dp_ofs = 0 and dp_sg is the index of the sg entry 5565 * the data pointer belongs to (or the end of the data) 5566 * Or, 5567 * dp_ofs < 0 and dp_sg is the index of the sg entry 5568 * the data pointer belongs to + 1. 5569 */ 5570 if (dp_ofs < 0) { 5571 int n; 5572 while (dp_sg > dp_sgmin) { 5573 --dp_sg; 5574 tmp = scr_to_cpu(cp->phys.data[dp_sg].size); 5575 n = dp_ofs + (tmp & 0xffffff); 5576 if (n > 0) { 5577 ++dp_sg; 5578 break; 5579 } 5580 dp_ofs = n; 5581 } 5582 } 5583 else if (dp_ofs > 0) { 5584 while (dp_sg < SYM_CONF_MAX_SG) { 5585 tmp = scr_to_cpu(cp->phys.data[dp_sg].size); 5586 dp_ofs -= (tmp & 0xffffff); 5587 ++dp_sg; 5588 if (dp_ofs <= 0) 5589 break; 5590 } 5591 } 5592 5593 /* 5594 * Make sure the data pointer is inside the data area. 5595 * If not, return some error. 5596 */ 5597 if (dp_sg < dp_sgmin || (dp_sg == dp_sgmin && dp_ofs < 0)) 5598 goto out_err; 5599 else if (dp_sg > SYM_CONF_MAX_SG || 5600 (dp_sg == SYM_CONF_MAX_SG && dp_ofs > 0)) 5601 goto out_err; 5602 5603 /* 5604 * Save the extreme pointer if needed. 5605 */ 5606 if (dp_sg > cp->ext_sg || 5607 (dp_sg == cp->ext_sg && dp_ofs > cp->ext_ofs)) { 5608 cp->ext_sg = dp_sg; 5609 cp->ext_ofs = dp_ofs; 5610 } 5611 5612 /* 5613 * Return data. 5614 */ 5615 *ofs = dp_ofs; 5616 return dp_sg; 5617 5618 out_err: 5619 return -1; 5620 } 5621 5622 /* 5623 * chip handler for MODIFY DATA POINTER MESSAGE 5624 * 5625 * We also call this function on IGNORE WIDE RESIDUE 5626 * messages that do not match a SWIDE full condition. 5627 * Btw, we assume in that situation that such a message 5628 * is equivalent to a MODIFY DATA POINTER (offset=-1). 5629 */ 5630 5631 static void sym_modify_dp(hcb_p np, tcb_p tp, ccb_p cp, int ofs) 5632 { 5633 int dp_ofs = ofs; 5634 u32 dp_scr = INL (nc_temp); 5635 u32 dp_ret; 5636 u32 tmp; 5637 u_char hflags; 5638 int dp_sg; 5639 struct sym_pmc *pm; 5640 5641 /* 5642 * Not supported for auto-sense. 5643 */ 5644 if (cp->host_flags & HF_SENSE) 5645 goto out_reject; 5646 5647 /* 5648 * Apply our alchemy:) (see comments in sym_evaluate_dp()), 5649 * to the resulted data pointer. 5650 */ 5651 dp_sg = sym_evaluate_dp(np, cp, dp_scr, &dp_ofs); 5652 if (dp_sg < 0) 5653 goto out_reject; 5654 5655 /* 5656 * And our alchemy:) allows to easily calculate the data 5657 * script address we want to return for the next data phase. 5658 */ 5659 dp_ret = cpu_to_scr(cp->phys.head.goalp); 5660 dp_ret = dp_ret - 8 - (SYM_CONF_MAX_SG - dp_sg) * (2*4); 5661 5662 /* 5663 * If offset / scatter entry is zero we donnot need 5664 * a context for the new current data pointer. 5665 */ 5666 if (dp_ofs == 0) { 5667 dp_scr = dp_ret; 5668 goto out_ok; 5669 } 5670 5671 /* 5672 * Get a context for the new current data pointer. 5673 */ 5674 hflags = INB (HF_PRT); 5675 5676 if (hflags & HF_DP_SAVED) 5677 hflags ^= HF_ACT_PM; 5678 5679 if (!(hflags & HF_ACT_PM)) { 5680 pm = &cp->phys.pm0; 5681 dp_scr = SCRIPTA_BA (np, pm0_data); 5682 } 5683 else { 5684 pm = &cp->phys.pm1; 5685 dp_scr = SCRIPTA_BA (np, pm1_data); 5686 } 5687 5688 hflags &= ~(HF_DP_SAVED); 5689 5690 OUTB (HF_PRT, hflags); 5691 5692 /* 5693 * Set up the new current data pointer. 5694 * ofs < 0 there, and for the next data phase, we 5695 * want to transfer part of the data of the sg entry 5696 * corresponding to index dp_sg-1 prior to returning 5697 * to the main data script. 5698 */ 5699 pm->ret = cpu_to_scr(dp_ret); 5700 tmp = scr_to_cpu(cp->phys.data[dp_sg-1].addr); 5701 tmp += scr_to_cpu(cp->phys.data[dp_sg-1].size) + dp_ofs; 5702 pm->sg.addr = cpu_to_scr(tmp); 5703 pm->sg.size = cpu_to_scr(-dp_ofs); 5704 5705 out_ok: 5706 OUTL (nc_temp, dp_scr); 5707 OUTL_DSP (SCRIPTA_BA (np, clrack)); 5708 return; 5709 5710 out_reject: 5711 OUTL_DSP (SCRIPTB_BA (np, msg_bad)); 5712 } 5713 5714 5715 /* 5716 * chip calculation of the data residual. 5717 * 5718 * As I used to say, the requirement of data residual 5719 * in SCSI is broken, useless and cannot be achieved 5720 * without huge complexity. 5721 * But most OSes and even the official CAM require it. 5722 * When stupidity happens to be so widely spread inside 5723 * a community, it gets hard to convince. 5724 * 5725 * Anyway, I don't care, since I am not going to use 5726 * any software that considers this data residual as 5727 * a relevant information. :) 5728 */ 5729 5730 static int sym_compute_residual(hcb_p np, ccb_p cp) 5731 { 5732 int dp_sg, dp_sgmin, resid = 0; 5733 int dp_ofs = 0; 5734 5735 /* 5736 * Check for some data lost or just thrown away. 5737 * We are not required to be quite accurate in this 5738 * situation. Btw, if we are odd for output and the 5739 * device claims some more data, it may well happen 5740 * than our residual be zero. :-) 5741 */ 5742 if (cp->xerr_status & (XE_EXTRA_DATA|XE_SODL_UNRUN|XE_SWIDE_OVRUN)) { 5743 if (cp->xerr_status & XE_EXTRA_DATA) 5744 resid -= cp->extra_bytes; 5745 if (cp->xerr_status & XE_SODL_UNRUN) 5746 ++resid; 5747 if (cp->xerr_status & XE_SWIDE_OVRUN) 5748 --resid; 5749 } 5750 5751 /* 5752 * If all data has been transferred, 5753 * there is no residual. 5754 */ 5755 if (cp->phys.head.lastp == cp->phys.head.goalp) 5756 return resid; 5757 5758 /* 5759 * If no data transfer occurs, or if the data 5760 * pointer is weird, return full residual. 5761 */ 5762 if (cp->startp == cp->phys.head.lastp || 5763 sym_evaluate_dp(np, cp, scr_to_cpu(cp->phys.head.lastp), 5764 &dp_ofs) < 0) { 5765 return cp->data_len; 5766 } 5767 5768 /* 5769 * If we were auto-sensing, then we are done. 5770 */ 5771 if (cp->host_flags & HF_SENSE) { 5772 return -dp_ofs; 5773 } 5774 5775 /* 5776 * We are now full comfortable in the computation 5777 * of the data residual (2's complement). 5778 */ 5779 dp_sgmin = SYM_CONF_MAX_SG - cp->segments; 5780 resid = -cp->ext_ofs; 5781 for (dp_sg = cp->ext_sg; dp_sg < SYM_CONF_MAX_SG; ++dp_sg) { 5782 u_int tmp = scr_to_cpu(cp->phys.data[dp_sg].size); 5783 resid += (tmp & 0xffffff); 5784 } 5785 5786 /* 5787 * Hopefully, the result is not too wrong. 5788 */ 5789 return resid; 5790 } 5791 5792 /* 5793 * Print out the content of a SCSI message. 5794 */ 5795 5796 static int sym_show_msg (u_char * msg) 5797 { 5798 u_char i; 5799 printf ("%x",*msg); 5800 if (*msg==M_EXTENDED) { 5801 for (i=1;i<8;i++) { 5802 if (i-1>msg[1]) break; 5803 printf ("-%x",msg[i]); 5804 }; 5805 return (i+1); 5806 } else if ((*msg & 0xf0) == 0x20) { 5807 printf ("-%x",msg[1]); 5808 return (2); 5809 }; 5810 return (1); 5811 } 5812 5813 static void sym_print_msg (ccb_p cp, char *label, u_char *msg) 5814 { 5815 PRINT_ADDR(cp); 5816 if (label) 5817 printf ("%s: ", label); 5818 5819 (void) sym_show_msg (msg); 5820 printf (".\n"); 5821 } 5822 5823 /* 5824 * Negotiation for WIDE and SYNCHRONOUS DATA TRANSFER. 5825 * 5826 * When we try to negotiate, we append the negotiation message 5827 * to the identify and (maybe) simple tag message. 5828 * The host status field is set to HS_NEGOTIATE to mark this 5829 * situation. 5830 * 5831 * If the target doesn't answer this message immediately 5832 * (as required by the standard), the SIR_NEGO_FAILED interrupt 5833 * will be raised eventually. 5834 * The handler removes the HS_NEGOTIATE status, and sets the 5835 * negotiated value to the default (async / nowide). 5836 * 5837 * If we receive a matching answer immediately, we check it 5838 * for validity, and set the values. 5839 * 5840 * If we receive a Reject message immediately, we assume the 5841 * negotiation has failed, and fall back to standard values. 5842 * 5843 * If we receive a negotiation message while not in HS_NEGOTIATE 5844 * state, it's a target initiated negotiation. We prepare a 5845 * (hopefully) valid answer, set our parameters, and send back 5846 * this answer to the target. 5847 * 5848 * If the target doesn't fetch the answer (no message out phase), 5849 * we assume the negotiation has failed, and fall back to default 5850 * settings (SIR_NEGO_PROTO interrupt). 5851 * 5852 * When we set the values, we adjust them in all ccbs belonging 5853 * to this target, in the controller's register, and in the "phys" 5854 * field of the controller's struct sym_hcb. 5855 */ 5856 5857 /* 5858 * chip handler for SYNCHRONOUS DATA TRANSFER REQUEST (SDTR) message. 5859 */ 5860 static void sym_sync_nego(hcb_p np, tcb_p tp, ccb_p cp) 5861 { 5862 u_char chg, ofs, per, fak, div; 5863 int req = 1; 5864 5865 /* 5866 * Synchronous request message received. 5867 */ 5868 if (DEBUG_FLAGS & DEBUG_NEGO) { 5869 sym_print_msg(cp, "sync msgin", np->msgin); 5870 }; 5871 5872 /* 5873 * request or answer ? 5874 */ 5875 if (INB (HS_PRT) == HS_NEGOTIATE) { 5876 OUTB (HS_PRT, HS_BUSY); 5877 if (cp->nego_status && cp->nego_status != NS_SYNC) 5878 goto reject_it; 5879 req = 0; 5880 } 5881 5882 /* 5883 * get requested values. 5884 */ 5885 chg = 0; 5886 per = np->msgin[3]; 5887 ofs = np->msgin[4]; 5888 5889 /* 5890 * check values against our limits. 5891 */ 5892 if (ofs) { 5893 if (ofs > np->maxoffs) 5894 {chg = 1; ofs = np->maxoffs;} 5895 if (req) { 5896 if (ofs > tp->tinfo.user.offset) 5897 {chg = 1; ofs = tp->tinfo.user.offset;} 5898 } 5899 } 5900 5901 if (ofs) { 5902 if (per < np->minsync) 5903 {chg = 1; per = np->minsync;} 5904 if (req) { 5905 if (per < tp->tinfo.user.period) 5906 {chg = 1; per = tp->tinfo.user.period;} 5907 } 5908 } 5909 5910 div = fak = 0; 5911 if (ofs && sym_getsync(np, 0, per, &div, &fak) < 0) 5912 goto reject_it; 5913 5914 if (DEBUG_FLAGS & DEBUG_NEGO) { 5915 PRINT_ADDR(cp); 5916 printf ("sdtr: ofs=%d per=%d div=%d fak=%d chg=%d.\n", 5917 ofs, per, div, fak, chg); 5918 } 5919 5920 /* 5921 * This was an answer message 5922 */ 5923 if (req == 0) { 5924 if (chg) /* Answer wasn't acceptable. */ 5925 goto reject_it; 5926 sym_setsync (np, cp, ofs, per, div, fak); 5927 OUTL_DSP (SCRIPTA_BA (np, clrack)); 5928 return; 5929 } 5930 5931 /* 5932 * It was a request. Set value and 5933 * prepare an answer message 5934 */ 5935 sym_setsync (np, cp, ofs, per, div, fak); 5936 5937 np->msgout[0] = M_EXTENDED; 5938 np->msgout[1] = 3; 5939 np->msgout[2] = M_X_SYNC_REQ; 5940 np->msgout[3] = per; 5941 np->msgout[4] = ofs; 5942 5943 cp->nego_status = NS_SYNC; 5944 5945 if (DEBUG_FLAGS & DEBUG_NEGO) { 5946 sym_print_msg(cp, "sync msgout", np->msgout); 5947 } 5948 5949 np->msgin [0] = M_NOOP; 5950 5951 OUTL_DSP (SCRIPTB_BA (np, sdtr_resp)); 5952 return; 5953 reject_it: 5954 sym_setsync (np, cp, 0, 0, 0, 0); 5955 OUTL_DSP (SCRIPTB_BA (np, msg_bad)); 5956 } 5957 5958 /* 5959 * chip handler for PARALLEL PROTOCOL REQUEST (PPR) message. 5960 */ 5961 static void sym_ppr_nego(hcb_p np, tcb_p tp, ccb_p cp) 5962 { 5963 u_char chg, ofs, per, fak, dt, div, wide; 5964 int req = 1; 5965 5966 /* 5967 * Synchronous request message received. 5968 */ 5969 if (DEBUG_FLAGS & DEBUG_NEGO) { 5970 sym_print_msg(cp, "ppr msgin", np->msgin); 5971 }; 5972 5973 /* 5974 * get requested values. 5975 */ 5976 chg = 0; 5977 per = np->msgin[3]; 5978 ofs = np->msgin[5]; 5979 wide = np->msgin[6]; 5980 dt = np->msgin[7] & PPR_OPT_DT; 5981 5982 /* 5983 * request or answer ? 5984 */ 5985 if (INB (HS_PRT) == HS_NEGOTIATE) { 5986 OUTB (HS_PRT, HS_BUSY); 5987 if (cp->nego_status && cp->nego_status != NS_PPR) 5988 goto reject_it; 5989 req = 0; 5990 } 5991 5992 /* 5993 * check values against our limits. 5994 */ 5995 if (wide > np->maxwide) 5996 {chg = 1; wide = np->maxwide;} 5997 if (!wide || !(np->features & FE_ULTRA3)) 5998 dt &= ~PPR_OPT_DT; 5999 if (req) { 6000 if (wide > tp->tinfo.user.width) 6001 {chg = 1; wide = tp->tinfo.user.width;} 6002 } 6003 6004 if (!(np->features & FE_U3EN)) /* Broken U3EN bit not supported */ 6005 dt &= ~PPR_OPT_DT; 6006 6007 if (dt != (np->msgin[7] & PPR_OPT_MASK)) chg = 1; 6008 6009 if (ofs) { 6010 if (dt) { 6011 if (ofs > np->maxoffs_dt) 6012 {chg = 1; ofs = np->maxoffs_dt;} 6013 } 6014 else if (ofs > np->maxoffs) 6015 {chg = 1; ofs = np->maxoffs;} 6016 if (req) { 6017 if (ofs > tp->tinfo.user.offset) 6018 {chg = 1; ofs = tp->tinfo.user.offset;} 6019 } 6020 } 6021 6022 if (ofs) { 6023 if (dt) { 6024 if (per < np->minsync_dt) 6025 {chg = 1; per = np->minsync_dt;} 6026 } 6027 else if (per < np->minsync) 6028 {chg = 1; per = np->minsync;} 6029 if (req) { 6030 if (per < tp->tinfo.user.period) 6031 {chg = 1; per = tp->tinfo.user.period;} 6032 } 6033 } 6034 6035 div = fak = 0; 6036 if (ofs && sym_getsync(np, dt, per, &div, &fak) < 0) 6037 goto reject_it; 6038 6039 if (DEBUG_FLAGS & DEBUG_NEGO) { 6040 PRINT_ADDR(cp); 6041 printf ("ppr: " 6042 "dt=%x ofs=%d per=%d wide=%d div=%d fak=%d chg=%d.\n", 6043 dt, ofs, per, wide, div, fak, chg); 6044 } 6045 6046 /* 6047 * It was an answer. 6048 */ 6049 if (req == 0) { 6050 if (chg) /* Answer wasn't acceptable */ 6051 goto reject_it; 6052 sym_setpprot (np, cp, dt, ofs, per, wide, div, fak); 6053 OUTL_DSP (SCRIPTA_BA (np, clrack)); 6054 return; 6055 } 6056 6057 /* 6058 * It was a request. Set value and 6059 * prepare an answer message 6060 */ 6061 sym_setpprot (np, cp, dt, ofs, per, wide, div, fak); 6062 6063 np->msgout[0] = M_EXTENDED; 6064 np->msgout[1] = 6; 6065 np->msgout[2] = M_X_PPR_REQ; 6066 np->msgout[3] = per; 6067 np->msgout[4] = 0; 6068 np->msgout[5] = ofs; 6069 np->msgout[6] = wide; 6070 np->msgout[7] = dt; 6071 6072 cp->nego_status = NS_PPR; 6073 6074 if (DEBUG_FLAGS & DEBUG_NEGO) { 6075 sym_print_msg(cp, "ppr msgout", np->msgout); 6076 } 6077 6078 np->msgin [0] = M_NOOP; 6079 6080 OUTL_DSP (SCRIPTB_BA (np, ppr_resp)); 6081 return; 6082 reject_it: 6083 sym_setpprot (np, cp, 0, 0, 0, 0, 0, 0); 6084 OUTL_DSP (SCRIPTB_BA (np, msg_bad)); 6085 /* 6086 * If it was a device response that should result in 6087 * ST, we may want to try a legacy negotiation later. 6088 */ 6089 if (!req && !dt) { 6090 tp->tinfo.goal.options = 0; 6091 tp->tinfo.goal.width = wide; 6092 tp->tinfo.goal.period = per; 6093 tp->tinfo.goal.offset = ofs; 6094 } 6095 return; 6096 } 6097 6098 /* 6099 * chip handler for WIDE DATA TRANSFER REQUEST (WDTR) message. 6100 */ 6101 static void sym_wide_nego(hcb_p np, tcb_p tp, ccb_p cp) 6102 { 6103 u_char chg, wide; 6104 int req = 1; 6105 6106 /* 6107 * Wide request message received. 6108 */ 6109 if (DEBUG_FLAGS & DEBUG_NEGO) { 6110 sym_print_msg(cp, "wide msgin", np->msgin); 6111 }; 6112 6113 /* 6114 * Is it a request from the device? 6115 */ 6116 if (INB (HS_PRT) == HS_NEGOTIATE) { 6117 OUTB (HS_PRT, HS_BUSY); 6118 if (cp->nego_status && cp->nego_status != NS_WIDE) 6119 goto reject_it; 6120 req = 0; 6121 } 6122 6123 /* 6124 * get requested values. 6125 */ 6126 chg = 0; 6127 wide = np->msgin[3]; 6128 6129 /* 6130 * check values against driver limits. 6131 */ 6132 if (wide > np->maxwide) 6133 {chg = 1; wide = np->maxwide;} 6134 if (req) { 6135 if (wide > tp->tinfo.user.width) 6136 {chg = 1; wide = tp->tinfo.user.width;} 6137 } 6138 6139 if (DEBUG_FLAGS & DEBUG_NEGO) { 6140 PRINT_ADDR(cp); 6141 printf ("wdtr: wide=%d chg=%d.\n", wide, chg); 6142 } 6143 6144 /* 6145 * This was an answer message 6146 */ 6147 if (req == 0) { 6148 if (chg) /* Answer wasn't acceptable. */ 6149 goto reject_it; 6150 sym_setwide (np, cp, wide); 6151 6152 /* 6153 * Negotiate for SYNC immediately after WIDE response. 6154 * This allows to negotiate for both WIDE and SYNC on 6155 * a single SCSI command (Suggested by Justin Gibbs). 6156 */ 6157 if (tp->tinfo.goal.offset) { 6158 np->msgout[0] = M_EXTENDED; 6159 np->msgout[1] = 3; 6160 np->msgout[2] = M_X_SYNC_REQ; 6161 np->msgout[3] = tp->tinfo.goal.period; 6162 np->msgout[4] = tp->tinfo.goal.offset; 6163 6164 if (DEBUG_FLAGS & DEBUG_NEGO) { 6165 sym_print_msg(cp, "sync msgout", np->msgout); 6166 } 6167 6168 cp->nego_status = NS_SYNC; 6169 OUTB (HS_PRT, HS_NEGOTIATE); 6170 OUTL_DSP (SCRIPTB_BA (np, sdtr_resp)); 6171 return; 6172 } 6173 6174 OUTL_DSP (SCRIPTA_BA (np, clrack)); 6175 return; 6176 }; 6177 6178 /* 6179 * It was a request, set value and 6180 * prepare an answer message 6181 */ 6182 sym_setwide (np, cp, wide); 6183 6184 np->msgout[0] = M_EXTENDED; 6185 np->msgout[1] = 2; 6186 np->msgout[2] = M_X_WIDE_REQ; 6187 np->msgout[3] = wide; 6188 6189 np->msgin [0] = M_NOOP; 6190 6191 cp->nego_status = NS_WIDE; 6192 6193 if (DEBUG_FLAGS & DEBUG_NEGO) { 6194 sym_print_msg(cp, "wide msgout", np->msgout); 6195 } 6196 6197 OUTL_DSP (SCRIPTB_BA (np, wdtr_resp)); 6198 return; 6199 reject_it: 6200 OUTL_DSP (SCRIPTB_BA (np, msg_bad)); 6201 } 6202 6203 /* 6204 * Reset SYNC or WIDE to default settings. 6205 * 6206 * Called when a negotiation does not succeed either 6207 * on rejection or on protocol error. 6208 * 6209 * If it was a PPR that made problems, we may want to 6210 * try a legacy negotiation later. 6211 */ 6212 static void sym_nego_default(hcb_p np, tcb_p tp, ccb_p cp) 6213 { 6214 /* 6215 * any error in negotiation: 6216 * fall back to default mode. 6217 */ 6218 switch (cp->nego_status) { 6219 case NS_PPR: 6220 #if 0 6221 sym_setpprot (np, cp, 0, 0, 0, 0, 0, 0); 6222 #else 6223 tp->tinfo.goal.options = 0; 6224 if (tp->tinfo.goal.period < np->minsync) 6225 tp->tinfo.goal.period = np->minsync; 6226 if (tp->tinfo.goal.offset > np->maxoffs) 6227 tp->tinfo.goal.offset = np->maxoffs; 6228 #endif 6229 break; 6230 case NS_SYNC: 6231 sym_setsync (np, cp, 0, 0, 0, 0); 6232 break; 6233 case NS_WIDE: 6234 sym_setwide (np, cp, 0); 6235 break; 6236 }; 6237 np->msgin [0] = M_NOOP; 6238 np->msgout[0] = M_NOOP; 6239 cp->nego_status = 0; 6240 } 6241 6242 /* 6243 * chip handler for MESSAGE REJECT received in response to 6244 * a WIDE or SYNCHRONOUS negotiation. 6245 */ 6246 static void sym_nego_rejected(hcb_p np, tcb_p tp, ccb_p cp) 6247 { 6248 sym_nego_default(np, tp, cp); 6249 OUTB (HS_PRT, HS_BUSY); 6250 } 6251 6252 /* 6253 * chip exception handler for programmed interrupts. 6254 */ 6255 static void sym_int_sir (hcb_p np) 6256 { 6257 u_char num = INB (nc_dsps); 6258 u32 dsa = INL (nc_dsa); 6259 ccb_p cp = sym_ccb_from_dsa(np, dsa); 6260 u_char target = INB (nc_sdid) & 0x0f; 6261 tcb_p tp = &np->target[target]; 6262 int tmp; 6263 6264 if (DEBUG_FLAGS & DEBUG_TINY) printf ("I#%d", num); 6265 6266 switch (num) { 6267 /* 6268 * Command has been completed with error condition 6269 * or has been auto-sensed. 6270 */ 6271 case SIR_COMPLETE_ERROR: 6272 sym_complete_error(np, cp); 6273 return; 6274 /* 6275 * The C code is currently trying to recover from something. 6276 * Typically, user want to abort some command. 6277 */ 6278 case SIR_SCRIPT_STOPPED: 6279 case SIR_TARGET_SELECTED: 6280 case SIR_ABORT_SENT: 6281 sym_sir_task_recovery(np, num); 6282 return; 6283 /* 6284 * The device didn't go to MSG OUT phase after having 6285 * been selected with ATN. We donnot want to handle 6286 * that. 6287 */ 6288 case SIR_SEL_ATN_NO_MSG_OUT: 6289 printf ("%s:%d: No MSG OUT phase after selection with ATN.\n", 6290 sym_name (np), target); 6291 goto out_stuck; 6292 /* 6293 * The device didn't switch to MSG IN phase after 6294 * having reseleted the initiator. 6295 */ 6296 case SIR_RESEL_NO_MSG_IN: 6297 printf ("%s:%d: No MSG IN phase after reselection.\n", 6298 sym_name (np), target); 6299 goto out_stuck; 6300 /* 6301 * After reselection, the device sent a message that wasn't 6302 * an IDENTIFY. 6303 */ 6304 case SIR_RESEL_NO_IDENTIFY: 6305 printf ("%s:%d: No IDENTIFY after reselection.\n", 6306 sym_name (np), target); 6307 goto out_stuck; 6308 /* 6309 * The device reselected a LUN we donnot know about. 6310 */ 6311 case SIR_RESEL_BAD_LUN: 6312 np->msgout[0] = M_RESET; 6313 goto out; 6314 /* 6315 * The device reselected for an untagged nexus and we 6316 * haven't any. 6317 */ 6318 case SIR_RESEL_BAD_I_T_L: 6319 np->msgout[0] = M_ABORT; 6320 goto out; 6321 /* 6322 * The device reselected for a tagged nexus that we donnot 6323 * have. 6324 */ 6325 case SIR_RESEL_BAD_I_T_L_Q: 6326 np->msgout[0] = M_ABORT_TAG; 6327 goto out; 6328 /* 6329 * The SCRIPTS let us know that the device has grabbed 6330 * our message and will abort the job. 6331 */ 6332 case SIR_RESEL_ABORTED: 6333 np->lastmsg = np->msgout[0]; 6334 np->msgout[0] = M_NOOP; 6335 printf ("%s:%d: message %x sent on bad reselection.\n", 6336 sym_name (np), target, np->lastmsg); 6337 goto out; 6338 /* 6339 * The SCRIPTS let us know that a message has been 6340 * successfully sent to the device. 6341 */ 6342 case SIR_MSG_OUT_DONE: 6343 np->lastmsg = np->msgout[0]; 6344 np->msgout[0] = M_NOOP; 6345 /* Should we really care of that */ 6346 if (np->lastmsg == M_PARITY || np->lastmsg == M_ID_ERROR) { 6347 if (cp) { 6348 cp->xerr_status &= ~XE_PARITY_ERR; 6349 if (!cp->xerr_status) 6350 OUTOFFB (HF_PRT, HF_EXT_ERR); 6351 } 6352 } 6353 goto out; 6354 /* 6355 * The device didn't send a GOOD SCSI status. 6356 * We may have some work to do prior to allow 6357 * the SCRIPTS processor to continue. 6358 */ 6359 case SIR_BAD_SCSI_STATUS: 6360 if (!cp) 6361 goto out; 6362 sym_sir_bad_scsi_status(np, num, cp); 6363 return; 6364 /* 6365 * We are asked by the SCRIPTS to prepare a 6366 * REJECT message. 6367 */ 6368 case SIR_REJECT_TO_SEND: 6369 sym_print_msg(cp, "M_REJECT to send for ", np->msgin); 6370 np->msgout[0] = M_REJECT; 6371 goto out; 6372 /* 6373 * We have been ODD at the end of a DATA IN 6374 * transfer and the device didn't send a 6375 * IGNORE WIDE RESIDUE message. 6376 * It is a data overrun condition. 6377 */ 6378 case SIR_SWIDE_OVERRUN: 6379 if (cp) { 6380 OUTONB (HF_PRT, HF_EXT_ERR); 6381 cp->xerr_status |= XE_SWIDE_OVRUN; 6382 } 6383 goto out; 6384 /* 6385 * We have been ODD at the end of a DATA OUT 6386 * transfer. 6387 * It is a data underrun condition. 6388 */ 6389 case SIR_SODL_UNDERRUN: 6390 if (cp) { 6391 OUTONB (HF_PRT, HF_EXT_ERR); 6392 cp->xerr_status |= XE_SODL_UNRUN; 6393 } 6394 goto out; 6395 /* 6396 * The device wants us to tranfer more data than 6397 * expected or in the wrong direction. 6398 * The number of extra bytes is in scratcha. 6399 * It is a data overrun condition. 6400 */ 6401 case SIR_DATA_OVERRUN: 6402 if (cp) { 6403 OUTONB (HF_PRT, HF_EXT_ERR); 6404 cp->xerr_status |= XE_EXTRA_DATA; 6405 cp->extra_bytes += INL (nc_scratcha); 6406 } 6407 goto out; 6408 /* 6409 * The device switched to an illegal phase (4/5). 6410 */ 6411 case SIR_BAD_PHASE: 6412 if (cp) { 6413 OUTONB (HF_PRT, HF_EXT_ERR); 6414 cp->xerr_status |= XE_BAD_PHASE; 6415 } 6416 goto out; 6417 /* 6418 * We received a message. 6419 */ 6420 case SIR_MSG_RECEIVED: 6421 if (!cp) 6422 goto out_stuck; 6423 switch (np->msgin [0]) { 6424 /* 6425 * We received an extended message. 6426 * We handle MODIFY DATA POINTER, SDTR, WDTR 6427 * and reject all other extended messages. 6428 */ 6429 case M_EXTENDED: 6430 switch (np->msgin [2]) { 6431 case M_X_MODIFY_DP: 6432 if (DEBUG_FLAGS & DEBUG_POINTER) 6433 sym_print_msg(cp,"modify DP",np->msgin); 6434 tmp = (np->msgin[3]<<24) + (np->msgin[4]<<16) + 6435 (np->msgin[5]<<8) + (np->msgin[6]); 6436 sym_modify_dp(np, tp, cp, tmp); 6437 return; 6438 case M_X_SYNC_REQ: 6439 sym_sync_nego(np, tp, cp); 6440 return; 6441 case M_X_PPR_REQ: 6442 sym_ppr_nego(np, tp, cp); 6443 return; 6444 case M_X_WIDE_REQ: 6445 sym_wide_nego(np, tp, cp); 6446 return; 6447 default: 6448 goto out_reject; 6449 } 6450 break; 6451 /* 6452 * We received a 1/2 byte message not handled from SCRIPTS. 6453 * We are only expecting MESSAGE REJECT and IGNORE WIDE 6454 * RESIDUE messages that haven't been anticipated by 6455 * SCRIPTS on SWIDE full condition. Unanticipated IGNORE 6456 * WIDE RESIDUE messages are aliased as MODIFY DP (-1). 6457 */ 6458 case M_IGN_RESIDUE: 6459 if (DEBUG_FLAGS & DEBUG_POINTER) 6460 sym_print_msg(cp,"ign wide residue", np->msgin); 6461 sym_modify_dp(np, tp, cp, -1); 6462 return; 6463 case M_REJECT: 6464 if (INB (HS_PRT) == HS_NEGOTIATE) 6465 sym_nego_rejected(np, tp, cp); 6466 else { 6467 PRINT_ADDR(cp); 6468 printf ("M_REJECT received (%x:%x).\n", 6469 scr_to_cpu(np->lastmsg), np->msgout[0]); 6470 } 6471 goto out_clrack; 6472 break; 6473 default: 6474 goto out_reject; 6475 } 6476 break; 6477 /* 6478 * We received an unknown message. 6479 * Ignore all MSG IN phases and reject it. 6480 */ 6481 case SIR_MSG_WEIRD: 6482 sym_print_msg(cp, "WEIRD message received", np->msgin); 6483 OUTL_DSP (SCRIPTB_BA (np, msg_weird)); 6484 return; 6485 /* 6486 * Negotiation failed. 6487 * Target does not send us the reply. 6488 * Remove the HS_NEGOTIATE status. 6489 */ 6490 case SIR_NEGO_FAILED: 6491 OUTB (HS_PRT, HS_BUSY); 6492 /* 6493 * Negotiation failed. 6494 * Target does not want answer message. 6495 */ 6496 case SIR_NEGO_PROTO: 6497 sym_nego_default(np, tp, cp); 6498 goto out; 6499 }; 6500 6501 out: 6502 OUTONB_STD (); 6503 return; 6504 out_reject: 6505 OUTL_DSP (SCRIPTB_BA (np, msg_bad)); 6506 return; 6507 out_clrack: 6508 OUTL_DSP (SCRIPTA_BA (np, clrack)); 6509 return; 6510 out_stuck: 6511 return; 6512 } 6513 6514 /* 6515 * Acquire a control block 6516 */ 6517 static ccb_p sym_get_ccb (hcb_p np, u_char tn, u_char ln, u_char tag_order) 6518 { 6519 tcb_p tp = &np->target[tn]; 6520 lcb_p lp = sym_lp(np, tp, ln); 6521 u_short tag = NO_TAG; 6522 SYM_QUEHEAD *qp; 6523 ccb_p cp = (ccb_p) 0; 6524 6525 /* 6526 * Look for a free CCB 6527 */ 6528 if (sym_que_empty(&np->free_ccbq)) 6529 (void) sym_alloc_ccb(np); 6530 qp = sym_remque_head(&np->free_ccbq); 6531 if (!qp) 6532 goto out; 6533 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 6534 6535 /* 6536 * If the LCB is not yet available and the LUN 6537 * has been probed ok, try to allocate the LCB. 6538 */ 6539 if (!lp && sym_is_bit(tp->lun_map, ln)) { 6540 lp = sym_alloc_lcb(np, tn, ln); 6541 if (!lp) 6542 goto out_free; 6543 } 6544 6545 /* 6546 * If the LCB is not available here, then the 6547 * logical unit is not yet discovered. For those 6548 * ones only accept 1 SCSI IO per logical unit, 6549 * since we cannot allow disconnections. 6550 */ 6551 if (!lp) { 6552 if (!sym_is_bit(tp->busy0_map, ln)) 6553 sym_set_bit(tp->busy0_map, ln); 6554 else 6555 goto out_free; 6556 } else { 6557 /* 6558 * If we have been asked for a tagged command. 6559 */ 6560 if (tag_order) { 6561 /* 6562 * Debugging purpose. 6563 */ 6564 assert(lp->busy_itl == 0); 6565 /* 6566 * Allocate resources for tags if not yet. 6567 */ 6568 if (!lp->cb_tags) { 6569 sym_alloc_lcb_tags(np, tn, ln); 6570 if (!lp->cb_tags) 6571 goto out_free; 6572 } 6573 /* 6574 * Get a tag for this SCSI IO and set up 6575 * the CCB bus address for reselection, 6576 * and count it for this LUN. 6577 * Toggle reselect path to tagged. 6578 */ 6579 if (lp->busy_itlq < SYM_CONF_MAX_TASK) { 6580 tag = lp->cb_tags[lp->ia_tag]; 6581 if (++lp->ia_tag == SYM_CONF_MAX_TASK) 6582 lp->ia_tag = 0; 6583 lp->itlq_tbl[tag] = cpu_to_scr(cp->ccb_ba); 6584 ++lp->busy_itlq; 6585 lp->head.resel_sa = 6586 cpu_to_scr(SCRIPTA_BA (np, resel_tag)); 6587 } 6588 else 6589 goto out_free; 6590 } 6591 /* 6592 * This command will not be tagged. 6593 * If we already have either a tagged or untagged 6594 * one, refuse to overlap this untagged one. 6595 */ 6596 else { 6597 /* 6598 * Debugging purpose. 6599 */ 6600 assert(lp->busy_itl == 0 && lp->busy_itlq == 0); 6601 /* 6602 * Count this nexus for this LUN. 6603 * Set up the CCB bus address for reselection. 6604 * Toggle reselect path to untagged. 6605 */ 6606 if (++lp->busy_itl == 1) { 6607 lp->head.itl_task_sa = cpu_to_scr(cp->ccb_ba); 6608 lp->head.resel_sa = 6609 cpu_to_scr(SCRIPTA_BA (np, resel_no_tag)); 6610 } 6611 else 6612 goto out_free; 6613 } 6614 } 6615 /* 6616 * Put the CCB into the busy queue. 6617 */ 6618 sym_insque_tail(&cp->link_ccbq, &np->busy_ccbq); 6619 6620 /* 6621 * Remember all informations needed to free this CCB. 6622 */ 6623 cp->to_abort = 0; 6624 cp->tag = tag; 6625 cp->target = tn; 6626 cp->lun = ln; 6627 6628 if (DEBUG_FLAGS & DEBUG_TAGS) { 6629 PRINT_LUN(np, tn, ln); 6630 printf ("ccb @%p using tag %d.\n", cp, tag); 6631 } 6632 6633 out: 6634 return cp; 6635 out_free: 6636 sym_insque_head(&cp->link_ccbq, &np->free_ccbq); 6637 return (ccb_p) 0; 6638 } 6639 6640 /* 6641 * Release one control block 6642 */ 6643 static void sym_free_ccb (hcb_p np, ccb_p cp) 6644 { 6645 tcb_p tp = &np->target[cp->target]; 6646 lcb_p lp = sym_lp(np, tp, cp->lun); 6647 6648 if (DEBUG_FLAGS & DEBUG_TAGS) { 6649 PRINT_LUN(np, cp->target, cp->lun); 6650 printf ("ccb @%p freeing tag %d.\n", cp, cp->tag); 6651 } 6652 6653 /* 6654 * If LCB available, 6655 */ 6656 if (lp) { 6657 /* 6658 * If tagged, release the tag, set the relect path 6659 */ 6660 if (cp->tag != NO_TAG) { 6661 /* 6662 * Free the tag value. 6663 */ 6664 lp->cb_tags[lp->if_tag] = cp->tag; 6665 if (++lp->if_tag == SYM_CONF_MAX_TASK) 6666 lp->if_tag = 0; 6667 /* 6668 * Make the reselect path invalid, 6669 * and uncount this CCB. 6670 */ 6671 lp->itlq_tbl[cp->tag] = cpu_to_scr(np->bad_itlq_ba); 6672 --lp->busy_itlq; 6673 } else { /* Untagged */ 6674 /* 6675 * Make the reselect path invalid, 6676 * and uncount this CCB. 6677 */ 6678 lp->head.itl_task_sa = cpu_to_scr(np->bad_itl_ba); 6679 --lp->busy_itl; 6680 } 6681 /* 6682 * If no JOB active, make the LUN reselect path invalid. 6683 */ 6684 if (lp->busy_itlq == 0 && lp->busy_itl == 0) 6685 lp->head.resel_sa = 6686 cpu_to_scr(SCRIPTB_BA (np, resel_bad_lun)); 6687 } 6688 /* 6689 * Otherwise, we only accept 1 IO per LUN. 6690 * Clear the bit that keeps track of this IO. 6691 */ 6692 else 6693 sym_clr_bit(tp->busy0_map, cp->lun); 6694 6695 /* 6696 * We donnot queue more than 1 ccb per target 6697 * with negotiation at any time. If this ccb was 6698 * used for negotiation, clear this info in the tcb. 6699 */ 6700 if (cp == tp->nego_cp) 6701 tp->nego_cp = 0; 6702 6703 #ifdef SYM_CONF_IARB_SUPPORT 6704 /* 6705 * If we just complete the last queued CCB, 6706 * clear this info that is no longer relevant. 6707 */ 6708 if (cp == np->last_cp) 6709 np->last_cp = 0; 6710 #endif 6711 6712 #ifdef FreeBSD_Bus_Dma_Abstraction 6713 /* 6714 * Unmap user data from DMA map if needed. 6715 */ 6716 if (cp->dmamapped) { 6717 bus_dmamap_unload(np->data_dmat, cp->dmamap); 6718 cp->dmamapped = 0; 6719 } 6720 #endif 6721 6722 /* 6723 * Make this CCB available. 6724 */ 6725 cp->cam_ccb = 0; 6726 cp->host_status = HS_IDLE; 6727 sym_remque(&cp->link_ccbq); 6728 sym_insque_head(&cp->link_ccbq, &np->free_ccbq); 6729 } 6730 6731 /* 6732 * Allocate a CCB from memory and initialize its fixed part. 6733 */ 6734 static ccb_p sym_alloc_ccb(hcb_p np) 6735 { 6736 ccb_p cp = 0; 6737 int hcode; 6738 6739 /* 6740 * Prevent from allocating more CCBs than we can 6741 * queue to the controller. 6742 */ 6743 if (np->actccbs >= SYM_CONF_MAX_START) 6744 return 0; 6745 6746 /* 6747 * Allocate memory for this CCB. 6748 */ 6749 cp = sym_calloc_dma(sizeof(struct sym_ccb), "CCB"); 6750 if (!cp) 6751 goto out_free; 6752 6753 /* 6754 * Allocate a bounce buffer for sense data. 6755 */ 6756 cp->sns_bbuf = sym_calloc_dma(SYM_SNS_BBUF_LEN, "SNS_BBUF"); 6757 if (!cp->sns_bbuf) 6758 goto out_free; 6759 6760 /* 6761 * Allocate a map for the DMA of user data. 6762 */ 6763 #ifdef FreeBSD_Bus_Dma_Abstraction 6764 if (bus_dmamap_create(np->data_dmat, 0, &cp->dmamap)) 6765 goto out_free; 6766 #endif 6767 /* 6768 * Count it. 6769 */ 6770 np->actccbs++; 6771 6772 /* 6773 * Compute the bus address of this ccb. 6774 */ 6775 cp->ccb_ba = vtobus(cp); 6776 6777 /* 6778 * Insert this ccb into the hashed list. 6779 */ 6780 hcode = CCB_HASH_CODE(cp->ccb_ba); 6781 cp->link_ccbh = np->ccbh[hcode]; 6782 np->ccbh[hcode] = cp; 6783 6784 /* 6785 * Initialyze the start and restart actions. 6786 */ 6787 cp->phys.head.go.start = cpu_to_scr(SCRIPTA_BA (np, idle)); 6788 cp->phys.head.go.restart = cpu_to_scr(SCRIPTB_BA (np, bad_i_t_l)); 6789 6790 /* 6791 * Initilialyze some other fields. 6792 */ 6793 cp->phys.smsg_ext.addr = cpu_to_scr(HCB_BA(np, msgin[2])); 6794 6795 /* 6796 * Chain into free ccb queue. 6797 */ 6798 sym_insque_head(&cp->link_ccbq, &np->free_ccbq); 6799 6800 return cp; 6801 out_free: 6802 if (cp) { 6803 if (cp->sns_bbuf) 6804 sym_mfree_dma(cp->sns_bbuf,SYM_SNS_BBUF_LEN,"SNS_BBUF"); 6805 sym_mfree_dma(cp, sizeof(*cp), "CCB"); 6806 } 6807 return 0; 6808 } 6809 6810 /* 6811 * Look up a CCB from a DSA value. 6812 */ 6813 static ccb_p sym_ccb_from_dsa(hcb_p np, u32 dsa) 6814 { 6815 int hcode; 6816 ccb_p cp; 6817 6818 hcode = CCB_HASH_CODE(dsa); 6819 cp = np->ccbh[hcode]; 6820 while (cp) { 6821 if (cp->ccb_ba == dsa) 6822 break; 6823 cp = cp->link_ccbh; 6824 } 6825 6826 return cp; 6827 } 6828 6829 /* 6830 * Target control block initialisation. 6831 * Nothing important to do at the moment. 6832 */ 6833 static void sym_init_tcb (hcb_p np, u_char tn) 6834 { 6835 /* 6836 * Check some alignments required by the chip. 6837 */ 6838 assert (((offsetof(struct sym_reg, nc_sxfer) ^ 6839 offsetof(struct sym_tcb, head.sval)) &3) == 0); 6840 assert (((offsetof(struct sym_reg, nc_scntl3) ^ 6841 offsetof(struct sym_tcb, head.wval)) &3) == 0); 6842 } 6843 6844 /* 6845 * Lun control block allocation and initialization. 6846 */ 6847 static lcb_p sym_alloc_lcb (hcb_p np, u_char tn, u_char ln) 6848 { 6849 tcb_p tp = &np->target[tn]; 6850 lcb_p lp = sym_lp(np, tp, ln); 6851 6852 /* 6853 * Already done, just return. 6854 */ 6855 if (lp) 6856 return lp; 6857 /* 6858 * Check against some race. 6859 */ 6860 assert(!sym_is_bit(tp->busy0_map, ln)); 6861 6862 /* 6863 * Initialize the target control block if not yet. 6864 */ 6865 sym_init_tcb (np, tn); 6866 6867 /* 6868 * Allocate the LCB bus address array. 6869 * Compute the bus address of this table. 6870 */ 6871 if (ln && !tp->luntbl) { 6872 int i; 6873 6874 tp->luntbl = sym_calloc_dma(256, "LUNTBL"); 6875 if (!tp->luntbl) 6876 goto fail; 6877 for (i = 0 ; i < 64 ; i++) 6878 tp->luntbl[i] = cpu_to_scr(vtobus(&np->badlun_sa)); 6879 tp->head.luntbl_sa = cpu_to_scr(vtobus(tp->luntbl)); 6880 } 6881 6882 /* 6883 * Allocate the table of pointers for LUN(s) > 0, if needed. 6884 */ 6885 if (ln && !tp->lunmp) { 6886 tp->lunmp = sym_calloc(SYM_CONF_MAX_LUN * sizeof(lcb_p), 6887 "LUNMP"); 6888 if (!tp->lunmp) 6889 goto fail; 6890 } 6891 6892 /* 6893 * Allocate the lcb. 6894 * Make it available to the chip. 6895 */ 6896 lp = sym_calloc_dma(sizeof(struct sym_lcb), "LCB"); 6897 if (!lp) 6898 goto fail; 6899 if (ln) { 6900 tp->lunmp[ln] = lp; 6901 tp->luntbl[ln] = cpu_to_scr(vtobus(lp)); 6902 } 6903 else { 6904 tp->lun0p = lp; 6905 tp->head.lun0_sa = cpu_to_scr(vtobus(lp)); 6906 } 6907 6908 /* 6909 * Let the itl task point to error handling. 6910 */ 6911 lp->head.itl_task_sa = cpu_to_scr(np->bad_itl_ba); 6912 6913 /* 6914 * Set the reselect pattern to our default. :) 6915 */ 6916 lp->head.resel_sa = cpu_to_scr(SCRIPTB_BA (np, resel_bad_lun)); 6917 6918 /* 6919 * Set user capabilities. 6920 */ 6921 lp->user_flags = tp->usrflags & (SYM_DISC_ENABLED | SYM_TAGS_ENABLED); 6922 6923 fail: 6924 return lp; 6925 } 6926 6927 /* 6928 * Allocate LCB resources for tagged command queuing. 6929 */ 6930 static void sym_alloc_lcb_tags (hcb_p np, u_char tn, u_char ln) 6931 { 6932 tcb_p tp = &np->target[tn]; 6933 lcb_p lp = sym_lp(np, tp, ln); 6934 int i; 6935 6936 /* 6937 * If LCB not available, try to allocate it. 6938 */ 6939 if (!lp && !(lp = sym_alloc_lcb(np, tn, ln))) 6940 goto fail; 6941 6942 /* 6943 * Allocate the task table and and the tag allocation 6944 * circular buffer. We want both or none. 6945 */ 6946 lp->itlq_tbl = sym_calloc_dma(SYM_CONF_MAX_TASK*4, "ITLQ_TBL"); 6947 if (!lp->itlq_tbl) 6948 goto fail; 6949 lp->cb_tags = sym_calloc(SYM_CONF_MAX_TASK, "CB_TAGS"); 6950 if (!lp->cb_tags) { 6951 sym_mfree_dma(lp->itlq_tbl, SYM_CONF_MAX_TASK*4, "ITLQ_TBL"); 6952 lp->itlq_tbl = 0; 6953 goto fail; 6954 } 6955 6956 /* 6957 * Initialize the task table with invalid entries. 6958 */ 6959 for (i = 0 ; i < SYM_CONF_MAX_TASK ; i++) 6960 lp->itlq_tbl[i] = cpu_to_scr(np->notask_ba); 6961 6962 /* 6963 * Fill up the tag buffer with tag numbers. 6964 */ 6965 for (i = 0 ; i < SYM_CONF_MAX_TASK ; i++) 6966 lp->cb_tags[i] = i; 6967 6968 /* 6969 * Make the task table available to SCRIPTS, 6970 * And accept tagged commands now. 6971 */ 6972 lp->head.itlq_tbl_sa = cpu_to_scr(vtobus(lp->itlq_tbl)); 6973 6974 return; 6975 fail: 6976 return; 6977 } 6978 6979 /* 6980 * Test the pci bus snoop logic :-( 6981 * 6982 * Has to be called with interrupts disabled. 6983 */ 6984 #ifndef SYM_CONF_IOMAPPED 6985 static int sym_regtest (hcb_p np) 6986 { 6987 register volatile u32 data; 6988 /* 6989 * chip registers may NOT be cached. 6990 * write 0xffffffff to a read only register area, 6991 * and try to read it back. 6992 */ 6993 data = 0xffffffff; 6994 OUTL_OFF(offsetof(struct sym_reg, nc_dstat), data); 6995 data = INL_OFF(offsetof(struct sym_reg, nc_dstat)); 6996 #if 1 6997 if (data == 0xffffffff) { 6998 #else 6999 if ((data & 0xe2f0fffd) != 0x02000080) { 7000 #endif 7001 printf ("CACHE TEST FAILED: reg dstat-sstat2 readback %x.\n", 7002 (unsigned) data); 7003 return (0x10); 7004 }; 7005 return (0); 7006 } 7007 #endif 7008 7009 static int sym_snooptest (hcb_p np) 7010 { 7011 u32 sym_rd, sym_wr, sym_bk, host_rd, host_wr, pc, dstat; 7012 int i, err=0; 7013 #ifndef SYM_CONF_IOMAPPED 7014 err |= sym_regtest (np); 7015 if (err) return (err); 7016 #endif 7017 restart_test: 7018 /* 7019 * Enable Master Parity Checking as we intend 7020 * to enable it for normal operations. 7021 */ 7022 OUTB (nc_ctest4, (np->rv_ctest4 & MPEE)); 7023 /* 7024 * init 7025 */ 7026 pc = SCRIPTB0_BA (np, snooptest); 7027 host_wr = 1; 7028 sym_wr = 2; 7029 /* 7030 * Set memory and register. 7031 */ 7032 np->cache = cpu_to_scr(host_wr); 7033 OUTL (nc_temp, sym_wr); 7034 /* 7035 * Start script (exchange values) 7036 */ 7037 OUTL (nc_dsa, np->hcb_ba); 7038 OUTL_DSP (pc); 7039 /* 7040 * Wait 'til done (with timeout) 7041 */ 7042 for (i=0; i<SYM_SNOOP_TIMEOUT; i++) 7043 if (INB(nc_istat) & (INTF|SIP|DIP)) 7044 break; 7045 if (i>=SYM_SNOOP_TIMEOUT) { 7046 printf ("CACHE TEST FAILED: timeout.\n"); 7047 return (0x20); 7048 }; 7049 /* 7050 * Check for fatal DMA errors. 7051 */ 7052 dstat = INB (nc_dstat); 7053 #if 1 /* Band aiding for broken hardwares that fail PCI parity */ 7054 if ((dstat & MDPE) && (np->rv_ctest4 & MPEE)) { 7055 printf ("%s: PCI DATA PARITY ERROR DETECTED - " 7056 "DISABLING MASTER DATA PARITY CHECKING.\n", 7057 sym_name(np)); 7058 np->rv_ctest4 &= ~MPEE; 7059 goto restart_test; 7060 } 7061 #endif 7062 if (dstat & (MDPE|BF|IID)) { 7063 printf ("CACHE TEST FAILED: DMA error (dstat=0x%02x).", dstat); 7064 return (0x80); 7065 } 7066 /* 7067 * Save termination position. 7068 */ 7069 pc = INL (nc_dsp); 7070 /* 7071 * Read memory and register. 7072 */ 7073 host_rd = scr_to_cpu(np->cache); 7074 sym_rd = INL (nc_scratcha); 7075 sym_bk = INL (nc_temp); 7076 7077 /* 7078 * Check termination position. 7079 */ 7080 if (pc != SCRIPTB0_BA (np, snoopend)+8) { 7081 printf ("CACHE TEST FAILED: script execution failed.\n"); 7082 printf ("start=%08lx, pc=%08lx, end=%08lx\n", 7083 (u_long) SCRIPTB0_BA (np, snooptest), (u_long) pc, 7084 (u_long) SCRIPTB0_BA (np, snoopend) +8); 7085 return (0x40); 7086 }; 7087 /* 7088 * Show results. 7089 */ 7090 if (host_wr != sym_rd) { 7091 printf ("CACHE TEST FAILED: host wrote %d, chip read %d.\n", 7092 (int) host_wr, (int) sym_rd); 7093 err |= 1; 7094 }; 7095 if (host_rd != sym_wr) { 7096 printf ("CACHE TEST FAILED: chip wrote %d, host read %d.\n", 7097 (int) sym_wr, (int) host_rd); 7098 err |= 2; 7099 }; 7100 if (sym_bk != sym_wr) { 7101 printf ("CACHE TEST FAILED: chip wrote %d, read back %d.\n", 7102 (int) sym_wr, (int) sym_bk); 7103 err |= 4; 7104 }; 7105 7106 return (err); 7107 } 7108 7109 /* 7110 * Determine the chip's clock frequency. 7111 * 7112 * This is essential for the negotiation of the synchronous 7113 * transfer rate. 7114 * 7115 * Note: we have to return the correct value. 7116 * THERE IS NO SAFE DEFAULT VALUE. 7117 * 7118 * Most NCR/SYMBIOS boards are delivered with a 40 Mhz clock. 7119 * 53C860 and 53C875 rev. 1 support fast20 transfers but 7120 * do not have a clock doubler and so are provided with a 7121 * 80 MHz clock. All other fast20 boards incorporate a doubler 7122 * and so should be delivered with a 40 MHz clock. 7123 * The recent fast40 chips (895/896/895A/1010) use a 40 Mhz base 7124 * clock and provide a clock quadrupler (160 Mhz). 7125 */ 7126 7127 /* 7128 * Select SCSI clock frequency 7129 */ 7130 static void sym_selectclock(hcb_p np, u_char scntl3) 7131 { 7132 /* 7133 * If multiplier not present or not selected, leave here. 7134 */ 7135 if (np->multiplier <= 1) { 7136 OUTB(nc_scntl3, scntl3); 7137 return; 7138 } 7139 7140 if (sym_verbose >= 2) 7141 printf ("%s: enabling clock multiplier\n", sym_name(np)); 7142 7143 OUTB(nc_stest1, DBLEN); /* Enable clock multiplier */ 7144 /* 7145 * Wait for the LCKFRQ bit to be set if supported by the chip. 7146 * Otherwise wait 20 micro-seconds. 7147 */ 7148 if (np->features & FE_LCKFRQ) { 7149 int i = 20; 7150 while (!(INB(nc_stest4) & LCKFRQ) && --i > 0) 7151 UDELAY (20); 7152 if (!i) 7153 printf("%s: the chip cannot lock the frequency\n", 7154 sym_name(np)); 7155 } else 7156 UDELAY (20); 7157 OUTB(nc_stest3, HSC); /* Halt the scsi clock */ 7158 OUTB(nc_scntl3, scntl3); 7159 OUTB(nc_stest1, (DBLEN|DBLSEL));/* Select clock multiplier */ 7160 OUTB(nc_stest3, 0x00); /* Restart scsi clock */ 7161 } 7162 7163 /* 7164 * calculate SCSI clock frequency (in KHz) 7165 */ 7166 static unsigned getfreq (hcb_p np, int gen) 7167 { 7168 unsigned int ms = 0; 7169 unsigned int f; 7170 7171 /* 7172 * Measure GEN timer delay in order 7173 * to calculate SCSI clock frequency 7174 * 7175 * This code will never execute too 7176 * many loop iterations (if DELAY is 7177 * reasonably correct). It could get 7178 * too low a delay (too high a freq.) 7179 * if the CPU is slow executing the 7180 * loop for some reason (an NMI, for 7181 * example). For this reason we will 7182 * if multiple measurements are to be 7183 * performed trust the higher delay 7184 * (lower frequency returned). 7185 */ 7186 OUTW (nc_sien , 0); /* mask all scsi interrupts */ 7187 (void) INW (nc_sist); /* clear pending scsi interrupt */ 7188 OUTB (nc_dien , 0); /* mask all dma interrupts */ 7189 (void) INW (nc_sist); /* another one, just to be sure :) */ 7190 OUTB (nc_scntl3, 4); /* set pre-scaler to divide by 3 */ 7191 OUTB (nc_stime1, 0); /* disable general purpose timer */ 7192 OUTB (nc_stime1, gen); /* set to nominal delay of 1<<gen * 125us */ 7193 while (!(INW(nc_sist) & GEN) && ms++ < 100000) 7194 UDELAY (1000); /* count ms */ 7195 OUTB (nc_stime1, 0); /* disable general purpose timer */ 7196 /* 7197 * set prescaler to divide by whatever 0 means 7198 * 0 ought to choose divide by 2, but appears 7199 * to set divide by 3.5 mode in my 53c810 ... 7200 */ 7201 OUTB (nc_scntl3, 0); 7202 7203 /* 7204 * adjust for prescaler, and convert into KHz 7205 */ 7206 f = ms ? ((1 << gen) * 4340) / ms : 0; 7207 7208 if (sym_verbose >= 2) 7209 printf ("%s: Delay (GEN=%d): %u msec, %u KHz\n", 7210 sym_name(np), gen, ms, f); 7211 7212 return f; 7213 } 7214 7215 static unsigned sym_getfreq (hcb_p np) 7216 { 7217 u_int f1, f2; 7218 int gen = 11; 7219 7220 (void) getfreq (np, gen); /* throw away first result */ 7221 f1 = getfreq (np, gen); 7222 f2 = getfreq (np, gen); 7223 if (f1 > f2) f1 = f2; /* trust lower result */ 7224 return f1; 7225 } 7226 7227 /* 7228 * Get/probe chip SCSI clock frequency 7229 */ 7230 static void sym_getclock (hcb_p np, int mult) 7231 { 7232 unsigned char scntl3 = np->sv_scntl3; 7233 unsigned char stest1 = np->sv_stest1; 7234 unsigned f1; 7235 7236 /* 7237 * For the C10 core, assume 40 MHz. 7238 */ 7239 if (np->features & FE_C10) { 7240 np->multiplier = mult; 7241 np->clock_khz = 40000 * mult; 7242 return; 7243 } 7244 7245 np->multiplier = 1; 7246 f1 = 40000; 7247 /* 7248 * True with 875/895/896/895A with clock multiplier selected 7249 */ 7250 if (mult > 1 && (stest1 & (DBLEN+DBLSEL)) == DBLEN+DBLSEL) { 7251 if (sym_verbose >= 2) 7252 printf ("%s: clock multiplier found\n", sym_name(np)); 7253 np->multiplier = mult; 7254 } 7255 7256 /* 7257 * If multiplier not found or scntl3 not 7,5,3, 7258 * reset chip and get frequency from general purpose timer. 7259 * Otherwise trust scntl3 BIOS setting. 7260 */ 7261 if (np->multiplier != mult || (scntl3 & 7) < 3 || !(scntl3 & 1)) { 7262 OUTB (nc_stest1, 0); /* make sure doubler is OFF */ 7263 f1 = sym_getfreq (np); 7264 7265 if (sym_verbose) 7266 printf ("%s: chip clock is %uKHz\n", sym_name(np), f1); 7267 7268 if (f1 < 45000) f1 = 40000; 7269 else if (f1 < 55000) f1 = 50000; 7270 else f1 = 80000; 7271 7272 if (f1 < 80000 && mult > 1) { 7273 if (sym_verbose >= 2) 7274 printf ("%s: clock multiplier assumed\n", 7275 sym_name(np)); 7276 np->multiplier = mult; 7277 } 7278 } else { 7279 if ((scntl3 & 7) == 3) f1 = 40000; 7280 else if ((scntl3 & 7) == 5) f1 = 80000; 7281 else f1 = 160000; 7282 7283 f1 /= np->multiplier; 7284 } 7285 7286 /* 7287 * Compute controller synchronous parameters. 7288 */ 7289 f1 *= np->multiplier; 7290 np->clock_khz = f1; 7291 } 7292 7293 /* 7294 * Get/probe PCI clock frequency 7295 */ 7296 static int sym_getpciclock (hcb_p np) 7297 { 7298 int f = 0; 7299 7300 /* 7301 * For the C1010-33, this doesn't work. 7302 * For the C1010-66, this will be tested when I'll have 7303 * such a beast to play with. 7304 */ 7305 if (!(np->features & FE_C10)) { 7306 OUTB (nc_stest1, SCLK); /* Use the PCI clock as SCSI clock */ 7307 f = (int) sym_getfreq (np); 7308 OUTB (nc_stest1, 0); 7309 } 7310 np->pciclk_khz = f; 7311 7312 return f; 7313 } 7314 7315 /*============= DRIVER ACTION/COMPLETION ====================*/ 7316 7317 /* 7318 * Print something that tells about extended errors. 7319 */ 7320 static void sym_print_xerr(ccb_p cp, int x_status) 7321 { 7322 if (x_status & XE_PARITY_ERR) { 7323 PRINT_ADDR(cp); 7324 printf ("unrecovered SCSI parity error.\n"); 7325 } 7326 if (x_status & XE_EXTRA_DATA) { 7327 PRINT_ADDR(cp); 7328 printf ("extraneous data discarded.\n"); 7329 } 7330 if (x_status & XE_BAD_PHASE) { 7331 PRINT_ADDR(cp); 7332 printf ("illegal scsi phase (4/5).\n"); 7333 } 7334 if (x_status & XE_SODL_UNRUN) { 7335 PRINT_ADDR(cp); 7336 printf ("ODD transfer in DATA OUT phase.\n"); 7337 } 7338 if (x_status & XE_SWIDE_OVRUN) { 7339 PRINT_ADDR(cp); 7340 printf ("ODD transfer in DATA IN phase.\n"); 7341 } 7342 } 7343 7344 /* 7345 * Choose the more appropriate CAM status if 7346 * the IO encountered an extended error. 7347 */ 7348 static int sym_xerr_cam_status(int cam_status, int x_status) 7349 { 7350 if (x_status) { 7351 if (x_status & XE_PARITY_ERR) 7352 cam_status = CAM_UNCOR_PARITY; 7353 else if (x_status &(XE_EXTRA_DATA|XE_SODL_UNRUN|XE_SWIDE_OVRUN)) 7354 cam_status = CAM_DATA_RUN_ERR; 7355 else if (x_status & XE_BAD_PHASE) 7356 cam_status = CAM_REQ_CMP_ERR; 7357 else 7358 cam_status = CAM_REQ_CMP_ERR; 7359 } 7360 return cam_status; 7361 } 7362 7363 /* 7364 * Complete execution of a SCSI command with extented 7365 * error, SCSI status error, or having been auto-sensed. 7366 * 7367 * The SCRIPTS processor is not running there, so we 7368 * can safely access IO registers and remove JOBs from 7369 * the START queue. 7370 * SCRATCHA is assumed to have been loaded with STARTPOS 7371 * before the SCRIPTS called the C code. 7372 */ 7373 static void sym_complete_error (hcb_p np, ccb_p cp) 7374 { 7375 struct ccb_scsiio *csio; 7376 u_int cam_status; 7377 int i; 7378 7379 /* 7380 * Paranoid check. :) 7381 */ 7382 if (!cp || !cp->cam_ccb) 7383 return; 7384 7385 if (DEBUG_FLAGS & (DEBUG_TINY|DEBUG_RESULT)) { 7386 printf ("CCB=%lx STAT=%x/%x/%x DEV=%d/%d\n", (unsigned long)cp, 7387 cp->host_status, cp->ssss_status, cp->host_flags, 7388 cp->target, cp->lun); 7389 MDELAY(100); 7390 } 7391 7392 /* 7393 * Get CAM command pointer. 7394 */ 7395 csio = &cp->cam_ccb->csio; 7396 7397 /* 7398 * Check for extended errors. 7399 */ 7400 if (cp->xerr_status) { 7401 if (sym_verbose) 7402 sym_print_xerr(cp, cp->xerr_status); 7403 if (cp->host_status == HS_COMPLETE) 7404 cp->host_status = HS_COMP_ERR; 7405 } 7406 7407 /* 7408 * Calculate the residual. 7409 */ 7410 csio->sense_resid = 0; 7411 csio->resid = sym_compute_residual(np, cp); 7412 7413 if (!SYM_CONF_RESIDUAL_SUPPORT) {/* If user does not want residuals */ 7414 csio->resid = 0; /* throw them away. :) */ 7415 cp->sv_resid = 0; 7416 } 7417 7418 if (cp->host_flags & HF_SENSE) { /* Auto sense */ 7419 csio->scsi_status = cp->sv_scsi_status; /* Restore status */ 7420 csio->sense_resid = csio->resid; /* Swap residuals */ 7421 csio->resid = cp->sv_resid; 7422 cp->sv_resid = 0; 7423 if (sym_verbose && cp->sv_xerr_status) 7424 sym_print_xerr(cp, cp->sv_xerr_status); 7425 if (cp->host_status == HS_COMPLETE && 7426 cp->ssss_status == S_GOOD && 7427 cp->xerr_status == 0) { 7428 cam_status = sym_xerr_cam_status(CAM_SCSI_STATUS_ERROR, 7429 cp->sv_xerr_status); 7430 cam_status |= CAM_AUTOSNS_VALID; 7431 /* 7432 * Bounce back the sense data to user and 7433 * fix the residual. 7434 */ 7435 bzero(&csio->sense_data, csio->sense_len); 7436 bcopy(cp->sns_bbuf, &csio->sense_data, 7437 MIN(csio->sense_len, SYM_SNS_BBUF_LEN)); 7438 csio->sense_resid += csio->sense_len; 7439 csio->sense_resid -= SYM_SNS_BBUF_LEN; 7440 #if 0 7441 /* 7442 * If the device reports a UNIT ATTENTION condition 7443 * due to a RESET condition, we should consider all 7444 * disconnect CCBs for this unit as aborted. 7445 */ 7446 if (1) { 7447 u_char *p; 7448 p = (u_char *) csio->sense_data; 7449 if (p[0]==0x70 && p[2]==0x6 && p[12]==0x29) 7450 sym_clear_tasks(np, CAM_REQ_ABORTED, 7451 cp->target,cp->lun, -1); 7452 } 7453 #endif 7454 } 7455 else 7456 cam_status = CAM_AUTOSENSE_FAIL; 7457 } 7458 else if (cp->host_status == HS_COMPLETE) { /* Bad SCSI status */ 7459 csio->scsi_status = cp->ssss_status; 7460 cam_status = CAM_SCSI_STATUS_ERROR; 7461 } 7462 else if (cp->host_status == HS_SEL_TIMEOUT) /* Selection timeout */ 7463 cam_status = CAM_SEL_TIMEOUT; 7464 else if (cp->host_status == HS_UNEXPECTED) /* Unexpected BUS FREE*/ 7465 cam_status = CAM_UNEXP_BUSFREE; 7466 else { /* Extended error */ 7467 if (sym_verbose) { 7468 PRINT_ADDR(cp); 7469 printf ("COMMAND FAILED (%x %x %x).\n", 7470 cp->host_status, cp->ssss_status, 7471 cp->xerr_status); 7472 } 7473 csio->scsi_status = cp->ssss_status; 7474 /* 7475 * Set the most appropriate value for CAM status. 7476 */ 7477 cam_status = sym_xerr_cam_status(CAM_REQ_CMP_ERR, 7478 cp->xerr_status); 7479 } 7480 7481 /* 7482 * Dequeue all queued CCBs for that device 7483 * not yet started by SCRIPTS. 7484 */ 7485 i = (INL (nc_scratcha) - np->squeue_ba) / 4; 7486 (void) sym_dequeue_from_squeue(np, i, cp->target, cp->lun, -1); 7487 7488 /* 7489 * Restart the SCRIPTS processor. 7490 */ 7491 OUTL_DSP (SCRIPTA_BA (np, start)); 7492 7493 #ifdef FreeBSD_Bus_Dma_Abstraction 7494 /* 7495 * Synchronize DMA map if needed. 7496 */ 7497 if (cp->dmamapped) { 7498 bus_dmamap_sync(np->data_dmat, cp->dmamap, 7499 (bus_dmasync_op_t)(cp->dmamapped == SYM_DMA_READ ? 7500 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 7501 } 7502 #endif 7503 /* 7504 * Add this one to the COMP queue. 7505 * Complete all those commands with either error 7506 * or requeue condition. 7507 */ 7508 sym_set_cam_status((union ccb *) csio, cam_status); 7509 sym_remque(&cp->link_ccbq); 7510 sym_insque_head(&cp->link_ccbq, &np->comp_ccbq); 7511 sym_flush_comp_queue(np, 0); 7512 } 7513 7514 /* 7515 * Complete execution of a successful SCSI command. 7516 * 7517 * Only successful commands go to the DONE queue, 7518 * since we need to have the SCRIPTS processor 7519 * stopped on any error condition. 7520 * The SCRIPTS processor is running while we are 7521 * completing successful commands. 7522 */ 7523 static void sym_complete_ok (hcb_p np, ccb_p cp) 7524 { 7525 struct ccb_scsiio *csio; 7526 tcb_p tp; 7527 lcb_p lp; 7528 7529 /* 7530 * Paranoid check. :) 7531 */ 7532 if (!cp || !cp->cam_ccb) 7533 return; 7534 assert (cp->host_status == HS_COMPLETE); 7535 7536 /* 7537 * Get command, target and lun pointers. 7538 */ 7539 csio = &cp->cam_ccb->csio; 7540 tp = &np->target[cp->target]; 7541 lp = sym_lp(np, tp, cp->lun); 7542 7543 /* 7544 * Assume device discovered on first success. 7545 */ 7546 if (!lp) 7547 sym_set_bit(tp->lun_map, cp->lun); 7548 7549 /* 7550 * If all data have been transferred, given than no 7551 * extended error did occur, there is no residual. 7552 */ 7553 csio->resid = 0; 7554 if (cp->phys.head.lastp != cp->phys.head.goalp) 7555 csio->resid = sym_compute_residual(np, cp); 7556 7557 /* 7558 * Wrong transfer residuals may be worse than just always 7559 * returning zero. User can disable this feature from 7560 * sym_conf.h. Residual support is enabled by default. 7561 */ 7562 if (!SYM_CONF_RESIDUAL_SUPPORT) 7563 csio->resid = 0; 7564 7565 #ifdef FreeBSD_Bus_Dma_Abstraction 7566 /* 7567 * Synchronize DMA map if needed. 7568 */ 7569 if (cp->dmamapped) { 7570 bus_dmamap_sync(np->data_dmat, cp->dmamap, 7571 (bus_dmasync_op_t)(cp->dmamapped == SYM_DMA_READ ? 7572 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 7573 } 7574 #endif 7575 /* 7576 * Set status and complete the command. 7577 */ 7578 csio->scsi_status = cp->ssss_status; 7579 sym_set_cam_status((union ccb *) csio, CAM_REQ_CMP); 7580 sym_free_ccb (np, cp); 7581 sym_xpt_done(np, (union ccb *) csio); 7582 } 7583 7584 /* 7585 * Our timeout handler. 7586 */ 7587 static void sym_timeout1(void *arg) 7588 { 7589 union ccb *ccb = (union ccb *) arg; 7590 hcb_p np = ccb->ccb_h.sym_hcb_ptr; 7591 7592 /* 7593 * Check that the CAM CCB is still queued. 7594 */ 7595 if (!np) 7596 return; 7597 7598 switch(ccb->ccb_h.func_code) { 7599 case XPT_SCSI_IO: 7600 (void) sym_abort_scsiio(np, ccb, 1); 7601 break; 7602 default: 7603 break; 7604 } 7605 } 7606 7607 static void sym_timeout(void *arg) 7608 { 7609 int s = splcam(); 7610 sym_timeout1(arg); 7611 splx(s); 7612 } 7613 7614 /* 7615 * Abort an SCSI IO. 7616 */ 7617 static int sym_abort_scsiio(hcb_p np, union ccb *ccb, int timed_out) 7618 { 7619 ccb_p cp; 7620 SYM_QUEHEAD *qp; 7621 7622 /* 7623 * Look up our CCB control block. 7624 */ 7625 cp = 0; 7626 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) { 7627 ccb_p cp2 = sym_que_entry(qp, struct sym_ccb, link_ccbq); 7628 if (cp2->cam_ccb == ccb) { 7629 cp = cp2; 7630 break; 7631 } 7632 } 7633 if (!cp || cp->host_status == HS_WAIT) 7634 return -1; 7635 7636 /* 7637 * If a previous abort didn't succeed in time, 7638 * perform a BUS reset. 7639 */ 7640 if (cp->to_abort) { 7641 sym_reset_scsi_bus(np, 1); 7642 return 0; 7643 } 7644 7645 /* 7646 * Mark the CCB for abort and allow time for. 7647 */ 7648 cp->to_abort = timed_out ? 2 : 1; 7649 ccb->ccb_h.timeout_ch = timeout(sym_timeout, (caddr_t) ccb, 10*hz); 7650 7651 /* 7652 * Tell the SCRIPTS processor to stop and synchronize with us. 7653 */ 7654 np->istat_sem = SEM; 7655 OUTB (nc_istat, SIGP|SEM); 7656 return 0; 7657 } 7658 7659 /* 7660 * Reset a SCSI device (all LUNs of a target). 7661 */ 7662 static void sym_reset_dev(hcb_p np, union ccb *ccb) 7663 { 7664 tcb_p tp; 7665 struct ccb_hdr *ccb_h = &ccb->ccb_h; 7666 7667 if (ccb_h->target_id == np->myaddr || 7668 ccb_h->target_id >= SYM_CONF_MAX_TARGET || 7669 ccb_h->target_lun >= SYM_CONF_MAX_LUN) { 7670 sym_xpt_done2(np, ccb, CAM_DEV_NOT_THERE); 7671 return; 7672 } 7673 7674 tp = &np->target[ccb_h->target_id]; 7675 7676 tp->to_reset = 1; 7677 sym_xpt_done2(np, ccb, CAM_REQ_CMP); 7678 7679 np->istat_sem = SEM; 7680 OUTB (nc_istat, SIGP|SEM); 7681 return; 7682 } 7683 7684 /* 7685 * SIM action entry point. 7686 */ 7687 static void sym_action(struct cam_sim *sim, union ccb *ccb) 7688 { 7689 int s = splcam(); 7690 sym_action1(sim, ccb); 7691 splx(s); 7692 } 7693 7694 static void sym_action1(struct cam_sim *sim, union ccb *ccb) 7695 { 7696 hcb_p np; 7697 tcb_p tp; 7698 lcb_p lp; 7699 ccb_p cp; 7700 int tmp; 7701 u_char idmsg, *msgptr; 7702 u_int msglen; 7703 struct ccb_scsiio *csio; 7704 struct ccb_hdr *ccb_h; 7705 7706 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("sym_action\n")); 7707 7708 /* 7709 * Retrieve our controller data structure. 7710 */ 7711 np = (hcb_p) cam_sim_softc(sim); 7712 7713 /* 7714 * The common case is SCSI IO. 7715 * We deal with other ones elsewhere. 7716 */ 7717 if (ccb->ccb_h.func_code != XPT_SCSI_IO) { 7718 sym_action2(sim, ccb); 7719 return; 7720 } 7721 csio = &ccb->csio; 7722 ccb_h = &csio->ccb_h; 7723 7724 /* 7725 * Work around races. 7726 */ 7727 if ((ccb_h->status & CAM_STATUS_MASK) != CAM_REQ_INPROG) { 7728 xpt_done(ccb); 7729 return; 7730 } 7731 7732 /* 7733 * Minimal checkings, so that we will not 7734 * go outside our tables. 7735 */ 7736 if (ccb_h->target_id == np->myaddr || 7737 ccb_h->target_id >= SYM_CONF_MAX_TARGET || 7738 ccb_h->target_lun >= SYM_CONF_MAX_LUN) { 7739 sym_xpt_done2(np, ccb, CAM_DEV_NOT_THERE); 7740 return; 7741 } 7742 7743 /* 7744 * Retreive the target and lun descriptors. 7745 */ 7746 tp = &np->target[ccb_h->target_id]; 7747 lp = sym_lp(np, tp, ccb_h->target_lun); 7748 7749 /* 7750 * Complete the 1st INQUIRY command with error 7751 * condition if the device is flagged NOSCAN 7752 * at BOOT in the NVRAM. This may speed up 7753 * the boot and maintain coherency with BIOS 7754 * device numbering. Clearing the flag allows 7755 * user to rescan skipped devices later. 7756 * We also return error for devices not flagged 7757 * for SCAN LUNS in the NVRAM since some mono-lun 7758 * devices behave badly when asked for some non 7759 * zero LUN. Btw, this is an absolute hack.:-) 7760 */ 7761 if (!(ccb_h->flags & CAM_CDB_PHYS) && 7762 (0x12 == ((ccb_h->flags & CAM_CDB_POINTER) ? 7763 csio->cdb_io.cdb_ptr[0] : csio->cdb_io.cdb_bytes[0]))) { 7764 if ((tp->usrflags & SYM_SCAN_BOOT_DISABLED) || 7765 ((tp->usrflags & SYM_SCAN_LUNS_DISABLED) && 7766 ccb_h->target_lun != 0)) { 7767 tp->usrflags &= ~SYM_SCAN_BOOT_DISABLED; 7768 sym_xpt_done2(np, ccb, CAM_DEV_NOT_THERE); 7769 return; 7770 } 7771 } 7772 7773 /* 7774 * Get a control block for this IO. 7775 */ 7776 tmp = ((ccb_h->flags & CAM_TAG_ACTION_VALID) != 0); 7777 cp = sym_get_ccb(np, ccb_h->target_id, ccb_h->target_lun, tmp); 7778 if (!cp) { 7779 sym_xpt_done2(np, ccb, CAM_RESRC_UNAVAIL); 7780 return; 7781 } 7782 7783 /* 7784 * Keep track of the IO in our CCB. 7785 */ 7786 cp->cam_ccb = ccb; 7787 7788 /* 7789 * Build the IDENTIFY message. 7790 */ 7791 idmsg = M_IDENTIFY | cp->lun; 7792 if (cp->tag != NO_TAG || (lp && (lp->current_flags & SYM_DISC_ENABLED))) 7793 idmsg |= 0x40; 7794 7795 msgptr = cp->scsi_smsg; 7796 msglen = 0; 7797 msgptr[msglen++] = idmsg; 7798 7799 /* 7800 * Build the tag message if present. 7801 */ 7802 if (cp->tag != NO_TAG) { 7803 u_char order = csio->tag_action; 7804 7805 switch(order) { 7806 case M_ORDERED_TAG: 7807 break; 7808 case M_HEAD_TAG: 7809 break; 7810 default: 7811 order = M_SIMPLE_TAG; 7812 } 7813 msgptr[msglen++] = order; 7814 7815 /* 7816 * For less than 128 tags, actual tags are numbered 7817 * 1,3,5,..2*MAXTAGS+1,since we may have to deal 7818 * with devices that have problems with #TAG 0 or too 7819 * great #TAG numbers. For more tags (up to 256), 7820 * we use directly our tag number. 7821 */ 7822 #if SYM_CONF_MAX_TASK > (512/4) 7823 msgptr[msglen++] = cp->tag; 7824 #else 7825 msgptr[msglen++] = (cp->tag << 1) + 1; 7826 #endif 7827 } 7828 7829 /* 7830 * Build a negotiation message if needed. 7831 * (nego_status is filled by sym_prepare_nego()) 7832 */ 7833 cp->nego_status = 0; 7834 if (tp->tinfo.current.width != tp->tinfo.goal.width || 7835 tp->tinfo.current.period != tp->tinfo.goal.period || 7836 tp->tinfo.current.offset != tp->tinfo.goal.offset || 7837 tp->tinfo.current.options != tp->tinfo.goal.options) { 7838 if (!tp->nego_cp && lp) 7839 msglen += sym_prepare_nego(np, cp, 0, msgptr + msglen); 7840 } 7841 7842 /* 7843 * Fill in our ccb 7844 */ 7845 7846 /* 7847 * Startqueue 7848 */ 7849 cp->phys.head.go.start = cpu_to_scr(SCRIPTA_BA (np, select)); 7850 cp->phys.head.go.restart = cpu_to_scr(SCRIPTA_BA (np, resel_dsa)); 7851 7852 /* 7853 * select 7854 */ 7855 cp->phys.select.sel_id = cp->target; 7856 cp->phys.select.sel_scntl3 = tp->head.wval; 7857 cp->phys.select.sel_sxfer = tp->head.sval; 7858 cp->phys.select.sel_scntl4 = tp->head.uval; 7859 7860 /* 7861 * message 7862 */ 7863 cp->phys.smsg.addr = cpu_to_scr(CCB_BA (cp, scsi_smsg)); 7864 cp->phys.smsg.size = cpu_to_scr(msglen); 7865 7866 /* 7867 * command 7868 */ 7869 if (sym_setup_cdb(np, csio, cp) < 0) { 7870 sym_free_ccb(np, cp); 7871 sym_xpt_done(np, ccb); 7872 return; 7873 } 7874 7875 /* 7876 * status 7877 */ 7878 #if 0 /* Provision */ 7879 cp->actualquirks = tp->quirks; 7880 #endif 7881 cp->actualquirks = SYM_QUIRK_AUTOSAVE; 7882 cp->host_status = cp->nego_status ? HS_NEGOTIATE : HS_BUSY; 7883 cp->ssss_status = S_ILLEGAL; 7884 cp->xerr_status = 0; 7885 cp->host_flags = 0; 7886 cp->extra_bytes = 0; 7887 7888 /* 7889 * extreme data pointer. 7890 * shall be positive, so -1 is lower than lowest.:) 7891 */ 7892 cp->ext_sg = -1; 7893 cp->ext_ofs = 0; 7894 7895 /* 7896 * Build the data descriptor block 7897 * and start the IO. 7898 */ 7899 sym_setup_data_and_start(np, csio, cp); 7900 } 7901 7902 /* 7903 * Setup buffers and pointers that address the CDB. 7904 * I bet, physical CDBs will never be used on the planet, 7905 * since they can be bounced without significant overhead. 7906 */ 7907 static int sym_setup_cdb(hcb_p np, struct ccb_scsiio *csio, ccb_p cp) 7908 { 7909 struct ccb_hdr *ccb_h; 7910 u32 cmd_ba; 7911 int cmd_len; 7912 7913 ccb_h = &csio->ccb_h; 7914 7915 /* 7916 * CDB is 16 bytes max. 7917 */ 7918 if (csio->cdb_len > sizeof(cp->cdb_buf)) { 7919 sym_set_cam_status(cp->cam_ccb, CAM_REQ_INVALID); 7920 return -1; 7921 } 7922 cmd_len = csio->cdb_len; 7923 7924 if (ccb_h->flags & CAM_CDB_POINTER) { 7925 /* CDB is a pointer */ 7926 if (!(ccb_h->flags & CAM_CDB_PHYS)) { 7927 /* CDB pointer is virtual */ 7928 bcopy(csio->cdb_io.cdb_ptr, cp->cdb_buf, cmd_len); 7929 cmd_ba = CCB_BA (cp, cdb_buf[0]); 7930 } else { 7931 /* CDB pointer is physical */ 7932 #if 0 7933 cmd_ba = ((u32)csio->cdb_io.cdb_ptr) & 0xffffffff; 7934 #else 7935 sym_set_cam_status(cp->cam_ccb, CAM_REQ_INVALID); 7936 return -1; 7937 #endif 7938 } 7939 } else { 7940 /* CDB is in the CAM ccb (buffer) */ 7941 bcopy(csio->cdb_io.cdb_bytes, cp->cdb_buf, cmd_len); 7942 cmd_ba = CCB_BA (cp, cdb_buf[0]); 7943 } 7944 7945 cp->phys.cmd.addr = cpu_to_scr(cmd_ba); 7946 cp->phys.cmd.size = cpu_to_scr(cmd_len); 7947 7948 return 0; 7949 } 7950 7951 /* 7952 * Set up data pointers used by SCRIPTS. 7953 */ 7954 static void __inline 7955 sym_setup_data_pointers(hcb_p np, ccb_p cp, int dir) 7956 { 7957 u32 lastp, goalp; 7958 7959 /* 7960 * No segments means no data. 7961 */ 7962 if (!cp->segments) 7963 dir = CAM_DIR_NONE; 7964 7965 /* 7966 * Set the data pointer. 7967 */ 7968 switch(dir) { 7969 case CAM_DIR_OUT: 7970 goalp = SCRIPTA_BA (np, data_out2) + 8; 7971 lastp = goalp - 8 - (cp->segments * (2*4)); 7972 break; 7973 case CAM_DIR_IN: 7974 cp->host_flags |= HF_DATA_IN; 7975 goalp = SCRIPTA_BA (np, data_in2) + 8; 7976 lastp = goalp - 8 - (cp->segments * (2*4)); 7977 break; 7978 case CAM_DIR_NONE: 7979 default: 7980 lastp = goalp = SCRIPTB_BA (np, no_data); 7981 break; 7982 } 7983 7984 cp->phys.head.lastp = cpu_to_scr(lastp); 7985 cp->phys.head.goalp = cpu_to_scr(goalp); 7986 cp->phys.head.savep = cpu_to_scr(lastp); 7987 cp->startp = cp->phys.head.savep; 7988 } 7989 7990 7991 #ifdef FreeBSD_Bus_Dma_Abstraction 7992 /* 7993 * Call back routine for the DMA map service. 7994 * If bounce buffers are used (why ?), we may sleep and then 7995 * be called there in another context. 7996 */ 7997 static void 7998 sym_execute_ccb(void *arg, bus_dma_segment_t *psegs, int nsegs, int error) 7999 { 8000 ccb_p cp; 8001 hcb_p np; 8002 union ccb *ccb; 8003 int s; 8004 8005 s = splcam(); 8006 8007 cp = (ccb_p) arg; 8008 ccb = cp->cam_ccb; 8009 np = (hcb_p) cp->arg; 8010 8011 /* 8012 * Deal with weird races. 8013 */ 8014 if (sym_get_cam_status(ccb) != CAM_REQ_INPROG) 8015 goto out_abort; 8016 8017 /* 8018 * Deal with weird errors. 8019 */ 8020 if (error) { 8021 cp->dmamapped = 0; 8022 sym_set_cam_status(cp->cam_ccb, CAM_REQ_ABORTED); 8023 goto out_abort; 8024 } 8025 8026 /* 8027 * Build the data descriptor for the chip. 8028 */ 8029 if (nsegs) { 8030 int retv; 8031 /* 896 rev 1 requires to be careful about boundaries */ 8032 if (np->device_id == PCI_ID_SYM53C896 && np->revision_id <= 1) 8033 retv = sym_scatter_sg_physical(np, cp, psegs, nsegs); 8034 else 8035 retv = sym_fast_scatter_sg_physical(np,cp, psegs,nsegs); 8036 if (retv < 0) { 8037 sym_set_cam_status(cp->cam_ccb, CAM_REQ_TOO_BIG); 8038 goto out_abort; 8039 } 8040 } 8041 8042 /* 8043 * Synchronize the DMA map only if we have 8044 * actually mapped the data. 8045 */ 8046 if (cp->dmamapped) { 8047 bus_dmamap_sync(np->data_dmat, cp->dmamap, 8048 (bus_dmasync_op_t)(cp->dmamapped == SYM_DMA_READ ? 8049 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 8050 } 8051 8052 /* 8053 * Set host status to busy state. 8054 * May have been set back to HS_WAIT to avoid a race. 8055 */ 8056 cp->host_status = cp->nego_status ? HS_NEGOTIATE : HS_BUSY; 8057 8058 /* 8059 * Set data pointers. 8060 */ 8061 sym_setup_data_pointers(np, cp, (ccb->ccb_h.flags & CAM_DIR_MASK)); 8062 8063 /* 8064 * Enqueue this IO in our pending queue. 8065 */ 8066 sym_enqueue_cam_ccb(np, ccb); 8067 8068 /* 8069 * When `#ifed 1', the code below makes the driver 8070 * panic on the first attempt to write to a SCSI device. 8071 * It is the first test we want to do after a driver 8072 * change that does not seem obviously safe. :) 8073 */ 8074 #if 0 8075 switch (cp->cdb_buf[0]) { 8076 case 0x0A: case 0x2A: case 0xAA: 8077 panic("XXXXXXXXXXXXX WRITE NOT YET ALLOWED XXXXXXXXXXXXXX\n"); 8078 MDELAY(10000); 8079 break; 8080 default: 8081 break; 8082 } 8083 #endif 8084 /* 8085 * Activate this job. 8086 */ 8087 sym_put_start_queue(np, cp); 8088 out: 8089 splx(s); 8090 return; 8091 out_abort: 8092 sym_free_ccb(np, cp); 8093 sym_xpt_done(np, ccb); 8094 goto out; 8095 } 8096 8097 /* 8098 * How complex it gets to deal with the data in CAM. 8099 * The Bus Dma stuff makes things still more complex. 8100 */ 8101 static void 8102 sym_setup_data_and_start(hcb_p np, struct ccb_scsiio *csio, ccb_p cp) 8103 { 8104 struct ccb_hdr *ccb_h; 8105 int dir, retv; 8106 8107 ccb_h = &csio->ccb_h; 8108 8109 /* 8110 * Now deal with the data. 8111 */ 8112 cp->data_len = csio->dxfer_len; 8113 cp->arg = np; 8114 8115 /* 8116 * No direction means no data. 8117 */ 8118 dir = (ccb_h->flags & CAM_DIR_MASK); 8119 if (dir == CAM_DIR_NONE) { 8120 sym_execute_ccb(cp, NULL, 0, 0); 8121 return; 8122 } 8123 8124 if (!(ccb_h->flags & CAM_SCATTER_VALID)) { 8125 /* Single buffer */ 8126 if (!(ccb_h->flags & CAM_DATA_PHYS)) { 8127 /* Buffer is virtual */ 8128 int s; 8129 8130 cp->dmamapped = (dir == CAM_DIR_IN) ? 8131 SYM_DMA_READ : SYM_DMA_WRITE; 8132 s = splsoftvm(); 8133 retv = bus_dmamap_load(np->data_dmat, cp->dmamap, 8134 csio->data_ptr, csio->dxfer_len, 8135 sym_execute_ccb, cp, 0); 8136 if (retv == EINPROGRESS) { 8137 cp->host_status = HS_WAIT; 8138 xpt_freeze_simq(np->sim, 1); 8139 csio->ccb_h.status |= CAM_RELEASE_SIMQ; 8140 } 8141 splx(s); 8142 } else { 8143 /* Buffer is physical */ 8144 struct bus_dma_segment seg; 8145 8146 seg.ds_addr = (bus_addr_t) csio->data_ptr; 8147 sym_execute_ccb(cp, &seg, 1, 0); 8148 } 8149 } else { 8150 /* Scatter/gather list */ 8151 struct bus_dma_segment *segs; 8152 8153 if ((ccb_h->flags & CAM_SG_LIST_PHYS) != 0) { 8154 /* The SG list pointer is physical */ 8155 sym_set_cam_status(cp->cam_ccb, CAM_REQ_INVALID); 8156 goto out_abort; 8157 } 8158 8159 if (!(ccb_h->flags & CAM_DATA_PHYS)) { 8160 /* SG buffer pointers are virtual */ 8161 sym_set_cam_status(cp->cam_ccb, CAM_REQ_INVALID); 8162 goto out_abort; 8163 } 8164 8165 /* SG buffer pointers are physical */ 8166 segs = (struct bus_dma_segment *)csio->data_ptr; 8167 sym_execute_ccb(cp, segs, csio->sglist_cnt, 0); 8168 } 8169 return; 8170 out_abort: 8171 sym_free_ccb(np, cp); 8172 sym_xpt_done(np, (union ccb *) csio); 8173 } 8174 8175 /* 8176 * Move the scatter list to our data block. 8177 */ 8178 static int 8179 sym_fast_scatter_sg_physical(hcb_p np, ccb_p cp, 8180 bus_dma_segment_t *psegs, int nsegs) 8181 { 8182 struct sym_tblmove *data; 8183 bus_dma_segment_t *psegs2; 8184 8185 if (nsegs > SYM_CONF_MAX_SG) 8186 return -1; 8187 8188 data = &cp->phys.data[SYM_CONF_MAX_SG-1]; 8189 psegs2 = &psegs[nsegs-1]; 8190 cp->segments = nsegs; 8191 8192 while (1) { 8193 data->addr = cpu_to_scr(psegs2->ds_addr); 8194 data->size = cpu_to_scr(psegs2->ds_len); 8195 if (DEBUG_FLAGS & DEBUG_SCATTER) { 8196 printf ("%s scatter: paddr=%lx len=%ld\n", 8197 sym_name(np), (long) psegs2->ds_addr, 8198 (long) psegs2->ds_len); 8199 } 8200 if (psegs2 != psegs) { 8201 --data; 8202 --psegs2; 8203 continue; 8204 } 8205 break; 8206 } 8207 return 0; 8208 } 8209 8210 #else /* FreeBSD_Bus_Dma_Abstraction */ 8211 8212 /* 8213 * How complex it gets to deal with the data in CAM. 8214 * Variant without the Bus Dma Abstraction option. 8215 */ 8216 static void 8217 sym_setup_data_and_start(hcb_p np, struct ccb_scsiio *csio, ccb_p cp) 8218 { 8219 struct ccb_hdr *ccb_h; 8220 int dir, retv; 8221 8222 ccb_h = &csio->ccb_h; 8223 8224 /* 8225 * Now deal with the data. 8226 */ 8227 cp->data_len = 0; 8228 cp->segments = 0; 8229 8230 /* 8231 * No direction means no data. 8232 */ 8233 dir = (ccb_h->flags & CAM_DIR_MASK); 8234 if (dir == CAM_DIR_NONE) 8235 goto end_scatter; 8236 8237 if (!(ccb_h->flags & CAM_SCATTER_VALID)) { 8238 /* Single buffer */ 8239 if (!(ccb_h->flags & CAM_DATA_PHYS)) { 8240 /* Buffer is virtual */ 8241 retv = sym_scatter_virtual(np, cp, 8242 (vm_offset_t) csio->data_ptr, 8243 (vm_size_t) csio->dxfer_len); 8244 } else { 8245 /* Buffer is physical */ 8246 retv = sym_scatter_physical(np, cp, 8247 (vm_offset_t) csio->data_ptr, 8248 (vm_size_t) csio->dxfer_len); 8249 } 8250 } else { 8251 /* Scatter/gather list */ 8252 int nsegs; 8253 struct bus_dma_segment *segs; 8254 segs = (struct bus_dma_segment *)csio->data_ptr; 8255 nsegs = csio->sglist_cnt; 8256 8257 if ((ccb_h->flags & CAM_SG_LIST_PHYS) != 0) { 8258 /* The SG list pointer is physical */ 8259 sym_set_cam_status(cp->cam_ccb, CAM_REQ_INVALID); 8260 goto out_abort; 8261 } 8262 if (!(ccb_h->flags & CAM_DATA_PHYS)) { 8263 /* SG buffer pointers are virtual */ 8264 retv = sym_scatter_sg_virtual(np, cp, segs, nsegs); 8265 } else { 8266 /* SG buffer pointers are physical */ 8267 retv = sym_scatter_sg_physical(np, cp, segs, nsegs); 8268 } 8269 } 8270 if (retv < 0) { 8271 sym_set_cam_status(cp->cam_ccb, CAM_REQ_TOO_BIG); 8272 goto out_abort; 8273 } 8274 8275 end_scatter: 8276 /* 8277 * Set data pointers. 8278 */ 8279 sym_setup_data_pointers(np, cp, dir); 8280 8281 /* 8282 * Enqueue this IO in our pending queue. 8283 */ 8284 sym_enqueue_cam_ccb(np, (union ccb *) csio); 8285 8286 /* 8287 * Activate this job. 8288 */ 8289 sym_put_start_queue(np, cp); 8290 8291 /* 8292 * Command is successfully queued. 8293 */ 8294 return; 8295 out_abort: 8296 sym_free_ccb(np, cp); 8297 sym_xpt_done(np, (union ccb *) csio); 8298 } 8299 8300 /* 8301 * Scatter a virtual buffer into bus addressable chunks. 8302 */ 8303 static int 8304 sym_scatter_virtual(hcb_p np, ccb_p cp, vm_offset_t vaddr, vm_size_t len) 8305 { 8306 u_long pe, pn; 8307 u_long n, k; 8308 int s; 8309 8310 cp->data_len += len; 8311 8312 pe = vaddr + len; 8313 n = len; 8314 s = SYM_CONF_MAX_SG - 1 - cp->segments; 8315 8316 while (n && s >= 0) { 8317 pn = (pe - 1) & ~PAGE_MASK; 8318 k = pe - pn; 8319 if (k > n) { 8320 k = n; 8321 pn = pe - n; 8322 } 8323 if (DEBUG_FLAGS & DEBUG_SCATTER) { 8324 printf ("%s scatter: va=%lx pa=%lx siz=%ld\n", 8325 sym_name(np), pn, (u_long) vtobus(pn), k); 8326 } 8327 cp->phys.data[s].addr = cpu_to_scr(vtobus(pn)); 8328 cp->phys.data[s].size = cpu_to_scr(k); 8329 pe = pn; 8330 n -= k; 8331 --s; 8332 } 8333 cp->segments = SYM_CONF_MAX_SG - 1 - s; 8334 8335 return n ? -1 : 0; 8336 } 8337 8338 /* 8339 * Scatter a SG list with virtual addresses into bus addressable chunks. 8340 */ 8341 static int 8342 sym_scatter_sg_virtual(hcb_p np, ccb_p cp, bus_dma_segment_t *psegs, int nsegs) 8343 { 8344 int i, retv = 0; 8345 8346 for (i = nsegs - 1 ; i >= 0 ; --i) { 8347 retv = sym_scatter_virtual(np, cp, 8348 psegs[i].ds_addr, psegs[i].ds_len); 8349 if (retv < 0) 8350 break; 8351 } 8352 return retv; 8353 } 8354 8355 /* 8356 * Scatter a physical buffer into bus addressable chunks. 8357 */ 8358 static int 8359 sym_scatter_physical(hcb_p np, ccb_p cp, vm_offset_t paddr, vm_size_t len) 8360 { 8361 struct bus_dma_segment seg; 8362 8363 seg.ds_addr = paddr; 8364 seg.ds_len = len; 8365 return sym_scatter_sg_physical(np, cp, &seg, 1); 8366 } 8367 8368 #endif /* FreeBSD_Bus_Dma_Abstraction */ 8369 8370 /* 8371 * Scatter a SG list with physical addresses into bus addressable chunks. 8372 * We need to ensure 16MB boundaries not to be crossed during DMA of 8373 * each segment, due to some chips being flawed. 8374 */ 8375 #define BOUND_MASK ((1UL<<24)-1) 8376 static int 8377 sym_scatter_sg_physical(hcb_p np, ccb_p cp, bus_dma_segment_t *psegs, int nsegs) 8378 { 8379 u_long ps, pe, pn; 8380 u_long k; 8381 int s, t; 8382 8383 #ifndef FreeBSD_Bus_Dma_Abstraction 8384 s = SYM_CONF_MAX_SG - 1 - cp->segments; 8385 #else 8386 s = SYM_CONF_MAX_SG - 1; 8387 #endif 8388 t = nsegs - 1; 8389 ps = psegs[t].ds_addr; 8390 pe = ps + psegs[t].ds_len; 8391 8392 while (s >= 0) { 8393 pn = (pe - 1) & ~BOUND_MASK; 8394 if (pn <= ps) 8395 pn = ps; 8396 k = pe - pn; 8397 if (DEBUG_FLAGS & DEBUG_SCATTER) { 8398 printf ("%s scatter: paddr=%lx len=%ld\n", 8399 sym_name(np), pn, k); 8400 } 8401 cp->phys.data[s].addr = cpu_to_scr(pn); 8402 cp->phys.data[s].size = cpu_to_scr(k); 8403 #ifndef FreeBSD_Bus_Dma_Abstraction 8404 cp->data_len += k; 8405 #endif 8406 --s; 8407 if (pn == ps) { 8408 if (--t < 0) 8409 break; 8410 ps = psegs[t].ds_addr; 8411 pe = ps + psegs[t].ds_len; 8412 } 8413 else 8414 pe = pn; 8415 } 8416 8417 cp->segments = SYM_CONF_MAX_SG - 1 - s; 8418 8419 return t >= 0 ? -1 : 0; 8420 } 8421 #undef BOUND_MASK 8422 8423 /* 8424 * SIM action for non performance critical stuff. 8425 */ 8426 static void sym_action2(struct cam_sim *sim, union ccb *ccb) 8427 { 8428 hcb_p np; 8429 tcb_p tp; 8430 lcb_p lp; 8431 struct ccb_hdr *ccb_h; 8432 8433 /* 8434 * Retrieve our controller data structure. 8435 */ 8436 np = (hcb_p) cam_sim_softc(sim); 8437 8438 ccb_h = &ccb->ccb_h; 8439 8440 switch (ccb_h->func_code) { 8441 case XPT_SET_TRAN_SETTINGS: 8442 { 8443 struct ccb_trans_settings *cts; 8444 8445 cts = &ccb->cts; 8446 tp = &np->target[ccb_h->target_id]; 8447 8448 /* 8449 * Update SPI transport settings in TARGET control block. 8450 * Update SCSI device settings in LUN control block. 8451 */ 8452 lp = sym_lp(np, tp, ccb_h->target_lun); 8453 #ifdef FreeBSD_New_Tran_Settings 8454 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) { 8455 #else 8456 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) { 8457 #endif 8458 sym_update_trans(np, tp, &tp->tinfo.goal, cts); 8459 if (lp) 8460 sym_update_dflags(np, &lp->current_flags, cts); 8461 } 8462 #ifdef FreeBSD_New_Tran_Settings 8463 if (cts->type == CTS_TYPE_USER_SETTINGS) { 8464 #else 8465 if ((cts->flags & CCB_TRANS_USER_SETTINGS) != 0) { 8466 #endif 8467 sym_update_trans(np, tp, &tp->tinfo.user, cts); 8468 if (lp) 8469 sym_update_dflags(np, &lp->user_flags, cts); 8470 } 8471 8472 sym_xpt_done2(np, ccb, CAM_REQ_CMP); 8473 break; 8474 } 8475 case XPT_GET_TRAN_SETTINGS: 8476 { 8477 struct ccb_trans_settings *cts; 8478 struct sym_trans *tip; 8479 u_char dflags; 8480 8481 cts = &ccb->cts; 8482 tp = &np->target[ccb_h->target_id]; 8483 lp = sym_lp(np, tp, ccb_h->target_lun); 8484 8485 #ifdef FreeBSD_New_Tran_Settings 8486 #define cts__scsi (&cts->proto_specific.scsi) 8487 #define cts__spi (&cts->xport_specific.spi) 8488 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) { 8489 tip = &tp->tinfo.current; 8490 dflags = lp ? lp->current_flags : 0; 8491 } 8492 else { 8493 tip = &tp->tinfo.user; 8494 dflags = lp ? lp->user_flags : tp->usrflags; 8495 } 8496 8497 cts->protocol = PROTO_SCSI; 8498 cts->transport = XPORT_SPI; 8499 cts->protocol_version = tip->scsi_version; 8500 cts->transport_version = tip->spi_version; 8501 8502 cts__spi->sync_period = tip->period; 8503 cts__spi->sync_offset = tip->offset; 8504 cts__spi->bus_width = tip->width; 8505 cts__spi->ppr_options = tip->options; 8506 8507 cts__spi->valid = CTS_SPI_VALID_SYNC_RATE 8508 | CTS_SPI_VALID_SYNC_OFFSET 8509 | CTS_SPI_VALID_BUS_WIDTH 8510 | CTS_SPI_VALID_PPR_OPTIONS; 8511 8512 cts__spi->flags &= ~CTS_SPI_FLAGS_DISC_ENB; 8513 if (dflags & SYM_DISC_ENABLED) 8514 cts__spi->flags |= CTS_SPI_FLAGS_DISC_ENB; 8515 cts__spi->valid |= CTS_SPI_VALID_DISC; 8516 8517 cts__scsi->flags &= ~CTS_SCSI_FLAGS_TAG_ENB; 8518 if (dflags & SYM_TAGS_ENABLED) 8519 cts__scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB; 8520 cts__scsi->valid |= CTS_SCSI_VALID_TQ; 8521 #undef cts__spi 8522 #undef cts__scsi 8523 #else 8524 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) { 8525 tip = &tp->tinfo.current; 8526 dflags = lp ? lp->current_flags : 0; 8527 } 8528 else { 8529 tip = &tp->tinfo.user; 8530 dflags = lp ? lp->user_flags : tp->usrflags; 8531 } 8532 8533 cts->sync_period = tip->period; 8534 cts->sync_offset = tip->offset; 8535 cts->bus_width = tip->width; 8536 8537 cts->valid = CCB_TRANS_SYNC_RATE_VALID 8538 | CCB_TRANS_SYNC_OFFSET_VALID 8539 | CCB_TRANS_BUS_WIDTH_VALID; 8540 8541 cts->flags &= ~(CCB_TRANS_DISC_ENB|CCB_TRANS_TAG_ENB); 8542 8543 if (dflags & SYM_DISC_ENABLED) 8544 cts->flags |= CCB_TRANS_DISC_ENB; 8545 8546 if (dflags & SYM_TAGS_ENABLED) 8547 cts->flags |= CCB_TRANS_TAG_ENB; 8548 8549 cts->valid |= CCB_TRANS_DISC_VALID; 8550 cts->valid |= CCB_TRANS_TQ_VALID; 8551 #endif 8552 sym_xpt_done2(np, ccb, CAM_REQ_CMP); 8553 break; 8554 } 8555 case XPT_CALC_GEOMETRY: 8556 { 8557 struct ccb_calc_geometry *ccg; 8558 u32 size_mb; 8559 u32 secs_per_cylinder; 8560 int extended; 8561 8562 /* 8563 * Silly DOS geometry. 8564 */ 8565 ccg = &ccb->ccg; 8566 size_mb = ccg->volume_size 8567 / ((1024L * 1024L) / ccg->block_size); 8568 extended = 1; 8569 8570 if (size_mb > 1024 && extended) { 8571 ccg->heads = 255; 8572 ccg->secs_per_track = 63; 8573 } else { 8574 ccg->heads = 64; 8575 ccg->secs_per_track = 32; 8576 } 8577 secs_per_cylinder = ccg->heads * ccg->secs_per_track; 8578 ccg->cylinders = ccg->volume_size / secs_per_cylinder; 8579 sym_xpt_done2(np, ccb, CAM_REQ_CMP); 8580 break; 8581 } 8582 case XPT_PATH_INQ: 8583 { 8584 struct ccb_pathinq *cpi = &ccb->cpi; 8585 cpi->version_num = 1; 8586 cpi->hba_inquiry = PI_MDP_ABLE|PI_SDTR_ABLE|PI_TAG_ABLE; 8587 if ((np->features & FE_WIDE) != 0) 8588 cpi->hba_inquiry |= PI_WIDE_16; 8589 cpi->target_sprt = 0; 8590 cpi->hba_misc = 0; 8591 if (np->usrflags & SYM_SCAN_TARGETS_HILO) 8592 cpi->hba_misc |= PIM_SCANHILO; 8593 if (np->usrflags & SYM_AVOID_BUS_RESET) 8594 cpi->hba_misc |= PIM_NOBUSRESET; 8595 cpi->hba_eng_cnt = 0; 8596 cpi->max_target = (np->features & FE_WIDE) ? 15 : 7; 8597 /* Semantic problem:)LUN number max = max number of LUNs - 1 */ 8598 cpi->max_lun = SYM_CONF_MAX_LUN-1; 8599 if (SYM_SETUP_MAX_LUN < SYM_CONF_MAX_LUN) 8600 cpi->max_lun = SYM_SETUP_MAX_LUN-1; 8601 cpi->bus_id = cam_sim_bus(sim); 8602 cpi->initiator_id = np->myaddr; 8603 cpi->base_transfer_speed = 3300; 8604 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 8605 strncpy(cpi->hba_vid, "Symbios", HBA_IDLEN); 8606 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 8607 cpi->unit_number = cam_sim_unit(sim); 8608 8609 #ifdef FreeBSD_New_Tran_Settings 8610 cpi->protocol = PROTO_SCSI; 8611 cpi->protocol_version = SCSI_REV_2; 8612 cpi->transport = XPORT_SPI; 8613 cpi->transport_version = 2; 8614 cpi->xport_specific.spi.ppr_options = SID_SPI_CLOCK_ST; 8615 if (np->features & FE_ULTRA3) { 8616 cpi->transport_version = 3; 8617 cpi->xport_specific.spi.ppr_options = 8618 SID_SPI_CLOCK_DT_ST; 8619 } 8620 #endif 8621 sym_xpt_done2(np, ccb, CAM_REQ_CMP); 8622 break; 8623 } 8624 case XPT_ABORT: 8625 { 8626 union ccb *abort_ccb = ccb->cab.abort_ccb; 8627 switch(abort_ccb->ccb_h.func_code) { 8628 case XPT_SCSI_IO: 8629 if (sym_abort_scsiio(np, abort_ccb, 0) == 0) { 8630 sym_xpt_done2(np, ccb, CAM_REQ_CMP); 8631 break; 8632 } 8633 default: 8634 sym_xpt_done2(np, ccb, CAM_UA_ABORT); 8635 break; 8636 } 8637 break; 8638 } 8639 case XPT_RESET_DEV: 8640 { 8641 sym_reset_dev(np, ccb); 8642 break; 8643 } 8644 case XPT_RESET_BUS: 8645 { 8646 sym_reset_scsi_bus(np, 0); 8647 if (sym_verbose) { 8648 xpt_print_path(np->path); 8649 printf("SCSI BUS reset delivered.\n"); 8650 } 8651 sym_init (np, 1); 8652 sym_xpt_done2(np, ccb, CAM_REQ_CMP); 8653 break; 8654 } 8655 case XPT_ACCEPT_TARGET_IO: 8656 case XPT_CONT_TARGET_IO: 8657 case XPT_EN_LUN: 8658 case XPT_NOTIFY_ACK: 8659 case XPT_IMMED_NOTIFY: 8660 case XPT_TERM_IO: 8661 default: 8662 sym_xpt_done2(np, ccb, CAM_REQ_INVALID); 8663 break; 8664 } 8665 } 8666 8667 /* 8668 * Asynchronous notification handler. 8669 */ 8670 static void 8671 sym_async(void *cb_arg, u32 code, struct cam_path *path, void *arg) 8672 { 8673 hcb_p np; 8674 struct cam_sim *sim; 8675 u_int tn; 8676 tcb_p tp; 8677 int s; 8678 8679 s = splcam(); 8680 8681 sim = (struct cam_sim *) cb_arg; 8682 np = (hcb_p) cam_sim_softc(sim); 8683 8684 switch (code) { 8685 case AC_LOST_DEVICE: 8686 tn = xpt_path_target_id(path); 8687 if (tn >= SYM_CONF_MAX_TARGET) 8688 break; 8689 8690 tp = &np->target[tn]; 8691 8692 tp->to_reset = 0; 8693 tp->head.sval = 0; 8694 tp->head.wval = np->rv_scntl3; 8695 tp->head.uval = 0; 8696 8697 tp->tinfo.current.period = tp->tinfo.goal.period = 0; 8698 tp->tinfo.current.offset = tp->tinfo.goal.offset = 0; 8699 tp->tinfo.current.width = tp->tinfo.goal.width = BUS_8_BIT; 8700 tp->tinfo.current.options = tp->tinfo.goal.options = 0; 8701 8702 break; 8703 default: 8704 break; 8705 } 8706 8707 splx(s); 8708 } 8709 8710 /* 8711 * Update transfer settings of a target. 8712 */ 8713 static void sym_update_trans(hcb_p np, tcb_p tp, struct sym_trans *tip, 8714 struct ccb_trans_settings *cts) 8715 { 8716 /* 8717 * Update the infos. 8718 */ 8719 #ifdef FreeBSD_New_Tran_Settings 8720 #define cts__spi (&cts->xport_specific.spi) 8721 if ((cts__spi->valid & CTS_SPI_VALID_BUS_WIDTH) != 0) 8722 tip->width = cts__spi->bus_width; 8723 if ((cts__spi->valid & CTS_SPI_VALID_SYNC_OFFSET) != 0) 8724 tip->offset = cts__spi->sync_offset; 8725 if ((cts__spi->valid & CTS_SPI_VALID_SYNC_RATE) != 0) 8726 tip->period = cts__spi->sync_period; 8727 if ((cts__spi->valid & CTS_SPI_VALID_PPR_OPTIONS) != 0) 8728 tip->options = (cts__spi->ppr_options & PPR_OPT_DT); 8729 if (cts->protocol_version != PROTO_VERSION_UNSPECIFIED && 8730 cts->protocol_version != PROTO_VERSION_UNKNOWN) 8731 tip->scsi_version = cts->protocol_version; 8732 if (cts->transport_version != XPORT_VERSION_UNSPECIFIED && 8733 cts->transport_version != XPORT_VERSION_UNKNOWN) 8734 tip->spi_version = cts->transport_version; 8735 #undef cts__spi 8736 #else 8737 if ((cts->valid & CCB_TRANS_BUS_WIDTH_VALID) != 0) 8738 tip->width = cts->bus_width; 8739 if ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) != 0) 8740 tip->offset = cts->sync_offset; 8741 if ((cts->valid & CCB_TRANS_SYNC_RATE_VALID) != 0) 8742 tip->period = cts->sync_period; 8743 #endif 8744 /* 8745 * Scale against driver configuration limits. 8746 */ 8747 if (tip->width > SYM_SETUP_MAX_WIDE) tip->width = SYM_SETUP_MAX_WIDE; 8748 if (tip->offset > SYM_SETUP_MAX_OFFS) tip->offset = SYM_SETUP_MAX_OFFS; 8749 if (tip->period < SYM_SETUP_MIN_SYNC) tip->period = SYM_SETUP_MIN_SYNC; 8750 8751 /* 8752 * Scale against actual controller BUS width. 8753 */ 8754 if (tip->width > np->maxwide) 8755 tip->width = np->maxwide; 8756 8757 #ifdef FreeBSD_New_Tran_Settings 8758 /* 8759 * Only accept DT if controller supports and SYNC/WIDE asked. 8760 */ 8761 if (!((np->features & (FE_C10|FE_ULTRA3)) == (FE_C10|FE_ULTRA3)) || 8762 !(tip->width == BUS_16_BIT && tip->offset)) { 8763 tip->options &= ~PPR_OPT_DT; 8764 } 8765 #else 8766 /* 8767 * For now, only assume DT if period <= 9, BUS 16 and offset != 0. 8768 */ 8769 tip->options = 0; 8770 if ((np->features & (FE_C10|FE_ULTRA3)) == (FE_C10|FE_ULTRA3) && 8771 tip->period <= 9 && tip->width == BUS_16_BIT && tip->offset) { 8772 tip->options |= PPR_OPT_DT; 8773 } 8774 #endif 8775 8776 /* 8777 * Scale period factor and offset against controller limits. 8778 */ 8779 if (tip->options & PPR_OPT_DT) { 8780 if (tip->period < np->minsync_dt) 8781 tip->period = np->minsync_dt; 8782 if (tip->period > np->maxsync_dt) 8783 tip->period = np->maxsync_dt; 8784 if (tip->offset > np->maxoffs_dt) 8785 tip->offset = np->maxoffs_dt; 8786 } 8787 else { 8788 if (tip->period < np->minsync) 8789 tip->period = np->minsync; 8790 if (tip->period > np->maxsync) 8791 tip->period = np->maxsync; 8792 if (tip->offset > np->maxoffs) 8793 tip->offset = np->maxoffs; 8794 } 8795 } 8796 8797 /* 8798 * Update flags for a device (logical unit). 8799 */ 8800 static void 8801 sym_update_dflags(hcb_p np, u_char *flags, struct ccb_trans_settings *cts) 8802 { 8803 #ifdef FreeBSD_New_Tran_Settings 8804 #define cts__scsi (&cts->proto_specific.scsi) 8805 #define cts__spi (&cts->xport_specific.spi) 8806 if ((cts__spi->valid & CTS_SPI_VALID_DISC) != 0) { 8807 if ((cts__spi->flags & CTS_SPI_FLAGS_DISC_ENB) != 0) 8808 *flags |= SYM_DISC_ENABLED; 8809 else 8810 *flags &= ~SYM_DISC_ENABLED; 8811 } 8812 8813 if ((cts__scsi->valid & CTS_SCSI_VALID_TQ) != 0) { 8814 if ((cts__scsi->flags & CTS_SCSI_FLAGS_TAG_ENB) != 0) 8815 *flags |= SYM_TAGS_ENABLED; 8816 else 8817 *flags &= ~SYM_TAGS_ENABLED; 8818 } 8819 #undef cts__spi 8820 #undef cts__scsi 8821 #else 8822 if ((cts->valid & CCB_TRANS_DISC_VALID) != 0) { 8823 if ((cts->flags & CCB_TRANS_DISC_ENB) != 0) 8824 *flags |= SYM_DISC_ENABLED; 8825 else 8826 *flags &= ~SYM_DISC_ENABLED; 8827 } 8828 8829 if ((cts->valid & CCB_TRANS_TQ_VALID) != 0) { 8830 if ((cts->flags & CCB_TRANS_TAG_ENB) != 0) 8831 *flags |= SYM_TAGS_ENABLED; 8832 else 8833 *flags &= ~SYM_TAGS_ENABLED; 8834 } 8835 #endif 8836 } 8837 8838 8839 /*============= DRIVER INITIALISATION ==================*/ 8840 8841 #ifdef FreeBSD_Bus_Io_Abstraction 8842 8843 static device_method_t sym_pci_methods[] = { 8844 DEVMETHOD(device_probe, sym_pci_probe), 8845 DEVMETHOD(device_attach, sym_pci_attach), 8846 { 0, 0 } 8847 }; 8848 8849 static driver_t sym_pci_driver = { 8850 "sym", 8851 sym_pci_methods, 8852 sizeof(struct sym_hcb) 8853 }; 8854 8855 static devclass_t sym_devclass; 8856 8857 DRIVER_MODULE(sym, pci, sym_pci_driver, sym_devclass, 0, 0); 8858 8859 #else /* Pre-FreeBSD_Bus_Io_Abstraction */ 8860 8861 static u_long sym_unit; 8862 8863 static struct pci_device sym_pci_driver = { 8864 "sym", 8865 sym_pci_probe, 8866 sym_pci_attach, 8867 &sym_unit, 8868 NULL 8869 }; 8870 8871 #if __FreeBSD_version >= 400000 8872 COMPAT_PCI_DRIVER (sym, sym_pci_driver); 8873 #else 8874 DATA_SET (pcidevice_set, sym_pci_driver); 8875 #endif 8876 8877 #endif /* FreeBSD_Bus_Io_Abstraction */ 8878 8879 static struct sym_pci_chip sym_pci_dev_table[] = { 8880 {PCI_ID_SYM53C810, 0x0f, "810", 4, 8, 4, 64, 8881 FE_ERL} 8882 , 8883 #ifdef SYM_DEBUG_GENERIC_SUPPORT 8884 {PCI_ID_SYM53C810, 0xff, "810a", 4, 8, 4, 1, 8885 FE_BOF} 8886 , 8887 #else 8888 {PCI_ID_SYM53C810, 0xff, "810a", 4, 8, 4, 1, 8889 FE_CACHE_SET|FE_LDSTR|FE_PFEN|FE_BOF} 8890 , 8891 #endif 8892 {PCI_ID_SYM53C815, 0xff, "815", 4, 8, 4, 64, 8893 FE_BOF|FE_ERL} 8894 , 8895 {PCI_ID_SYM53C825, 0x0f, "825", 6, 8, 4, 64, 8896 FE_WIDE|FE_BOF|FE_ERL|FE_DIFF} 8897 , 8898 {PCI_ID_SYM53C825, 0xff, "825a", 6, 8, 4, 2, 8899 FE_WIDE|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM|FE_DIFF} 8900 , 8901 {PCI_ID_SYM53C860, 0xff, "860", 4, 8, 5, 1, 8902 FE_ULTRA|FE_CLK80|FE_CACHE_SET|FE_BOF|FE_LDSTR|FE_PFEN} 8903 , 8904 {PCI_ID_SYM53C875, 0x01, "875", 6, 16, 5, 2, 8905 FE_WIDE|FE_ULTRA|FE_CLK80|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 8906 FE_RAM|FE_DIFF} 8907 , 8908 {PCI_ID_SYM53C875, 0xff, "875", 6, 16, 5, 2, 8909 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 8910 FE_RAM|FE_DIFF} 8911 , 8912 {PCI_ID_SYM53C875_2, 0xff, "875", 6, 16, 5, 2, 8913 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 8914 FE_RAM|FE_DIFF} 8915 , 8916 {PCI_ID_SYM53C885, 0xff, "885", 6, 16, 5, 2, 8917 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 8918 FE_RAM|FE_DIFF} 8919 , 8920 #ifdef SYM_DEBUG_GENERIC_SUPPORT 8921 {PCI_ID_SYM53C895, 0xff, "895", 6, 31, 7, 2, 8922 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS| 8923 FE_RAM|FE_LCKFRQ} 8924 , 8925 #else 8926 {PCI_ID_SYM53C895, 0xff, "895", 6, 31, 7, 2, 8927 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 8928 FE_RAM|FE_LCKFRQ} 8929 , 8930 #endif 8931 {PCI_ID_SYM53C896, 0xff, "896", 6, 31, 7, 4, 8932 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 8933 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_LCKFRQ} 8934 , 8935 {PCI_ID_SYM53C895A, 0xff, "895a", 6, 31, 7, 4, 8936 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 8937 FE_RAM|FE_RAM8K|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_LCKFRQ} 8938 , 8939 {PCI_ID_LSI53C1010, 0x00, "1010-33", 6, 31, 7, 8, 8940 FE_WIDE|FE_ULTRA3|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFBC|FE_LDSTR|FE_PFEN| 8941 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_CRC| 8942 FE_C10} 8943 , 8944 {PCI_ID_LSI53C1010, 0xff, "1010-33", 6, 31, 7, 8, 8945 FE_WIDE|FE_ULTRA3|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFBC|FE_LDSTR|FE_PFEN| 8946 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_CRC| 8947 FE_C10|FE_U3EN} 8948 , 8949 {PCI_ID_LSI53C1010_2, 0xff, "1010-66", 6, 31, 7, 8, 8950 FE_WIDE|FE_ULTRA3|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFBC|FE_LDSTR|FE_PFEN| 8951 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_66MHZ|FE_CRC| 8952 FE_C10|FE_U3EN} 8953 , 8954 {PCI_ID_LSI53C1510D, 0xff, "1510d", 6, 31, 7, 4, 8955 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 8956 FE_RAM|FE_IO256|FE_LEDC} 8957 }; 8958 8959 #define sym_pci_num_devs \ 8960 (sizeof(sym_pci_dev_table) / sizeof(sym_pci_dev_table[0])) 8961 8962 /* 8963 * Look up the chip table. 8964 * 8965 * Return a pointer to the chip entry if found, 8966 * zero otherwise. 8967 */ 8968 static struct sym_pci_chip * 8969 #ifdef FreeBSD_Bus_Io_Abstraction 8970 sym_find_pci_chip(device_t dev) 8971 #else 8972 sym_find_pci_chip(pcici_t pci_tag) 8973 #endif 8974 { 8975 struct sym_pci_chip *chip; 8976 int i; 8977 u_short device_id; 8978 u_char revision; 8979 8980 #ifdef FreeBSD_Bus_Io_Abstraction 8981 if (pci_get_vendor(dev) != PCI_VENDOR_NCR) 8982 return 0; 8983 8984 device_id = pci_get_device(dev); 8985 revision = pci_get_revid(dev); 8986 #else 8987 if (pci_cfgread(pci_tag, PCIR_VENDOR, 2) != PCI_VENDOR_NCR) 8988 return 0; 8989 8990 device_id = pci_cfgread(pci_tag, PCIR_DEVICE, 2); 8991 revision = pci_cfgread(pci_tag, PCIR_REVID, 1); 8992 #endif 8993 8994 for (i = 0; i < sym_pci_num_devs; i++) { 8995 chip = &sym_pci_dev_table[i]; 8996 if (device_id != chip->device_id) 8997 continue; 8998 if (revision > chip->revision_id) 8999 continue; 9000 return chip; 9001 } 9002 9003 return 0; 9004 } 9005 9006 /* 9007 * Tell upper layer if the chip is supported. 9008 */ 9009 #ifdef FreeBSD_Bus_Io_Abstraction 9010 static int 9011 sym_pci_probe(device_t dev) 9012 { 9013 struct sym_pci_chip *chip; 9014 9015 chip = sym_find_pci_chip(dev); 9016 if (chip && sym_find_firmware(chip)) { 9017 device_set_desc(dev, chip->name); 9018 return (chip->lp_probe_bit & SYM_SETUP_LP_PROBE_MAP)? -2000 : 0; 9019 } 9020 return ENXIO; 9021 } 9022 #else /* Pre-FreeBSD_Bus_Io_Abstraction */ 9023 static const char * 9024 sym_pci_probe(pcici_t pci_tag, pcidi_t type) 9025 { 9026 struct sym_pci_chip *chip; 9027 9028 chip = sym_find_pci_chip(pci_tag); 9029 if (chip && sym_find_firmware(chip)) { 9030 #if NNCR > 0 9031 /* Only claim chips we are allowed to take precedence over the ncr */ 9032 if (!(chip->lp_probe_bit & SYM_SETUP_LP_PROBE_MAP)) 9033 #else 9034 if (1) 9035 #endif 9036 return chip->name; 9037 } 9038 return 0; 9039 } 9040 #endif 9041 9042 /* 9043 * Attach a sym53c8xx device. 9044 */ 9045 #ifdef FreeBSD_Bus_Io_Abstraction 9046 static int 9047 sym_pci_attach(device_t dev) 9048 #else 9049 static void 9050 sym_pci_attach(pcici_t pci_tag, int unit) 9051 { 9052 int err = sym_pci_attach2(pci_tag, unit); 9053 if (err) 9054 printf("sym: failed to attach unit %d - err=%d.\n", unit, err); 9055 } 9056 static int 9057 sym_pci_attach2(pcici_t pci_tag, int unit) 9058 #endif 9059 { 9060 struct sym_pci_chip *chip; 9061 u_short command; 9062 u_char cachelnsz; 9063 struct sym_hcb *np = 0; 9064 struct sym_nvram nvram; 9065 struct sym_fw *fw = 0; 9066 int i; 9067 #ifdef FreeBSD_Bus_Dma_Abstraction 9068 bus_dma_tag_t bus_dmat; 9069 9070 /* 9071 * I expected to be told about a parent 9072 * DMA tag, but didn't find any. 9073 */ 9074 bus_dmat = NULL; 9075 #endif 9076 9077 /* 9078 * Only probed devices should be attached. 9079 * We just enjoy being paranoid. :) 9080 */ 9081 #ifdef FreeBSD_Bus_Io_Abstraction 9082 chip = sym_find_pci_chip(dev); 9083 #else 9084 chip = sym_find_pci_chip(pci_tag); 9085 #endif 9086 if (chip == NULL || (fw = sym_find_firmware(chip)) == NULL) 9087 return (ENXIO); 9088 9089 /* 9090 * Allocate immediately the host control block, 9091 * since we are only expecting to succeed. :) 9092 * We keep track in the HCB of all the resources that 9093 * are to be released on error. 9094 */ 9095 #ifdef FreeBSD_Bus_Dma_Abstraction 9096 np = __sym_calloc_dma(bus_dmat, sizeof(*np), "HCB"); 9097 if (np) 9098 np->bus_dmat = bus_dmat; 9099 else 9100 goto attach_failed; 9101 #else 9102 np = sym_calloc_dma(sizeof(*np), "HCB"); 9103 if (!np) 9104 goto attach_failed; 9105 #endif 9106 9107 /* 9108 * Copy some useful infos to the HCB. 9109 */ 9110 np->hcb_ba = vtobus(np); 9111 np->verbose = bootverbose; 9112 #ifdef FreeBSD_Bus_Io_Abstraction 9113 np->device = dev; 9114 np->unit = device_get_unit(dev); 9115 np->device_id = pci_get_device(dev); 9116 np->revision_id = pci_get_revid(dev); 9117 #else 9118 np->pci_tag = pci_tag; 9119 np->unit = unit; 9120 np->device_id = pci_cfgread(pci_tag, PCIR_DEVICE, 2); 9121 np->revision_id = pci_cfgread(pci_tag, PCIR_REVID, 1); 9122 #endif 9123 np->features = chip->features; 9124 np->clock_divn = chip->nr_divisor; 9125 np->maxoffs = chip->offset_max; 9126 np->maxburst = chip->burst_max; 9127 np->scripta_sz = fw->a_size; 9128 np->scriptb_sz = fw->b_size; 9129 np->fw_setup = fw->setup; 9130 np->fw_patch = fw->patch; 9131 np->fw_name = fw->name; 9132 9133 /* 9134 * Edit its name. 9135 */ 9136 snprintf(np->inst_name, sizeof(np->inst_name), "sym%d", np->unit); 9137 9138 /* 9139 * Initialyze the CCB free and busy queues. 9140 */ 9141 sym_que_init(&np->free_ccbq); 9142 sym_que_init(&np->busy_ccbq); 9143 sym_que_init(&np->comp_ccbq); 9144 sym_que_init(&np->cam_ccbq); 9145 9146 /* 9147 * Allocate a tag for the DMA of user data. 9148 */ 9149 #ifdef FreeBSD_Bus_Dma_Abstraction 9150 if (bus_dma_tag_create(np->bus_dmat, 1, (1<<24), 9151 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 9152 NULL, NULL, 9153 BUS_SPACE_MAXSIZE, SYM_CONF_MAX_SG, 9154 (1<<24), 0, &np->data_dmat)) { 9155 device_printf(dev, "failed to create DMA tag.\n"); 9156 goto attach_failed; 9157 } 9158 #endif 9159 /* 9160 * Read and apply some fix-ups to the PCI COMMAND 9161 * register. We want the chip to be enabled for: 9162 * - BUS mastering 9163 * - PCI parity checking (reporting would also be fine) 9164 * - Write And Invalidate. 9165 */ 9166 #ifdef FreeBSD_Bus_Io_Abstraction 9167 command = pci_read_config(dev, PCIR_COMMAND, 2); 9168 #else 9169 command = pci_cfgread(pci_tag, PCIR_COMMAND, 2); 9170 #endif 9171 command |= PCIM_CMD_BUSMASTEREN; 9172 command |= PCIM_CMD_PERRESPEN; 9173 command |= /* PCIM_CMD_MWIEN */ 0x0010; 9174 #ifdef FreeBSD_Bus_Io_Abstraction 9175 pci_write_config(dev, PCIR_COMMAND, command, 2); 9176 #else 9177 pci_cfgwrite(pci_tag, PCIR_COMMAND, command, 2); 9178 #endif 9179 9180 /* 9181 * Let the device know about the cache line size, 9182 * if it doesn't yet. 9183 */ 9184 #ifdef FreeBSD_Bus_Io_Abstraction 9185 cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 9186 #else 9187 cachelnsz = pci_cfgread(pci_tag, PCIR_CACHELNSZ, 1); 9188 #endif 9189 if (!cachelnsz) { 9190 cachelnsz = 8; 9191 #ifdef FreeBSD_Bus_Io_Abstraction 9192 pci_write_config(dev, PCIR_CACHELNSZ, cachelnsz, 1); 9193 #else 9194 pci_cfgwrite(pci_tag, PCIR_CACHELNSZ, cachelnsz, 1); 9195 #endif 9196 } 9197 9198 /* 9199 * Alloc/get/map/retrieve everything that deals with MMIO. 9200 */ 9201 #ifdef FreeBSD_Bus_Io_Abstraction 9202 if ((command & PCIM_CMD_MEMEN) != 0) { 9203 int regs_id = SYM_PCI_MMIO; 9204 np->mmio_res = bus_alloc_resource(dev, SYS_RES_MEMORY, ®s_id, 9205 0, ~0, 1, RF_ACTIVE); 9206 } 9207 if (!np->mmio_res) { 9208 device_printf(dev, "failed to allocate MMIO resources\n"); 9209 goto attach_failed; 9210 } 9211 np->mmio_bsh = rman_get_bushandle(np->mmio_res); 9212 np->mmio_tag = rman_get_bustag(np->mmio_res); 9213 np->mmio_pa = rman_get_start(np->mmio_res); 9214 np->mmio_va = (vm_offset_t) rman_get_virtual(np->mmio_res); 9215 np->mmio_ba = np->mmio_pa; 9216 #else 9217 if ((command & PCIM_CMD_MEMEN) != 0) { 9218 vm_offset_t vaddr, paddr; 9219 if (!pci_map_mem(pci_tag, SYM_PCI_MMIO, &vaddr, &paddr)) { 9220 printf("%s: failed to map MMIO window\n", sym_name(np)); 9221 goto attach_failed; 9222 } 9223 np->mmio_va = vaddr; 9224 np->mmio_pa = paddr; 9225 np->mmio_ba = paddr; 9226 } 9227 #endif 9228 9229 /* 9230 * Allocate the IRQ. 9231 */ 9232 #ifdef FreeBSD_Bus_Io_Abstraction 9233 i = 0; 9234 np->irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &i, 9235 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 9236 if (!np->irq_res) { 9237 device_printf(dev, "failed to allocate IRQ resource\n"); 9238 goto attach_failed; 9239 } 9240 #endif 9241 9242 #ifdef SYM_CONF_IOMAPPED 9243 /* 9244 * User want us to use normal IO with PCI. 9245 * Alloc/get/map/retrieve everything that deals with IO. 9246 */ 9247 #ifdef FreeBSD_Bus_Io_Abstraction 9248 if ((command & PCI_COMMAND_IO_ENABLE) != 0) { 9249 int regs_id = SYM_PCI_IO; 9250 np->io_res = bus_alloc_resource(dev, SYS_RES_IOPORT, ®s_id, 9251 0, ~0, 1, RF_ACTIVE); 9252 } 9253 if (!np->io_res) { 9254 device_printf(dev, "failed to allocate IO resources\n"); 9255 goto attach_failed; 9256 } 9257 np->io_bsh = rman_get_bushandle(np->io_res); 9258 np->io_tag = rman_get_bustag(np->io_res); 9259 np->io_port = rman_get_start(np->io_res); 9260 #else 9261 if ((command & PCI_COMMAND_IO_ENABLE) != 0) { 9262 pci_port_t io_port; 9263 if (!pci_map_port (pci_tag, SYM_PCI_IO, &io_port)) { 9264 printf("%s: failed to map IO window\n", sym_name(np)); 9265 goto attach_failed; 9266 } 9267 np->io_port = io_port; 9268 } 9269 #endif 9270 9271 #endif /* SYM_CONF_IOMAPPED */ 9272 9273 /* 9274 * If the chip has RAM. 9275 * Alloc/get/map/retrieve the corresponding resources. 9276 */ 9277 if ((np->features & (FE_RAM|FE_RAM8K)) && 9278 (command & PCIM_CMD_MEMEN) != 0) { 9279 #ifdef FreeBSD_Bus_Io_Abstraction 9280 int regs_id = SYM_PCI_RAM; 9281 if (np->features & FE_64BIT) 9282 regs_id = SYM_PCI_RAM64; 9283 np->ram_res = bus_alloc_resource(dev, SYS_RES_MEMORY, ®s_id, 9284 0, ~0, 1, RF_ACTIVE); 9285 if (!np->ram_res) { 9286 device_printf(dev,"failed to allocate RAM resources\n"); 9287 goto attach_failed; 9288 } 9289 np->ram_id = regs_id; 9290 np->ram_bsh = rman_get_bushandle(np->ram_res); 9291 np->ram_tag = rman_get_bustag(np->ram_res); 9292 np->ram_pa = rman_get_start(np->ram_res); 9293 np->ram_va = (vm_offset_t) rman_get_virtual(np->ram_res); 9294 np->ram_ba = np->ram_pa; 9295 #else 9296 vm_offset_t vaddr, paddr; 9297 int regs_id = SYM_PCI_RAM; 9298 if (np->features & FE_64BIT) 9299 regs_id = SYM_PCI_RAM64; 9300 if (!pci_map_mem(pci_tag, regs_id, &vaddr, &paddr)) { 9301 printf("%s: failed to map RAM window\n", sym_name(np)); 9302 goto attach_failed; 9303 } 9304 np->ram_va = vaddr; 9305 np->ram_pa = paddr; 9306 np->ram_ba = paddr; 9307 #endif 9308 } 9309 9310 /* 9311 * Save setting of some IO registers, so we will 9312 * be able to probe specific implementations. 9313 */ 9314 sym_save_initial_setting (np); 9315 9316 /* 9317 * Reset the chip now, since it has been reported 9318 * that SCSI clock calibration may not work properly 9319 * if the chip is currently active. 9320 */ 9321 sym_chip_reset (np); 9322 9323 /* 9324 * Try to read the user set-up. 9325 */ 9326 (void) sym_read_nvram(np, &nvram); 9327 9328 /* 9329 * Prepare controller and devices settings, according 9330 * to chip features, user set-up and driver set-up. 9331 */ 9332 (void) sym_prepare_setting(np, &nvram); 9333 9334 /* 9335 * Check the PCI clock frequency. 9336 * Must be performed after prepare_setting since it destroys 9337 * STEST1 that is used to probe for the clock doubler. 9338 */ 9339 i = sym_getpciclock(np); 9340 if (i > 37000) 9341 #ifdef FreeBSD_Bus_Io_Abstraction 9342 device_printf(dev, "PCI BUS clock seems too high: %u KHz.\n",i); 9343 #else 9344 printf("%s: PCI BUS clock seems too high: %u KHz.\n", 9345 sym_name(np), i); 9346 #endif 9347 9348 /* 9349 * Allocate the start queue. 9350 */ 9351 np->squeue = (u32 *) sym_calloc_dma(sizeof(u32)*(MAX_QUEUE*2),"SQUEUE"); 9352 if (!np->squeue) 9353 goto attach_failed; 9354 np->squeue_ba = vtobus(np->squeue); 9355 9356 /* 9357 * Allocate the done queue. 9358 */ 9359 np->dqueue = (u32 *) sym_calloc_dma(sizeof(u32)*(MAX_QUEUE*2),"DQUEUE"); 9360 if (!np->dqueue) 9361 goto attach_failed; 9362 np->dqueue_ba = vtobus(np->dqueue); 9363 9364 /* 9365 * Allocate the target bus address array. 9366 */ 9367 np->targtbl = (u32 *) sym_calloc_dma(256, "TARGTBL"); 9368 if (!np->targtbl) 9369 goto attach_failed; 9370 np->targtbl_ba = vtobus(np->targtbl); 9371 9372 /* 9373 * Allocate SCRIPTS areas. 9374 */ 9375 np->scripta0 = sym_calloc_dma(np->scripta_sz, "SCRIPTA0"); 9376 np->scriptb0 = sym_calloc_dma(np->scriptb_sz, "SCRIPTB0"); 9377 if (!np->scripta0 || !np->scriptb0) 9378 goto attach_failed; 9379 9380 /* 9381 * Allocate some CCB. We need at least ONE. 9382 */ 9383 if (!sym_alloc_ccb(np)) 9384 goto attach_failed; 9385 9386 /* 9387 * Calculate BUS addresses where we are going 9388 * to load the SCRIPTS. 9389 */ 9390 np->scripta_ba = vtobus(np->scripta0); 9391 np->scriptb_ba = vtobus(np->scriptb0); 9392 np->scriptb0_ba = np->scriptb_ba; 9393 9394 if (np->ram_ba) { 9395 np->scripta_ba = np->ram_ba; 9396 if (np->features & FE_RAM8K) { 9397 np->ram_ws = 8192; 9398 np->scriptb_ba = np->scripta_ba + 4096; 9399 #if BITS_PER_LONG > 32 9400 np->scr_ram_seg = cpu_to_scr(np->scripta_ba >> 32); 9401 #endif 9402 } 9403 else 9404 np->ram_ws = 4096; 9405 } 9406 9407 /* 9408 * Copy scripts to controller instance. 9409 */ 9410 bcopy(fw->a_base, np->scripta0, np->scripta_sz); 9411 bcopy(fw->b_base, np->scriptb0, np->scriptb_sz); 9412 9413 /* 9414 * Setup variable parts in scripts and compute 9415 * scripts bus addresses used from the C code. 9416 */ 9417 np->fw_setup(np, fw); 9418 9419 /* 9420 * Bind SCRIPTS with physical addresses usable by the 9421 * SCRIPTS processor (as seen from the BUS = BUS addresses). 9422 */ 9423 sym_fw_bind_script(np, (u32 *) np->scripta0, np->scripta_sz); 9424 sym_fw_bind_script(np, (u32 *) np->scriptb0, np->scriptb_sz); 9425 9426 #ifdef SYM_CONF_IARB_SUPPORT 9427 /* 9428 * If user wants IARB to be set when we win arbitration 9429 * and have other jobs, compute the max number of consecutive 9430 * settings of IARB hints before we leave devices a chance to 9431 * arbitrate for reselection. 9432 */ 9433 #ifdef SYM_SETUP_IARB_MAX 9434 np->iarb_max = SYM_SETUP_IARB_MAX; 9435 #else 9436 np->iarb_max = 4; 9437 #endif 9438 #endif 9439 9440 /* 9441 * Prepare the idle and invalid task actions. 9442 */ 9443 np->idletask.start = cpu_to_scr(SCRIPTA_BA (np, idle)); 9444 np->idletask.restart = cpu_to_scr(SCRIPTB_BA (np, bad_i_t_l)); 9445 np->idletask_ba = vtobus(&np->idletask); 9446 9447 np->notask.start = cpu_to_scr(SCRIPTA_BA (np, idle)); 9448 np->notask.restart = cpu_to_scr(SCRIPTB_BA (np, bad_i_t_l)); 9449 np->notask_ba = vtobus(&np->notask); 9450 9451 np->bad_itl.start = cpu_to_scr(SCRIPTA_BA (np, idle)); 9452 np->bad_itl.restart = cpu_to_scr(SCRIPTB_BA (np, bad_i_t_l)); 9453 np->bad_itl_ba = vtobus(&np->bad_itl); 9454 9455 np->bad_itlq.start = cpu_to_scr(SCRIPTA_BA (np, idle)); 9456 np->bad_itlq.restart = cpu_to_scr(SCRIPTB_BA (np,bad_i_t_l_q)); 9457 np->bad_itlq_ba = vtobus(&np->bad_itlq); 9458 9459 /* 9460 * Allocate and prepare the lun JUMP table that is used 9461 * for a target prior the probing of devices (bad lun table). 9462 * A private table will be allocated for the target on the 9463 * first INQUIRY response received. 9464 */ 9465 np->badluntbl = sym_calloc_dma(256, "BADLUNTBL"); 9466 if (!np->badluntbl) 9467 goto attach_failed; 9468 9469 np->badlun_sa = cpu_to_scr(SCRIPTB_BA (np, resel_bad_lun)); 9470 for (i = 0 ; i < 64 ; i++) /* 64 luns/target, no less */ 9471 np->badluntbl[i] = cpu_to_scr(vtobus(&np->badlun_sa)); 9472 9473 /* 9474 * Prepare the bus address array that contains the bus 9475 * address of each target control block. 9476 * For now, assume all logical units are wrong. :) 9477 */ 9478 for (i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) { 9479 np->targtbl[i] = cpu_to_scr(vtobus(&np->target[i])); 9480 np->target[i].head.luntbl_sa = 9481 cpu_to_scr(vtobus(np->badluntbl)); 9482 np->target[i].head.lun0_sa = 9483 cpu_to_scr(vtobus(&np->badlun_sa)); 9484 } 9485 9486 /* 9487 * Now check the cache handling of the pci chipset. 9488 */ 9489 if (sym_snooptest (np)) { 9490 #ifdef FreeBSD_Bus_Io_Abstraction 9491 device_printf(dev, "CACHE INCORRECTLY CONFIGURED.\n"); 9492 #else 9493 printf("%s: CACHE INCORRECTLY CONFIGURED.\n", sym_name(np)); 9494 #endif 9495 goto attach_failed; 9496 }; 9497 9498 /* 9499 * Now deal with CAM. 9500 * Hopefully, we will succeed with that one.:) 9501 */ 9502 if (!sym_cam_attach(np)) 9503 goto attach_failed; 9504 9505 /* 9506 * Sigh! we are done. 9507 */ 9508 return 0; 9509 9510 /* 9511 * We have failed. 9512 * We will try to free all the resources we have 9513 * allocated, but if we are a boot device, this 9514 * will not help that much.;) 9515 */ 9516 attach_failed: 9517 if (np) 9518 sym_pci_free(np); 9519 return ENXIO; 9520 } 9521 9522 /* 9523 * Free everything that have been allocated for this device. 9524 */ 9525 static void sym_pci_free(hcb_p np) 9526 { 9527 SYM_QUEHEAD *qp; 9528 ccb_p cp; 9529 tcb_p tp; 9530 lcb_p lp; 9531 int target, lun; 9532 int s; 9533 9534 /* 9535 * First free CAM resources. 9536 */ 9537 s = splcam(); 9538 sym_cam_free(np); 9539 splx(s); 9540 9541 /* 9542 * Now every should be quiet for us to 9543 * free other resources. 9544 */ 9545 #ifdef FreeBSD_Bus_Io_Abstraction 9546 if (np->ram_res) 9547 bus_release_resource(np->device, SYS_RES_MEMORY, 9548 np->ram_id, np->ram_res); 9549 if (np->mmio_res) 9550 bus_release_resource(np->device, SYS_RES_MEMORY, 9551 SYM_PCI_MMIO, np->mmio_res); 9552 if (np->io_res) 9553 bus_release_resource(np->device, SYS_RES_IOPORT, 9554 SYM_PCI_IO, np->io_res); 9555 if (np->irq_res) 9556 bus_release_resource(np->device, SYS_RES_IRQ, 9557 0, np->irq_res); 9558 #else 9559 /* 9560 * YEAH!!! 9561 * It seems there is no means to free MMIO resources. 9562 */ 9563 #endif 9564 9565 if (np->scriptb0) 9566 sym_mfree_dma(np->scriptb0, np->scriptb_sz, "SCRIPTB0"); 9567 if (np->scripta0) 9568 sym_mfree_dma(np->scripta0, np->scripta_sz, "SCRIPTA0"); 9569 if (np->squeue) 9570 sym_mfree_dma(np->squeue, sizeof(u32)*(MAX_QUEUE*2), "SQUEUE"); 9571 if (np->dqueue) 9572 sym_mfree_dma(np->dqueue, sizeof(u32)*(MAX_QUEUE*2), "DQUEUE"); 9573 9574 while ((qp = sym_remque_head(&np->free_ccbq)) != 0) { 9575 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 9576 #ifdef FreeBSD_Bus_Dma_Abstraction 9577 bus_dmamap_destroy(np->data_dmat, cp->dmamap); 9578 #endif 9579 sym_mfree_dma(cp->sns_bbuf, SYM_SNS_BBUF_LEN, "SNS_BBUF"); 9580 sym_mfree_dma(cp, sizeof(*cp), "CCB"); 9581 } 9582 9583 if (np->badluntbl) 9584 sym_mfree_dma(np->badluntbl, 256,"BADLUNTBL"); 9585 9586 for (target = 0; target < SYM_CONF_MAX_TARGET ; target++) { 9587 tp = &np->target[target]; 9588 for (lun = 0 ; lun < SYM_CONF_MAX_LUN ; lun++) { 9589 lp = sym_lp(np, tp, lun); 9590 if (!lp) 9591 continue; 9592 if (lp->itlq_tbl) 9593 sym_mfree_dma(lp->itlq_tbl, SYM_CONF_MAX_TASK*4, 9594 "ITLQ_TBL"); 9595 if (lp->cb_tags) 9596 sym_mfree(lp->cb_tags, SYM_CONF_MAX_TASK, 9597 "CB_TAGS"); 9598 sym_mfree_dma(lp, sizeof(*lp), "LCB"); 9599 } 9600 #if SYM_CONF_MAX_LUN > 1 9601 if (tp->lunmp) 9602 sym_mfree(tp->lunmp, SYM_CONF_MAX_LUN*sizeof(lcb_p), 9603 "LUNMP"); 9604 #endif 9605 } 9606 if (np->targtbl) 9607 sym_mfree_dma(np->targtbl, 256, "TARGTBL"); 9608 #ifdef FreeBSD_Bus_Dma_Abstraction 9609 if (np->data_dmat) 9610 bus_dma_tag_destroy(np->data_dmat); 9611 #endif 9612 sym_mfree_dma(np, sizeof(*np), "HCB"); 9613 } 9614 9615 /* 9616 * Allocate CAM resources and register a bus to CAM. 9617 */ 9618 static int sym_cam_attach(hcb_p np) 9619 { 9620 struct cam_devq *devq = 0; 9621 struct cam_sim *sim = 0; 9622 struct cam_path *path = 0; 9623 struct ccb_setasync csa; 9624 int err, s; 9625 9626 s = splcam(); 9627 9628 /* 9629 * Establish our interrupt handler. 9630 */ 9631 #ifdef FreeBSD_Bus_Io_Abstraction 9632 err = bus_setup_intr(np->device, np->irq_res, 9633 INTR_TYPE_CAM | INTR_ENTROPY, sym_intr, np, 9634 &np->intr); 9635 if (err) { 9636 device_printf(np->device, "bus_setup_intr() failed: %d\n", 9637 err); 9638 goto fail; 9639 } 9640 #else 9641 err = 0; 9642 if (!pci_map_int (np->pci_tag, sym_intr, np, &cam_imask)) { 9643 printf("%s: failed to map interrupt\n", sym_name(np)); 9644 goto fail; 9645 } 9646 #endif 9647 9648 /* 9649 * Create the device queue for our sym SIM. 9650 */ 9651 devq = cam_simq_alloc(SYM_CONF_MAX_START); 9652 if (!devq) 9653 goto fail; 9654 9655 /* 9656 * Construct our SIM entry. 9657 */ 9658 sim = cam_sim_alloc(sym_action, sym_poll, "sym", np, np->unit, 9659 1, SYM_SETUP_MAX_TAG, devq); 9660 if (!sim) 9661 goto fail; 9662 devq = 0; 9663 9664 if (xpt_bus_register(sim, 0) != CAM_SUCCESS) 9665 goto fail; 9666 np->sim = sim; 9667 sim = 0; 9668 9669 if (xpt_create_path(&path, 0, 9670 cam_sim_path(np->sim), CAM_TARGET_WILDCARD, 9671 CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 9672 goto fail; 9673 } 9674 np->path = path; 9675 9676 /* 9677 * Hmmm... This should be useful, but I donnot want to 9678 * know about. 9679 */ 9680 #if __FreeBSD_version < 400000 9681 #ifdef __alpha__ 9682 #ifdef FreeBSD_Bus_Io_Abstraction 9683 alpha_register_pci_scsi(pci_get_bus(np->device), 9684 pci_get_slot(np->device), np->sim); 9685 #else 9686 alpha_register_pci_scsi(pci_tag->bus, pci_tag->slot, np->sim); 9687 #endif 9688 #endif 9689 #endif 9690 9691 /* 9692 * Establish our async notification handler. 9693 */ 9694 xpt_setup_ccb(&csa.ccb_h, np->path, 5); 9695 csa.ccb_h.func_code = XPT_SASYNC_CB; 9696 csa.event_enable = AC_LOST_DEVICE; 9697 csa.callback = sym_async; 9698 csa.callback_arg = np->sim; 9699 xpt_action((union ccb *)&csa); 9700 9701 /* 9702 * Start the chip now, without resetting the BUS, since 9703 * it seems that this must stay under control of CAM. 9704 * With LVD/SE capable chips and BUS in SE mode, we may 9705 * get a spurious SMBC interrupt. 9706 */ 9707 sym_init (np, 0); 9708 9709 splx(s); 9710 return 1; 9711 fail: 9712 if (sim) 9713 cam_sim_free(sim, FALSE); 9714 if (devq) 9715 cam_simq_free(devq); 9716 9717 sym_cam_free(np); 9718 9719 splx(s); 9720 return 0; 9721 } 9722 9723 /* 9724 * Free everything that deals with CAM. 9725 */ 9726 static void sym_cam_free(hcb_p np) 9727 { 9728 #ifdef FreeBSD_Bus_Io_Abstraction 9729 if (np->intr) 9730 bus_teardown_intr(np->device, np->irq_res, np->intr); 9731 #else 9732 /* pci_unmap_int(np->pci_tag); */ /* Does nothing */ 9733 #endif 9734 9735 if (np->sim) { 9736 xpt_bus_deregister(cam_sim_path(np->sim)); 9737 cam_sim_free(np->sim, /*free_devq*/ TRUE); 9738 } 9739 if (np->path) 9740 xpt_free_path(np->path); 9741 } 9742 9743 /*============ OPTIONNAL NVRAM SUPPORT =================*/ 9744 9745 /* 9746 * Get host setup from NVRAM. 9747 */ 9748 static void sym_nvram_setup_host (hcb_p np, struct sym_nvram *nvram) 9749 { 9750 #ifdef SYM_CONF_NVRAM_SUPPORT 9751 /* 9752 * Get parity checking, host ID, verbose mode 9753 * and miscellaneous host flags from NVRAM. 9754 */ 9755 switch(nvram->type) { 9756 case SYM_SYMBIOS_NVRAM: 9757 if (!(nvram->data.Symbios.flags & SYMBIOS_PARITY_ENABLE)) 9758 np->rv_scntl0 &= ~0x0a; 9759 np->myaddr = nvram->data.Symbios.host_id & 0x0f; 9760 if (nvram->data.Symbios.flags & SYMBIOS_VERBOSE_MSGS) 9761 np->verbose += 1; 9762 if (nvram->data.Symbios.flags1 & SYMBIOS_SCAN_HI_LO) 9763 np->usrflags |= SYM_SCAN_TARGETS_HILO; 9764 if (nvram->data.Symbios.flags2 & SYMBIOS_AVOID_BUS_RESET) 9765 np->usrflags |= SYM_AVOID_BUS_RESET; 9766 break; 9767 case SYM_TEKRAM_NVRAM: 9768 np->myaddr = nvram->data.Tekram.host_id & 0x0f; 9769 break; 9770 default: 9771 break; 9772 } 9773 #endif 9774 } 9775 9776 /* 9777 * Get target setup from NVRAM. 9778 */ 9779 #ifdef SYM_CONF_NVRAM_SUPPORT 9780 static void sym_Symbios_setup_target(hcb_p np,int target, Symbios_nvram *nvram); 9781 static void sym_Tekram_setup_target(hcb_p np,int target, Tekram_nvram *nvram); 9782 #endif 9783 9784 static void 9785 sym_nvram_setup_target (hcb_p np, int target, struct sym_nvram *nvp) 9786 { 9787 #ifdef SYM_CONF_NVRAM_SUPPORT 9788 switch(nvp->type) { 9789 case SYM_SYMBIOS_NVRAM: 9790 sym_Symbios_setup_target (np, target, &nvp->data.Symbios); 9791 break; 9792 case SYM_TEKRAM_NVRAM: 9793 sym_Tekram_setup_target (np, target, &nvp->data.Tekram); 9794 break; 9795 default: 9796 break; 9797 } 9798 #endif 9799 } 9800 9801 #ifdef SYM_CONF_NVRAM_SUPPORT 9802 /* 9803 * Get target set-up from Symbios format NVRAM. 9804 */ 9805 static void 9806 sym_Symbios_setup_target(hcb_p np, int target, Symbios_nvram *nvram) 9807 { 9808 tcb_p tp = &np->target[target]; 9809 Symbios_target *tn = &nvram->target[target]; 9810 9811 tp->tinfo.user.period = tn->sync_period ? (tn->sync_period + 3) / 4 : 0; 9812 tp->tinfo.user.width = tn->bus_width == 0x10 ? BUS_16_BIT : BUS_8_BIT; 9813 tp->usrtags = 9814 (tn->flags & SYMBIOS_QUEUE_TAGS_ENABLED)? SYM_SETUP_MAX_TAG : 0; 9815 9816 if (!(tn->flags & SYMBIOS_DISCONNECT_ENABLE)) 9817 tp->usrflags &= ~SYM_DISC_ENABLED; 9818 if (!(tn->flags & SYMBIOS_SCAN_AT_BOOT_TIME)) 9819 tp->usrflags |= SYM_SCAN_BOOT_DISABLED; 9820 if (!(tn->flags & SYMBIOS_SCAN_LUNS)) 9821 tp->usrflags |= SYM_SCAN_LUNS_DISABLED; 9822 } 9823 9824 /* 9825 * Get target set-up from Tekram format NVRAM. 9826 */ 9827 static void 9828 sym_Tekram_setup_target(hcb_p np, int target, Tekram_nvram *nvram) 9829 { 9830 tcb_p tp = &np->target[target]; 9831 struct Tekram_target *tn = &nvram->target[target]; 9832 int i; 9833 9834 if (tn->flags & TEKRAM_SYNC_NEGO) { 9835 i = tn->sync_index & 0xf; 9836 tp->tinfo.user.period = Tekram_sync[i]; 9837 } 9838 9839 tp->tinfo.user.width = 9840 (tn->flags & TEKRAM_WIDE_NEGO) ? BUS_16_BIT : BUS_8_BIT; 9841 9842 if (tn->flags & TEKRAM_TAGGED_COMMANDS) { 9843 tp->usrtags = 2 << nvram->max_tags_index; 9844 } 9845 9846 if (tn->flags & TEKRAM_DISCONNECT_ENABLE) 9847 tp->usrflags |= SYM_DISC_ENABLED; 9848 9849 /* If any device does not support parity, we will not use this option */ 9850 if (!(tn->flags & TEKRAM_PARITY_CHECK)) 9851 np->rv_scntl0 &= ~0x0a; /* SCSI parity checking disabled */ 9852 } 9853 9854 #ifdef SYM_CONF_DEBUG_NVRAM 9855 /* 9856 * Dump Symbios format NVRAM for debugging purpose. 9857 */ 9858 static void sym_display_Symbios_nvram(hcb_p np, Symbios_nvram *nvram) 9859 { 9860 int i; 9861 9862 /* display Symbios nvram host data */ 9863 printf("%s: HOST ID=%d%s%s%s%s%s%s\n", 9864 sym_name(np), nvram->host_id & 0x0f, 9865 (nvram->flags & SYMBIOS_SCAM_ENABLE) ? " SCAM" :"", 9866 (nvram->flags & SYMBIOS_PARITY_ENABLE) ? " PARITY" :"", 9867 (nvram->flags & SYMBIOS_VERBOSE_MSGS) ? " VERBOSE" :"", 9868 (nvram->flags & SYMBIOS_CHS_MAPPING) ? " CHS_ALT" :"", 9869 (nvram->flags2 & SYMBIOS_AVOID_BUS_RESET)?" NO_RESET" :"", 9870 (nvram->flags1 & SYMBIOS_SCAN_HI_LO) ? " HI_LO" :""); 9871 9872 /* display Symbios nvram drive data */ 9873 for (i = 0 ; i < 15 ; i++) { 9874 struct Symbios_target *tn = &nvram->target[i]; 9875 printf("%s-%d:%s%s%s%s WIDTH=%d SYNC=%d TMO=%d\n", 9876 sym_name(np), i, 9877 (tn->flags & SYMBIOS_DISCONNECT_ENABLE) ? " DISC" : "", 9878 (tn->flags & SYMBIOS_SCAN_AT_BOOT_TIME) ? " SCAN_BOOT" : "", 9879 (tn->flags & SYMBIOS_SCAN_LUNS) ? " SCAN_LUNS" : "", 9880 (tn->flags & SYMBIOS_QUEUE_TAGS_ENABLED)? " TCQ" : "", 9881 tn->bus_width, 9882 tn->sync_period / 4, 9883 tn->timeout); 9884 } 9885 } 9886 9887 /* 9888 * Dump TEKRAM format NVRAM for debugging purpose. 9889 */ 9890 static u_char Tekram_boot_delay[7] = {3, 5, 10, 20, 30, 60, 120}; 9891 static void sym_display_Tekram_nvram(hcb_p np, Tekram_nvram *nvram) 9892 { 9893 int i, tags, boot_delay; 9894 char *rem; 9895 9896 /* display Tekram nvram host data */ 9897 tags = 2 << nvram->max_tags_index; 9898 boot_delay = 0; 9899 if (nvram->boot_delay_index < 6) 9900 boot_delay = Tekram_boot_delay[nvram->boot_delay_index]; 9901 switch((nvram->flags & TEKRAM_REMOVABLE_FLAGS) >> 6) { 9902 default: 9903 case 0: rem = ""; break; 9904 case 1: rem = " REMOVABLE=boot device"; break; 9905 case 2: rem = " REMOVABLE=all"; break; 9906 } 9907 9908 printf("%s: HOST ID=%d%s%s%s%s%s%s%s%s%s BOOT DELAY=%d tags=%d\n", 9909 sym_name(np), nvram->host_id & 0x0f, 9910 (nvram->flags1 & SYMBIOS_SCAM_ENABLE) ? " SCAM" :"", 9911 (nvram->flags & TEKRAM_MORE_THAN_2_DRIVES) ? " >2DRIVES" :"", 9912 (nvram->flags & TEKRAM_DRIVES_SUP_1GB) ? " >1GB" :"", 9913 (nvram->flags & TEKRAM_RESET_ON_POWER_ON) ? " RESET" :"", 9914 (nvram->flags & TEKRAM_ACTIVE_NEGATION) ? " ACT_NEG" :"", 9915 (nvram->flags & TEKRAM_IMMEDIATE_SEEK) ? " IMM_SEEK" :"", 9916 (nvram->flags & TEKRAM_SCAN_LUNS) ? " SCAN_LUNS" :"", 9917 (nvram->flags1 & TEKRAM_F2_F6_ENABLED) ? " F2_F6" :"", 9918 rem, boot_delay, tags); 9919 9920 /* display Tekram nvram drive data */ 9921 for (i = 0; i <= 15; i++) { 9922 int sync, j; 9923 struct Tekram_target *tn = &nvram->target[i]; 9924 j = tn->sync_index & 0xf; 9925 sync = Tekram_sync[j]; 9926 printf("%s-%d:%s%s%s%s%s%s PERIOD=%d\n", 9927 sym_name(np), i, 9928 (tn->flags & TEKRAM_PARITY_CHECK) ? " PARITY" : "", 9929 (tn->flags & TEKRAM_SYNC_NEGO) ? " SYNC" : "", 9930 (tn->flags & TEKRAM_DISCONNECT_ENABLE) ? " DISC" : "", 9931 (tn->flags & TEKRAM_START_CMD) ? " START" : "", 9932 (tn->flags & TEKRAM_TAGGED_COMMANDS) ? " TCQ" : "", 9933 (tn->flags & TEKRAM_WIDE_NEGO) ? " WIDE" : "", 9934 sync); 9935 } 9936 } 9937 #endif /* SYM_CONF_DEBUG_NVRAM */ 9938 #endif /* SYM_CONF_NVRAM_SUPPORT */ 9939 9940 9941 /* 9942 * Try reading Symbios or Tekram NVRAM 9943 */ 9944 #ifdef SYM_CONF_NVRAM_SUPPORT 9945 static int sym_read_Symbios_nvram (hcb_p np, Symbios_nvram *nvram); 9946 static int sym_read_Tekram_nvram (hcb_p np, Tekram_nvram *nvram); 9947 #endif 9948 9949 static int sym_read_nvram(hcb_p np, struct sym_nvram *nvp) 9950 { 9951 #ifdef SYM_CONF_NVRAM_SUPPORT 9952 /* 9953 * Try to read SYMBIOS nvram. 9954 * Try to read TEKRAM nvram if Symbios nvram not found. 9955 */ 9956 if (SYM_SETUP_SYMBIOS_NVRAM && 9957 !sym_read_Symbios_nvram (np, &nvp->data.Symbios)) { 9958 nvp->type = SYM_SYMBIOS_NVRAM; 9959 #ifdef SYM_CONF_DEBUG_NVRAM 9960 sym_display_Symbios_nvram(np, &nvp->data.Symbios); 9961 #endif 9962 } 9963 else if (SYM_SETUP_TEKRAM_NVRAM && 9964 !sym_read_Tekram_nvram (np, &nvp->data.Tekram)) { 9965 nvp->type = SYM_TEKRAM_NVRAM; 9966 #ifdef SYM_CONF_DEBUG_NVRAM 9967 sym_display_Tekram_nvram(np, &nvp->data.Tekram); 9968 #endif 9969 } 9970 else 9971 nvp->type = 0; 9972 #else 9973 nvp->type = 0; 9974 #endif 9975 return nvp->type; 9976 } 9977 9978 9979 #ifdef SYM_CONF_NVRAM_SUPPORT 9980 /* 9981 * 24C16 EEPROM reading. 9982 * 9983 * GPOI0 - data in/data out 9984 * GPIO1 - clock 9985 * Symbios NVRAM wiring now also used by Tekram. 9986 */ 9987 9988 #define SET_BIT 0 9989 #define CLR_BIT 1 9990 #define SET_CLK 2 9991 #define CLR_CLK 3 9992 9993 /* 9994 * Set/clear data/clock bit in GPIO0 9995 */ 9996 static void S24C16_set_bit(hcb_p np, u_char write_bit, u_char *gpreg, 9997 int bit_mode) 9998 { 9999 UDELAY (5); 10000 switch (bit_mode){ 10001 case SET_BIT: 10002 *gpreg |= write_bit; 10003 break; 10004 case CLR_BIT: 10005 *gpreg &= 0xfe; 10006 break; 10007 case SET_CLK: 10008 *gpreg |= 0x02; 10009 break; 10010 case CLR_CLK: 10011 *gpreg &= 0xfd; 10012 break; 10013 10014 } 10015 OUTB (nc_gpreg, *gpreg); 10016 UDELAY (5); 10017 } 10018 10019 /* 10020 * Send START condition to NVRAM to wake it up. 10021 */ 10022 static void S24C16_start(hcb_p np, u_char *gpreg) 10023 { 10024 S24C16_set_bit(np, 1, gpreg, SET_BIT); 10025 S24C16_set_bit(np, 0, gpreg, SET_CLK); 10026 S24C16_set_bit(np, 0, gpreg, CLR_BIT); 10027 S24C16_set_bit(np, 0, gpreg, CLR_CLK); 10028 } 10029 10030 /* 10031 * Send STOP condition to NVRAM - puts NVRAM to sleep... ZZzzzz!! 10032 */ 10033 static void S24C16_stop(hcb_p np, u_char *gpreg) 10034 { 10035 S24C16_set_bit(np, 0, gpreg, SET_CLK); 10036 S24C16_set_bit(np, 1, gpreg, SET_BIT); 10037 } 10038 10039 /* 10040 * Read or write a bit to the NVRAM, 10041 * read if GPIO0 input else write if GPIO0 output 10042 */ 10043 static void S24C16_do_bit(hcb_p np, u_char *read_bit, u_char write_bit, 10044 u_char *gpreg) 10045 { 10046 S24C16_set_bit(np, write_bit, gpreg, SET_BIT); 10047 S24C16_set_bit(np, 0, gpreg, SET_CLK); 10048 if (read_bit) 10049 *read_bit = INB (nc_gpreg); 10050 S24C16_set_bit(np, 0, gpreg, CLR_CLK); 10051 S24C16_set_bit(np, 0, gpreg, CLR_BIT); 10052 } 10053 10054 /* 10055 * Output an ACK to the NVRAM after reading, 10056 * change GPIO0 to output and when done back to an input 10057 */ 10058 static void S24C16_write_ack(hcb_p np, u_char write_bit, u_char *gpreg, 10059 u_char *gpcntl) 10060 { 10061 OUTB (nc_gpcntl, *gpcntl & 0xfe); 10062 S24C16_do_bit(np, 0, write_bit, gpreg); 10063 OUTB (nc_gpcntl, *gpcntl); 10064 } 10065 10066 /* 10067 * Input an ACK from NVRAM after writing, 10068 * change GPIO0 to input and when done back to an output 10069 */ 10070 static void S24C16_read_ack(hcb_p np, u_char *read_bit, u_char *gpreg, 10071 u_char *gpcntl) 10072 { 10073 OUTB (nc_gpcntl, *gpcntl | 0x01); 10074 S24C16_do_bit(np, read_bit, 1, gpreg); 10075 OUTB (nc_gpcntl, *gpcntl); 10076 } 10077 10078 /* 10079 * WRITE a byte to the NVRAM and then get an ACK to see it was accepted OK, 10080 * GPIO0 must already be set as an output 10081 */ 10082 static void S24C16_write_byte(hcb_p np, u_char *ack_data, u_char write_data, 10083 u_char *gpreg, u_char *gpcntl) 10084 { 10085 int x; 10086 10087 for (x = 0; x < 8; x++) 10088 S24C16_do_bit(np, 0, (write_data >> (7 - x)) & 0x01, gpreg); 10089 10090 S24C16_read_ack(np, ack_data, gpreg, gpcntl); 10091 } 10092 10093 /* 10094 * READ a byte from the NVRAM and then send an ACK to say we have got it, 10095 * GPIO0 must already be set as an input 10096 */ 10097 static void S24C16_read_byte(hcb_p np, u_char *read_data, u_char ack_data, 10098 u_char *gpreg, u_char *gpcntl) 10099 { 10100 int x; 10101 u_char read_bit; 10102 10103 *read_data = 0; 10104 for (x = 0; x < 8; x++) { 10105 S24C16_do_bit(np, &read_bit, 1, gpreg); 10106 *read_data |= ((read_bit & 0x01) << (7 - x)); 10107 } 10108 10109 S24C16_write_ack(np, ack_data, gpreg, gpcntl); 10110 } 10111 10112 /* 10113 * Read 'len' bytes starting at 'offset'. 10114 */ 10115 static int sym_read_S24C16_nvram (hcb_p np, int offset, u_char *data, int len) 10116 { 10117 u_char gpcntl, gpreg; 10118 u_char old_gpcntl, old_gpreg; 10119 u_char ack_data; 10120 int retv = 1; 10121 int x; 10122 10123 /* save current state of GPCNTL and GPREG */ 10124 old_gpreg = INB (nc_gpreg); 10125 old_gpcntl = INB (nc_gpcntl); 10126 gpcntl = old_gpcntl & 0x1c; 10127 10128 /* set up GPREG & GPCNTL to set GPIO0 and GPIO1 in to known state */ 10129 OUTB (nc_gpreg, old_gpreg); 10130 OUTB (nc_gpcntl, gpcntl); 10131 10132 /* this is to set NVRAM into a known state with GPIO0/1 both low */ 10133 gpreg = old_gpreg; 10134 S24C16_set_bit(np, 0, &gpreg, CLR_CLK); 10135 S24C16_set_bit(np, 0, &gpreg, CLR_BIT); 10136 10137 /* now set NVRAM inactive with GPIO0/1 both high */ 10138 S24C16_stop(np, &gpreg); 10139 10140 /* activate NVRAM */ 10141 S24C16_start(np, &gpreg); 10142 10143 /* write device code and random address MSB */ 10144 S24C16_write_byte(np, &ack_data, 10145 0xa0 | ((offset >> 7) & 0x0e), &gpreg, &gpcntl); 10146 if (ack_data & 0x01) 10147 goto out; 10148 10149 /* write random address LSB */ 10150 S24C16_write_byte(np, &ack_data, 10151 offset & 0xff, &gpreg, &gpcntl); 10152 if (ack_data & 0x01) 10153 goto out; 10154 10155 /* regenerate START state to set up for reading */ 10156 S24C16_start(np, &gpreg); 10157 10158 /* rewrite device code and address MSB with read bit set (lsb = 0x01) */ 10159 S24C16_write_byte(np, &ack_data, 10160 0xa1 | ((offset >> 7) & 0x0e), &gpreg, &gpcntl); 10161 if (ack_data & 0x01) 10162 goto out; 10163 10164 /* now set up GPIO0 for inputting data */ 10165 gpcntl |= 0x01; 10166 OUTB (nc_gpcntl, gpcntl); 10167 10168 /* input all requested data - only part of total NVRAM */ 10169 for (x = 0; x < len; x++) 10170 S24C16_read_byte(np, &data[x], (x == (len-1)), &gpreg, &gpcntl); 10171 10172 /* finally put NVRAM back in inactive mode */ 10173 gpcntl &= 0xfe; 10174 OUTB (nc_gpcntl, gpcntl); 10175 S24C16_stop(np, &gpreg); 10176 retv = 0; 10177 out: 10178 /* return GPIO0/1 to original states after having accessed NVRAM */ 10179 OUTB (nc_gpcntl, old_gpcntl); 10180 OUTB (nc_gpreg, old_gpreg); 10181 10182 return retv; 10183 } 10184 10185 #undef SET_BIT /* 0 */ 10186 #undef CLR_BIT /* 1 */ 10187 #undef SET_CLK /* 2 */ 10188 #undef CLR_CLK /* 3 */ 10189 10190 /* 10191 * Try reading Symbios NVRAM. 10192 * Return 0 if OK. 10193 */ 10194 static int sym_read_Symbios_nvram (hcb_p np, Symbios_nvram *nvram) 10195 { 10196 static u_char Symbios_trailer[6] = {0xfe, 0xfe, 0, 0, 0, 0}; 10197 u_char *data = (u_char *) nvram; 10198 int len = sizeof(*nvram); 10199 u_short csum; 10200 int x; 10201 10202 /* probe the 24c16 and read the SYMBIOS 24c16 area */ 10203 if (sym_read_S24C16_nvram (np, SYMBIOS_NVRAM_ADDRESS, data, len)) 10204 return 1; 10205 10206 /* check valid NVRAM signature, verify byte count and checksum */ 10207 if (nvram->type != 0 || 10208 bcmp(nvram->trailer, Symbios_trailer, 6) || 10209 nvram->byte_count != len - 12) 10210 return 1; 10211 10212 /* verify checksum */ 10213 for (x = 6, csum = 0; x < len - 6; x++) 10214 csum += data[x]; 10215 if (csum != nvram->checksum) 10216 return 1; 10217 10218 return 0; 10219 } 10220 10221 /* 10222 * 93C46 EEPROM reading. 10223 * 10224 * GPOI0 - data in 10225 * GPIO1 - data out 10226 * GPIO2 - clock 10227 * GPIO4 - chip select 10228 * 10229 * Used by Tekram. 10230 */ 10231 10232 /* 10233 * Pulse clock bit in GPIO0 10234 */ 10235 static void T93C46_Clk(hcb_p np, u_char *gpreg) 10236 { 10237 OUTB (nc_gpreg, *gpreg | 0x04); 10238 UDELAY (2); 10239 OUTB (nc_gpreg, *gpreg); 10240 } 10241 10242 /* 10243 * Read bit from NVRAM 10244 */ 10245 static void T93C46_Read_Bit(hcb_p np, u_char *read_bit, u_char *gpreg) 10246 { 10247 UDELAY (2); 10248 T93C46_Clk(np, gpreg); 10249 *read_bit = INB (nc_gpreg); 10250 } 10251 10252 /* 10253 * Write bit to GPIO0 10254 */ 10255 static void T93C46_Write_Bit(hcb_p np, u_char write_bit, u_char *gpreg) 10256 { 10257 if (write_bit & 0x01) 10258 *gpreg |= 0x02; 10259 else 10260 *gpreg &= 0xfd; 10261 10262 *gpreg |= 0x10; 10263 10264 OUTB (nc_gpreg, *gpreg); 10265 UDELAY (2); 10266 10267 T93C46_Clk(np, gpreg); 10268 } 10269 10270 /* 10271 * Send STOP condition to NVRAM - puts NVRAM to sleep... ZZZzzz!! 10272 */ 10273 static void T93C46_Stop(hcb_p np, u_char *gpreg) 10274 { 10275 *gpreg &= 0xef; 10276 OUTB (nc_gpreg, *gpreg); 10277 UDELAY (2); 10278 10279 T93C46_Clk(np, gpreg); 10280 } 10281 10282 /* 10283 * Send read command and address to NVRAM 10284 */ 10285 static void T93C46_Send_Command(hcb_p np, u_short write_data, 10286 u_char *read_bit, u_char *gpreg) 10287 { 10288 int x; 10289 10290 /* send 9 bits, start bit (1), command (2), address (6) */ 10291 for (x = 0; x < 9; x++) 10292 T93C46_Write_Bit(np, (u_char) (write_data >> (8 - x)), gpreg); 10293 10294 *read_bit = INB (nc_gpreg); 10295 } 10296 10297 /* 10298 * READ 2 bytes from the NVRAM 10299 */ 10300 static void T93C46_Read_Word(hcb_p np, u_short *nvram_data, u_char *gpreg) 10301 { 10302 int x; 10303 u_char read_bit; 10304 10305 *nvram_data = 0; 10306 for (x = 0; x < 16; x++) { 10307 T93C46_Read_Bit(np, &read_bit, gpreg); 10308 10309 if (read_bit & 0x01) 10310 *nvram_data |= (0x01 << (15 - x)); 10311 else 10312 *nvram_data &= ~(0x01 << (15 - x)); 10313 } 10314 } 10315 10316 /* 10317 * Read Tekram NvRAM data. 10318 */ 10319 static int T93C46_Read_Data(hcb_p np, u_short *data,int len,u_char *gpreg) 10320 { 10321 u_char read_bit; 10322 int x; 10323 10324 for (x = 0; x < len; x++) { 10325 10326 /* output read command and address */ 10327 T93C46_Send_Command(np, 0x180 | x, &read_bit, gpreg); 10328 if (read_bit & 0x01) 10329 return 1; /* Bad */ 10330 T93C46_Read_Word(np, &data[x], gpreg); 10331 T93C46_Stop(np, gpreg); 10332 } 10333 10334 return 0; 10335 } 10336 10337 /* 10338 * Try reading 93C46 Tekram NVRAM. 10339 */ 10340 static int sym_read_T93C46_nvram (hcb_p np, Tekram_nvram *nvram) 10341 { 10342 u_char gpcntl, gpreg; 10343 u_char old_gpcntl, old_gpreg; 10344 int retv = 1; 10345 10346 /* save current state of GPCNTL and GPREG */ 10347 old_gpreg = INB (nc_gpreg); 10348 old_gpcntl = INB (nc_gpcntl); 10349 10350 /* set up GPREG & GPCNTL to set GPIO0/1/2/4 in to known state, 0 in, 10351 1/2/4 out */ 10352 gpreg = old_gpreg & 0xe9; 10353 OUTB (nc_gpreg, gpreg); 10354 gpcntl = (old_gpcntl & 0xe9) | 0x09; 10355 OUTB (nc_gpcntl, gpcntl); 10356 10357 /* input all of NVRAM, 64 words */ 10358 retv = T93C46_Read_Data(np, (u_short *) nvram, 10359 sizeof(*nvram) / sizeof(short), &gpreg); 10360 10361 /* return GPIO0/1/2/4 to original states after having accessed NVRAM */ 10362 OUTB (nc_gpcntl, old_gpcntl); 10363 OUTB (nc_gpreg, old_gpreg); 10364 10365 return retv; 10366 } 10367 10368 /* 10369 * Try reading Tekram NVRAM. 10370 * Return 0 if OK. 10371 */ 10372 static int sym_read_Tekram_nvram (hcb_p np, Tekram_nvram *nvram) 10373 { 10374 u_char *data = (u_char *) nvram; 10375 int len = sizeof(*nvram); 10376 u_short csum; 10377 int x; 10378 10379 switch (np->device_id) { 10380 case PCI_ID_SYM53C885: 10381 case PCI_ID_SYM53C895: 10382 case PCI_ID_SYM53C896: 10383 x = sym_read_S24C16_nvram(np, TEKRAM_24C16_NVRAM_ADDRESS, 10384 data, len); 10385 break; 10386 case PCI_ID_SYM53C875: 10387 x = sym_read_S24C16_nvram(np, TEKRAM_24C16_NVRAM_ADDRESS, 10388 data, len); 10389 if (!x) 10390 break; 10391 default: 10392 x = sym_read_T93C46_nvram(np, nvram); 10393 break; 10394 } 10395 if (x) 10396 return 1; 10397 10398 /* verify checksum */ 10399 for (x = 0, csum = 0; x < len - 1; x += 2) 10400 csum += data[x] + (data[x+1] << 8); 10401 if (csum != 0x1234) 10402 return 1; 10403 10404 return 0; 10405 } 10406 10407 #endif /* SYM_CONF_NVRAM_SUPPORT */ 10408