1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Device driver optimized for the Symbios/LSI 53C896/53C895A/53C1010 5 * PCI-SCSI controllers. 6 * 7 * Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr> 8 * 9 * This driver also supports the following Symbios/LSI PCI-SCSI chips: 10 * 53C810A, 53C825A, 53C860, 53C875, 53C876, 53C885, 53C895, 11 * 53C810, 53C815, 53C825 and the 53C1510D is 53C8XX mode. 12 * 13 * 14 * This driver for FreeBSD-CAM is derived from the Linux sym53c8xx driver. 15 * Copyright (C) 1998-1999 Gerard Roudier 16 * 17 * The sym53c8xx driver is derived from the ncr53c8xx driver that had been 18 * a port of the FreeBSD ncr driver to Linux-1.2.13. 19 * 20 * The original ncr driver has been written for 386bsd and FreeBSD by 21 * Wolfgang Stanglmeier <wolf@cologne.de> 22 * Stefan Esser <se@mi.Uni-Koeln.de> 23 * Copyright (C) 1994 Wolfgang Stanglmeier 24 * 25 * The initialisation code, and part of the code that addresses 26 * FreeBSD-CAM services is based on the aic7xxx driver for FreeBSD-CAM 27 * written by Justin T. Gibbs. 28 * 29 * Other major contributions: 30 * 31 * NVRAM detection and reading. 32 * Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk> 33 * 34 *----------------------------------------------------------------------------- 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. The name of the author may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND 48 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 49 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 50 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 51 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 52 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 53 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 54 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 55 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 56 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 57 * SUCH DAMAGE. 58 */ 59 60 #include <sys/cdefs.h> 61 __FBSDID("$FreeBSD$"); 62 63 #define SYM_DRIVER_NAME "sym-1.6.5-20000902" 64 65 /* #define SYM_DEBUG_GENERIC_SUPPORT */ 66 67 #include <sys/param.h> 68 69 /* 70 * Driver configuration options. 71 */ 72 #include "opt_sym.h" 73 #include <dev/sym/sym_conf.h> 74 75 #include <sys/systm.h> 76 #include <sys/malloc.h> 77 #include <sys/endian.h> 78 #include <sys/kernel.h> 79 #include <sys/lock.h> 80 #include <sys/mutex.h> 81 #include <sys/module.h> 82 #include <sys/bus.h> 83 84 #include <sys/proc.h> 85 86 #include <dev/pci/pcireg.h> 87 #include <dev/pci/pcivar.h> 88 89 #include <machine/bus.h> 90 #include <machine/resource.h> 91 #include <machine/atomic.h> 92 93 #include <sys/rman.h> 94 95 #include <cam/cam.h> 96 #include <cam/cam_ccb.h> 97 #include <cam/cam_sim.h> 98 #include <cam/cam_xpt_sim.h> 99 #include <cam/cam_debug.h> 100 101 #include <cam/scsi/scsi_all.h> 102 #include <cam/scsi/scsi_message.h> 103 104 /* Short and quite clear integer types */ 105 typedef int8_t s8; 106 typedef int16_t s16; 107 typedef int32_t s32; 108 typedef u_int8_t u8; 109 typedef u_int16_t u16; 110 typedef u_int32_t u32; 111 112 /* 113 * Driver definitions. 114 */ 115 #include <dev/sym/sym_defs.h> 116 #include <dev/sym/sym_fw.h> 117 118 /* 119 * IA32 architecture does not reorder STORES and prevents 120 * LOADS from passing STORES. It is called `program order' 121 * by Intel and allows device drivers to deal with memory 122 * ordering by only ensuring that the code is not reordered 123 * by the compiler when ordering is required. 124 * Other architectures implement a weaker ordering that 125 * requires memory barriers (and also IO barriers when they 126 * make sense) to be used. 127 */ 128 #if defined __i386__ || defined __amd64__ 129 #define MEMORY_BARRIER() do { ; } while(0) 130 #elif defined __powerpc__ 131 #define MEMORY_BARRIER() __asm__ volatile("eieio; sync" : : : "memory") 132 #elif defined __arm__ 133 #define MEMORY_BARRIER() dmb() 134 #elif defined __aarch64__ 135 #define MEMORY_BARRIER() dmb(sy) 136 #elif defined __riscv 137 #define MEMORY_BARRIER() fence() 138 #else 139 #error "Not supported platform" 140 #endif 141 142 /* 143 * A la VMS/CAM-3 queue management. 144 */ 145 typedef struct sym_quehead { 146 struct sym_quehead *flink; /* Forward pointer */ 147 struct sym_quehead *blink; /* Backward pointer */ 148 } SYM_QUEHEAD; 149 150 #define sym_que_init(ptr) do { \ 151 (ptr)->flink = (ptr); (ptr)->blink = (ptr); \ 152 } while (0) 153 154 static __inline void __sym_que_add(struct sym_quehead * new, 155 struct sym_quehead * blink, 156 struct sym_quehead * flink) 157 { 158 flink->blink = new; 159 new->flink = flink; 160 new->blink = blink; 161 blink->flink = new; 162 } 163 164 static __inline void __sym_que_del(struct sym_quehead * blink, 165 struct sym_quehead * flink) 166 { 167 flink->blink = blink; 168 blink->flink = flink; 169 } 170 171 static __inline int sym_que_empty(struct sym_quehead *head) 172 { 173 return head->flink == head; 174 } 175 176 static __inline void sym_que_splice(struct sym_quehead *list, 177 struct sym_quehead *head) 178 { 179 struct sym_quehead *first = list->flink; 180 181 if (first != list) { 182 struct sym_quehead *last = list->blink; 183 struct sym_quehead *at = head->flink; 184 185 first->blink = head; 186 head->flink = first; 187 188 last->flink = at; 189 at->blink = last; 190 } 191 } 192 193 #define sym_que_entry(ptr, type, member) \ 194 ((type *)((char *)(ptr)-(size_t)(&((type *)0)->member))) 195 196 #define sym_insque(new, pos) __sym_que_add(new, pos, (pos)->flink) 197 198 #define sym_remque(el) __sym_que_del((el)->blink, (el)->flink) 199 200 #define sym_insque_head(new, head) __sym_que_add(new, head, (head)->flink) 201 202 static __inline struct sym_quehead *sym_remque_head(struct sym_quehead *head) 203 { 204 struct sym_quehead *elem = head->flink; 205 206 if (elem != head) 207 __sym_que_del(head, elem->flink); 208 else 209 elem = NULL; 210 return elem; 211 } 212 213 #define sym_insque_tail(new, head) __sym_que_add(new, (head)->blink, head) 214 215 /* 216 * This one may be useful. 217 */ 218 #define FOR_EACH_QUEUED_ELEMENT(head, qp) \ 219 for (qp = (head)->flink; qp != (head); qp = qp->flink) 220 /* 221 * FreeBSD does not offer our kind of queue in the CAM CCB. 222 * So, we have to cast. 223 */ 224 #define sym_qptr(p) ((struct sym_quehead *) (p)) 225 226 /* 227 * Simple bitmap operations. 228 */ 229 #define sym_set_bit(p, n) (((u32 *)(p))[(n)>>5] |= (1<<((n)&0x1f))) 230 #define sym_clr_bit(p, n) (((u32 *)(p))[(n)>>5] &= ~(1<<((n)&0x1f))) 231 #define sym_is_bit(p, n) (((u32 *)(p))[(n)>>5] & (1<<((n)&0x1f))) 232 233 /* 234 * Number of tasks per device we want to handle. 235 */ 236 #if SYM_CONF_MAX_TAG_ORDER > 8 237 #error "more than 256 tags per logical unit not allowed." 238 #endif 239 #define SYM_CONF_MAX_TASK (1<<SYM_CONF_MAX_TAG_ORDER) 240 241 /* 242 * Donnot use more tasks that we can handle. 243 */ 244 #ifndef SYM_CONF_MAX_TAG 245 #define SYM_CONF_MAX_TAG SYM_CONF_MAX_TASK 246 #endif 247 #if SYM_CONF_MAX_TAG > SYM_CONF_MAX_TASK 248 #undef SYM_CONF_MAX_TAG 249 #define SYM_CONF_MAX_TAG SYM_CONF_MAX_TASK 250 #endif 251 252 /* 253 * This one means 'NO TAG for this job' 254 */ 255 #define NO_TAG (256) 256 257 /* 258 * Number of SCSI targets. 259 */ 260 #if SYM_CONF_MAX_TARGET > 16 261 #error "more than 16 targets not allowed." 262 #endif 263 264 /* 265 * Number of logical units per target. 266 */ 267 #if SYM_CONF_MAX_LUN > 64 268 #error "more than 64 logical units per target not allowed." 269 #endif 270 271 /* 272 * Asynchronous pre-scaler (ns). Shall be 40 for 273 * the SCSI timings to be compliant. 274 */ 275 #define SYM_CONF_MIN_ASYNC (40) 276 277 /* 278 * Number of entries in the START and DONE queues. 279 * 280 * We limit to 1 PAGE in order to succeed allocation of 281 * these queues. Each entry is 8 bytes long (2 DWORDS). 282 */ 283 #ifdef SYM_CONF_MAX_START 284 #define SYM_CONF_MAX_QUEUE (SYM_CONF_MAX_START+2) 285 #else 286 #define SYM_CONF_MAX_QUEUE (7*SYM_CONF_MAX_TASK+2) 287 #define SYM_CONF_MAX_START (SYM_CONF_MAX_QUEUE-2) 288 #endif 289 290 #if SYM_CONF_MAX_QUEUE > PAGE_SIZE/8 291 #undef SYM_CONF_MAX_QUEUE 292 #define SYM_CONF_MAX_QUEUE PAGE_SIZE/8 293 #undef SYM_CONF_MAX_START 294 #define SYM_CONF_MAX_START (SYM_CONF_MAX_QUEUE-2) 295 #endif 296 297 /* 298 * For this one, we want a short name :-) 299 */ 300 #define MAX_QUEUE SYM_CONF_MAX_QUEUE 301 302 /* 303 * Active debugging tags and verbosity. 304 */ 305 #define DEBUG_ALLOC (0x0001) 306 #define DEBUG_PHASE (0x0002) 307 #define DEBUG_POLL (0x0004) 308 #define DEBUG_QUEUE (0x0008) 309 #define DEBUG_RESULT (0x0010) 310 #define DEBUG_SCATTER (0x0020) 311 #define DEBUG_SCRIPT (0x0040) 312 #define DEBUG_TINY (0x0080) 313 #define DEBUG_TIMING (0x0100) 314 #define DEBUG_NEGO (0x0200) 315 #define DEBUG_TAGS (0x0400) 316 #define DEBUG_POINTER (0x0800) 317 318 #if 0 319 static int sym_debug = 0; 320 #define DEBUG_FLAGS sym_debug 321 #else 322 /* #define DEBUG_FLAGS (0x0631) */ 323 #define DEBUG_FLAGS (0x0000) 324 325 #endif 326 #define sym_verbose (np->verbose) 327 328 /* 329 * Insert a delay in micro-seconds and milli-seconds. 330 */ 331 static void UDELAY(int us) { DELAY(us); } 332 static void MDELAY(int ms) { while (ms--) UDELAY(1000); } 333 334 /* 335 * Simple power of two buddy-like allocator. 336 * 337 * This simple code is not intended to be fast, but to 338 * provide power of 2 aligned memory allocations. 339 * Since the SCRIPTS processor only supplies 8 bit arithmetic, 340 * this allocator allows simple and fast address calculations 341 * from the SCRIPTS code. In addition, cache line alignment 342 * is guaranteed for power of 2 cache line size. 343 * 344 * This allocator has been developed for the Linux sym53c8xx 345 * driver, since this O/S does not provide naturally aligned 346 * allocations. 347 * It has the advantage of allowing the driver to use private 348 * pages of memory that will be useful if we ever need to deal 349 * with IO MMUs for PCI. 350 */ 351 #define MEMO_SHIFT 4 /* 16 bytes minimum memory chunk */ 352 #define MEMO_PAGE_ORDER 0 /* 1 PAGE maximum */ 353 #if 0 354 #define MEMO_FREE_UNUSED /* Free unused pages immediately */ 355 #endif 356 #define MEMO_WARN 1 357 #define MEMO_CLUSTER_SHIFT (PAGE_SHIFT+MEMO_PAGE_ORDER) 358 #define MEMO_CLUSTER_SIZE (1UL << MEMO_CLUSTER_SHIFT) 359 #define MEMO_CLUSTER_MASK (MEMO_CLUSTER_SIZE-1) 360 361 #define get_pages() malloc(MEMO_CLUSTER_SIZE, M_DEVBUF, M_NOWAIT) 362 #define free_pages(p) free((p), M_DEVBUF) 363 364 typedef u_long m_addr_t; /* Enough bits to bit-hack addresses */ 365 366 typedef struct m_link { /* Link between free memory chunks */ 367 struct m_link *next; 368 } m_link_s; 369 370 typedef struct m_vtob { /* Virtual to Bus address translation */ 371 struct m_vtob *next; 372 bus_dmamap_t dmamap; /* Map for this chunk */ 373 m_addr_t vaddr; /* Virtual address */ 374 m_addr_t baddr; /* Bus physical address */ 375 } m_vtob_s; 376 /* Hash this stuff a bit to speed up translations */ 377 #define VTOB_HASH_SHIFT 5 378 #define VTOB_HASH_SIZE (1UL << VTOB_HASH_SHIFT) 379 #define VTOB_HASH_MASK (VTOB_HASH_SIZE-1) 380 #define VTOB_HASH_CODE(m) \ 381 ((((m_addr_t) (m)) >> MEMO_CLUSTER_SHIFT) & VTOB_HASH_MASK) 382 383 typedef struct m_pool { /* Memory pool of a given kind */ 384 bus_dma_tag_t dev_dmat; /* Identifies the pool */ 385 bus_dma_tag_t dmat; /* Tag for our fixed allocations */ 386 m_addr_t (*getp)(struct m_pool *); 387 #ifdef MEMO_FREE_UNUSED 388 void (*freep)(struct m_pool *, m_addr_t); 389 #endif 390 #define M_GETP() mp->getp(mp) 391 #define M_FREEP(p) mp->freep(mp, p) 392 int nump; 393 m_vtob_s *(vtob[VTOB_HASH_SIZE]); 394 struct m_pool *next; 395 struct m_link h[MEMO_CLUSTER_SHIFT - MEMO_SHIFT + 1]; 396 } m_pool_s; 397 398 static void *___sym_malloc(m_pool_s *mp, int size) 399 { 400 int i = 0; 401 int s = (1 << MEMO_SHIFT); 402 int j; 403 m_addr_t a; 404 m_link_s *h = mp->h; 405 406 if (size > MEMO_CLUSTER_SIZE) 407 return NULL; 408 409 while (size > s) { 410 s <<= 1; 411 ++i; 412 } 413 414 j = i; 415 while (!h[j].next) { 416 if (s == MEMO_CLUSTER_SIZE) { 417 h[j].next = (m_link_s *) M_GETP(); 418 if (h[j].next) 419 h[j].next->next = NULL; 420 break; 421 } 422 ++j; 423 s <<= 1; 424 } 425 a = (m_addr_t) h[j].next; 426 if (a) { 427 h[j].next = h[j].next->next; 428 while (j > i) { 429 j -= 1; 430 s >>= 1; 431 h[j].next = (m_link_s *) (a+s); 432 h[j].next->next = NULL; 433 } 434 } 435 #ifdef DEBUG 436 printf("___sym_malloc(%d) = %p\n", size, (void *) a); 437 #endif 438 return (void *) a; 439 } 440 441 static void ___sym_mfree(m_pool_s *mp, void *ptr, int size) 442 { 443 int i = 0; 444 int s = (1 << MEMO_SHIFT); 445 m_link_s *q; 446 m_addr_t a, b; 447 m_link_s *h = mp->h; 448 449 #ifdef DEBUG 450 printf("___sym_mfree(%p, %d)\n", ptr, size); 451 #endif 452 453 if (size > MEMO_CLUSTER_SIZE) 454 return; 455 456 while (size > s) { 457 s <<= 1; 458 ++i; 459 } 460 461 a = (m_addr_t) ptr; 462 463 while (1) { 464 #ifdef MEMO_FREE_UNUSED 465 if (s == MEMO_CLUSTER_SIZE) { 466 M_FREEP(a); 467 break; 468 } 469 #endif 470 b = a ^ s; 471 q = &h[i]; 472 while (q->next && q->next != (m_link_s *) b) { 473 q = q->next; 474 } 475 if (!q->next) { 476 ((m_link_s *) a)->next = h[i].next; 477 h[i].next = (m_link_s *) a; 478 break; 479 } 480 q->next = q->next->next; 481 a = a & b; 482 s <<= 1; 483 ++i; 484 } 485 } 486 487 static void *__sym_calloc2(m_pool_s *mp, int size, char *name, int uflags) 488 { 489 void *p; 490 491 p = ___sym_malloc(mp, size); 492 493 if (DEBUG_FLAGS & DEBUG_ALLOC) 494 printf ("new %-10s[%4d] @%p.\n", name, size, p); 495 496 if (p) 497 bzero(p, size); 498 else if (uflags & MEMO_WARN) 499 printf ("__sym_calloc2: failed to allocate %s[%d]\n", name, size); 500 501 return p; 502 } 503 504 #define __sym_calloc(mp, s, n) __sym_calloc2(mp, s, n, MEMO_WARN) 505 506 static void __sym_mfree(m_pool_s *mp, void *ptr, int size, char *name) 507 { 508 if (DEBUG_FLAGS & DEBUG_ALLOC) 509 printf ("freeing %-10s[%4d] @%p.\n", name, size, ptr); 510 511 ___sym_mfree(mp, ptr, size); 512 513 } 514 515 /* 516 * Default memory pool we donnot need to involve in DMA. 517 */ 518 /* 519 * With the `bus dma abstraction', we use a separate pool for 520 * memory we donnot need to involve in DMA. 521 */ 522 static m_addr_t ___mp0_getp(m_pool_s *mp) 523 { 524 m_addr_t m = (m_addr_t) get_pages(); 525 if (m) 526 ++mp->nump; 527 return m; 528 } 529 530 #ifdef MEMO_FREE_UNUSED 531 static void ___mp0_freep(m_pool_s *mp, m_addr_t m) 532 { 533 free_pages(m); 534 --mp->nump; 535 } 536 #endif 537 538 #ifdef MEMO_FREE_UNUSED 539 static m_pool_s mp0 = {0, 0, ___mp0_getp, ___mp0_freep}; 540 #else 541 static m_pool_s mp0 = {0, 0, ___mp0_getp}; 542 #endif 543 544 /* 545 * Actual memory allocation routine for non-DMAed memory. 546 */ 547 static void *sym_calloc(int size, char *name) 548 { 549 void *m; 550 /* Lock */ 551 m = __sym_calloc(&mp0, size, name); 552 /* Unlock */ 553 return m; 554 } 555 556 /* 557 * Actual memory allocation routine for non-DMAed memory. 558 */ 559 static void sym_mfree(void *ptr, int size, char *name) 560 { 561 /* Lock */ 562 __sym_mfree(&mp0, ptr, size, name); 563 /* Unlock */ 564 } 565 566 /* 567 * DMAable pools. 568 */ 569 /* 570 * With `bus dma abstraction', we use a separate pool per parent 571 * BUS handle. A reverse table (hashed) is maintained for virtual 572 * to BUS address translation. 573 */ 574 static void getbaddrcb(void *arg, bus_dma_segment_t *segs, int nseg __unused, 575 int error) 576 { 577 bus_addr_t *baddr; 578 579 KASSERT(nseg == 1, ("%s: too many DMA segments (%d)", __func__, nseg)); 580 581 baddr = (bus_addr_t *)arg; 582 if (error) 583 *baddr = 0; 584 else 585 *baddr = segs->ds_addr; 586 } 587 588 static m_addr_t ___dma_getp(m_pool_s *mp) 589 { 590 m_vtob_s *vbp; 591 void *vaddr = NULL; 592 bus_addr_t baddr = 0; 593 594 vbp = __sym_calloc(&mp0, sizeof(*vbp), "VTOB"); 595 if (!vbp) 596 goto out_err; 597 598 if (bus_dmamem_alloc(mp->dmat, &vaddr, 599 BUS_DMA_COHERENT | BUS_DMA_WAITOK, &vbp->dmamap)) 600 goto out_err; 601 bus_dmamap_load(mp->dmat, vbp->dmamap, vaddr, 602 MEMO_CLUSTER_SIZE, getbaddrcb, &baddr, BUS_DMA_NOWAIT); 603 if (baddr) { 604 int hc = VTOB_HASH_CODE(vaddr); 605 vbp->vaddr = (m_addr_t) vaddr; 606 vbp->baddr = (m_addr_t) baddr; 607 vbp->next = mp->vtob[hc]; 608 mp->vtob[hc] = vbp; 609 ++mp->nump; 610 return (m_addr_t) vaddr; 611 } 612 out_err: 613 if (baddr) 614 bus_dmamap_unload(mp->dmat, vbp->dmamap); 615 if (vaddr) 616 bus_dmamem_free(mp->dmat, vaddr, vbp->dmamap); 617 if (vbp) 618 __sym_mfree(&mp0, vbp, sizeof(*vbp), "VTOB"); 619 return 0; 620 } 621 622 #ifdef MEMO_FREE_UNUSED 623 static void ___dma_freep(m_pool_s *mp, m_addr_t m) 624 { 625 m_vtob_s **vbpp, *vbp; 626 int hc = VTOB_HASH_CODE(m); 627 628 vbpp = &mp->vtob[hc]; 629 while (*vbpp && (*vbpp)->vaddr != m) 630 vbpp = &(*vbpp)->next; 631 if (*vbpp) { 632 vbp = *vbpp; 633 *vbpp = (*vbpp)->next; 634 bus_dmamap_unload(mp->dmat, vbp->dmamap); 635 bus_dmamem_free(mp->dmat, (void *) vbp->vaddr, vbp->dmamap); 636 __sym_mfree(&mp0, vbp, sizeof(*vbp), "VTOB"); 637 --mp->nump; 638 } 639 } 640 #endif 641 642 static __inline m_pool_s *___get_dma_pool(bus_dma_tag_t dev_dmat) 643 { 644 m_pool_s *mp; 645 for (mp = mp0.next; mp && mp->dev_dmat != dev_dmat; mp = mp->next); 646 return mp; 647 } 648 649 static m_pool_s *___cre_dma_pool(bus_dma_tag_t dev_dmat) 650 { 651 m_pool_s *mp = NULL; 652 653 mp = __sym_calloc(&mp0, sizeof(*mp), "MPOOL"); 654 if (mp) { 655 mp->dev_dmat = dev_dmat; 656 if (!bus_dma_tag_create(dev_dmat, 1, MEMO_CLUSTER_SIZE, 657 BUS_SPACE_MAXADDR_32BIT, 658 BUS_SPACE_MAXADDR, 659 NULL, NULL, MEMO_CLUSTER_SIZE, 1, 660 MEMO_CLUSTER_SIZE, 0, 661 NULL, NULL, &mp->dmat)) { 662 mp->getp = ___dma_getp; 663 #ifdef MEMO_FREE_UNUSED 664 mp->freep = ___dma_freep; 665 #endif 666 mp->next = mp0.next; 667 mp0.next = mp; 668 return mp; 669 } 670 } 671 if (mp) 672 __sym_mfree(&mp0, mp, sizeof(*mp), "MPOOL"); 673 return NULL; 674 } 675 676 #ifdef MEMO_FREE_UNUSED 677 static void ___del_dma_pool(m_pool_s *p) 678 { 679 struct m_pool **pp = &mp0.next; 680 681 while (*pp && *pp != p) 682 pp = &(*pp)->next; 683 if (*pp) { 684 *pp = (*pp)->next; 685 bus_dma_tag_destroy(p->dmat); 686 __sym_mfree(&mp0, p, sizeof(*p), "MPOOL"); 687 } 688 } 689 #endif 690 691 static void *__sym_calloc_dma(bus_dma_tag_t dev_dmat, int size, char *name) 692 { 693 struct m_pool *mp; 694 void *m = NULL; 695 696 /* Lock */ 697 mp = ___get_dma_pool(dev_dmat); 698 if (!mp) 699 mp = ___cre_dma_pool(dev_dmat); 700 if (mp) 701 m = __sym_calloc(mp, size, name); 702 #ifdef MEMO_FREE_UNUSED 703 if (mp && !mp->nump) 704 ___del_dma_pool(mp); 705 #endif 706 /* Unlock */ 707 708 return m; 709 } 710 711 static void 712 __sym_mfree_dma(bus_dma_tag_t dev_dmat, void *m, int size, char *name) 713 { 714 struct m_pool *mp; 715 716 /* Lock */ 717 mp = ___get_dma_pool(dev_dmat); 718 if (mp) 719 __sym_mfree(mp, m, size, name); 720 #ifdef MEMO_FREE_UNUSED 721 if (mp && !mp->nump) 722 ___del_dma_pool(mp); 723 #endif 724 /* Unlock */ 725 } 726 727 static m_addr_t __vtobus(bus_dma_tag_t dev_dmat, void *m) 728 { 729 m_pool_s *mp; 730 int hc = VTOB_HASH_CODE(m); 731 m_vtob_s *vp = NULL; 732 m_addr_t a = ((m_addr_t) m) & ~MEMO_CLUSTER_MASK; 733 734 /* Lock */ 735 mp = ___get_dma_pool(dev_dmat); 736 if (mp) { 737 vp = mp->vtob[hc]; 738 while (vp && (m_addr_t) vp->vaddr != a) 739 vp = vp->next; 740 } 741 /* Unlock */ 742 if (!vp) 743 panic("sym: VTOBUS FAILED!\n"); 744 return vp ? vp->baddr + (((m_addr_t) m) - a) : 0; 745 } 746 747 /* 748 * Verbs for DMAable memory handling. 749 * The _uvptv_ macro avoids a nasty warning about pointer to volatile 750 * being discarded. 751 */ 752 #define _uvptv_(p) ((void *)((vm_offset_t)(p))) 753 #define _sym_calloc_dma(np, s, n) __sym_calloc_dma(np->bus_dmat, s, n) 754 #define _sym_mfree_dma(np, p, s, n) \ 755 __sym_mfree_dma(np->bus_dmat, _uvptv_(p), s, n) 756 #define sym_calloc_dma(s, n) _sym_calloc_dma(np, s, n) 757 #define sym_mfree_dma(p, s, n) _sym_mfree_dma(np, p, s, n) 758 #define _vtobus(np, p) __vtobus(np->bus_dmat, _uvptv_(p)) 759 #define vtobus(p) _vtobus(np, p) 760 761 /* 762 * Print a buffer in hexadecimal format. 763 */ 764 static void sym_printb_hex (u_char *p, int n) 765 { 766 while (n-- > 0) 767 printf (" %x", *p++); 768 } 769 770 /* 771 * Same with a label at beginning and .\n at end. 772 */ 773 static void sym_printl_hex (char *label, u_char *p, int n) 774 { 775 printf ("%s", label); 776 sym_printb_hex (p, n); 777 printf (".\n"); 778 } 779 780 /* 781 * Return a string for SCSI BUS mode. 782 */ 783 static const char *sym_scsi_bus_mode(int mode) 784 { 785 switch(mode) { 786 case SMODE_HVD: return "HVD"; 787 case SMODE_SE: return "SE"; 788 case SMODE_LVD: return "LVD"; 789 } 790 return "??"; 791 } 792 793 /* 794 * Some poor and bogus sync table that refers to Tekram NVRAM layout. 795 */ 796 #ifdef SYM_CONF_NVRAM_SUPPORT 797 static const u_char Tekram_sync[16] = 798 {25,31,37,43, 50,62,75,125, 12,15,18,21, 6,7,9,10}; 799 #endif 800 801 /* 802 * Union of supported NVRAM formats. 803 */ 804 struct sym_nvram { 805 int type; 806 #define SYM_SYMBIOS_NVRAM (1) 807 #define SYM_TEKRAM_NVRAM (2) 808 #ifdef SYM_CONF_NVRAM_SUPPORT 809 union { 810 Symbios_nvram Symbios; 811 Tekram_nvram Tekram; 812 } data; 813 #endif 814 }; 815 816 /* 817 * This one is hopefully useless, but actually useful. :-) 818 */ 819 #ifndef assert 820 #define assert(expression) { \ 821 if (!(expression)) { \ 822 (void)panic( \ 823 "assertion \"%s\" failed: file \"%s\", line %d\n", \ 824 #expression, \ 825 __FILE__, __LINE__); \ 826 } \ 827 } 828 #endif 829 830 /* 831 * Some provision for a possible big endian mode supported by 832 * Symbios chips (never seen, by the way). 833 * For now, this stuff does not deserve any comments. :) 834 */ 835 #define sym_offb(o) (o) 836 #define sym_offw(o) (o) 837 838 /* 839 * Some provision for support for BIG ENDIAN CPU. 840 */ 841 #define cpu_to_scr(dw) htole32(dw) 842 #define scr_to_cpu(dw) le32toh(dw) 843 844 /* 845 * Access to the chip IO registers and on-chip RAM. 846 * We use the `bus space' interface under FreeBSD-4 and 847 * later kernel versions. 848 */ 849 #if defined(SYM_CONF_IOMAPPED) 850 851 #define INB_OFF(o) bus_read_1(np->io_res, (o)) 852 #define INW_OFF(o) bus_read_2(np->io_res, (o)) 853 #define INL_OFF(o) bus_read_4(np->io_res, (o)) 854 855 #define OUTB_OFF(o, v) bus_write_1(np->io_res, (o), (v)) 856 #define OUTW_OFF(o, v) bus_write_2(np->io_res, (o), (v)) 857 #define OUTL_OFF(o, v) bus_write_4(np->io_res, (o), (v)) 858 859 #else /* Memory mapped IO */ 860 861 #define INB_OFF(o) bus_read_1(np->mmio_res, (o)) 862 #define INW_OFF(o) bus_read_2(np->mmio_res, (o)) 863 #define INL_OFF(o) bus_read_4(np->mmio_res, (o)) 864 865 #define OUTB_OFF(o, v) bus_write_1(np->mmio_res, (o), (v)) 866 #define OUTW_OFF(o, v) bus_write_2(np->mmio_res, (o), (v)) 867 #define OUTL_OFF(o, v) bus_write_4(np->mmio_res, (o), (v)) 868 869 #endif /* SYM_CONF_IOMAPPED */ 870 871 #define OUTRAM_OFF(o, a, l) \ 872 bus_write_region_1(np->ram_res, (o), (a), (l)) 873 874 /* 875 * Common definitions for both bus space and legacy IO methods. 876 */ 877 #define INB(r) INB_OFF(offsetof(struct sym_reg,r)) 878 #define INW(r) INW_OFF(offsetof(struct sym_reg,r)) 879 #define INL(r) INL_OFF(offsetof(struct sym_reg,r)) 880 881 #define OUTB(r, v) OUTB_OFF(offsetof(struct sym_reg,r), (v)) 882 #define OUTW(r, v) OUTW_OFF(offsetof(struct sym_reg,r), (v)) 883 #define OUTL(r, v) OUTL_OFF(offsetof(struct sym_reg,r), (v)) 884 885 #define OUTONB(r, m) OUTB(r, INB(r) | (m)) 886 #define OUTOFFB(r, m) OUTB(r, INB(r) & ~(m)) 887 #define OUTONW(r, m) OUTW(r, INW(r) | (m)) 888 #define OUTOFFW(r, m) OUTW(r, INW(r) & ~(m)) 889 #define OUTONL(r, m) OUTL(r, INL(r) | (m)) 890 #define OUTOFFL(r, m) OUTL(r, INL(r) & ~(m)) 891 892 /* 893 * We normally want the chip to have a consistent view 894 * of driver internal data structures when we restart it. 895 * Thus these macros. 896 */ 897 #define OUTL_DSP(v) \ 898 do { \ 899 MEMORY_BARRIER(); \ 900 OUTL (nc_dsp, (v)); \ 901 } while (0) 902 903 #define OUTONB_STD() \ 904 do { \ 905 MEMORY_BARRIER(); \ 906 OUTONB (nc_dcntl, (STD|NOCOM)); \ 907 } while (0) 908 909 /* 910 * Command control block states. 911 */ 912 #define HS_IDLE (0) 913 #define HS_BUSY (1) 914 #define HS_NEGOTIATE (2) /* sync/wide data transfer*/ 915 #define HS_DISCONNECT (3) /* Disconnected by target */ 916 #define HS_WAIT (4) /* waiting for resource */ 917 918 #define HS_DONEMASK (0x80) 919 #define HS_COMPLETE (4|HS_DONEMASK) 920 #define HS_SEL_TIMEOUT (5|HS_DONEMASK) /* Selection timeout */ 921 #define HS_UNEXPECTED (6|HS_DONEMASK) /* Unexpected disconnect */ 922 #define HS_COMP_ERR (7|HS_DONEMASK) /* Completed with error */ 923 924 /* 925 * Software Interrupt Codes 926 */ 927 #define SIR_BAD_SCSI_STATUS (1) 928 #define SIR_SEL_ATN_NO_MSG_OUT (2) 929 #define SIR_MSG_RECEIVED (3) 930 #define SIR_MSG_WEIRD (4) 931 #define SIR_NEGO_FAILED (5) 932 #define SIR_NEGO_PROTO (6) 933 #define SIR_SCRIPT_STOPPED (7) 934 #define SIR_REJECT_TO_SEND (8) 935 #define SIR_SWIDE_OVERRUN (9) 936 #define SIR_SODL_UNDERRUN (10) 937 #define SIR_RESEL_NO_MSG_IN (11) 938 #define SIR_RESEL_NO_IDENTIFY (12) 939 #define SIR_RESEL_BAD_LUN (13) 940 #define SIR_TARGET_SELECTED (14) 941 #define SIR_RESEL_BAD_I_T_L (15) 942 #define SIR_RESEL_BAD_I_T_L_Q (16) 943 #define SIR_ABORT_SENT (17) 944 #define SIR_RESEL_ABORTED (18) 945 #define SIR_MSG_OUT_DONE (19) 946 #define SIR_COMPLETE_ERROR (20) 947 #define SIR_DATA_OVERRUN (21) 948 #define SIR_BAD_PHASE (22) 949 #define SIR_MAX (22) 950 951 /* 952 * Extended error bit codes. 953 * xerr_status field of struct sym_ccb. 954 */ 955 #define XE_EXTRA_DATA (1) /* unexpected data phase */ 956 #define XE_BAD_PHASE (1<<1) /* illegal phase (4/5) */ 957 #define XE_PARITY_ERR (1<<2) /* unrecovered SCSI parity error */ 958 #define XE_SODL_UNRUN (1<<3) /* ODD transfer in DATA OUT phase */ 959 #define XE_SWIDE_OVRUN (1<<4) /* ODD transfer in DATA IN phase */ 960 961 /* 962 * Negotiation status. 963 * nego_status field of struct sym_ccb. 964 */ 965 #define NS_SYNC (1) 966 #define NS_WIDE (2) 967 #define NS_PPR (3) 968 969 /* 970 * A CCB hashed table is used to retrieve CCB address 971 * from DSA value. 972 */ 973 #define CCB_HASH_SHIFT 8 974 #define CCB_HASH_SIZE (1UL << CCB_HASH_SHIFT) 975 #define CCB_HASH_MASK (CCB_HASH_SIZE-1) 976 #define CCB_HASH_CODE(dsa) (((dsa) >> 9) & CCB_HASH_MASK) 977 978 /* 979 * Device flags. 980 */ 981 #define SYM_DISC_ENABLED (1) 982 #define SYM_TAGS_ENABLED (1<<1) 983 #define SYM_SCAN_BOOT_DISABLED (1<<2) 984 #define SYM_SCAN_LUNS_DISABLED (1<<3) 985 986 /* 987 * Host adapter miscellaneous flags. 988 */ 989 #define SYM_AVOID_BUS_RESET (1) 990 #define SYM_SCAN_TARGETS_HILO (1<<1) 991 992 /* 993 * Device quirks. 994 * Some devices, for example the CHEETAH 2 LVD, disconnects without 995 * saving the DATA POINTER then reselects and terminates the IO. 996 * On reselection, the automatic RESTORE DATA POINTER makes the 997 * CURRENT DATA POINTER not point at the end of the IO. 998 * This behaviour just breaks our calculation of the residual. 999 * For now, we just force an AUTO SAVE on disconnection and will 1000 * fix that in a further driver version. 1001 */ 1002 #define SYM_QUIRK_AUTOSAVE 1 1003 1004 /* 1005 * Misc. 1006 */ 1007 #define SYM_LOCK() mtx_lock(&np->mtx) 1008 #define SYM_LOCK_ASSERT(_what) mtx_assert(&np->mtx, (_what)) 1009 #define SYM_LOCK_DESTROY() mtx_destroy(&np->mtx) 1010 #define SYM_LOCK_INIT() mtx_init(&np->mtx, "sym_lock", NULL, MTX_DEF) 1011 #define SYM_LOCK_INITIALIZED() mtx_initialized(&np->mtx) 1012 #define SYM_UNLOCK() mtx_unlock(&np->mtx) 1013 1014 #define SYM_SNOOP_TIMEOUT (10000000) 1015 #define SYM_PCI_IO PCIR_BAR(0) 1016 #define SYM_PCI_MMIO PCIR_BAR(1) 1017 #define SYM_PCI_RAM PCIR_BAR(2) 1018 #define SYM_PCI_RAM64 PCIR_BAR(3) 1019 1020 /* 1021 * Back-pointer from the CAM CCB to our data structures. 1022 */ 1023 #define sym_hcb_ptr spriv_ptr0 1024 /* #define sym_ccb_ptr spriv_ptr1 */ 1025 1026 /* 1027 * We mostly have to deal with pointers. 1028 * Thus these typedef's. 1029 */ 1030 typedef struct sym_tcb *tcb_p; 1031 typedef struct sym_lcb *lcb_p; 1032 typedef struct sym_ccb *ccb_p; 1033 typedef struct sym_hcb *hcb_p; 1034 1035 /* 1036 * Gather negotiable parameters value 1037 */ 1038 struct sym_trans { 1039 u8 scsi_version; 1040 u8 spi_version; 1041 u8 period; 1042 u8 offset; 1043 u8 width; 1044 u8 options; /* PPR options */ 1045 }; 1046 1047 struct sym_tinfo { 1048 struct sym_trans current; 1049 struct sym_trans goal; 1050 struct sym_trans user; 1051 }; 1052 1053 #define BUS_8_BIT MSG_EXT_WDTR_BUS_8_BIT 1054 #define BUS_16_BIT MSG_EXT_WDTR_BUS_16_BIT 1055 1056 /* 1057 * Global TCB HEADER. 1058 * 1059 * Due to lack of indirect addressing on earlier NCR chips, 1060 * this substructure is copied from the TCB to a global 1061 * address after selection. 1062 * For SYMBIOS chips that support LOAD/STORE this copy is 1063 * not needed and thus not performed. 1064 */ 1065 struct sym_tcbh { 1066 /* 1067 * Scripts bus addresses of LUN table accessed from scripts. 1068 * LUN #0 is a special case, since multi-lun devices are rare, 1069 * and we we want to speed-up the general case and not waste 1070 * resources. 1071 */ 1072 u32 luntbl_sa; /* bus address of this table */ 1073 u32 lun0_sa; /* bus address of LCB #0 */ 1074 /* 1075 * Actual SYNC/WIDE IO registers value for this target. 1076 * 'sval', 'wval' and 'uval' are read from SCRIPTS and 1077 * so have alignment constraints. 1078 */ 1079 /*0*/ u_char uval; /* -> SCNTL4 register */ 1080 /*1*/ u_char sval; /* -> SXFER io register */ 1081 /*2*/ u_char filler1; 1082 /*3*/ u_char wval; /* -> SCNTL3 io register */ 1083 }; 1084 1085 /* 1086 * Target Control Block 1087 */ 1088 struct sym_tcb { 1089 /* 1090 * TCB header. 1091 * Assumed at offset 0. 1092 */ 1093 /*0*/ struct sym_tcbh head; 1094 1095 /* 1096 * LUN table used by the SCRIPTS processor. 1097 * An array of bus addresses is used on reselection. 1098 */ 1099 u32 *luntbl; /* LCBs bus address table */ 1100 1101 /* 1102 * LUN table used by the C code. 1103 */ 1104 lcb_p lun0p; /* LCB of LUN #0 (usual case) */ 1105 #if SYM_CONF_MAX_LUN > 1 1106 lcb_p *lunmp; /* Other LCBs [1..MAX_LUN] */ 1107 #endif 1108 1109 /* 1110 * Bitmap that tells about LUNs that succeeded at least 1111 * 1 IO and therefore assumed to be a real device. 1112 * Avoid useless allocation of the LCB structure. 1113 */ 1114 u32 lun_map[(SYM_CONF_MAX_LUN+31)/32]; 1115 1116 /* 1117 * Bitmap that tells about LUNs that haven't yet an LCB 1118 * allocated (not discovered or LCB allocation failed). 1119 */ 1120 u32 busy0_map[(SYM_CONF_MAX_LUN+31)/32]; 1121 1122 /* 1123 * Transfer capabilities (SIP) 1124 */ 1125 struct sym_tinfo tinfo; 1126 1127 /* 1128 * Keep track of the CCB used for the negotiation in order 1129 * to ensure that only 1 negotiation is queued at a time. 1130 */ 1131 ccb_p nego_cp; /* CCB used for the nego */ 1132 1133 /* 1134 * Set when we want to reset the device. 1135 */ 1136 u_char to_reset; 1137 1138 /* 1139 * Other user settable limits and options. 1140 * These limits are read from the NVRAM if present. 1141 */ 1142 u_char usrflags; 1143 u_short usrtags; 1144 }; 1145 1146 /* 1147 * Assert some alignments required by the chip. 1148 */ 1149 CTASSERT(((offsetof(struct sym_reg, nc_sxfer) ^ 1150 offsetof(struct sym_tcb, head.sval)) &3) == 0); 1151 CTASSERT(((offsetof(struct sym_reg, nc_scntl3) ^ 1152 offsetof(struct sym_tcb, head.wval)) &3) == 0); 1153 1154 /* 1155 * Global LCB HEADER. 1156 * 1157 * Due to lack of indirect addressing on earlier NCR chips, 1158 * this substructure is copied from the LCB to a global 1159 * address after selection. 1160 * For SYMBIOS chips that support LOAD/STORE this copy is 1161 * not needed and thus not performed. 1162 */ 1163 struct sym_lcbh { 1164 /* 1165 * SCRIPTS address jumped by SCRIPTS on reselection. 1166 * For not probed logical units, this address points to 1167 * SCRIPTS that deal with bad LU handling (must be at 1168 * offset zero of the LCB for that reason). 1169 */ 1170 /*0*/ u32 resel_sa; 1171 1172 /* 1173 * Task (bus address of a CCB) read from SCRIPTS that points 1174 * to the unique ITL nexus allowed to be disconnected. 1175 */ 1176 u32 itl_task_sa; 1177 1178 /* 1179 * Task table bus address (read from SCRIPTS). 1180 */ 1181 u32 itlq_tbl_sa; 1182 }; 1183 1184 /* 1185 * Logical Unit Control Block 1186 */ 1187 struct sym_lcb { 1188 /* 1189 * TCB header. 1190 * Assumed at offset 0. 1191 */ 1192 /*0*/ struct sym_lcbh head; 1193 1194 /* 1195 * Task table read from SCRIPTS that contains pointers to 1196 * ITLQ nexuses. The bus address read from SCRIPTS is 1197 * inside the header. 1198 */ 1199 u32 *itlq_tbl; /* Kernel virtual address */ 1200 1201 /* 1202 * Busy CCBs management. 1203 */ 1204 u_short busy_itlq; /* Number of busy tagged CCBs */ 1205 u_short busy_itl; /* Number of busy untagged CCBs */ 1206 1207 /* 1208 * Circular tag allocation buffer. 1209 */ 1210 u_short ia_tag; /* Tag allocation index */ 1211 u_short if_tag; /* Tag release index */ 1212 u_char *cb_tags; /* Circular tags buffer */ 1213 1214 /* 1215 * Set when we want to clear all tasks. 1216 */ 1217 u_char to_clear; 1218 1219 /* 1220 * Capabilities. 1221 */ 1222 u_char user_flags; 1223 u_char current_flags; 1224 }; 1225 1226 /* 1227 * Action from SCRIPTS on a task. 1228 * Is part of the CCB, but is also used separately to plug 1229 * error handling action to perform from SCRIPTS. 1230 */ 1231 struct sym_actscr { 1232 u32 start; /* Jumped by SCRIPTS after selection */ 1233 u32 restart; /* Jumped by SCRIPTS on relection */ 1234 }; 1235 1236 /* 1237 * Phase mismatch context. 1238 * 1239 * It is part of the CCB and is used as parameters for the 1240 * DATA pointer. We need two contexts to handle correctly the 1241 * SAVED DATA POINTER. 1242 */ 1243 struct sym_pmc { 1244 struct sym_tblmove sg; /* Updated interrupted SG block */ 1245 u32 ret; /* SCRIPT return address */ 1246 }; 1247 1248 /* 1249 * LUN control block lookup. 1250 * We use a direct pointer for LUN #0, and a table of 1251 * pointers which is only allocated for devices that support 1252 * LUN(s) > 0. 1253 */ 1254 #if SYM_CONF_MAX_LUN <= 1 1255 #define sym_lp(tp, lun) (!lun) ? (tp)->lun0p : 0 1256 #else 1257 #define sym_lp(tp, lun) \ 1258 (!lun) ? (tp)->lun0p : (tp)->lunmp ? (tp)->lunmp[(lun)] : 0 1259 #endif 1260 1261 /* 1262 * Status are used by the host and the script processor. 1263 * 1264 * The last four bytes (status[4]) are copied to the 1265 * scratchb register (declared as scr0..scr3) just after the 1266 * select/reselect, and copied back just after disconnecting. 1267 * Inside the script the XX_REG are used. 1268 */ 1269 1270 /* 1271 * Last four bytes (script) 1272 */ 1273 #define QU_REG scr0 1274 #define HS_REG scr1 1275 #define HS_PRT nc_scr1 1276 #define SS_REG scr2 1277 #define SS_PRT nc_scr2 1278 #define HF_REG scr3 1279 #define HF_PRT nc_scr3 1280 1281 /* 1282 * Last four bytes (host) 1283 */ 1284 #define actualquirks phys.head.status[0] 1285 #define host_status phys.head.status[1] 1286 #define ssss_status phys.head.status[2] 1287 #define host_flags phys.head.status[3] 1288 1289 /* 1290 * Host flags 1291 */ 1292 #define HF_IN_PM0 1u 1293 #define HF_IN_PM1 (1u<<1) 1294 #define HF_ACT_PM (1u<<2) 1295 #define HF_DP_SAVED (1u<<3) 1296 #define HF_SENSE (1u<<4) 1297 #define HF_EXT_ERR (1u<<5) 1298 #define HF_DATA_IN (1u<<6) 1299 #ifdef SYM_CONF_IARB_SUPPORT 1300 #define HF_HINT_IARB (1u<<7) 1301 #endif 1302 1303 /* 1304 * Global CCB HEADER. 1305 * 1306 * Due to lack of indirect addressing on earlier NCR chips, 1307 * this substructure is copied from the ccb to a global 1308 * address after selection (or reselection) and copied back 1309 * before disconnect. 1310 * For SYMBIOS chips that support LOAD/STORE this copy is 1311 * not needed and thus not performed. 1312 */ 1313 struct sym_ccbh { 1314 /* 1315 * Start and restart SCRIPTS addresses (must be at 0). 1316 */ 1317 /*0*/ struct sym_actscr go; 1318 1319 /* 1320 * SCRIPTS jump address that deal with data pointers. 1321 * 'savep' points to the position in the script responsible 1322 * for the actual transfer of data. 1323 * It's written on reception of a SAVE_DATA_POINTER message. 1324 */ 1325 u32 savep; /* Jump address to saved data pointer */ 1326 u32 lastp; /* SCRIPTS address at end of data */ 1327 u32 goalp; /* Not accessed for now from SCRIPTS */ 1328 1329 /* 1330 * Status fields. 1331 */ 1332 u8 status[4]; 1333 }; 1334 1335 /* 1336 * Data Structure Block 1337 * 1338 * During execution of a ccb by the script processor, the 1339 * DSA (data structure address) register points to this 1340 * substructure of the ccb. 1341 */ 1342 struct sym_dsb { 1343 /* 1344 * CCB header. 1345 * Also assumed at offset 0 of the sym_ccb structure. 1346 */ 1347 /*0*/ struct sym_ccbh head; 1348 1349 /* 1350 * Phase mismatch contexts. 1351 * We need two to handle correctly the SAVED DATA POINTER. 1352 * MUST BOTH BE AT OFFSET < 256, due to using 8 bit arithmetic 1353 * for address calculation from SCRIPTS. 1354 */ 1355 struct sym_pmc pm0; 1356 struct sym_pmc pm1; 1357 1358 /* 1359 * Table data for Script 1360 */ 1361 struct sym_tblsel select; 1362 struct sym_tblmove smsg; 1363 struct sym_tblmove smsg_ext; 1364 struct sym_tblmove cmd; 1365 struct sym_tblmove sense; 1366 struct sym_tblmove wresid; 1367 struct sym_tblmove data [SYM_CONF_MAX_SG]; 1368 }; 1369 1370 /* 1371 * Our Command Control Block 1372 */ 1373 struct sym_ccb { 1374 /* 1375 * This is the data structure which is pointed by the DSA 1376 * register when it is executed by the script processor. 1377 * It must be the first entry. 1378 */ 1379 struct sym_dsb phys; 1380 1381 /* 1382 * Pointer to CAM ccb and related stuff. 1383 */ 1384 struct callout ch; /* callout handle */ 1385 union ccb *cam_ccb; /* CAM scsiio ccb */ 1386 u8 cdb_buf[16]; /* Copy of CDB */ 1387 u8 *sns_bbuf; /* Bounce buffer for sense data */ 1388 #define SYM_SNS_BBUF_LEN sizeof(struct scsi_sense_data) 1389 int data_len; /* Total data length */ 1390 int segments; /* Number of SG segments */ 1391 1392 /* 1393 * Miscellaneous status'. 1394 */ 1395 u_char nego_status; /* Negotiation status */ 1396 u_char xerr_status; /* Extended error flags */ 1397 u32 extra_bytes; /* Extraneous bytes transferred */ 1398 1399 /* 1400 * Message areas. 1401 * We prepare a message to be sent after selection. 1402 * We may use a second one if the command is rescheduled 1403 * due to CHECK_CONDITION or COMMAND TERMINATED. 1404 * Contents are IDENTIFY and SIMPLE_TAG. 1405 * While negotiating sync or wide transfer, 1406 * a SDTR or WDTR message is appended. 1407 */ 1408 u_char scsi_smsg [12]; 1409 u_char scsi_smsg2[12]; 1410 1411 /* 1412 * Auto request sense related fields. 1413 */ 1414 u_char sensecmd[6]; /* Request Sense command */ 1415 u_char sv_scsi_status; /* Saved SCSI status */ 1416 u_char sv_xerr_status; /* Saved extended status */ 1417 int sv_resid; /* Saved residual */ 1418 1419 /* 1420 * Map for the DMA of user data. 1421 */ 1422 void *arg; /* Argument for some callback */ 1423 bus_dmamap_t dmamap; /* DMA map for user data */ 1424 u_char dmamapped; 1425 #define SYM_DMA_NONE 0 1426 #define SYM_DMA_READ 1 1427 #define SYM_DMA_WRITE 2 1428 /* 1429 * Other fields. 1430 */ 1431 u32 ccb_ba; /* BUS address of this CCB */ 1432 u_short tag; /* Tag for this transfer */ 1433 /* NO_TAG means no tag */ 1434 u_char target; 1435 u_char lun; 1436 ccb_p link_ccbh; /* Host adapter CCB hash chain */ 1437 SYM_QUEHEAD 1438 link_ccbq; /* Link to free/busy CCB queue */ 1439 u32 startp; /* Initial data pointer */ 1440 int ext_sg; /* Extreme data pointer, used */ 1441 int ext_ofs; /* to calculate the residual. */ 1442 u_char to_abort; /* Want this IO to be aborted */ 1443 }; 1444 1445 #define CCB_BA(cp,lbl) (cp->ccb_ba + offsetof(struct sym_ccb, lbl)) 1446 1447 /* 1448 * Host Control Block 1449 */ 1450 struct sym_hcb { 1451 struct mtx mtx; 1452 1453 /* 1454 * Global headers. 1455 * Due to poorness of addressing capabilities, earlier 1456 * chips (810, 815, 825) copy part of the data structures 1457 * (CCB, TCB and LCB) in fixed areas. 1458 */ 1459 #ifdef SYM_CONF_GENERIC_SUPPORT 1460 struct sym_ccbh ccb_head; 1461 struct sym_tcbh tcb_head; 1462 struct sym_lcbh lcb_head; 1463 #endif 1464 /* 1465 * Idle task and invalid task actions and 1466 * their bus addresses. 1467 */ 1468 struct sym_actscr idletask, notask, bad_itl, bad_itlq; 1469 vm_offset_t idletask_ba, notask_ba, bad_itl_ba, bad_itlq_ba; 1470 1471 /* 1472 * Dummy lun table to protect us against target 1473 * returning bad lun number on reselection. 1474 */ 1475 u32 *badluntbl; /* Table physical address */ 1476 u32 badlun_sa; /* SCRIPT handler BUS address */ 1477 1478 /* 1479 * Bus address of this host control block. 1480 */ 1481 u32 hcb_ba; 1482 1483 /* 1484 * Bit 32-63 of the on-chip RAM bus address in LE format. 1485 * The START_RAM64 script loads the MMRS and MMWS from this 1486 * field. 1487 */ 1488 u32 scr_ram_seg; 1489 1490 /* 1491 * Chip and controller indentification. 1492 */ 1493 device_t device; 1494 1495 /* 1496 * Initial value of some IO register bits. 1497 * These values are assumed to have been set by BIOS, and may 1498 * be used to probe adapter implementation differences. 1499 */ 1500 u_char sv_scntl0, sv_scntl3, sv_dmode, sv_dcntl, sv_ctest3, sv_ctest4, 1501 sv_ctest5, sv_gpcntl, sv_stest2, sv_stest4, sv_scntl4, 1502 sv_stest1; 1503 1504 /* 1505 * Actual initial value of IO register bits used by the 1506 * driver. They are loaded at initialisation according to 1507 * features that are to be enabled/disabled. 1508 */ 1509 u_char rv_scntl0, rv_scntl3, rv_dmode, rv_dcntl, rv_ctest3, rv_ctest4, 1510 rv_ctest5, rv_stest2, rv_ccntl0, rv_ccntl1, rv_scntl4; 1511 1512 /* 1513 * Target data. 1514 */ 1515 #ifdef __amd64__ 1516 struct sym_tcb *target; 1517 #else 1518 struct sym_tcb target[SYM_CONF_MAX_TARGET]; 1519 #endif 1520 1521 /* 1522 * Target control block bus address array used by the SCRIPT 1523 * on reselection. 1524 */ 1525 u32 *targtbl; 1526 u32 targtbl_ba; 1527 1528 /* 1529 * CAM SIM information for this instance. 1530 */ 1531 struct cam_sim *sim; 1532 struct cam_path *path; 1533 1534 /* 1535 * Allocated hardware resources. 1536 */ 1537 struct resource *irq_res; 1538 struct resource *io_res; 1539 struct resource *mmio_res; 1540 struct resource *ram_res; 1541 int ram_id; 1542 void *intr; 1543 1544 /* 1545 * Bus stuff. 1546 * 1547 * My understanding of PCI is that all agents must share the 1548 * same addressing range and model. 1549 * But some hardware architecture guys provide complex and 1550 * brain-deaded stuff that makes shit. 1551 * This driver only support PCI compliant implementations and 1552 * deals with part of the BUS stuff complexity only to fit O/S 1553 * requirements. 1554 */ 1555 1556 /* 1557 * DMA stuff. 1558 */ 1559 bus_dma_tag_t bus_dmat; /* DMA tag from parent BUS */ 1560 bus_dma_tag_t data_dmat; /* DMA tag for user data */ 1561 /* 1562 * BUS addresses of the chip 1563 */ 1564 vm_offset_t mmio_ba; /* MMIO BUS address */ 1565 int mmio_ws; /* MMIO Window size */ 1566 1567 vm_offset_t ram_ba; /* RAM BUS address */ 1568 int ram_ws; /* RAM window size */ 1569 1570 /* 1571 * SCRIPTS virtual and physical bus addresses. 1572 * 'script' is loaded in the on-chip RAM if present. 1573 * 'scripth' stays in main memory for all chips except the 1574 * 53C895A, 53C896 and 53C1010 that provide 8K on-chip RAM. 1575 */ 1576 u_char *scripta0; /* Copies of script and scripth */ 1577 u_char *scriptb0; /* Copies of script and scripth */ 1578 vm_offset_t scripta_ba; /* Actual script and scripth */ 1579 vm_offset_t scriptb_ba; /* bus addresses. */ 1580 vm_offset_t scriptb0_ba; 1581 u_short scripta_sz; /* Actual size of script A */ 1582 u_short scriptb_sz; /* Actual size of script B */ 1583 1584 /* 1585 * Bus addresses, setup and patch methods for 1586 * the selected firmware. 1587 */ 1588 struct sym_fwa_ba fwa_bas; /* Useful SCRIPTA bus addresses */ 1589 struct sym_fwb_ba fwb_bas; /* Useful SCRIPTB bus addresses */ 1590 void (*fw_setup)(hcb_p np, const struct sym_fw *fw); 1591 void (*fw_patch)(hcb_p np); 1592 const char *fw_name; 1593 1594 /* 1595 * General controller parameters and configuration. 1596 */ 1597 u_short device_id; /* PCI device id */ 1598 u_char revision_id; /* PCI device revision id */ 1599 u_int features; /* Chip features map */ 1600 u_char myaddr; /* SCSI id of the adapter */ 1601 u_char maxburst; /* log base 2 of dwords burst */ 1602 u_char maxwide; /* Maximum transfer width */ 1603 u_char minsync; /* Min sync period factor (ST) */ 1604 u_char maxsync; /* Max sync period factor (ST) */ 1605 u_char maxoffs; /* Max scsi offset (ST) */ 1606 u_char minsync_dt; /* Min sync period factor (DT) */ 1607 u_char maxsync_dt; /* Max sync period factor (DT) */ 1608 u_char maxoffs_dt; /* Max scsi offset (DT) */ 1609 u_char multiplier; /* Clock multiplier (1,2,4) */ 1610 u_char clock_divn; /* Number of clock divisors */ 1611 u32 clock_khz; /* SCSI clock frequency in KHz */ 1612 u32 pciclk_khz; /* Estimated PCI clock in KHz */ 1613 /* 1614 * Start queue management. 1615 * It is filled up by the host processor and accessed by the 1616 * SCRIPTS processor in order to start SCSI commands. 1617 */ 1618 volatile /* Prevent code optimizations */ 1619 u32 *squeue; /* Start queue virtual address */ 1620 u32 squeue_ba; /* Start queue BUS address */ 1621 u_short squeueput; /* Next free slot of the queue */ 1622 u_short actccbs; /* Number of allocated CCBs */ 1623 1624 /* 1625 * Command completion queue. 1626 * It is the same size as the start queue to avoid overflow. 1627 */ 1628 u_short dqueueget; /* Next position to scan */ 1629 volatile /* Prevent code optimizations */ 1630 u32 *dqueue; /* Completion (done) queue */ 1631 u32 dqueue_ba; /* Done queue BUS address */ 1632 1633 /* 1634 * Miscellaneous buffers accessed by the scripts-processor. 1635 * They shall be DWORD aligned, because they may be read or 1636 * written with a script command. 1637 */ 1638 u_char msgout[8]; /* Buffer for MESSAGE OUT */ 1639 u_char msgin [8]; /* Buffer for MESSAGE IN */ 1640 u32 lastmsg; /* Last SCSI message sent */ 1641 u_char scratch; /* Scratch for SCSI receive */ 1642 1643 /* 1644 * Miscellaneous configuration and status parameters. 1645 */ 1646 u_char usrflags; /* Miscellaneous user flags */ 1647 u_char scsi_mode; /* Current SCSI BUS mode */ 1648 u_char verbose; /* Verbosity for this controller*/ 1649 u32 cache; /* Used for cache test at init. */ 1650 1651 /* 1652 * CCB lists and queue. 1653 */ 1654 ccb_p ccbh[CCB_HASH_SIZE]; /* CCB hashed by DSA value */ 1655 SYM_QUEHEAD free_ccbq; /* Queue of available CCBs */ 1656 SYM_QUEHEAD busy_ccbq; /* Queue of busy CCBs */ 1657 1658 /* 1659 * During error handling and/or recovery, 1660 * active CCBs that are to be completed with 1661 * error or requeued are moved from the busy_ccbq 1662 * to the comp_ccbq prior to completion. 1663 */ 1664 SYM_QUEHEAD comp_ccbq; 1665 1666 /* 1667 * CAM CCB pending queue. 1668 */ 1669 SYM_QUEHEAD cam_ccbq; 1670 1671 /* 1672 * IMMEDIATE ARBITRATION (IARB) control. 1673 * 1674 * We keep track in 'last_cp' of the last CCB that has been 1675 * queued to the SCRIPTS processor and clear 'last_cp' when 1676 * this CCB completes. If last_cp is not zero at the moment 1677 * we queue a new CCB, we set a flag in 'last_cp' that is 1678 * used by the SCRIPTS as a hint for setting IARB. 1679 * We donnot set more than 'iarb_max' consecutive hints for 1680 * IARB in order to leave devices a chance to reselect. 1681 * By the way, any non zero value of 'iarb_max' is unfair. :) 1682 */ 1683 #ifdef SYM_CONF_IARB_SUPPORT 1684 u_short iarb_max; /* Max. # consecutive IARB hints*/ 1685 u_short iarb_count; /* Actual # of these hints */ 1686 ccb_p last_cp; 1687 #endif 1688 1689 /* 1690 * Command abort handling. 1691 * We need to synchronize tightly with the SCRIPTS 1692 * processor in order to handle things correctly. 1693 */ 1694 u_char abrt_msg[4]; /* Message to send buffer */ 1695 struct sym_tblmove abrt_tbl; /* Table for the MOV of it */ 1696 struct sym_tblsel abrt_sel; /* Sync params for selection */ 1697 u_char istat_sem; /* Tells the chip to stop (SEM) */ 1698 }; 1699 1700 #define HCB_BA(np, lbl) (np->hcb_ba + offsetof(struct sym_hcb, lbl)) 1701 1702 /* 1703 * Return the name of the controller. 1704 */ 1705 static __inline const char *sym_name(hcb_p np) 1706 { 1707 return device_get_nameunit(np->device); 1708 } 1709 1710 /*--------------------------------------------------------------------------*/ 1711 /*------------------------------ FIRMWARES ---------------------------------*/ 1712 /*--------------------------------------------------------------------------*/ 1713 1714 /* 1715 * This stuff will be moved to a separate source file when 1716 * the driver will be broken into several source modules. 1717 */ 1718 1719 /* 1720 * Macros used for all firmwares. 1721 */ 1722 #define SYM_GEN_A(s, label) ((short) offsetof(s, label)), 1723 #define SYM_GEN_B(s, label) ((short) offsetof(s, label)), 1724 #define PADDR_A(label) SYM_GEN_PADDR_A(struct SYM_FWA_SCR, label) 1725 #define PADDR_B(label) SYM_GEN_PADDR_B(struct SYM_FWB_SCR, label) 1726 1727 #ifdef SYM_CONF_GENERIC_SUPPORT 1728 /* 1729 * Allocate firmware #1 script area. 1730 */ 1731 #define SYM_FWA_SCR sym_fw1a_scr 1732 #define SYM_FWB_SCR sym_fw1b_scr 1733 #include <dev/sym/sym_fw1.h> 1734 static const struct sym_fwa_ofs sym_fw1a_ofs = { 1735 SYM_GEN_FW_A(struct SYM_FWA_SCR) 1736 }; 1737 static const struct sym_fwb_ofs sym_fw1b_ofs = { 1738 SYM_GEN_FW_B(struct SYM_FWB_SCR) 1739 }; 1740 #undef SYM_FWA_SCR 1741 #undef SYM_FWB_SCR 1742 #endif /* SYM_CONF_GENERIC_SUPPORT */ 1743 1744 /* 1745 * Allocate firmware #2 script area. 1746 */ 1747 #define SYM_FWA_SCR sym_fw2a_scr 1748 #define SYM_FWB_SCR sym_fw2b_scr 1749 #include <dev/sym/sym_fw2.h> 1750 static const struct sym_fwa_ofs sym_fw2a_ofs = { 1751 SYM_GEN_FW_A(struct SYM_FWA_SCR) 1752 }; 1753 static const struct sym_fwb_ofs sym_fw2b_ofs = { 1754 SYM_GEN_FW_B(struct SYM_FWB_SCR) 1755 SYM_GEN_B(struct SYM_FWB_SCR, start64) 1756 SYM_GEN_B(struct SYM_FWB_SCR, pm_handle) 1757 }; 1758 #undef SYM_FWA_SCR 1759 #undef SYM_FWB_SCR 1760 1761 #undef SYM_GEN_A 1762 #undef SYM_GEN_B 1763 #undef PADDR_A 1764 #undef PADDR_B 1765 1766 #ifdef SYM_CONF_GENERIC_SUPPORT 1767 /* 1768 * Patch routine for firmware #1. 1769 */ 1770 static void 1771 sym_fw1_patch(hcb_p np) 1772 { 1773 struct sym_fw1a_scr *scripta0; 1774 struct sym_fw1b_scr *scriptb0; 1775 1776 scripta0 = (struct sym_fw1a_scr *) np->scripta0; 1777 scriptb0 = (struct sym_fw1b_scr *) np->scriptb0; 1778 1779 /* 1780 * Remove LED support if not needed. 1781 */ 1782 if (!(np->features & FE_LED0)) { 1783 scripta0->idle[0] = cpu_to_scr(SCR_NO_OP); 1784 scripta0->reselected[0] = cpu_to_scr(SCR_NO_OP); 1785 scripta0->start[0] = cpu_to_scr(SCR_NO_OP); 1786 } 1787 1788 #ifdef SYM_CONF_IARB_SUPPORT 1789 /* 1790 * If user does not want to use IMMEDIATE ARBITRATION 1791 * when we are reselected while attempting to arbitrate, 1792 * patch the SCRIPTS accordingly with a SCRIPT NO_OP. 1793 */ 1794 if (!SYM_CONF_SET_IARB_ON_ARB_LOST) 1795 scripta0->ungetjob[0] = cpu_to_scr(SCR_NO_OP); 1796 #endif 1797 /* 1798 * Patch some data in SCRIPTS. 1799 * - start and done queue initial bus address. 1800 * - target bus address table bus address. 1801 */ 1802 scriptb0->startpos[0] = cpu_to_scr(np->squeue_ba); 1803 scriptb0->done_pos[0] = cpu_to_scr(np->dqueue_ba); 1804 scriptb0->targtbl[0] = cpu_to_scr(np->targtbl_ba); 1805 } 1806 #endif /* SYM_CONF_GENERIC_SUPPORT */ 1807 1808 /* 1809 * Patch routine for firmware #2. 1810 */ 1811 static void 1812 sym_fw2_patch(hcb_p np) 1813 { 1814 struct sym_fw2a_scr *scripta0; 1815 struct sym_fw2b_scr *scriptb0; 1816 1817 scripta0 = (struct sym_fw2a_scr *) np->scripta0; 1818 scriptb0 = (struct sym_fw2b_scr *) np->scriptb0; 1819 1820 /* 1821 * Remove LED support if not needed. 1822 */ 1823 if (!(np->features & FE_LED0)) { 1824 scripta0->idle[0] = cpu_to_scr(SCR_NO_OP); 1825 scripta0->reselected[0] = cpu_to_scr(SCR_NO_OP); 1826 scripta0->start[0] = cpu_to_scr(SCR_NO_OP); 1827 } 1828 1829 #ifdef SYM_CONF_IARB_SUPPORT 1830 /* 1831 * If user does not want to use IMMEDIATE ARBITRATION 1832 * when we are reselected while attempting to arbitrate, 1833 * patch the SCRIPTS accordingly with a SCRIPT NO_OP. 1834 */ 1835 if (!SYM_CONF_SET_IARB_ON_ARB_LOST) 1836 scripta0->ungetjob[0] = cpu_to_scr(SCR_NO_OP); 1837 #endif 1838 /* 1839 * Patch some variable in SCRIPTS. 1840 * - start and done queue initial bus address. 1841 * - target bus address table bus address. 1842 */ 1843 scriptb0->startpos[0] = cpu_to_scr(np->squeue_ba); 1844 scriptb0->done_pos[0] = cpu_to_scr(np->dqueue_ba); 1845 scriptb0->targtbl[0] = cpu_to_scr(np->targtbl_ba); 1846 1847 /* 1848 * Remove the load of SCNTL4 on reselection if not a C10. 1849 */ 1850 if (!(np->features & FE_C10)) { 1851 scripta0->resel_scntl4[0] = cpu_to_scr(SCR_NO_OP); 1852 scripta0->resel_scntl4[1] = cpu_to_scr(0); 1853 } 1854 1855 /* 1856 * Remove a couple of work-arounds specific to C1010 if 1857 * they are not desirable. See `sym_fw2.h' for more details. 1858 */ 1859 if (!(np->device_id == PCI_ID_LSI53C1010_2 && 1860 np->revision_id < 0x1 && 1861 np->pciclk_khz < 60000)) { 1862 scripta0->datao_phase[0] = cpu_to_scr(SCR_NO_OP); 1863 scripta0->datao_phase[1] = cpu_to_scr(0); 1864 } 1865 if (!(np->device_id == PCI_ID_LSI53C1010 && 1866 /* np->revision_id < 0xff */ 1)) { 1867 scripta0->sel_done[0] = cpu_to_scr(SCR_NO_OP); 1868 scripta0->sel_done[1] = cpu_to_scr(0); 1869 } 1870 1871 /* 1872 * Patch some other variables in SCRIPTS. 1873 * These ones are loaded by the SCRIPTS processor. 1874 */ 1875 scriptb0->pm0_data_addr[0] = 1876 cpu_to_scr(np->scripta_ba + 1877 offsetof(struct sym_fw2a_scr, pm0_data)); 1878 scriptb0->pm1_data_addr[0] = 1879 cpu_to_scr(np->scripta_ba + 1880 offsetof(struct sym_fw2a_scr, pm1_data)); 1881 } 1882 1883 /* 1884 * Fill the data area in scripts. 1885 * To be done for all firmwares. 1886 */ 1887 static void 1888 sym_fw_fill_data (u32 *in, u32 *out) 1889 { 1890 int i; 1891 1892 for (i = 0; i < SYM_CONF_MAX_SG; i++) { 1893 *in++ = SCR_CHMOV_TBL ^ SCR_DATA_IN; 1894 *in++ = offsetof (struct sym_dsb, data[i]); 1895 *out++ = SCR_CHMOV_TBL ^ SCR_DATA_OUT; 1896 *out++ = offsetof (struct sym_dsb, data[i]); 1897 } 1898 } 1899 1900 /* 1901 * Setup useful script bus addresses. 1902 * To be done for all firmwares. 1903 */ 1904 static void 1905 sym_fw_setup_bus_addresses(hcb_p np, const struct sym_fw *fw) 1906 { 1907 u32 *pa; 1908 const u_short *po; 1909 int i; 1910 1911 /* 1912 * Build the bus address table for script A 1913 * from the script A offset table. 1914 */ 1915 po = (const u_short *) fw->a_ofs; 1916 pa = (u32 *) &np->fwa_bas; 1917 for (i = 0 ; i < sizeof(np->fwa_bas)/sizeof(u32) ; i++) 1918 pa[i] = np->scripta_ba + po[i]; 1919 1920 /* 1921 * Same for script B. 1922 */ 1923 po = (const u_short *) fw->b_ofs; 1924 pa = (u32 *) &np->fwb_bas; 1925 for (i = 0 ; i < sizeof(np->fwb_bas)/sizeof(u32) ; i++) 1926 pa[i] = np->scriptb_ba + po[i]; 1927 } 1928 1929 #ifdef SYM_CONF_GENERIC_SUPPORT 1930 /* 1931 * Setup routine for firmware #1. 1932 */ 1933 static void 1934 sym_fw1_setup(hcb_p np, const struct sym_fw *fw) 1935 { 1936 struct sym_fw1a_scr *scripta0; 1937 1938 scripta0 = (struct sym_fw1a_scr *) np->scripta0; 1939 1940 /* 1941 * Fill variable parts in scripts. 1942 */ 1943 sym_fw_fill_data(scripta0->data_in, scripta0->data_out); 1944 1945 /* 1946 * Setup bus addresses used from the C code.. 1947 */ 1948 sym_fw_setup_bus_addresses(np, fw); 1949 } 1950 #endif /* SYM_CONF_GENERIC_SUPPORT */ 1951 1952 /* 1953 * Setup routine for firmware #2. 1954 */ 1955 static void 1956 sym_fw2_setup(hcb_p np, const struct sym_fw *fw) 1957 { 1958 struct sym_fw2a_scr *scripta0; 1959 1960 scripta0 = (struct sym_fw2a_scr *) np->scripta0; 1961 1962 /* 1963 * Fill variable parts in scripts. 1964 */ 1965 sym_fw_fill_data(scripta0->data_in, scripta0->data_out); 1966 1967 /* 1968 * Setup bus addresses used from the C code.. 1969 */ 1970 sym_fw_setup_bus_addresses(np, fw); 1971 } 1972 1973 /* 1974 * Allocate firmware descriptors. 1975 */ 1976 #ifdef SYM_CONF_GENERIC_SUPPORT 1977 static const struct sym_fw sym_fw1 = SYM_FW_ENTRY(sym_fw1, "NCR-generic"); 1978 #endif /* SYM_CONF_GENERIC_SUPPORT */ 1979 static const struct sym_fw sym_fw2 = SYM_FW_ENTRY(sym_fw2, "LOAD/STORE-based"); 1980 1981 /* 1982 * Find the most appropriate firmware for a chip. 1983 */ 1984 static const struct sym_fw * 1985 sym_find_firmware(const struct sym_pci_chip *chip) 1986 { 1987 if (chip->features & FE_LDSTR) 1988 return &sym_fw2; 1989 #ifdef SYM_CONF_GENERIC_SUPPORT 1990 else if (!(chip->features & (FE_PFEN|FE_NOPM|FE_DAC))) 1991 return &sym_fw1; 1992 #endif 1993 else 1994 return NULL; 1995 } 1996 1997 /* 1998 * Bind a script to physical addresses. 1999 */ 2000 static void sym_fw_bind_script (hcb_p np, u32 *start, int len) 2001 { 2002 u32 opcode, new, old, tmp1, tmp2; 2003 u32 *end, *cur; 2004 int relocs; 2005 2006 cur = start; 2007 end = start + len/4; 2008 2009 while (cur < end) { 2010 2011 opcode = *cur; 2012 2013 /* 2014 * If we forget to change the length 2015 * in scripts, a field will be 2016 * padded with 0. This is an illegal 2017 * command. 2018 */ 2019 if (opcode == 0) { 2020 printf ("%s: ERROR0 IN SCRIPT at %d.\n", 2021 sym_name(np), (int) (cur-start)); 2022 MDELAY (10000); 2023 ++cur; 2024 continue; 2025 } 2026 2027 /* 2028 * We use the bogus value 0xf00ff00f ;-) 2029 * to reserve data area in SCRIPTS. 2030 */ 2031 if (opcode == SCR_DATA_ZERO) { 2032 *cur++ = 0; 2033 continue; 2034 } 2035 2036 if (DEBUG_FLAGS & DEBUG_SCRIPT) 2037 printf ("%d: <%x>\n", (int) (cur-start), 2038 (unsigned)opcode); 2039 2040 /* 2041 * We don't have to decode ALL commands 2042 */ 2043 switch (opcode >> 28) { 2044 case 0xf: 2045 /* 2046 * LOAD / STORE DSA relative, don't relocate. 2047 */ 2048 relocs = 0; 2049 break; 2050 case 0xe: 2051 /* 2052 * LOAD / STORE absolute. 2053 */ 2054 relocs = 1; 2055 break; 2056 case 0xc: 2057 /* 2058 * COPY has TWO arguments. 2059 */ 2060 relocs = 2; 2061 tmp1 = cur[1]; 2062 tmp2 = cur[2]; 2063 if ((tmp1 ^ tmp2) & 3) { 2064 printf ("%s: ERROR1 IN SCRIPT at %d.\n", 2065 sym_name(np), (int) (cur-start)); 2066 MDELAY (10000); 2067 } 2068 /* 2069 * If PREFETCH feature not enabled, remove 2070 * the NO FLUSH bit if present. 2071 */ 2072 if ((opcode & SCR_NO_FLUSH) && 2073 !(np->features & FE_PFEN)) { 2074 opcode = (opcode & ~SCR_NO_FLUSH); 2075 } 2076 break; 2077 case 0x0: 2078 /* 2079 * MOVE/CHMOV (absolute address) 2080 */ 2081 if (!(np->features & FE_WIDE)) 2082 opcode = (opcode | OPC_MOVE); 2083 relocs = 1; 2084 break; 2085 case 0x1: 2086 /* 2087 * MOVE/CHMOV (table indirect) 2088 */ 2089 if (!(np->features & FE_WIDE)) 2090 opcode = (opcode | OPC_MOVE); 2091 relocs = 0; 2092 break; 2093 case 0x8: 2094 /* 2095 * JUMP / CALL 2096 * dont't relocate if relative :-) 2097 */ 2098 if (opcode & 0x00800000) 2099 relocs = 0; 2100 else if ((opcode & 0xf8400000) == 0x80400000)/*JUMP64*/ 2101 relocs = 2; 2102 else 2103 relocs = 1; 2104 break; 2105 case 0x4: 2106 case 0x5: 2107 case 0x6: 2108 case 0x7: 2109 relocs = 1; 2110 break; 2111 default: 2112 relocs = 0; 2113 break; 2114 } 2115 2116 /* 2117 * Scriptify:) the opcode. 2118 */ 2119 *cur++ = cpu_to_scr(opcode); 2120 2121 /* 2122 * If no relocation, assume 1 argument 2123 * and just scriptize:) it. 2124 */ 2125 if (!relocs) { 2126 *cur = cpu_to_scr(*cur); 2127 ++cur; 2128 continue; 2129 } 2130 2131 /* 2132 * Otherwise performs all needed relocations. 2133 */ 2134 while (relocs--) { 2135 old = *cur; 2136 2137 switch (old & RELOC_MASK) { 2138 case RELOC_REGISTER: 2139 new = (old & ~RELOC_MASK) + np->mmio_ba; 2140 break; 2141 case RELOC_LABEL_A: 2142 new = (old & ~RELOC_MASK) + np->scripta_ba; 2143 break; 2144 case RELOC_LABEL_B: 2145 new = (old & ~RELOC_MASK) + np->scriptb_ba; 2146 break; 2147 case RELOC_SOFTC: 2148 new = (old & ~RELOC_MASK) + np->hcb_ba; 2149 break; 2150 case 0: 2151 /* 2152 * Don't relocate a 0 address. 2153 * They are mostly used for patched or 2154 * script self-modified areas. 2155 */ 2156 if (old == 0) { 2157 new = old; 2158 break; 2159 } 2160 /* fall through */ 2161 default: 2162 new = 0; 2163 panic("sym_fw_bind_script: " 2164 "weird relocation %x\n", old); 2165 break; 2166 } 2167 2168 *cur++ = cpu_to_scr(new); 2169 } 2170 } 2171 } 2172 2173 /*---------------------------------------------------------------------------*/ 2174 /*--------------------------- END OF FIRMWARES -----------------------------*/ 2175 /*---------------------------------------------------------------------------*/ 2176 2177 /* 2178 * Function prototypes. 2179 */ 2180 static void sym_save_initial_setting (hcb_p np); 2181 static int sym_prepare_setting (hcb_p np, struct sym_nvram *nvram); 2182 static int sym_prepare_nego (hcb_p np, ccb_p cp, int nego, u_char *msgptr); 2183 static void sym_put_start_queue (hcb_p np, ccb_p cp); 2184 static void sym_chip_reset (hcb_p np); 2185 static void sym_soft_reset (hcb_p np); 2186 static void sym_start_reset (hcb_p np); 2187 static int sym_reset_scsi_bus (hcb_p np, int enab_int); 2188 static int sym_wakeup_done (hcb_p np); 2189 static void sym_flush_busy_queue (hcb_p np, int cam_status); 2190 static void sym_flush_comp_queue (hcb_p np, int cam_status); 2191 static void sym_init (hcb_p np, int reason); 2192 static int sym_getsync(hcb_p np, u_char dt, u_char sfac, u_char *divp, 2193 u_char *fakp); 2194 static void sym_setsync (hcb_p np, ccb_p cp, u_char ofs, u_char per, 2195 u_char div, u_char fak); 2196 static void sym_setwide (hcb_p np, ccb_p cp, u_char wide); 2197 static void sym_setpprot(hcb_p np, ccb_p cp, u_char dt, u_char ofs, 2198 u_char per, u_char wide, u_char div, u_char fak); 2199 static void sym_settrans(hcb_p np, ccb_p cp, u_char dt, u_char ofs, 2200 u_char per, u_char wide, u_char div, u_char fak); 2201 static void sym_log_hard_error (hcb_p np, u_short sist, u_char dstat); 2202 static void sym_intr (void *arg); 2203 static void sym_poll (struct cam_sim *sim); 2204 static void sym_recover_scsi_int (hcb_p np, u_char hsts); 2205 static void sym_int_sto (hcb_p np); 2206 static void sym_int_udc (hcb_p np); 2207 static void sym_int_sbmc (hcb_p np); 2208 static void sym_int_par (hcb_p np, u_short sist); 2209 static void sym_int_ma (hcb_p np); 2210 static int sym_dequeue_from_squeue(hcb_p np, int i, int target, int lun, 2211 int task); 2212 static void sym_sir_bad_scsi_status (hcb_p np, ccb_p cp); 2213 static int sym_clear_tasks (hcb_p np, int status, int targ, int lun, int task); 2214 static void sym_sir_task_recovery (hcb_p np, int num); 2215 static int sym_evaluate_dp (hcb_p np, ccb_p cp, u32 scr, int *ofs); 2216 static void sym_modify_dp(hcb_p np, ccb_p cp, int ofs); 2217 static int sym_compute_residual (hcb_p np, ccb_p cp); 2218 static int sym_show_msg (u_char * msg); 2219 static void sym_print_msg (ccb_p cp, char *label, u_char *msg); 2220 static void sym_sync_nego (hcb_p np, tcb_p tp, ccb_p cp); 2221 static void sym_ppr_nego (hcb_p np, tcb_p tp, ccb_p cp); 2222 static void sym_wide_nego (hcb_p np, tcb_p tp, ccb_p cp); 2223 static void sym_nego_default (hcb_p np, tcb_p tp, ccb_p cp); 2224 static void sym_nego_rejected (hcb_p np, tcb_p tp, ccb_p cp); 2225 static void sym_int_sir (hcb_p np); 2226 static void sym_free_ccb (hcb_p np, ccb_p cp); 2227 static ccb_p sym_get_ccb (hcb_p np, u_char tn, u_char ln, u_char tag_order); 2228 static ccb_p sym_alloc_ccb (hcb_p np); 2229 static ccb_p sym_ccb_from_dsa (hcb_p np, u32 dsa); 2230 static lcb_p sym_alloc_lcb (hcb_p np, u_char tn, u_char ln); 2231 static void sym_alloc_lcb_tags (hcb_p np, u_char tn, u_char ln); 2232 static int sym_snooptest (hcb_p np); 2233 static void sym_selectclock(hcb_p np, u_char scntl3); 2234 static void sym_getclock (hcb_p np, int mult); 2235 static int sym_getpciclock (hcb_p np); 2236 static void sym_complete_ok (hcb_p np, ccb_p cp); 2237 static void sym_complete_error (hcb_p np, ccb_p cp); 2238 static void sym_callout (void *arg); 2239 static int sym_abort_scsiio (hcb_p np, union ccb *ccb, int timed_out); 2240 static void sym_reset_dev (hcb_p np, union ccb *ccb); 2241 static void sym_action (struct cam_sim *sim, union ccb *ccb); 2242 static int sym_setup_cdb (hcb_p np, struct ccb_scsiio *csio, ccb_p cp); 2243 static void sym_setup_data_and_start (hcb_p np, struct ccb_scsiio *csio, 2244 ccb_p cp); 2245 static int sym_fast_scatter_sg_physical(hcb_p np, ccb_p cp, 2246 bus_dma_segment_t *psegs, int nsegs); 2247 static int sym_scatter_sg_physical (hcb_p np, ccb_p cp, 2248 bus_dma_segment_t *psegs, int nsegs); 2249 static void sym_action2 (struct cam_sim *sim, union ccb *ccb); 2250 static void sym_update_trans(hcb_p np, struct sym_trans *tip, 2251 struct ccb_trans_settings *cts); 2252 static void sym_update_dflags(hcb_p np, u_char *flags, 2253 struct ccb_trans_settings *cts); 2254 2255 static const struct sym_pci_chip *sym_find_pci_chip (device_t dev); 2256 static int sym_pci_probe (device_t dev); 2257 static int sym_pci_attach (device_t dev); 2258 2259 static void sym_pci_free (hcb_p np); 2260 static int sym_cam_attach (hcb_p np); 2261 static void sym_cam_free (hcb_p np); 2262 2263 static void sym_nvram_setup_host (hcb_p np, struct sym_nvram *nvram); 2264 static void sym_nvram_setup_target (hcb_p np, int targ, struct sym_nvram *nvp); 2265 static int sym_read_nvram (hcb_p np, struct sym_nvram *nvp); 2266 2267 /* 2268 * Print something which allows to retrieve the controller type, 2269 * unit, target, lun concerned by a kernel message. 2270 */ 2271 static void PRINT_TARGET (hcb_p np, int target) 2272 { 2273 printf ("%s:%d:", sym_name(np), target); 2274 } 2275 2276 static void PRINT_LUN(hcb_p np, int target, int lun) 2277 { 2278 printf ("%s:%d:%d:", sym_name(np), target, lun); 2279 } 2280 2281 static void PRINT_ADDR (ccb_p cp) 2282 { 2283 if (cp && cp->cam_ccb) 2284 xpt_print_path(cp->cam_ccb->ccb_h.path); 2285 } 2286 2287 /* 2288 * Take into account this ccb in the freeze count. 2289 */ 2290 static void sym_freeze_cam_ccb(union ccb *ccb) 2291 { 2292 if (!(ccb->ccb_h.flags & CAM_DEV_QFRZDIS)) { 2293 if (!(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 2294 ccb->ccb_h.status |= CAM_DEV_QFRZN; 2295 xpt_freeze_devq(ccb->ccb_h.path, 1); 2296 } 2297 } 2298 } 2299 2300 /* 2301 * Set the status field of a CAM CCB. 2302 */ 2303 static __inline void sym_set_cam_status(union ccb *ccb, cam_status status) 2304 { 2305 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2306 ccb->ccb_h.status |= status; 2307 } 2308 2309 /* 2310 * Get the status field of a CAM CCB. 2311 */ 2312 static __inline int sym_get_cam_status(union ccb *ccb) 2313 { 2314 return ccb->ccb_h.status & CAM_STATUS_MASK; 2315 } 2316 2317 /* 2318 * Enqueue a CAM CCB. 2319 */ 2320 static void sym_enqueue_cam_ccb(ccb_p cp) 2321 { 2322 hcb_p np; 2323 union ccb *ccb; 2324 2325 ccb = cp->cam_ccb; 2326 np = (hcb_p) cp->arg; 2327 2328 assert(!(ccb->ccb_h.status & CAM_SIM_QUEUED)); 2329 ccb->ccb_h.status = CAM_REQ_INPROG; 2330 2331 callout_reset_sbt(&cp->ch, SBT_1MS * ccb->ccb_h.timeout, 0, sym_callout, 2332 (caddr_t)ccb, 0); 2333 ccb->ccb_h.status |= CAM_SIM_QUEUED; 2334 ccb->ccb_h.sym_hcb_ptr = np; 2335 2336 sym_insque_tail(sym_qptr(&ccb->ccb_h.sim_links), &np->cam_ccbq); 2337 } 2338 2339 /* 2340 * Complete a pending CAM CCB. 2341 */ 2342 2343 static void sym_xpt_done(hcb_p np, union ccb *ccb, ccb_p cp) 2344 { 2345 2346 SYM_LOCK_ASSERT(MA_OWNED); 2347 2348 if (ccb->ccb_h.status & CAM_SIM_QUEUED) { 2349 callout_stop(&cp->ch); 2350 sym_remque(sym_qptr(&ccb->ccb_h.sim_links)); 2351 ccb->ccb_h.status &= ~CAM_SIM_QUEUED; 2352 ccb->ccb_h.sym_hcb_ptr = NULL; 2353 } 2354 xpt_done(ccb); 2355 } 2356 2357 static void sym_xpt_done2(hcb_p np, union ccb *ccb, int cam_status) 2358 { 2359 2360 SYM_LOCK_ASSERT(MA_OWNED); 2361 2362 sym_set_cam_status(ccb, cam_status); 2363 xpt_done(ccb); 2364 } 2365 2366 /* 2367 * SYMBIOS chip clock divisor table. 2368 * 2369 * Divisors are multiplied by 10,000,000 in order to make 2370 * calculations more simple. 2371 */ 2372 #define _5M 5000000 2373 static const u32 div_10M[] = 2374 {2*_5M, 3*_5M, 4*_5M, 6*_5M, 8*_5M, 12*_5M, 16*_5M}; 2375 2376 /* 2377 * SYMBIOS chips allow burst lengths of 2, 4, 8, 16, 32, 64, 2378 * 128 transfers. All chips support at least 16 transfers 2379 * bursts. The 825A, 875 and 895 chips support bursts of up 2380 * to 128 transfers and the 895A and 896 support bursts of up 2381 * to 64 transfers. All other chips support up to 16 2382 * transfers bursts. 2383 * 2384 * For PCI 32 bit data transfers each transfer is a DWORD. 2385 * It is a QUADWORD (8 bytes) for PCI 64 bit data transfers. 2386 * 2387 * We use log base 2 (burst length) as internal code, with 2388 * value 0 meaning "burst disabled". 2389 */ 2390 2391 /* 2392 * Burst length from burst code. 2393 */ 2394 #define burst_length(bc) (!(bc))? 0 : 1 << (bc) 2395 2396 /* 2397 * Burst code from io register bits. 2398 */ 2399 #define burst_code(dmode, ctest4, ctest5) \ 2400 (ctest4) & 0x80? 0 : (((dmode) & 0xc0) >> 6) + ((ctest5) & 0x04) + 1 2401 2402 /* 2403 * Set initial io register bits from burst code. 2404 */ 2405 static __inline void sym_init_burst(hcb_p np, u_char bc) 2406 { 2407 np->rv_ctest4 &= ~0x80; 2408 np->rv_dmode &= ~(0x3 << 6); 2409 np->rv_ctest5 &= ~0x4; 2410 2411 if (!bc) { 2412 np->rv_ctest4 |= 0x80; 2413 } 2414 else { 2415 --bc; 2416 np->rv_dmode |= ((bc & 0x3) << 6); 2417 np->rv_ctest5 |= (bc & 0x4); 2418 } 2419 } 2420 2421 /* 2422 * Print out the list of targets that have some flag disabled by user. 2423 */ 2424 static void sym_print_targets_flag(hcb_p np, int mask, char *msg) 2425 { 2426 int cnt; 2427 int i; 2428 2429 for (cnt = 0, i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) { 2430 if (i == np->myaddr) 2431 continue; 2432 if (np->target[i].usrflags & mask) { 2433 if (!cnt++) 2434 printf("%s: %s disabled for targets", 2435 sym_name(np), msg); 2436 printf(" %d", i); 2437 } 2438 } 2439 if (cnt) 2440 printf(".\n"); 2441 } 2442 2443 /* 2444 * Save initial settings of some IO registers. 2445 * Assumed to have been set by BIOS. 2446 * We cannot reset the chip prior to reading the 2447 * IO registers, since informations will be lost. 2448 * Since the SCRIPTS processor may be running, this 2449 * is not safe on paper, but it seems to work quite 2450 * well. :) 2451 */ 2452 static void sym_save_initial_setting (hcb_p np) 2453 { 2454 np->sv_scntl0 = INB(nc_scntl0) & 0x0a; 2455 np->sv_scntl3 = INB(nc_scntl3) & 0x07; 2456 np->sv_dmode = INB(nc_dmode) & 0xce; 2457 np->sv_dcntl = INB(nc_dcntl) & 0xa8; 2458 np->sv_ctest3 = INB(nc_ctest3) & 0x01; 2459 np->sv_ctest4 = INB(nc_ctest4) & 0x80; 2460 np->sv_gpcntl = INB(nc_gpcntl); 2461 np->sv_stest1 = INB(nc_stest1); 2462 np->sv_stest2 = INB(nc_stest2) & 0x20; 2463 np->sv_stest4 = INB(nc_stest4); 2464 if (np->features & FE_C10) { /* Always large DMA fifo + ultra3 */ 2465 np->sv_scntl4 = INB(nc_scntl4); 2466 np->sv_ctest5 = INB(nc_ctest5) & 0x04; 2467 } 2468 else 2469 np->sv_ctest5 = INB(nc_ctest5) & 0x24; 2470 } 2471 2472 /* 2473 * Prepare io register values used by sym_init() according 2474 * to selected and supported features. 2475 */ 2476 static int sym_prepare_setting(hcb_p np, struct sym_nvram *nvram) 2477 { 2478 u_char burst_max; 2479 u32 period; 2480 int i; 2481 2482 /* 2483 * Wide ? 2484 */ 2485 np->maxwide = (np->features & FE_WIDE)? 1 : 0; 2486 2487 /* 2488 * Get the frequency of the chip's clock. 2489 */ 2490 if (np->features & FE_QUAD) 2491 np->multiplier = 4; 2492 else if (np->features & FE_DBLR) 2493 np->multiplier = 2; 2494 else 2495 np->multiplier = 1; 2496 2497 np->clock_khz = (np->features & FE_CLK80)? 80000 : 40000; 2498 np->clock_khz *= np->multiplier; 2499 2500 if (np->clock_khz != 40000) 2501 sym_getclock(np, np->multiplier); 2502 2503 /* 2504 * Divisor to be used for async (timer pre-scaler). 2505 */ 2506 i = np->clock_divn - 1; 2507 while (--i >= 0) { 2508 if (10ul * SYM_CONF_MIN_ASYNC * np->clock_khz > div_10M[i]) { 2509 ++i; 2510 break; 2511 } 2512 } 2513 np->rv_scntl3 = i+1; 2514 2515 /* 2516 * The C1010 uses hardwired divisors for async. 2517 * So, we just throw away, the async. divisor.:-) 2518 */ 2519 if (np->features & FE_C10) 2520 np->rv_scntl3 = 0; 2521 2522 /* 2523 * Minimum synchronous period factor supported by the chip. 2524 * Btw, 'period' is in tenths of nanoseconds. 2525 */ 2526 period = howmany(4 * div_10M[0], np->clock_khz); 2527 if (period <= 250) np->minsync = 10; 2528 else if (period <= 303) np->minsync = 11; 2529 else if (period <= 500) np->minsync = 12; 2530 else np->minsync = howmany(period, 40); 2531 2532 /* 2533 * Check against chip SCSI standard support (SCSI-2,ULTRA,ULTRA2). 2534 */ 2535 if (np->minsync < 25 && 2536 !(np->features & (FE_ULTRA|FE_ULTRA2|FE_ULTRA3))) 2537 np->minsync = 25; 2538 else if (np->minsync < 12 && 2539 !(np->features & (FE_ULTRA2|FE_ULTRA3))) 2540 np->minsync = 12; 2541 2542 /* 2543 * Maximum synchronous period factor supported by the chip. 2544 */ 2545 period = (11 * div_10M[np->clock_divn - 1]) / (4 * np->clock_khz); 2546 np->maxsync = period > 2540 ? 254 : period / 10; 2547 2548 /* 2549 * If chip is a C1010, guess the sync limits in DT mode. 2550 */ 2551 if ((np->features & (FE_C10|FE_ULTRA3)) == (FE_C10|FE_ULTRA3)) { 2552 if (np->clock_khz == 160000) { 2553 np->minsync_dt = 9; 2554 np->maxsync_dt = 50; 2555 np->maxoffs_dt = 62; 2556 } 2557 } 2558 2559 /* 2560 * 64 bit addressing (895A/896/1010) ? 2561 */ 2562 if (np->features & FE_DAC) 2563 #ifdef __LP64__ 2564 np->rv_ccntl1 |= (XTIMOD | EXTIBMV); 2565 #else 2566 np->rv_ccntl1 |= (DDAC); 2567 #endif 2568 2569 /* 2570 * Phase mismatch handled by SCRIPTS (895A/896/1010) ? 2571 */ 2572 if (np->features & FE_NOPM) 2573 np->rv_ccntl0 |= (ENPMJ); 2574 2575 /* 2576 * C1010 Errata. 2577 * In dual channel mode, contention occurs if internal cycles 2578 * are used. Disable internal cycles. 2579 */ 2580 if (np->device_id == PCI_ID_LSI53C1010 && 2581 np->revision_id < 0x2) 2582 np->rv_ccntl0 |= DILS; 2583 2584 /* 2585 * Select burst length (dwords) 2586 */ 2587 burst_max = SYM_SETUP_BURST_ORDER; 2588 if (burst_max == 255) 2589 burst_max = burst_code(np->sv_dmode, np->sv_ctest4, 2590 np->sv_ctest5); 2591 if (burst_max > 7) 2592 burst_max = 7; 2593 if (burst_max > np->maxburst) 2594 burst_max = np->maxburst; 2595 2596 /* 2597 * DEL 352 - 53C810 Rev x11 - Part Number 609-0392140 - ITEM 2. 2598 * This chip and the 860 Rev 1 may wrongly use PCI cache line 2599 * based transactions on LOAD/STORE instructions. So we have 2600 * to prevent these chips from using such PCI transactions in 2601 * this driver. The generic ncr driver that does not use 2602 * LOAD/STORE instructions does not need this work-around. 2603 */ 2604 if ((np->device_id == PCI_ID_SYM53C810 && 2605 np->revision_id >= 0x10 && np->revision_id <= 0x11) || 2606 (np->device_id == PCI_ID_SYM53C860 && 2607 np->revision_id <= 0x1)) 2608 np->features &= ~(FE_WRIE|FE_ERL|FE_ERMP); 2609 2610 /* 2611 * Select all supported special features. 2612 * If we are using on-board RAM for scripts, prefetch (PFEN) 2613 * does not help, but burst op fetch (BOF) does. 2614 * Disabling PFEN makes sure BOF will be used. 2615 */ 2616 if (np->features & FE_ERL) 2617 np->rv_dmode |= ERL; /* Enable Read Line */ 2618 if (np->features & FE_BOF) 2619 np->rv_dmode |= BOF; /* Burst Opcode Fetch */ 2620 if (np->features & FE_ERMP) 2621 np->rv_dmode |= ERMP; /* Enable Read Multiple */ 2622 #if 1 2623 if ((np->features & FE_PFEN) && !np->ram_ba) 2624 #else 2625 if (np->features & FE_PFEN) 2626 #endif 2627 np->rv_dcntl |= PFEN; /* Prefetch Enable */ 2628 if (np->features & FE_CLSE) 2629 np->rv_dcntl |= CLSE; /* Cache Line Size Enable */ 2630 if (np->features & FE_WRIE) 2631 np->rv_ctest3 |= WRIE; /* Write and Invalidate */ 2632 if (np->features & FE_DFS) 2633 np->rv_ctest5 |= DFS; /* Dma Fifo Size */ 2634 2635 /* 2636 * Select some other 2637 */ 2638 if (SYM_SETUP_PCI_PARITY) 2639 np->rv_ctest4 |= MPEE; /* Master parity checking */ 2640 if (SYM_SETUP_SCSI_PARITY) 2641 np->rv_scntl0 |= 0x0a; /* full arb., ena parity, par->ATN */ 2642 2643 /* 2644 * Get parity checking, host ID and verbose mode from NVRAM 2645 */ 2646 np->myaddr = 255; 2647 sym_nvram_setup_host (np, nvram); 2648 2649 /* 2650 * Get SCSI addr of host adapter (set by bios?). 2651 */ 2652 if (np->myaddr == 255) { 2653 np->myaddr = INB(nc_scid) & 0x07; 2654 if (!np->myaddr) 2655 np->myaddr = SYM_SETUP_HOST_ID; 2656 } 2657 2658 /* 2659 * Prepare initial io register bits for burst length 2660 */ 2661 sym_init_burst(np, burst_max); 2662 2663 /* 2664 * Set SCSI BUS mode. 2665 * - LVD capable chips (895/895A/896/1010) report the 2666 * current BUS mode through the STEST4 IO register. 2667 * - For previous generation chips (825/825A/875), 2668 * user has to tell us how to check against HVD, 2669 * since a 100% safe algorithm is not possible. 2670 */ 2671 np->scsi_mode = SMODE_SE; 2672 if (np->features & (FE_ULTRA2|FE_ULTRA3)) 2673 np->scsi_mode = (np->sv_stest4 & SMODE); 2674 else if (np->features & FE_DIFF) { 2675 if (SYM_SETUP_SCSI_DIFF == 1) { 2676 if (np->sv_scntl3) { 2677 if (np->sv_stest2 & 0x20) 2678 np->scsi_mode = SMODE_HVD; 2679 } 2680 else if (nvram->type == SYM_SYMBIOS_NVRAM) { 2681 if (!(INB(nc_gpreg) & 0x08)) 2682 np->scsi_mode = SMODE_HVD; 2683 } 2684 } 2685 else if (SYM_SETUP_SCSI_DIFF == 2) 2686 np->scsi_mode = SMODE_HVD; 2687 } 2688 if (np->scsi_mode == SMODE_HVD) 2689 np->rv_stest2 |= 0x20; 2690 2691 /* 2692 * Set LED support from SCRIPTS. 2693 * Ignore this feature for boards known to use a 2694 * specific GPIO wiring and for the 895A, 896 2695 * and 1010 that drive the LED directly. 2696 */ 2697 if ((SYM_SETUP_SCSI_LED || 2698 (nvram->type == SYM_SYMBIOS_NVRAM || 2699 (nvram->type == SYM_TEKRAM_NVRAM && 2700 np->device_id == PCI_ID_SYM53C895))) && 2701 !(np->features & FE_LEDC) && !(np->sv_gpcntl & 0x01)) 2702 np->features |= FE_LED0; 2703 2704 /* 2705 * Set irq mode. 2706 */ 2707 switch(SYM_SETUP_IRQ_MODE & 3) { 2708 case 2: 2709 np->rv_dcntl |= IRQM; 2710 break; 2711 case 1: 2712 np->rv_dcntl |= (np->sv_dcntl & IRQM); 2713 break; 2714 default: 2715 break; 2716 } 2717 2718 /* 2719 * Configure targets according to driver setup. 2720 * If NVRAM present get targets setup from NVRAM. 2721 */ 2722 for (i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) { 2723 tcb_p tp = &np->target[i]; 2724 2725 tp->tinfo.user.scsi_version = tp->tinfo.current.scsi_version= 2; 2726 tp->tinfo.user.spi_version = tp->tinfo.current.spi_version = 2; 2727 tp->tinfo.user.period = np->minsync; 2728 if (np->features & FE_ULTRA3) 2729 tp->tinfo.user.period = np->minsync_dt; 2730 tp->tinfo.user.offset = np->maxoffs; 2731 tp->tinfo.user.width = np->maxwide ? BUS_16_BIT : BUS_8_BIT; 2732 tp->usrflags |= (SYM_DISC_ENABLED | SYM_TAGS_ENABLED); 2733 tp->usrtags = SYM_SETUP_MAX_TAG; 2734 2735 sym_nvram_setup_target (np, i, nvram); 2736 2737 /* 2738 * For now, guess PPR/DT support from the period 2739 * and BUS width. 2740 */ 2741 if (np->features & FE_ULTRA3) { 2742 if (tp->tinfo.user.period <= 9 && 2743 tp->tinfo.user.width == BUS_16_BIT) { 2744 tp->tinfo.user.options |= PPR_OPT_DT; 2745 tp->tinfo.user.offset = np->maxoffs_dt; 2746 tp->tinfo.user.spi_version = 3; 2747 } 2748 } 2749 2750 if (!tp->usrtags) 2751 tp->usrflags &= ~SYM_TAGS_ENABLED; 2752 } 2753 2754 /* 2755 * Let user know about the settings. 2756 */ 2757 i = nvram->type; 2758 printf("%s: %s NVRAM, ID %d, Fast-%d, %s, %s\n", sym_name(np), 2759 i == SYM_SYMBIOS_NVRAM ? "Symbios" : 2760 (i == SYM_TEKRAM_NVRAM ? "Tekram" : "No"), 2761 np->myaddr, 2762 (np->features & FE_ULTRA3) ? 80 : 2763 (np->features & FE_ULTRA2) ? 40 : 2764 (np->features & FE_ULTRA) ? 20 : 10, 2765 sym_scsi_bus_mode(np->scsi_mode), 2766 (np->rv_scntl0 & 0xa) ? "parity checking" : "NO parity"); 2767 /* 2768 * Tell him more on demand. 2769 */ 2770 if (sym_verbose) { 2771 printf("%s: %s IRQ line driver%s\n", 2772 sym_name(np), 2773 np->rv_dcntl & IRQM ? "totem pole" : "open drain", 2774 np->ram_ba ? ", using on-chip SRAM" : ""); 2775 printf("%s: using %s firmware.\n", sym_name(np), np->fw_name); 2776 if (np->features & FE_NOPM) 2777 printf("%s: handling phase mismatch from SCRIPTS.\n", 2778 sym_name(np)); 2779 } 2780 /* 2781 * And still more. 2782 */ 2783 if (sym_verbose > 1) { 2784 printf ("%s: initial SCNTL3/DMODE/DCNTL/CTEST3/4/5 = " 2785 "(hex) %02x/%02x/%02x/%02x/%02x/%02x\n", 2786 sym_name(np), np->sv_scntl3, np->sv_dmode, np->sv_dcntl, 2787 np->sv_ctest3, np->sv_ctest4, np->sv_ctest5); 2788 2789 printf ("%s: final SCNTL3/DMODE/DCNTL/CTEST3/4/5 = " 2790 "(hex) %02x/%02x/%02x/%02x/%02x/%02x\n", 2791 sym_name(np), np->rv_scntl3, np->rv_dmode, np->rv_dcntl, 2792 np->rv_ctest3, np->rv_ctest4, np->rv_ctest5); 2793 } 2794 /* 2795 * Let user be aware of targets that have some disable flags set. 2796 */ 2797 sym_print_targets_flag(np, SYM_SCAN_BOOT_DISABLED, "SCAN AT BOOT"); 2798 if (sym_verbose) 2799 sym_print_targets_flag(np, SYM_SCAN_LUNS_DISABLED, 2800 "SCAN FOR LUNS"); 2801 2802 return 0; 2803 } 2804 2805 /* 2806 * Prepare the next negotiation message if needed. 2807 * 2808 * Fill in the part of message buffer that contains the 2809 * negotiation and the nego_status field of the CCB. 2810 * Returns the size of the message in bytes. 2811 */ 2812 static int sym_prepare_nego(hcb_p np, ccb_p cp, int nego, u_char *msgptr) 2813 { 2814 tcb_p tp = &np->target[cp->target]; 2815 int msglen = 0; 2816 2817 /* 2818 * Early C1010 chips need a work-around for DT 2819 * data transfer to work. 2820 */ 2821 if (!(np->features & FE_U3EN)) 2822 tp->tinfo.goal.options = 0; 2823 /* 2824 * negotiate using PPR ? 2825 */ 2826 if (tp->tinfo.goal.options & PPR_OPT_MASK) 2827 nego = NS_PPR; 2828 /* 2829 * negotiate wide transfers ? 2830 */ 2831 else if (tp->tinfo.current.width != tp->tinfo.goal.width) 2832 nego = NS_WIDE; 2833 /* 2834 * negotiate synchronous transfers? 2835 */ 2836 else if (tp->tinfo.current.period != tp->tinfo.goal.period || 2837 tp->tinfo.current.offset != tp->tinfo.goal.offset) 2838 nego = NS_SYNC; 2839 2840 switch (nego) { 2841 case NS_SYNC: 2842 msgptr[msglen++] = M_EXTENDED; 2843 msgptr[msglen++] = 3; 2844 msgptr[msglen++] = M_X_SYNC_REQ; 2845 msgptr[msglen++] = tp->tinfo.goal.period; 2846 msgptr[msglen++] = tp->tinfo.goal.offset; 2847 break; 2848 case NS_WIDE: 2849 msgptr[msglen++] = M_EXTENDED; 2850 msgptr[msglen++] = 2; 2851 msgptr[msglen++] = M_X_WIDE_REQ; 2852 msgptr[msglen++] = tp->tinfo.goal.width; 2853 break; 2854 case NS_PPR: 2855 msgptr[msglen++] = M_EXTENDED; 2856 msgptr[msglen++] = 6; 2857 msgptr[msglen++] = M_X_PPR_REQ; 2858 msgptr[msglen++] = tp->tinfo.goal.period; 2859 msgptr[msglen++] = 0; 2860 msgptr[msglen++] = tp->tinfo.goal.offset; 2861 msgptr[msglen++] = tp->tinfo.goal.width; 2862 msgptr[msglen++] = tp->tinfo.goal.options & PPR_OPT_DT; 2863 break; 2864 } 2865 2866 cp->nego_status = nego; 2867 2868 if (nego) { 2869 tp->nego_cp = cp; /* Keep track a nego will be performed */ 2870 if (DEBUG_FLAGS & DEBUG_NEGO) { 2871 sym_print_msg(cp, nego == NS_SYNC ? "sync msgout" : 2872 nego == NS_WIDE ? "wide msgout" : 2873 "ppr msgout", msgptr); 2874 } 2875 } 2876 2877 return msglen; 2878 } 2879 2880 /* 2881 * Insert a job into the start queue. 2882 */ 2883 static void sym_put_start_queue(hcb_p np, ccb_p cp) 2884 { 2885 u_short qidx; 2886 2887 #ifdef SYM_CONF_IARB_SUPPORT 2888 /* 2889 * If the previously queued CCB is not yet done, 2890 * set the IARB hint. The SCRIPTS will go with IARB 2891 * for this job when starting the previous one. 2892 * We leave devices a chance to win arbitration by 2893 * not using more than 'iarb_max' consecutive 2894 * immediate arbitrations. 2895 */ 2896 if (np->last_cp && np->iarb_count < np->iarb_max) { 2897 np->last_cp->host_flags |= HF_HINT_IARB; 2898 ++np->iarb_count; 2899 } 2900 else 2901 np->iarb_count = 0; 2902 np->last_cp = cp; 2903 #endif 2904 2905 /* 2906 * Insert first the idle task and then our job. 2907 * The MB should ensure proper ordering. 2908 */ 2909 qidx = np->squeueput + 2; 2910 if (qidx >= MAX_QUEUE*2) qidx = 0; 2911 2912 np->squeue [qidx] = cpu_to_scr(np->idletask_ba); 2913 MEMORY_BARRIER(); 2914 np->squeue [np->squeueput] = cpu_to_scr(cp->ccb_ba); 2915 2916 np->squeueput = qidx; 2917 2918 if (DEBUG_FLAGS & DEBUG_QUEUE) 2919 printf ("%s: queuepos=%d.\n", sym_name (np), np->squeueput); 2920 2921 /* 2922 * Script processor may be waiting for reselect. 2923 * Wake it up. 2924 */ 2925 MEMORY_BARRIER(); 2926 OUTB (nc_istat, SIGP|np->istat_sem); 2927 } 2928 2929 /* 2930 * Soft reset the chip. 2931 * 2932 * Raising SRST when the chip is running may cause 2933 * problems on dual function chips (see below). 2934 * On the other hand, LVD devices need some delay 2935 * to settle and report actual BUS mode in STEST4. 2936 */ 2937 static void sym_chip_reset (hcb_p np) 2938 { 2939 OUTB (nc_istat, SRST); 2940 UDELAY (10); 2941 OUTB (nc_istat, 0); 2942 UDELAY(2000); /* For BUS MODE to settle */ 2943 } 2944 2945 /* 2946 * Soft reset the chip. 2947 * 2948 * Some 896 and 876 chip revisions may hang-up if we set 2949 * the SRST (soft reset) bit at the wrong time when SCRIPTS 2950 * are running. 2951 * So, we need to abort the current operation prior to 2952 * soft resetting the chip. 2953 */ 2954 static void sym_soft_reset (hcb_p np) 2955 { 2956 u_char istat; 2957 int i; 2958 2959 OUTB (nc_istat, CABRT); 2960 for (i = 1000000 ; i ; --i) { 2961 istat = INB (nc_istat); 2962 if (istat & SIP) { 2963 INW (nc_sist); 2964 continue; 2965 } 2966 if (istat & DIP) { 2967 OUTB (nc_istat, 0); 2968 INB (nc_dstat); 2969 break; 2970 } 2971 } 2972 if (!i) 2973 printf("%s: unable to abort current chip operation.\n", 2974 sym_name(np)); 2975 sym_chip_reset (np); 2976 } 2977 2978 /* 2979 * Start reset process. 2980 * 2981 * The interrupt handler will reinitialize the chip. 2982 */ 2983 static void sym_start_reset(hcb_p np) 2984 { 2985 (void) sym_reset_scsi_bus(np, 1); 2986 } 2987 2988 static int sym_reset_scsi_bus(hcb_p np, int enab_int) 2989 { 2990 u32 term; 2991 int retv = 0; 2992 2993 sym_soft_reset(np); /* Soft reset the chip */ 2994 if (enab_int) 2995 OUTW (nc_sien, RST); 2996 /* 2997 * Enable Tolerant, reset IRQD if present and 2998 * properly set IRQ mode, prior to resetting the bus. 2999 */ 3000 OUTB (nc_stest3, TE); 3001 OUTB (nc_dcntl, (np->rv_dcntl & IRQM)); 3002 OUTB (nc_scntl1, CRST); 3003 UDELAY (200); 3004 3005 if (!SYM_SETUP_SCSI_BUS_CHECK) 3006 goto out; 3007 /* 3008 * Check for no terminators or SCSI bus shorts to ground. 3009 * Read SCSI data bus, data parity bits and control signals. 3010 * We are expecting RESET to be TRUE and other signals to be 3011 * FALSE. 3012 */ 3013 term = INB(nc_sstat0); 3014 term = ((term & 2) << 7) + ((term & 1) << 17); /* rst sdp0 */ 3015 term |= ((INB(nc_sstat2) & 0x01) << 26) | /* sdp1 */ 3016 ((INW(nc_sbdl) & 0xff) << 9) | /* d7-0 */ 3017 ((INW(nc_sbdl) & 0xff00) << 10) | /* d15-8 */ 3018 INB(nc_sbcl); /* req ack bsy sel atn msg cd io */ 3019 3020 if (!(np->features & FE_WIDE)) 3021 term &= 0x3ffff; 3022 3023 if (term != (2<<7)) { 3024 printf("%s: suspicious SCSI data while resetting the BUS.\n", 3025 sym_name(np)); 3026 printf("%s: %sdp0,d7-0,rst,req,ack,bsy,sel,atn,msg,c/d,i/o = " 3027 "0x%lx, expecting 0x%lx\n", 3028 sym_name(np), 3029 (np->features & FE_WIDE) ? "dp1,d15-8," : "", 3030 (u_long)term, (u_long)(2<<7)); 3031 if (SYM_SETUP_SCSI_BUS_CHECK == 1) 3032 retv = 1; 3033 } 3034 out: 3035 OUTB (nc_scntl1, 0); 3036 /* MDELAY(100); */ 3037 return retv; 3038 } 3039 3040 /* 3041 * The chip may have completed jobs. Look at the DONE QUEUE. 3042 * 3043 * On architectures that may reorder LOAD/STORE operations, 3044 * a memory barrier may be needed after the reading of the 3045 * so-called `flag' and prior to dealing with the data. 3046 */ 3047 static int sym_wakeup_done (hcb_p np) 3048 { 3049 ccb_p cp; 3050 int i, n; 3051 u32 dsa; 3052 3053 SYM_LOCK_ASSERT(MA_OWNED); 3054 3055 n = 0; 3056 i = np->dqueueget; 3057 while (1) { 3058 dsa = scr_to_cpu(np->dqueue[i]); 3059 if (!dsa) 3060 break; 3061 np->dqueue[i] = 0; 3062 if ((i = i+2) >= MAX_QUEUE*2) 3063 i = 0; 3064 3065 cp = sym_ccb_from_dsa(np, dsa); 3066 if (cp) { 3067 MEMORY_BARRIER(); 3068 sym_complete_ok (np, cp); 3069 ++n; 3070 } 3071 else 3072 printf ("%s: bad DSA (%x) in done queue.\n", 3073 sym_name(np), (u_int) dsa); 3074 } 3075 np->dqueueget = i; 3076 3077 return n; 3078 } 3079 3080 /* 3081 * Complete all active CCBs with error. 3082 * Used on CHIP/SCSI RESET. 3083 */ 3084 static void sym_flush_busy_queue (hcb_p np, int cam_status) 3085 { 3086 /* 3087 * Move all active CCBs to the COMP queue 3088 * and flush this queue. 3089 */ 3090 sym_que_splice(&np->busy_ccbq, &np->comp_ccbq); 3091 sym_que_init(&np->busy_ccbq); 3092 sym_flush_comp_queue(np, cam_status); 3093 } 3094 3095 /* 3096 * Start chip. 3097 * 3098 * 'reason' means: 3099 * 0: initialisation. 3100 * 1: SCSI BUS RESET delivered or received. 3101 * 2: SCSI BUS MODE changed. 3102 */ 3103 static void sym_init (hcb_p np, int reason) 3104 { 3105 int i; 3106 u32 phys; 3107 3108 SYM_LOCK_ASSERT(MA_OWNED); 3109 3110 /* 3111 * Reset chip if asked, otherwise just clear fifos. 3112 */ 3113 if (reason == 1) 3114 sym_soft_reset(np); 3115 else { 3116 OUTB (nc_stest3, TE|CSF); 3117 OUTONB (nc_ctest3, CLF); 3118 } 3119 3120 /* 3121 * Clear Start Queue 3122 */ 3123 phys = np->squeue_ba; 3124 for (i = 0; i < MAX_QUEUE*2; i += 2) { 3125 np->squeue[i] = cpu_to_scr(np->idletask_ba); 3126 np->squeue[i+1] = cpu_to_scr(phys + (i+2)*4); 3127 } 3128 np->squeue[MAX_QUEUE*2-1] = cpu_to_scr(phys); 3129 3130 /* 3131 * Start at first entry. 3132 */ 3133 np->squeueput = 0; 3134 3135 /* 3136 * Clear Done Queue 3137 */ 3138 phys = np->dqueue_ba; 3139 for (i = 0; i < MAX_QUEUE*2; i += 2) { 3140 np->dqueue[i] = 0; 3141 np->dqueue[i+1] = cpu_to_scr(phys + (i+2)*4); 3142 } 3143 np->dqueue[MAX_QUEUE*2-1] = cpu_to_scr(phys); 3144 3145 /* 3146 * Start at first entry. 3147 */ 3148 np->dqueueget = 0; 3149 3150 /* 3151 * Install patches in scripts. 3152 * This also let point to first position the start 3153 * and done queue pointers used from SCRIPTS. 3154 */ 3155 np->fw_patch(np); 3156 3157 /* 3158 * Wakeup all pending jobs. 3159 */ 3160 sym_flush_busy_queue(np, CAM_SCSI_BUS_RESET); 3161 3162 /* 3163 * Init chip. 3164 */ 3165 OUTB (nc_istat, 0x00 ); /* Remove Reset, abort */ 3166 UDELAY (2000); /* The 895 needs time for the bus mode to settle */ 3167 3168 OUTB (nc_scntl0, np->rv_scntl0 | 0xc0); 3169 /* full arb., ena parity, par->ATN */ 3170 OUTB (nc_scntl1, 0x00); /* odd parity, and remove CRST!! */ 3171 3172 sym_selectclock(np, np->rv_scntl3); /* Select SCSI clock */ 3173 3174 OUTB (nc_scid , RRE|np->myaddr); /* Adapter SCSI address */ 3175 OUTW (nc_respid, 1ul<<np->myaddr); /* Id to respond to */ 3176 OUTB (nc_istat , SIGP ); /* Signal Process */ 3177 OUTB (nc_dmode , np->rv_dmode); /* Burst length, dma mode */ 3178 OUTB (nc_ctest5, np->rv_ctest5); /* Large fifo + large burst */ 3179 3180 OUTB (nc_dcntl , NOCOM|np->rv_dcntl); /* Protect SFBR */ 3181 OUTB (nc_ctest3, np->rv_ctest3); /* Write and invalidate */ 3182 OUTB (nc_ctest4, np->rv_ctest4); /* Master parity checking */ 3183 3184 /* Extended Sreq/Sack filtering not supported on the C10 */ 3185 if (np->features & FE_C10) 3186 OUTB (nc_stest2, np->rv_stest2); 3187 else 3188 OUTB (nc_stest2, EXT|np->rv_stest2); 3189 3190 OUTB (nc_stest3, TE); /* TolerANT enable */ 3191 OUTB (nc_stime0, 0x0c); /* HTH disabled STO 0.25 sec */ 3192 3193 /* 3194 * For now, disable AIP generation on C1010-66. 3195 */ 3196 if (np->device_id == PCI_ID_LSI53C1010_2) 3197 OUTB (nc_aipcntl1, DISAIP); 3198 3199 /* 3200 * C10101 Errata. 3201 * Errant SGE's when in narrow. Write bits 4 & 5 of 3202 * STEST1 register to disable SGE. We probably should do 3203 * that from SCRIPTS for each selection/reselection, but 3204 * I just don't want. :) 3205 */ 3206 if (np->device_id == PCI_ID_LSI53C1010 && 3207 /* np->revision_id < 0xff */ 1) 3208 OUTB (nc_stest1, INB(nc_stest1) | 0x30); 3209 3210 /* 3211 * DEL 441 - 53C876 Rev 5 - Part Number 609-0392787/2788 - ITEM 2. 3212 * Disable overlapped arbitration for some dual function devices, 3213 * regardless revision id (kind of post-chip-design feature. ;-)) 3214 */ 3215 if (np->device_id == PCI_ID_SYM53C875) 3216 OUTB (nc_ctest0, (1<<5)); 3217 else if (np->device_id == PCI_ID_SYM53C896) 3218 np->rv_ccntl0 |= DPR; 3219 3220 /* 3221 * Write CCNTL0/CCNTL1 for chips capable of 64 bit addressing 3222 * and/or hardware phase mismatch, since only such chips 3223 * seem to support those IO registers. 3224 */ 3225 if (np->features & (FE_DAC|FE_NOPM)) { 3226 OUTB (nc_ccntl0, np->rv_ccntl0); 3227 OUTB (nc_ccntl1, np->rv_ccntl1); 3228 } 3229 3230 /* 3231 * If phase mismatch handled by scripts (895A/896/1010), 3232 * set PM jump addresses. 3233 */ 3234 if (np->features & FE_NOPM) { 3235 OUTL (nc_pmjad1, SCRIPTB_BA (np, pm_handle)); 3236 OUTL (nc_pmjad2, SCRIPTB_BA (np, pm_handle)); 3237 } 3238 3239 /* 3240 * Enable GPIO0 pin for writing if LED support from SCRIPTS. 3241 * Also set GPIO5 and clear GPIO6 if hardware LED control. 3242 */ 3243 if (np->features & FE_LED0) 3244 OUTB(nc_gpcntl, INB(nc_gpcntl) & ~0x01); 3245 else if (np->features & FE_LEDC) 3246 OUTB(nc_gpcntl, (INB(nc_gpcntl) & ~0x41) | 0x20); 3247 3248 /* 3249 * enable ints 3250 */ 3251 OUTW (nc_sien , STO|HTH|MA|SGE|UDC|RST|PAR); 3252 OUTB (nc_dien , MDPE|BF|SSI|SIR|IID); 3253 3254 /* 3255 * For 895/6 enable SBMC interrupt and save current SCSI bus mode. 3256 * Try to eat the spurious SBMC interrupt that may occur when 3257 * we reset the chip but not the SCSI BUS (at initialization). 3258 */ 3259 if (np->features & (FE_ULTRA2|FE_ULTRA3)) { 3260 OUTONW (nc_sien, SBMC); 3261 if (reason == 0) { 3262 MDELAY(100); 3263 INW (nc_sist); 3264 } 3265 np->scsi_mode = INB (nc_stest4) & SMODE; 3266 } 3267 3268 /* 3269 * Fill in target structure. 3270 * Reinitialize usrsync. 3271 * Reinitialize usrwide. 3272 * Prepare sync negotiation according to actual SCSI bus mode. 3273 */ 3274 for (i=0;i<SYM_CONF_MAX_TARGET;i++) { 3275 tcb_p tp = &np->target[i]; 3276 3277 tp->to_reset = 0; 3278 tp->head.sval = 0; 3279 tp->head.wval = np->rv_scntl3; 3280 tp->head.uval = 0; 3281 3282 tp->tinfo.current.period = 0; 3283 tp->tinfo.current.offset = 0; 3284 tp->tinfo.current.width = BUS_8_BIT; 3285 tp->tinfo.current.options = 0; 3286 } 3287 3288 /* 3289 * Download SCSI SCRIPTS to on-chip RAM if present, 3290 * and start script processor. 3291 */ 3292 if (np->ram_ba) { 3293 if (sym_verbose > 1) 3294 printf ("%s: Downloading SCSI SCRIPTS.\n", 3295 sym_name(np)); 3296 if (np->ram_ws == 8192) { 3297 OUTRAM_OFF(4096, np->scriptb0, np->scriptb_sz); 3298 OUTL (nc_mmws, np->scr_ram_seg); 3299 OUTL (nc_mmrs, np->scr_ram_seg); 3300 OUTL (nc_sfs, np->scr_ram_seg); 3301 phys = SCRIPTB_BA (np, start64); 3302 } 3303 else 3304 phys = SCRIPTA_BA (np, init); 3305 OUTRAM_OFF(0, np->scripta0, np->scripta_sz); 3306 } 3307 else 3308 phys = SCRIPTA_BA (np, init); 3309 3310 np->istat_sem = 0; 3311 3312 OUTL (nc_dsa, np->hcb_ba); 3313 OUTL_DSP (phys); 3314 3315 /* 3316 * Notify the XPT about the RESET condition. 3317 */ 3318 if (reason != 0) 3319 xpt_async(AC_BUS_RESET, np->path, NULL); 3320 } 3321 3322 /* 3323 * Get clock factor and sync divisor for a given 3324 * synchronous factor period. 3325 */ 3326 static int 3327 sym_getsync(hcb_p np, u_char dt, u_char sfac, u_char *divp, u_char *fakp) 3328 { 3329 u32 clk = np->clock_khz; /* SCSI clock frequency in kHz */ 3330 int div = np->clock_divn; /* Number of divisors supported */ 3331 u32 fak; /* Sync factor in sxfer */ 3332 u32 per; /* Period in tenths of ns */ 3333 u32 kpc; /* (per * clk) */ 3334 int ret; 3335 3336 /* 3337 * Compute the synchronous period in tenths of nano-seconds 3338 */ 3339 if (dt && sfac <= 9) per = 125; 3340 else if (sfac <= 10) per = 250; 3341 else if (sfac == 11) per = 303; 3342 else if (sfac == 12) per = 500; 3343 else per = 40 * sfac; 3344 ret = per; 3345 3346 kpc = per * clk; 3347 if (dt) 3348 kpc <<= 1; 3349 3350 /* 3351 * For earliest C10 revision 0, we cannot use extra 3352 * clocks for the setting of the SCSI clocking. 3353 * Note that this limits the lowest sync data transfer 3354 * to 5 Mega-transfers per second and may result in 3355 * using higher clock divisors. 3356 */ 3357 #if 1 3358 if ((np->features & (FE_C10|FE_U3EN)) == FE_C10) { 3359 /* 3360 * Look for the lowest clock divisor that allows an 3361 * output speed not faster than the period. 3362 */ 3363 while (div > 0) { 3364 --div; 3365 if (kpc > (div_10M[div] << 2)) { 3366 ++div; 3367 break; 3368 } 3369 } 3370 fak = 0; /* No extra clocks */ 3371 if (div == np->clock_divn) { /* Are we too fast ? */ 3372 ret = -1; 3373 } 3374 *divp = div; 3375 *fakp = fak; 3376 return ret; 3377 } 3378 #endif 3379 3380 /* 3381 * Look for the greatest clock divisor that allows an 3382 * input speed faster than the period. 3383 */ 3384 while (div-- > 0) 3385 if (kpc >= (div_10M[div] << 2)) break; 3386 3387 /* 3388 * Calculate the lowest clock factor that allows an output 3389 * speed not faster than the period, and the max output speed. 3390 * If fak >= 1 we will set both XCLKH_ST and XCLKH_DT. 3391 * If fak >= 2 we will also set XCLKS_ST and XCLKS_DT. 3392 */ 3393 if (dt) { 3394 fak = (kpc - 1) / (div_10M[div] << 1) + 1 - 2; 3395 /* ret = ((2+fak)*div_10M[div])/np->clock_khz; */ 3396 } 3397 else { 3398 fak = (kpc - 1) / div_10M[div] + 1 - 4; 3399 /* ret = ((4+fak)*div_10M[div])/np->clock_khz; */ 3400 } 3401 3402 /* 3403 * Check against our hardware limits, or bugs :). 3404 */ 3405 if (fak > 2) {fak = 2; ret = -1;} 3406 3407 /* 3408 * Compute and return sync parameters. 3409 */ 3410 *divp = div; 3411 *fakp = fak; 3412 3413 return ret; 3414 } 3415 3416 /* 3417 * Tell the SCSI layer about the new transfer parameters. 3418 */ 3419 static void 3420 sym_xpt_async_transfer_neg(hcb_p np, int target, u_int spi_valid) 3421 { 3422 struct ccb_trans_settings cts; 3423 struct cam_path *path; 3424 int sts; 3425 tcb_p tp = &np->target[target]; 3426 3427 sts = xpt_create_path(&path, NULL, cam_sim_path(np->sim), target, 3428 CAM_LUN_WILDCARD); 3429 if (sts != CAM_REQ_CMP) 3430 return; 3431 3432 bzero(&cts, sizeof(cts)); 3433 3434 #define cts__scsi (cts.proto_specific.scsi) 3435 #define cts__spi (cts.xport_specific.spi) 3436 3437 cts.type = CTS_TYPE_CURRENT_SETTINGS; 3438 cts.protocol = PROTO_SCSI; 3439 cts.transport = XPORT_SPI; 3440 cts.protocol_version = tp->tinfo.current.scsi_version; 3441 cts.transport_version = tp->tinfo.current.spi_version; 3442 3443 cts__spi.valid = spi_valid; 3444 if (spi_valid & CTS_SPI_VALID_SYNC_RATE) 3445 cts__spi.sync_period = tp->tinfo.current.period; 3446 if (spi_valid & CTS_SPI_VALID_SYNC_OFFSET) 3447 cts__spi.sync_offset = tp->tinfo.current.offset; 3448 if (spi_valid & CTS_SPI_VALID_BUS_WIDTH) 3449 cts__spi.bus_width = tp->tinfo.current.width; 3450 if (spi_valid & CTS_SPI_VALID_PPR_OPTIONS) 3451 cts__spi.ppr_options = tp->tinfo.current.options; 3452 #undef cts__spi 3453 #undef cts__scsi 3454 xpt_setup_ccb(&cts.ccb_h, path, /*priority*/1); 3455 xpt_async(AC_TRANSFER_NEG, path, &cts); 3456 xpt_free_path(path); 3457 } 3458 3459 #define SYM_SPI_VALID_WDTR \ 3460 CTS_SPI_VALID_BUS_WIDTH | \ 3461 CTS_SPI_VALID_SYNC_RATE | \ 3462 CTS_SPI_VALID_SYNC_OFFSET 3463 #define SYM_SPI_VALID_SDTR \ 3464 CTS_SPI_VALID_SYNC_RATE | \ 3465 CTS_SPI_VALID_SYNC_OFFSET 3466 #define SYM_SPI_VALID_PPR \ 3467 CTS_SPI_VALID_PPR_OPTIONS | \ 3468 CTS_SPI_VALID_BUS_WIDTH | \ 3469 CTS_SPI_VALID_SYNC_RATE | \ 3470 CTS_SPI_VALID_SYNC_OFFSET 3471 3472 /* 3473 * We received a WDTR. 3474 * Let everything be aware of the changes. 3475 */ 3476 static void sym_setwide(hcb_p np, ccb_p cp, u_char wide) 3477 { 3478 tcb_p tp = &np->target[cp->target]; 3479 3480 sym_settrans(np, cp, 0, 0, 0, wide, 0, 0); 3481 3482 /* 3483 * Tell the SCSI layer about the new transfer parameters. 3484 */ 3485 tp->tinfo.goal.width = tp->tinfo.current.width = wide; 3486 tp->tinfo.current.offset = 0; 3487 tp->tinfo.current.period = 0; 3488 tp->tinfo.current.options = 0; 3489 3490 sym_xpt_async_transfer_neg(np, cp->target, SYM_SPI_VALID_WDTR); 3491 } 3492 3493 /* 3494 * We received a SDTR. 3495 * Let everything be aware of the changes. 3496 */ 3497 static void 3498 sym_setsync(hcb_p np, ccb_p cp, u_char ofs, u_char per, u_char div, u_char fak) 3499 { 3500 tcb_p tp = &np->target[cp->target]; 3501 u_char wide = (cp->phys.select.sel_scntl3 & EWS) ? 1 : 0; 3502 3503 sym_settrans(np, cp, 0, ofs, per, wide, div, fak); 3504 3505 /* 3506 * Tell the SCSI layer about the new transfer parameters. 3507 */ 3508 tp->tinfo.goal.period = tp->tinfo.current.period = per; 3509 tp->tinfo.goal.offset = tp->tinfo.current.offset = ofs; 3510 tp->tinfo.goal.options = tp->tinfo.current.options = 0; 3511 3512 sym_xpt_async_transfer_neg(np, cp->target, SYM_SPI_VALID_SDTR); 3513 } 3514 3515 /* 3516 * We received a PPR. 3517 * Let everything be aware of the changes. 3518 */ 3519 static void sym_setpprot(hcb_p np, ccb_p cp, u_char dt, u_char ofs, 3520 u_char per, u_char wide, u_char div, u_char fak) 3521 { 3522 tcb_p tp = &np->target[cp->target]; 3523 3524 sym_settrans(np, cp, dt, ofs, per, wide, div, fak); 3525 3526 /* 3527 * Tell the SCSI layer about the new transfer parameters. 3528 */ 3529 tp->tinfo.goal.width = tp->tinfo.current.width = wide; 3530 tp->tinfo.goal.period = tp->tinfo.current.period = per; 3531 tp->tinfo.goal.offset = tp->tinfo.current.offset = ofs; 3532 tp->tinfo.goal.options = tp->tinfo.current.options = dt; 3533 3534 sym_xpt_async_transfer_neg(np, cp->target, SYM_SPI_VALID_PPR); 3535 } 3536 3537 /* 3538 * Switch trans mode for current job and it's target. 3539 */ 3540 static void sym_settrans(hcb_p np, ccb_p cp, u_char dt, u_char ofs, 3541 u_char per, u_char wide, u_char div, u_char fak) 3542 { 3543 SYM_QUEHEAD *qp; 3544 union ccb *ccb; 3545 tcb_p tp; 3546 u_char target = INB (nc_sdid) & 0x0f; 3547 u_char sval, wval, uval; 3548 3549 assert (cp); 3550 if (!cp) return; 3551 ccb = cp->cam_ccb; 3552 assert (ccb); 3553 if (!ccb) return; 3554 assert (target == (cp->target & 0xf)); 3555 tp = &np->target[target]; 3556 3557 sval = tp->head.sval; 3558 wval = tp->head.wval; 3559 uval = tp->head.uval; 3560 3561 #if 0 3562 printf("XXXX sval=%x wval=%x uval=%x (%x)\n", 3563 sval, wval, uval, np->rv_scntl3); 3564 #endif 3565 /* 3566 * Set the offset. 3567 */ 3568 if (!(np->features & FE_C10)) 3569 sval = (sval & ~0x1f) | ofs; 3570 else 3571 sval = (sval & ~0x3f) | ofs; 3572 3573 /* 3574 * Set the sync divisor and extra clock factor. 3575 */ 3576 if (ofs != 0) { 3577 wval = (wval & ~0x70) | ((div+1) << 4); 3578 if (!(np->features & FE_C10)) 3579 sval = (sval & ~0xe0) | (fak << 5); 3580 else { 3581 uval = uval & ~(XCLKH_ST|XCLKH_DT|XCLKS_ST|XCLKS_DT); 3582 if (fak >= 1) uval |= (XCLKH_ST|XCLKH_DT); 3583 if (fak >= 2) uval |= (XCLKS_ST|XCLKS_DT); 3584 } 3585 } 3586 3587 /* 3588 * Set the bus width. 3589 */ 3590 wval = wval & ~EWS; 3591 if (wide != 0) 3592 wval |= EWS; 3593 3594 /* 3595 * Set misc. ultra enable bits. 3596 */ 3597 if (np->features & FE_C10) { 3598 uval = uval & ~(U3EN|AIPCKEN); 3599 if (dt) { 3600 assert(np->features & FE_U3EN); 3601 uval |= U3EN; 3602 } 3603 } 3604 else { 3605 wval = wval & ~ULTRA; 3606 if (per <= 12) wval |= ULTRA; 3607 } 3608 3609 /* 3610 * Stop there if sync parameters are unchanged. 3611 */ 3612 if (tp->head.sval == sval && 3613 tp->head.wval == wval && 3614 tp->head.uval == uval) 3615 return; 3616 tp->head.sval = sval; 3617 tp->head.wval = wval; 3618 tp->head.uval = uval; 3619 3620 /* 3621 * Disable extended Sreq/Sack filtering if per < 50. 3622 * Not supported on the C1010. 3623 */ 3624 if (per < 50 && !(np->features & FE_C10)) 3625 OUTOFFB (nc_stest2, EXT); 3626 3627 /* 3628 * set actual value and sync_status 3629 */ 3630 OUTB (nc_sxfer, tp->head.sval); 3631 OUTB (nc_scntl3, tp->head.wval); 3632 3633 if (np->features & FE_C10) { 3634 OUTB (nc_scntl4, tp->head.uval); 3635 } 3636 3637 /* 3638 * patch ALL busy ccbs of this target. 3639 */ 3640 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) { 3641 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 3642 if (cp->target != target) 3643 continue; 3644 cp->phys.select.sel_scntl3 = tp->head.wval; 3645 cp->phys.select.sel_sxfer = tp->head.sval; 3646 if (np->features & FE_C10) { 3647 cp->phys.select.sel_scntl4 = tp->head.uval; 3648 } 3649 } 3650 } 3651 3652 /* 3653 * log message for real hard errors 3654 * 3655 * sym0 targ 0?: ERROR (ds:si) (so-si-sd) (sxfer/scntl3) @ name (dsp:dbc). 3656 * reg: r0 r1 r2 r3 r4 r5 r6 ..... rf. 3657 * 3658 * exception register: 3659 * ds: dstat 3660 * si: sist 3661 * 3662 * SCSI bus lines: 3663 * so: control lines as driven by chip. 3664 * si: control lines as seen by chip. 3665 * sd: scsi data lines as seen by chip. 3666 * 3667 * wide/fastmode: 3668 * sxfer: (see the manual) 3669 * scntl3: (see the manual) 3670 * 3671 * current script command: 3672 * dsp: script address (relative to start of script). 3673 * dbc: first word of script command. 3674 * 3675 * First 24 register of the chip: 3676 * r0..rf 3677 */ 3678 static void sym_log_hard_error(hcb_p np, u_short sist, u_char dstat) 3679 { 3680 u32 dsp; 3681 int script_ofs; 3682 int script_size; 3683 char *script_name; 3684 u_char *script_base; 3685 int i; 3686 3687 dsp = INL (nc_dsp); 3688 3689 if (dsp > np->scripta_ba && 3690 dsp <= np->scripta_ba + np->scripta_sz) { 3691 script_ofs = dsp - np->scripta_ba; 3692 script_size = np->scripta_sz; 3693 script_base = (u_char *) np->scripta0; 3694 script_name = "scripta"; 3695 } 3696 else if (np->scriptb_ba < dsp && 3697 dsp <= np->scriptb_ba + np->scriptb_sz) { 3698 script_ofs = dsp - np->scriptb_ba; 3699 script_size = np->scriptb_sz; 3700 script_base = (u_char *) np->scriptb0; 3701 script_name = "scriptb"; 3702 } else { 3703 script_ofs = dsp; 3704 script_size = 0; 3705 script_base = NULL; 3706 script_name = "mem"; 3707 } 3708 3709 printf ("%s:%d: ERROR (%x:%x) (%x-%x-%x) (%x/%x) @ (%s %x:%08x).\n", 3710 sym_name (np), (unsigned)INB (nc_sdid)&0x0f, dstat, sist, 3711 (unsigned)INB (nc_socl), (unsigned)INB (nc_sbcl), 3712 (unsigned)INB (nc_sbdl), (unsigned)INB (nc_sxfer), 3713 (unsigned)INB (nc_scntl3), script_name, script_ofs, 3714 (unsigned)INL (nc_dbc)); 3715 3716 if (((script_ofs & 3) == 0) && 3717 (unsigned)script_ofs < script_size) { 3718 printf ("%s: script cmd = %08x\n", sym_name(np), 3719 scr_to_cpu((int) *(u32 *)(script_base + script_ofs))); 3720 } 3721 3722 printf ("%s: regdump:", sym_name(np)); 3723 for (i=0; i<24;i++) 3724 printf (" %02x", (unsigned)INB_OFF(i)); 3725 printf (".\n"); 3726 3727 /* 3728 * PCI BUS error, read the PCI ststus register. 3729 */ 3730 if (dstat & (MDPE|BF)) { 3731 u_short pci_sts; 3732 pci_sts = pci_read_config(np->device, PCIR_STATUS, 2); 3733 if (pci_sts & 0xf900) { 3734 pci_write_config(np->device, PCIR_STATUS, pci_sts, 2); 3735 printf("%s: PCI STATUS = 0x%04x\n", 3736 sym_name(np), pci_sts & 0xf900); 3737 } 3738 } 3739 } 3740 3741 /* 3742 * chip interrupt handler 3743 * 3744 * In normal situations, interrupt conditions occur one at 3745 * a time. But when something bad happens on the SCSI BUS, 3746 * the chip may raise several interrupt flags before 3747 * stopping and interrupting the CPU. The additionnal 3748 * interrupt flags are stacked in some extra registers 3749 * after the SIP and/or DIP flag has been raised in the 3750 * ISTAT. After the CPU has read the interrupt condition 3751 * flag from SIST or DSTAT, the chip unstacks the other 3752 * interrupt flags and sets the corresponding bits in 3753 * SIST or DSTAT. Since the chip starts stacking once the 3754 * SIP or DIP flag is set, there is a small window of time 3755 * where the stacking does not occur. 3756 * 3757 * Typically, multiple interrupt conditions may happen in 3758 * the following situations: 3759 * 3760 * - SCSI parity error + Phase mismatch (PAR|MA) 3761 * When a parity error is detected in input phase 3762 * and the device switches to msg-in phase inside a 3763 * block MOV. 3764 * - SCSI parity error + Unexpected disconnect (PAR|UDC) 3765 * When a stupid device does not want to handle the 3766 * recovery of an SCSI parity error. 3767 * - Some combinations of STO, PAR, UDC, ... 3768 * When using non compliant SCSI stuff, when user is 3769 * doing non compliant hot tampering on the BUS, when 3770 * something really bad happens to a device, etc ... 3771 * 3772 * The heuristic suggested by SYMBIOS to handle 3773 * multiple interrupts is to try unstacking all 3774 * interrupts conditions and to handle them on some 3775 * priority based on error severity. 3776 * This will work when the unstacking has been 3777 * successful, but we cannot be 100 % sure of that, 3778 * since the CPU may have been faster to unstack than 3779 * the chip is able to stack. Hmmm ... But it seems that 3780 * such a situation is very unlikely to happen. 3781 * 3782 * If this happen, for example STO caught by the CPU 3783 * then UDC happenning before the CPU have restarted 3784 * the SCRIPTS, the driver may wrongly complete the 3785 * same command on UDC, since the SCRIPTS didn't restart 3786 * and the DSA still points to the same command. 3787 * We avoid this situation by setting the DSA to an 3788 * invalid value when the CCB is completed and before 3789 * restarting the SCRIPTS. 3790 * 3791 * Another issue is that we need some section of our 3792 * recovery procedures to be somehow uninterruptible but 3793 * the SCRIPTS processor does not provides such a 3794 * feature. For this reason, we handle recovery preferently 3795 * from the C code and check against some SCRIPTS critical 3796 * sections from the C code. 3797 * 3798 * Hopefully, the interrupt handling of the driver is now 3799 * able to resist to weird BUS error conditions, but donnot 3800 * ask me for any guarantee that it will never fail. :-) 3801 * Use at your own decision and risk. 3802 */ 3803 static void sym_intr1 (hcb_p np) 3804 { 3805 u_char istat, istatc; 3806 u_char dstat; 3807 u_short sist; 3808 3809 SYM_LOCK_ASSERT(MA_OWNED); 3810 3811 /* 3812 * interrupt on the fly ? 3813 * 3814 * A `dummy read' is needed to ensure that the 3815 * clear of the INTF flag reaches the device 3816 * before the scanning of the DONE queue. 3817 */ 3818 istat = INB (nc_istat); 3819 if (istat & INTF) { 3820 OUTB (nc_istat, (istat & SIGP) | INTF | np->istat_sem); 3821 istat = INB (nc_istat); /* DUMMY READ */ 3822 if (DEBUG_FLAGS & DEBUG_TINY) printf ("F "); 3823 (void)sym_wakeup_done (np); 3824 } 3825 3826 if (!(istat & (SIP|DIP))) 3827 return; 3828 3829 #if 0 /* We should never get this one */ 3830 if (istat & CABRT) 3831 OUTB (nc_istat, CABRT); 3832 #endif 3833 3834 /* 3835 * PAR and MA interrupts may occur at the same time, 3836 * and we need to know of both in order to handle 3837 * this situation properly. We try to unstack SCSI 3838 * interrupts for that reason. BTW, I dislike a LOT 3839 * such a loop inside the interrupt routine. 3840 * Even if DMA interrupt stacking is very unlikely to 3841 * happen, we also try unstacking these ones, since 3842 * this has no performance impact. 3843 */ 3844 sist = 0; 3845 dstat = 0; 3846 istatc = istat; 3847 do { 3848 if (istatc & SIP) 3849 sist |= INW (nc_sist); 3850 if (istatc & DIP) 3851 dstat |= INB (nc_dstat); 3852 istatc = INB (nc_istat); 3853 istat |= istatc; 3854 } while (istatc & (SIP|DIP)); 3855 3856 if (DEBUG_FLAGS & DEBUG_TINY) 3857 printf ("<%d|%x:%x|%x:%x>", 3858 (int)INB(nc_scr0), 3859 dstat,sist, 3860 (unsigned)INL(nc_dsp), 3861 (unsigned)INL(nc_dbc)); 3862 /* 3863 * On paper, a memory barrier may be needed here. 3864 * And since we are paranoid ... :) 3865 */ 3866 MEMORY_BARRIER(); 3867 3868 /* 3869 * First, interrupts we want to service cleanly. 3870 * 3871 * Phase mismatch (MA) is the most frequent interrupt 3872 * for chip earlier than the 896 and so we have to service 3873 * it as quickly as possible. 3874 * A SCSI parity error (PAR) may be combined with a phase 3875 * mismatch condition (MA). 3876 * Programmed interrupts (SIR) are used to call the C code 3877 * from SCRIPTS. 3878 * The single step interrupt (SSI) is not used in this 3879 * driver. 3880 */ 3881 if (!(sist & (STO|GEN|HTH|SGE|UDC|SBMC|RST)) && 3882 !(dstat & (MDPE|BF|ABRT|IID))) { 3883 if (sist & PAR) sym_int_par (np, sist); 3884 else if (sist & MA) sym_int_ma (np); 3885 else if (dstat & SIR) sym_int_sir (np); 3886 else if (dstat & SSI) OUTONB_STD (); 3887 else goto unknown_int; 3888 return; 3889 } 3890 3891 /* 3892 * Now, interrupts that donnot happen in normal 3893 * situations and that we may need to recover from. 3894 * 3895 * On SCSI RESET (RST), we reset everything. 3896 * On SCSI BUS MODE CHANGE (SBMC), we complete all 3897 * active CCBs with RESET status, prepare all devices 3898 * for negotiating again and restart the SCRIPTS. 3899 * On STO and UDC, we complete the CCB with the corres- 3900 * ponding status and restart the SCRIPTS. 3901 */ 3902 if (sist & RST) { 3903 xpt_print_path(np->path); 3904 printf("SCSI BUS reset detected.\n"); 3905 sym_init (np, 1); 3906 return; 3907 } 3908 3909 OUTB (nc_ctest3, np->rv_ctest3 | CLF); /* clear dma fifo */ 3910 OUTB (nc_stest3, TE|CSF); /* clear scsi fifo */ 3911 3912 if (!(sist & (GEN|HTH|SGE)) && 3913 !(dstat & (MDPE|BF|ABRT|IID))) { 3914 if (sist & SBMC) sym_int_sbmc (np); 3915 else if (sist & STO) sym_int_sto (np); 3916 else if (sist & UDC) sym_int_udc (np); 3917 else goto unknown_int; 3918 return; 3919 } 3920 3921 /* 3922 * Now, interrupts we are not able to recover cleanly. 3923 * 3924 * Log message for hard errors. 3925 * Reset everything. 3926 */ 3927 3928 sym_log_hard_error(np, sist, dstat); 3929 3930 if ((sist & (GEN|HTH|SGE)) || 3931 (dstat & (MDPE|BF|ABRT|IID))) { 3932 sym_start_reset(np); 3933 return; 3934 } 3935 3936 unknown_int: 3937 /* 3938 * We just miss the cause of the interrupt. :( 3939 * Print a message. The timeout will do the real work. 3940 */ 3941 printf( "%s: unknown interrupt(s) ignored, " 3942 "ISTAT=0x%x DSTAT=0x%x SIST=0x%x\n", 3943 sym_name(np), istat, dstat, sist); 3944 } 3945 3946 static void sym_intr(void *arg) 3947 { 3948 hcb_p np = arg; 3949 3950 SYM_LOCK(); 3951 3952 if (DEBUG_FLAGS & DEBUG_TINY) printf ("["); 3953 sym_intr1((hcb_p) arg); 3954 if (DEBUG_FLAGS & DEBUG_TINY) printf ("]"); 3955 3956 SYM_UNLOCK(); 3957 } 3958 3959 static void sym_poll(struct cam_sim *sim) 3960 { 3961 sym_intr1(cam_sim_softc(sim)); 3962 } 3963 3964 /* 3965 * generic recovery from scsi interrupt 3966 * 3967 * The doc says that when the chip gets an SCSI interrupt, 3968 * it tries to stop in an orderly fashion, by completing 3969 * an instruction fetch that had started or by flushing 3970 * the DMA fifo for a write to memory that was executing. 3971 * Such a fashion is not enough to know if the instruction 3972 * that was just before the current DSP value has been 3973 * executed or not. 3974 * 3975 * There are some small SCRIPTS sections that deal with 3976 * the start queue and the done queue that may break any 3977 * assomption from the C code if we are interrupted 3978 * inside, so we reset if this happens. Btw, since these 3979 * SCRIPTS sections are executed while the SCRIPTS hasn't 3980 * started SCSI operations, it is very unlikely to happen. 3981 * 3982 * All the driver data structures are supposed to be 3983 * allocated from the same 4 GB memory window, so there 3984 * is a 1 to 1 relationship between DSA and driver data 3985 * structures. Since we are careful :) to invalidate the 3986 * DSA when we complete a command or when the SCRIPTS 3987 * pushes a DSA into a queue, we can trust it when it 3988 * points to a CCB. 3989 */ 3990 static void sym_recover_scsi_int (hcb_p np, u_char hsts) 3991 { 3992 u32 dsp = INL (nc_dsp); 3993 u32 dsa = INL (nc_dsa); 3994 ccb_p cp = sym_ccb_from_dsa(np, dsa); 3995 3996 /* 3997 * If we haven't been interrupted inside the SCRIPTS 3998 * critical paths, we can safely restart the SCRIPTS 3999 * and trust the DSA value if it matches a CCB. 4000 */ 4001 if ((!(dsp > SCRIPTA_BA (np, getjob_begin) && 4002 dsp < SCRIPTA_BA (np, getjob_end) + 1)) && 4003 (!(dsp > SCRIPTA_BA (np, ungetjob) && 4004 dsp < SCRIPTA_BA (np, reselect) + 1)) && 4005 (!(dsp > SCRIPTB_BA (np, sel_for_abort) && 4006 dsp < SCRIPTB_BA (np, sel_for_abort_1) + 1)) && 4007 (!(dsp > SCRIPTA_BA (np, done) && 4008 dsp < SCRIPTA_BA (np, done_end) + 1))) { 4009 OUTB (nc_ctest3, np->rv_ctest3 | CLF); /* clear dma fifo */ 4010 OUTB (nc_stest3, TE|CSF); /* clear scsi fifo */ 4011 /* 4012 * If we have a CCB, let the SCRIPTS call us back for 4013 * the handling of the error with SCRATCHA filled with 4014 * STARTPOS. This way, we will be able to freeze the 4015 * device queue and requeue awaiting IOs. 4016 */ 4017 if (cp) { 4018 cp->host_status = hsts; 4019 OUTL_DSP (SCRIPTA_BA (np, complete_error)); 4020 } 4021 /* 4022 * Otherwise just restart the SCRIPTS. 4023 */ 4024 else { 4025 OUTL (nc_dsa, 0xffffff); 4026 OUTL_DSP (SCRIPTA_BA (np, start)); 4027 } 4028 } 4029 else 4030 goto reset_all; 4031 4032 return; 4033 4034 reset_all: 4035 sym_start_reset(np); 4036 } 4037 4038 /* 4039 * chip exception handler for selection timeout 4040 */ 4041 static void sym_int_sto (hcb_p np) 4042 { 4043 u32 dsp = INL (nc_dsp); 4044 4045 if (DEBUG_FLAGS & DEBUG_TINY) printf ("T"); 4046 4047 if (dsp == SCRIPTA_BA (np, wf_sel_done) + 8) 4048 sym_recover_scsi_int(np, HS_SEL_TIMEOUT); 4049 else 4050 sym_start_reset(np); 4051 } 4052 4053 /* 4054 * chip exception handler for unexpected disconnect 4055 */ 4056 static void sym_int_udc (hcb_p np) 4057 { 4058 printf ("%s: unexpected disconnect\n", sym_name(np)); 4059 sym_recover_scsi_int(np, HS_UNEXPECTED); 4060 } 4061 4062 /* 4063 * chip exception handler for SCSI bus mode change 4064 * 4065 * spi2-r12 11.2.3 says a transceiver mode change must 4066 * generate a reset event and a device that detects a reset 4067 * event shall initiate a hard reset. It says also that a 4068 * device that detects a mode change shall set data transfer 4069 * mode to eight bit asynchronous, etc... 4070 * So, just reinitializing all except chip should be enough. 4071 */ 4072 static void sym_int_sbmc (hcb_p np) 4073 { 4074 u_char scsi_mode = INB (nc_stest4) & SMODE; 4075 4076 /* 4077 * Notify user. 4078 */ 4079 xpt_print_path(np->path); 4080 printf("SCSI BUS mode change from %s to %s.\n", 4081 sym_scsi_bus_mode(np->scsi_mode), sym_scsi_bus_mode(scsi_mode)); 4082 4083 /* 4084 * Should suspend command processing for a few seconds and 4085 * reinitialize all except the chip. 4086 */ 4087 sym_init (np, 2); 4088 } 4089 4090 /* 4091 * chip exception handler for SCSI parity error. 4092 * 4093 * When the chip detects a SCSI parity error and is 4094 * currently executing a (CH)MOV instruction, it does 4095 * not interrupt immediately, but tries to finish the 4096 * transfer of the current scatter entry before 4097 * interrupting. The following situations may occur: 4098 * 4099 * - The complete scatter entry has been transferred 4100 * without the device having changed phase. 4101 * The chip will then interrupt with the DSP pointing 4102 * to the instruction that follows the MOV. 4103 * 4104 * - A phase mismatch occurs before the MOV finished 4105 * and phase errors are to be handled by the C code. 4106 * The chip will then interrupt with both PAR and MA 4107 * conditions set. 4108 * 4109 * - A phase mismatch occurs before the MOV finished and 4110 * phase errors are to be handled by SCRIPTS. 4111 * The chip will load the DSP with the phase mismatch 4112 * JUMP address and interrupt the host processor. 4113 */ 4114 static void sym_int_par (hcb_p np, u_short sist) 4115 { 4116 u_char hsts = INB (HS_PRT); 4117 u32 dsp = INL (nc_dsp); 4118 u32 dbc = INL (nc_dbc); 4119 u32 dsa = INL (nc_dsa); 4120 u_char sbcl = INB (nc_sbcl); 4121 u_char cmd = dbc >> 24; 4122 int phase = cmd & 7; 4123 ccb_p cp = sym_ccb_from_dsa(np, dsa); 4124 4125 printf("%s: SCSI parity error detected: SCR1=%d DBC=%x SBCL=%x\n", 4126 sym_name(np), hsts, dbc, sbcl); 4127 4128 /* 4129 * Check that the chip is connected to the SCSI BUS. 4130 */ 4131 if (!(INB (nc_scntl1) & ISCON)) { 4132 sym_recover_scsi_int(np, HS_UNEXPECTED); 4133 return; 4134 } 4135 4136 /* 4137 * If the nexus is not clearly identified, reset the bus. 4138 * We will try to do better later. 4139 */ 4140 if (!cp) 4141 goto reset_all; 4142 4143 /* 4144 * Check instruction was a MOV, direction was INPUT and 4145 * ATN is asserted. 4146 */ 4147 if ((cmd & 0xc0) || !(phase & 1) || !(sbcl & 0x8)) 4148 goto reset_all; 4149 4150 /* 4151 * Keep track of the parity error. 4152 */ 4153 OUTONB (HF_PRT, HF_EXT_ERR); 4154 cp->xerr_status |= XE_PARITY_ERR; 4155 4156 /* 4157 * Prepare the message to send to the device. 4158 */ 4159 np->msgout[0] = (phase == 7) ? M_PARITY : M_ID_ERROR; 4160 4161 /* 4162 * If the old phase was DATA IN phase, we have to deal with 4163 * the 3 situations described above. 4164 * For other input phases (MSG IN and STATUS), the device 4165 * must resend the whole thing that failed parity checking 4166 * or signal error. So, jumping to dispatcher should be OK. 4167 */ 4168 if (phase == 1 || phase == 5) { 4169 /* Phase mismatch handled by SCRIPTS */ 4170 if (dsp == SCRIPTB_BA (np, pm_handle)) 4171 OUTL_DSP (dsp); 4172 /* Phase mismatch handled by the C code */ 4173 else if (sist & MA) 4174 sym_int_ma (np); 4175 /* No phase mismatch occurred */ 4176 else { 4177 OUTL (nc_temp, dsp); 4178 OUTL_DSP (SCRIPTA_BA (np, dispatch)); 4179 } 4180 } 4181 else 4182 OUTL_DSP (SCRIPTA_BA (np, clrack)); 4183 return; 4184 4185 reset_all: 4186 sym_start_reset(np); 4187 } 4188 4189 /* 4190 * chip exception handler for phase errors. 4191 * 4192 * We have to construct a new transfer descriptor, 4193 * to transfer the rest of the current block. 4194 */ 4195 static void sym_int_ma (hcb_p np) 4196 { 4197 u32 dbc; 4198 u32 rest; 4199 u32 dsp; 4200 u32 dsa; 4201 u32 nxtdsp; 4202 u32 *vdsp; 4203 u32 oadr, olen; 4204 u32 *tblp; 4205 u32 newcmd; 4206 u_int delta; 4207 u_char cmd; 4208 u_char hflags, hflags0; 4209 struct sym_pmc *pm; 4210 ccb_p cp; 4211 4212 dsp = INL (nc_dsp); 4213 dbc = INL (nc_dbc); 4214 dsa = INL (nc_dsa); 4215 4216 cmd = dbc >> 24; 4217 rest = dbc & 0xffffff; 4218 delta = 0; 4219 4220 /* 4221 * locate matching cp if any. 4222 */ 4223 cp = sym_ccb_from_dsa(np, dsa); 4224 4225 /* 4226 * Donnot take into account dma fifo and various buffers in 4227 * INPUT phase since the chip flushes everything before 4228 * raising the MA interrupt for interrupted INPUT phases. 4229 * For DATA IN phase, we will check for the SWIDE later. 4230 */ 4231 if ((cmd & 7) != 1 && (cmd & 7) != 5) { 4232 u_char ss0, ss2; 4233 4234 if (np->features & FE_DFBC) 4235 delta = INW (nc_dfbc); 4236 else { 4237 u32 dfifo; 4238 4239 /* 4240 * Read DFIFO, CTEST[4-6] using 1 PCI bus ownership. 4241 */ 4242 dfifo = INL(nc_dfifo); 4243 4244 /* 4245 * Calculate remaining bytes in DMA fifo. 4246 * (CTEST5 = dfifo >> 16) 4247 */ 4248 if (dfifo & (DFS << 16)) 4249 delta = ((((dfifo >> 8) & 0x300) | 4250 (dfifo & 0xff)) - rest) & 0x3ff; 4251 else 4252 delta = ((dfifo & 0xff) - rest) & 0x7f; 4253 } 4254 4255 /* 4256 * The data in the dma fifo has not been transferred to 4257 * the target -> add the amount to the rest 4258 * and clear the data. 4259 * Check the sstat2 register in case of wide transfer. 4260 */ 4261 rest += delta; 4262 ss0 = INB (nc_sstat0); 4263 if (ss0 & OLF) rest++; 4264 if (!(np->features & FE_C10)) 4265 if (ss0 & ORF) rest++; 4266 if (cp && (cp->phys.select.sel_scntl3 & EWS)) { 4267 ss2 = INB (nc_sstat2); 4268 if (ss2 & OLF1) rest++; 4269 if (!(np->features & FE_C10)) 4270 if (ss2 & ORF1) rest++; 4271 } 4272 4273 /* 4274 * Clear fifos. 4275 */ 4276 OUTB (nc_ctest3, np->rv_ctest3 | CLF); /* dma fifo */ 4277 OUTB (nc_stest3, TE|CSF); /* scsi fifo */ 4278 } 4279 4280 /* 4281 * log the information 4282 */ 4283 if (DEBUG_FLAGS & (DEBUG_TINY|DEBUG_PHASE)) 4284 printf ("P%x%x RL=%d D=%d ", cmd&7, INB(nc_sbcl)&7, 4285 (unsigned) rest, (unsigned) delta); 4286 4287 /* 4288 * try to find the interrupted script command, 4289 * and the address at which to continue. 4290 */ 4291 vdsp = NULL; 4292 nxtdsp = 0; 4293 if (dsp > np->scripta_ba && 4294 dsp <= np->scripta_ba + np->scripta_sz) { 4295 vdsp = (u32 *)((char*)np->scripta0 + (dsp-np->scripta_ba-8)); 4296 nxtdsp = dsp; 4297 } 4298 else if (dsp > np->scriptb_ba && 4299 dsp <= np->scriptb_ba + np->scriptb_sz) { 4300 vdsp = (u32 *)((char*)np->scriptb0 + (dsp-np->scriptb_ba-8)); 4301 nxtdsp = dsp; 4302 } 4303 4304 /* 4305 * log the information 4306 */ 4307 if (DEBUG_FLAGS & DEBUG_PHASE) { 4308 printf ("\nCP=%p DSP=%x NXT=%x VDSP=%p CMD=%x ", 4309 cp, (unsigned)dsp, (unsigned)nxtdsp, vdsp, cmd); 4310 } 4311 4312 if (!vdsp) { 4313 printf ("%s: interrupted SCRIPT address not found.\n", 4314 sym_name (np)); 4315 goto reset_all; 4316 } 4317 4318 if (!cp) { 4319 printf ("%s: SCSI phase error fixup: CCB already dequeued.\n", 4320 sym_name (np)); 4321 goto reset_all; 4322 } 4323 4324 /* 4325 * get old startaddress and old length. 4326 */ 4327 oadr = scr_to_cpu(vdsp[1]); 4328 4329 if (cmd & 0x10) { /* Table indirect */ 4330 tblp = (u32 *) ((char*) &cp->phys + oadr); 4331 olen = scr_to_cpu(tblp[0]); 4332 oadr = scr_to_cpu(tblp[1]); 4333 } else { 4334 tblp = (u32 *) 0; 4335 olen = scr_to_cpu(vdsp[0]) & 0xffffff; 4336 } 4337 4338 if (DEBUG_FLAGS & DEBUG_PHASE) { 4339 printf ("OCMD=%x\nTBLP=%p OLEN=%x OADR=%x\n", 4340 (unsigned) (scr_to_cpu(vdsp[0]) >> 24), 4341 tblp, 4342 (unsigned) olen, 4343 (unsigned) oadr); 4344 } 4345 4346 /* 4347 * check cmd against assumed interrupted script command. 4348 * If dt data phase, the MOVE instruction hasn't bit 4 of 4349 * the phase. 4350 */ 4351 if (((cmd & 2) ? cmd : (cmd & ~4)) != (scr_to_cpu(vdsp[0]) >> 24)) { 4352 PRINT_ADDR(cp); 4353 printf ("internal error: cmd=%02x != %02x=(vdsp[0] >> 24)\n", 4354 (unsigned)cmd, (unsigned)scr_to_cpu(vdsp[0]) >> 24); 4355 4356 goto reset_all; 4357 } 4358 4359 /* 4360 * if old phase not dataphase, leave here. 4361 */ 4362 if (cmd & 2) { 4363 PRINT_ADDR(cp); 4364 printf ("phase change %x-%x %d@%08x resid=%d.\n", 4365 cmd&7, INB(nc_sbcl)&7, (unsigned)olen, 4366 (unsigned)oadr, (unsigned)rest); 4367 goto unexpected_phase; 4368 } 4369 4370 /* 4371 * Choose the correct PM save area. 4372 * 4373 * Look at the PM_SAVE SCRIPT if you want to understand 4374 * this stuff. The equivalent code is implemented in 4375 * SCRIPTS for the 895A, 896 and 1010 that are able to 4376 * handle PM from the SCRIPTS processor. 4377 */ 4378 hflags0 = INB (HF_PRT); 4379 hflags = hflags0; 4380 4381 if (hflags & (HF_IN_PM0 | HF_IN_PM1 | HF_DP_SAVED)) { 4382 if (hflags & HF_IN_PM0) 4383 nxtdsp = scr_to_cpu(cp->phys.pm0.ret); 4384 else if (hflags & HF_IN_PM1) 4385 nxtdsp = scr_to_cpu(cp->phys.pm1.ret); 4386 4387 if (hflags & HF_DP_SAVED) 4388 hflags ^= HF_ACT_PM; 4389 } 4390 4391 if (!(hflags & HF_ACT_PM)) { 4392 pm = &cp->phys.pm0; 4393 newcmd = SCRIPTA_BA (np, pm0_data); 4394 } 4395 else { 4396 pm = &cp->phys.pm1; 4397 newcmd = SCRIPTA_BA (np, pm1_data); 4398 } 4399 4400 hflags &= ~(HF_IN_PM0 | HF_IN_PM1 | HF_DP_SAVED); 4401 if (hflags != hflags0) 4402 OUTB (HF_PRT, hflags); 4403 4404 /* 4405 * fillin the phase mismatch context 4406 */ 4407 pm->sg.addr = cpu_to_scr(oadr + olen - rest); 4408 pm->sg.size = cpu_to_scr(rest); 4409 pm->ret = cpu_to_scr(nxtdsp); 4410 4411 /* 4412 * If we have a SWIDE, 4413 * - prepare the address to write the SWIDE from SCRIPTS, 4414 * - compute the SCRIPTS address to restart from, 4415 * - move current data pointer context by one byte. 4416 */ 4417 nxtdsp = SCRIPTA_BA (np, dispatch); 4418 if ((cmd & 7) == 1 && cp && (cp->phys.select.sel_scntl3 & EWS) && 4419 (INB (nc_scntl2) & WSR)) { 4420 u32 tmp; 4421 4422 /* 4423 * Set up the table indirect for the MOVE 4424 * of the residual byte and adjust the data 4425 * pointer context. 4426 */ 4427 tmp = scr_to_cpu(pm->sg.addr); 4428 cp->phys.wresid.addr = cpu_to_scr(tmp); 4429 pm->sg.addr = cpu_to_scr(tmp + 1); 4430 tmp = scr_to_cpu(pm->sg.size); 4431 cp->phys.wresid.size = cpu_to_scr((tmp&0xff000000) | 1); 4432 pm->sg.size = cpu_to_scr(tmp - 1); 4433 4434 /* 4435 * If only the residual byte is to be moved, 4436 * no PM context is needed. 4437 */ 4438 if ((tmp&0xffffff) == 1) 4439 newcmd = pm->ret; 4440 4441 /* 4442 * Prepare the address of SCRIPTS that will 4443 * move the residual byte to memory. 4444 */ 4445 nxtdsp = SCRIPTB_BA (np, wsr_ma_helper); 4446 } 4447 4448 if (DEBUG_FLAGS & DEBUG_PHASE) { 4449 PRINT_ADDR(cp); 4450 printf ("PM %x %x %x / %x %x %x.\n", 4451 hflags0, hflags, newcmd, 4452 (unsigned)scr_to_cpu(pm->sg.addr), 4453 (unsigned)scr_to_cpu(pm->sg.size), 4454 (unsigned)scr_to_cpu(pm->ret)); 4455 } 4456 4457 /* 4458 * Restart the SCRIPTS processor. 4459 */ 4460 OUTL (nc_temp, newcmd); 4461 OUTL_DSP (nxtdsp); 4462 return; 4463 4464 /* 4465 * Unexpected phase changes that occurs when the current phase 4466 * is not a DATA IN or DATA OUT phase are due to error conditions. 4467 * Such event may only happen when the SCRIPTS is using a 4468 * multibyte SCSI MOVE. 4469 * 4470 * Phase change Some possible cause 4471 * 4472 * COMMAND --> MSG IN SCSI parity error detected by target. 4473 * COMMAND --> STATUS Bad command or refused by target. 4474 * MSG OUT --> MSG IN Message rejected by target. 4475 * MSG OUT --> COMMAND Bogus target that discards extended 4476 * negotiation messages. 4477 * 4478 * The code below does not care of the new phase and so 4479 * trusts the target. Why to annoy it ? 4480 * If the interrupted phase is COMMAND phase, we restart at 4481 * dispatcher. 4482 * If a target does not get all the messages after selection, 4483 * the code assumes blindly that the target discards extended 4484 * messages and clears the negotiation status. 4485 * If the target does not want all our response to negotiation, 4486 * we force a SIR_NEGO_PROTO interrupt (it is a hack that avoids 4487 * bloat for such a should_not_happen situation). 4488 * In all other situation, we reset the BUS. 4489 * Are these assumptions reasonnable ? (Wait and see ...) 4490 */ 4491 unexpected_phase: 4492 dsp -= 8; 4493 nxtdsp = 0; 4494 4495 switch (cmd & 7) { 4496 case 2: /* COMMAND phase */ 4497 nxtdsp = SCRIPTA_BA (np, dispatch); 4498 break; 4499 #if 0 4500 case 3: /* STATUS phase */ 4501 nxtdsp = SCRIPTA_BA (np, dispatch); 4502 break; 4503 #endif 4504 case 6: /* MSG OUT phase */ 4505 /* 4506 * If the device may want to use untagged when we want 4507 * tagged, we prepare an IDENTIFY without disc. granted, 4508 * since we will not be able to handle reselect. 4509 * Otherwise, we just don't care. 4510 */ 4511 if (dsp == SCRIPTA_BA (np, send_ident)) { 4512 if (cp->tag != NO_TAG && olen - rest <= 3) { 4513 cp->host_status = HS_BUSY; 4514 np->msgout[0] = M_IDENTIFY | cp->lun; 4515 nxtdsp = SCRIPTB_BA (np, ident_break_atn); 4516 } 4517 else 4518 nxtdsp = SCRIPTB_BA (np, ident_break); 4519 } 4520 else if (dsp == SCRIPTB_BA (np, send_wdtr) || 4521 dsp == SCRIPTB_BA (np, send_sdtr) || 4522 dsp == SCRIPTB_BA (np, send_ppr)) { 4523 nxtdsp = SCRIPTB_BA (np, nego_bad_phase); 4524 } 4525 break; 4526 #if 0 4527 case 7: /* MSG IN phase */ 4528 nxtdsp = SCRIPTA_BA (np, clrack); 4529 break; 4530 #endif 4531 } 4532 4533 if (nxtdsp) { 4534 OUTL_DSP (nxtdsp); 4535 return; 4536 } 4537 4538 reset_all: 4539 sym_start_reset(np); 4540 } 4541 4542 /* 4543 * Dequeue from the START queue all CCBs that match 4544 * a given target/lun/task condition (-1 means all), 4545 * and move them from the BUSY queue to the COMP queue 4546 * with CAM_REQUEUE_REQ status condition. 4547 * This function is used during error handling/recovery. 4548 * It is called with SCRIPTS not running. 4549 */ 4550 static int 4551 sym_dequeue_from_squeue(hcb_p np, int i, int target, int lun, int task) 4552 { 4553 int j; 4554 ccb_p cp; 4555 4556 /* 4557 * Make sure the starting index is within range. 4558 */ 4559 assert((i >= 0) && (i < 2*MAX_QUEUE)); 4560 4561 /* 4562 * Walk until end of START queue and dequeue every job 4563 * that matches the target/lun/task condition. 4564 */ 4565 j = i; 4566 while (i != np->squeueput) { 4567 cp = sym_ccb_from_dsa(np, scr_to_cpu(np->squeue[i])); 4568 assert(cp); 4569 #ifdef SYM_CONF_IARB_SUPPORT 4570 /* Forget hints for IARB, they may be no longer relevant */ 4571 cp->host_flags &= ~HF_HINT_IARB; 4572 #endif 4573 if ((target == -1 || cp->target == target) && 4574 (lun == -1 || cp->lun == lun) && 4575 (task == -1 || cp->tag == task)) { 4576 sym_set_cam_status(cp->cam_ccb, CAM_REQUEUE_REQ); 4577 sym_remque(&cp->link_ccbq); 4578 sym_insque_tail(&cp->link_ccbq, &np->comp_ccbq); 4579 } 4580 else { 4581 if (i != j) 4582 np->squeue[j] = np->squeue[i]; 4583 if ((j += 2) >= MAX_QUEUE*2) j = 0; 4584 } 4585 if ((i += 2) >= MAX_QUEUE*2) i = 0; 4586 } 4587 if (i != j) /* Copy back the idle task if needed */ 4588 np->squeue[j] = np->squeue[i]; 4589 np->squeueput = j; /* Update our current start queue pointer */ 4590 4591 return (i - j) / 2; 4592 } 4593 4594 /* 4595 * Complete all CCBs queued to the COMP queue. 4596 * 4597 * These CCBs are assumed: 4598 * - Not to be referenced either by devices or 4599 * SCRIPTS-related queues and datas. 4600 * - To have to be completed with an error condition 4601 * or requeued. 4602 * 4603 * The device queue freeze count is incremented 4604 * for each CCB that does not prevent this. 4605 * This function is called when all CCBs involved 4606 * in error handling/recovery have been reaped. 4607 */ 4608 static void 4609 sym_flush_comp_queue(hcb_p np, int cam_status) 4610 { 4611 SYM_QUEHEAD *qp; 4612 ccb_p cp; 4613 4614 while ((qp = sym_remque_head(&np->comp_ccbq)) != NULL) { 4615 union ccb *ccb; 4616 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 4617 sym_insque_tail(&cp->link_ccbq, &np->busy_ccbq); 4618 /* Leave quiet CCBs waiting for resources */ 4619 if (cp->host_status == HS_WAIT) 4620 continue; 4621 ccb = cp->cam_ccb; 4622 if (cam_status) 4623 sym_set_cam_status(ccb, cam_status); 4624 sym_freeze_cam_ccb(ccb); 4625 sym_xpt_done(np, ccb, cp); 4626 sym_free_ccb(np, cp); 4627 } 4628 } 4629 4630 /* 4631 * chip handler for bad SCSI status condition 4632 * 4633 * In case of bad SCSI status, we unqueue all the tasks 4634 * currently queued to the controller but not yet started 4635 * and then restart the SCRIPTS processor immediately. 4636 * 4637 * QUEUE FULL and BUSY conditions are handled the same way. 4638 * Basically all the not yet started tasks are requeued in 4639 * device queue and the queue is frozen until a completion. 4640 * 4641 * For CHECK CONDITION and COMMAND TERMINATED status, we use 4642 * the CCB of the failed command to prepare a REQUEST SENSE 4643 * SCSI command and queue it to the controller queue. 4644 * 4645 * SCRATCHA is assumed to have been loaded with STARTPOS 4646 * before the SCRIPTS called the C code. 4647 */ 4648 static void sym_sir_bad_scsi_status(hcb_p np, ccb_p cp) 4649 { 4650 tcb_p tp = &np->target[cp->target]; 4651 u32 startp; 4652 u_char s_status = cp->ssss_status; 4653 u_char h_flags = cp->host_flags; 4654 int msglen; 4655 int nego; 4656 int i; 4657 4658 SYM_LOCK_ASSERT(MA_OWNED); 4659 4660 /* 4661 * Compute the index of the next job to start from SCRIPTS. 4662 */ 4663 i = (INL (nc_scratcha) - np->squeue_ba) / 4; 4664 4665 /* 4666 * The last CCB queued used for IARB hint may be 4667 * no longer relevant. Forget it. 4668 */ 4669 #ifdef SYM_CONF_IARB_SUPPORT 4670 if (np->last_cp) 4671 np->last_cp = NULL; 4672 #endif 4673 4674 /* 4675 * Now deal with the SCSI status. 4676 */ 4677 switch(s_status) { 4678 case S_BUSY: 4679 case S_QUEUE_FULL: 4680 if (sym_verbose >= 2) { 4681 PRINT_ADDR(cp); 4682 printf (s_status == S_BUSY ? "BUSY" : "QUEUE FULL\n"); 4683 } 4684 default: /* S_INT, S_INT_COND_MET, S_CONFLICT */ 4685 sym_complete_error (np, cp); 4686 break; 4687 case S_TERMINATED: 4688 case S_CHECK_COND: 4689 /* 4690 * If we get an SCSI error when requesting sense, give up. 4691 */ 4692 if (h_flags & HF_SENSE) { 4693 sym_complete_error (np, cp); 4694 break; 4695 } 4696 4697 /* 4698 * Dequeue all queued CCBs for that device not yet started, 4699 * and restart the SCRIPTS processor immediately. 4700 */ 4701 (void) sym_dequeue_from_squeue(np, i, cp->target, cp->lun, -1); 4702 OUTL_DSP (SCRIPTA_BA (np, start)); 4703 4704 /* 4705 * Save some info of the actual IO. 4706 * Compute the data residual. 4707 */ 4708 cp->sv_scsi_status = cp->ssss_status; 4709 cp->sv_xerr_status = cp->xerr_status; 4710 cp->sv_resid = sym_compute_residual(np, cp); 4711 4712 /* 4713 * Prepare all needed data structures for 4714 * requesting sense data. 4715 */ 4716 4717 /* 4718 * identify message 4719 */ 4720 cp->scsi_smsg2[0] = M_IDENTIFY | cp->lun; 4721 msglen = 1; 4722 4723 /* 4724 * If we are currently using anything different from 4725 * async. 8 bit data transfers with that target, 4726 * start a negotiation, since the device may want 4727 * to report us a UNIT ATTENTION condition due to 4728 * a cause we currently ignore, and we donnot want 4729 * to be stuck with WIDE and/or SYNC data transfer. 4730 * 4731 * cp->nego_status is filled by sym_prepare_nego(). 4732 */ 4733 cp->nego_status = 0; 4734 nego = 0; 4735 if (tp->tinfo.current.options & PPR_OPT_MASK) 4736 nego = NS_PPR; 4737 else if (tp->tinfo.current.width != BUS_8_BIT) 4738 nego = NS_WIDE; 4739 else if (tp->tinfo.current.offset != 0) 4740 nego = NS_SYNC; 4741 if (nego) 4742 msglen += 4743 sym_prepare_nego (np,cp, nego, &cp->scsi_smsg2[msglen]); 4744 /* 4745 * Message table indirect structure. 4746 */ 4747 cp->phys.smsg.addr = cpu_to_scr(CCB_BA (cp, scsi_smsg2)); 4748 cp->phys.smsg.size = cpu_to_scr(msglen); 4749 4750 /* 4751 * sense command 4752 */ 4753 cp->phys.cmd.addr = cpu_to_scr(CCB_BA (cp, sensecmd)); 4754 cp->phys.cmd.size = cpu_to_scr(6); 4755 4756 /* 4757 * patch requested size into sense command 4758 */ 4759 cp->sensecmd[0] = 0x03; 4760 cp->sensecmd[1] = cp->lun << 5; 4761 if (tp->tinfo.current.scsi_version > 2 || cp->lun > 7) 4762 cp->sensecmd[1] = 0; 4763 cp->sensecmd[4] = SYM_SNS_BBUF_LEN; 4764 cp->data_len = SYM_SNS_BBUF_LEN; 4765 4766 /* 4767 * sense data 4768 */ 4769 bzero(cp->sns_bbuf, SYM_SNS_BBUF_LEN); 4770 cp->phys.sense.addr = cpu_to_scr(vtobus(cp->sns_bbuf)); 4771 cp->phys.sense.size = cpu_to_scr(SYM_SNS_BBUF_LEN); 4772 4773 /* 4774 * requeue the command. 4775 */ 4776 startp = SCRIPTB_BA (np, sdata_in); 4777 4778 cp->phys.head.savep = cpu_to_scr(startp); 4779 cp->phys.head.goalp = cpu_to_scr(startp + 16); 4780 cp->phys.head.lastp = cpu_to_scr(startp); 4781 cp->startp = cpu_to_scr(startp); 4782 4783 cp->actualquirks = SYM_QUIRK_AUTOSAVE; 4784 cp->host_status = cp->nego_status ? HS_NEGOTIATE : HS_BUSY; 4785 cp->ssss_status = S_ILLEGAL; 4786 cp->host_flags = (HF_SENSE|HF_DATA_IN); 4787 cp->xerr_status = 0; 4788 cp->extra_bytes = 0; 4789 4790 cp->phys.head.go.start = cpu_to_scr(SCRIPTA_BA (np, select)); 4791 4792 /* 4793 * Requeue the command. 4794 */ 4795 sym_put_start_queue(np, cp); 4796 4797 /* 4798 * Give back to upper layer everything we have dequeued. 4799 */ 4800 sym_flush_comp_queue(np, 0); 4801 break; 4802 } 4803 } 4804 4805 /* 4806 * After a device has accepted some management message 4807 * as BUS DEVICE RESET, ABORT TASK, etc ..., or when 4808 * a device signals a UNIT ATTENTION condition, some 4809 * tasks are thrown away by the device. We are required 4810 * to reflect that on our tasks list since the device 4811 * will never complete these tasks. 4812 * 4813 * This function move from the BUSY queue to the COMP 4814 * queue all disconnected CCBs for a given target that 4815 * match the following criteria: 4816 * - lun=-1 means any logical UNIT otherwise a given one. 4817 * - task=-1 means any task, otherwise a given one. 4818 */ 4819 static int 4820 sym_clear_tasks(hcb_p np, int cam_status, int target, int lun, int task) 4821 { 4822 SYM_QUEHEAD qtmp, *qp; 4823 int i = 0; 4824 ccb_p cp; 4825 4826 /* 4827 * Move the entire BUSY queue to our temporary queue. 4828 */ 4829 sym_que_init(&qtmp); 4830 sym_que_splice(&np->busy_ccbq, &qtmp); 4831 sym_que_init(&np->busy_ccbq); 4832 4833 /* 4834 * Put all CCBs that matches our criteria into 4835 * the COMP queue and put back other ones into 4836 * the BUSY queue. 4837 */ 4838 while ((qp = sym_remque_head(&qtmp)) != NULL) { 4839 union ccb *ccb; 4840 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 4841 ccb = cp->cam_ccb; 4842 if (cp->host_status != HS_DISCONNECT || 4843 cp->target != target || 4844 (lun != -1 && cp->lun != lun) || 4845 (task != -1 && 4846 (cp->tag != NO_TAG && cp->scsi_smsg[2] != task))) { 4847 sym_insque_tail(&cp->link_ccbq, &np->busy_ccbq); 4848 continue; 4849 } 4850 sym_insque_tail(&cp->link_ccbq, &np->comp_ccbq); 4851 4852 /* Preserve the software timeout condition */ 4853 if (sym_get_cam_status(ccb) != CAM_CMD_TIMEOUT) 4854 sym_set_cam_status(ccb, cam_status); 4855 ++i; 4856 #if 0 4857 printf("XXXX TASK @%p CLEARED\n", cp); 4858 #endif 4859 } 4860 return i; 4861 } 4862 4863 /* 4864 * chip handler for TASKS recovery 4865 * 4866 * We cannot safely abort a command, while the SCRIPTS 4867 * processor is running, since we just would be in race 4868 * with it. 4869 * 4870 * As long as we have tasks to abort, we keep the SEM 4871 * bit set in the ISTAT. When this bit is set, the 4872 * SCRIPTS processor interrupts (SIR_SCRIPT_STOPPED) 4873 * each time it enters the scheduler. 4874 * 4875 * If we have to reset a target, clear tasks of a unit, 4876 * or to perform the abort of a disconnected job, we 4877 * restart the SCRIPTS for selecting the target. Once 4878 * selected, the SCRIPTS interrupts (SIR_TARGET_SELECTED). 4879 * If it loses arbitration, the SCRIPTS will interrupt again 4880 * the next time it will enter its scheduler, and so on ... 4881 * 4882 * On SIR_TARGET_SELECTED, we scan for the more 4883 * appropriate thing to do: 4884 * 4885 * - If nothing, we just sent a M_ABORT message to the 4886 * target to get rid of the useless SCSI bus ownership. 4887 * According to the specs, no tasks shall be affected. 4888 * - If the target is to be reset, we send it a M_RESET 4889 * message. 4890 * - If a logical UNIT is to be cleared , we send the 4891 * IDENTIFY(lun) + M_ABORT. 4892 * - If an untagged task is to be aborted, we send the 4893 * IDENTIFY(lun) + M_ABORT. 4894 * - If a tagged task is to be aborted, we send the 4895 * IDENTIFY(lun) + task attributes + M_ABORT_TAG. 4896 * 4897 * Once our 'kiss of death' :) message has been accepted 4898 * by the target, the SCRIPTS interrupts again 4899 * (SIR_ABORT_SENT). On this interrupt, we complete 4900 * all the CCBs that should have been aborted by the 4901 * target according to our message. 4902 */ 4903 static void sym_sir_task_recovery(hcb_p np, int num) 4904 { 4905 SYM_QUEHEAD *qp; 4906 ccb_p cp; 4907 tcb_p tp; 4908 int target=-1, lun=-1, task; 4909 int i, k; 4910 4911 switch(num) { 4912 /* 4913 * The SCRIPTS processor stopped before starting 4914 * the next command in order to allow us to perform 4915 * some task recovery. 4916 */ 4917 case SIR_SCRIPT_STOPPED: 4918 /* 4919 * Do we have any target to reset or unit to clear ? 4920 */ 4921 for (i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) { 4922 tp = &np->target[i]; 4923 if (tp->to_reset || 4924 (tp->lun0p && tp->lun0p->to_clear)) { 4925 target = i; 4926 break; 4927 } 4928 if (!tp->lunmp) 4929 continue; 4930 for (k = 1 ; k < SYM_CONF_MAX_LUN ; k++) { 4931 if (tp->lunmp[k] && tp->lunmp[k]->to_clear) { 4932 target = i; 4933 break; 4934 } 4935 } 4936 if (target != -1) 4937 break; 4938 } 4939 4940 /* 4941 * If not, walk the busy queue for any 4942 * disconnected CCB to be aborted. 4943 */ 4944 if (target == -1) { 4945 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) { 4946 cp = sym_que_entry(qp,struct sym_ccb,link_ccbq); 4947 if (cp->host_status != HS_DISCONNECT) 4948 continue; 4949 if (cp->to_abort) { 4950 target = cp->target; 4951 break; 4952 } 4953 } 4954 } 4955 4956 /* 4957 * If some target is to be selected, 4958 * prepare and start the selection. 4959 */ 4960 if (target != -1) { 4961 tp = &np->target[target]; 4962 np->abrt_sel.sel_id = target; 4963 np->abrt_sel.sel_scntl3 = tp->head.wval; 4964 np->abrt_sel.sel_sxfer = tp->head.sval; 4965 OUTL(nc_dsa, np->hcb_ba); 4966 OUTL_DSP (SCRIPTB_BA (np, sel_for_abort)); 4967 return; 4968 } 4969 4970 /* 4971 * Now look for a CCB to abort that haven't started yet. 4972 * Btw, the SCRIPTS processor is still stopped, so 4973 * we are not in race. 4974 */ 4975 i = 0; 4976 cp = NULL; 4977 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) { 4978 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 4979 if (cp->host_status != HS_BUSY && 4980 cp->host_status != HS_NEGOTIATE) 4981 continue; 4982 if (!cp->to_abort) 4983 continue; 4984 #ifdef SYM_CONF_IARB_SUPPORT 4985 /* 4986 * If we are using IMMEDIATE ARBITRATION, we donnot 4987 * want to cancel the last queued CCB, since the 4988 * SCRIPTS may have anticipated the selection. 4989 */ 4990 if (cp == np->last_cp) { 4991 cp->to_abort = 0; 4992 continue; 4993 } 4994 #endif 4995 i = 1; /* Means we have found some */ 4996 break; 4997 } 4998 if (!i) { 4999 /* 5000 * We are done, so we donnot need 5001 * to synchronize with the SCRIPTS anylonger. 5002 * Remove the SEM flag from the ISTAT. 5003 */ 5004 np->istat_sem = 0; 5005 OUTB (nc_istat, SIGP); 5006 break; 5007 } 5008 /* 5009 * Compute index of next position in the start 5010 * queue the SCRIPTS intends to start and dequeue 5011 * all CCBs for that device that haven't been started. 5012 */ 5013 i = (INL (nc_scratcha) - np->squeue_ba) / 4; 5014 i = sym_dequeue_from_squeue(np, i, cp->target, cp->lun, -1); 5015 5016 /* 5017 * Make sure at least our IO to abort has been dequeued. 5018 */ 5019 assert(i && sym_get_cam_status(cp->cam_ccb) == CAM_REQUEUE_REQ); 5020 5021 /* 5022 * Keep track in cam status of the reason of the abort. 5023 */ 5024 if (cp->to_abort == 2) 5025 sym_set_cam_status(cp->cam_ccb, CAM_CMD_TIMEOUT); 5026 else 5027 sym_set_cam_status(cp->cam_ccb, CAM_REQ_ABORTED); 5028 5029 /* 5030 * Complete with error everything that we have dequeued. 5031 */ 5032 sym_flush_comp_queue(np, 0); 5033 break; 5034 /* 5035 * The SCRIPTS processor has selected a target 5036 * we may have some manual recovery to perform for. 5037 */ 5038 case SIR_TARGET_SELECTED: 5039 target = (INB (nc_sdid) & 0xf); 5040 tp = &np->target[target]; 5041 5042 np->abrt_tbl.addr = cpu_to_scr(vtobus(np->abrt_msg)); 5043 5044 /* 5045 * If the target is to be reset, prepare a 5046 * M_RESET message and clear the to_reset flag 5047 * since we donnot expect this operation to fail. 5048 */ 5049 if (tp->to_reset) { 5050 np->abrt_msg[0] = M_RESET; 5051 np->abrt_tbl.size = 1; 5052 tp->to_reset = 0; 5053 break; 5054 } 5055 5056 /* 5057 * Otherwise, look for some logical unit to be cleared. 5058 */ 5059 if (tp->lun0p && tp->lun0p->to_clear) 5060 lun = 0; 5061 else if (tp->lunmp) { 5062 for (k = 1 ; k < SYM_CONF_MAX_LUN ; k++) { 5063 if (tp->lunmp[k] && tp->lunmp[k]->to_clear) { 5064 lun = k; 5065 break; 5066 } 5067 } 5068 } 5069 5070 /* 5071 * If a logical unit is to be cleared, prepare 5072 * an IDENTIFY(lun) + ABORT MESSAGE. 5073 */ 5074 if (lun != -1) { 5075 lcb_p lp = sym_lp(tp, lun); 5076 lp->to_clear = 0; /* We donnot expect to fail here */ 5077 np->abrt_msg[0] = M_IDENTIFY | lun; 5078 np->abrt_msg[1] = M_ABORT; 5079 np->abrt_tbl.size = 2; 5080 break; 5081 } 5082 5083 /* 5084 * Otherwise, look for some disconnected job to 5085 * abort for this target. 5086 */ 5087 i = 0; 5088 cp = NULL; 5089 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) { 5090 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 5091 if (cp->host_status != HS_DISCONNECT) 5092 continue; 5093 if (cp->target != target) 5094 continue; 5095 if (!cp->to_abort) 5096 continue; 5097 i = 1; /* Means we have some */ 5098 break; 5099 } 5100 5101 /* 5102 * If we have none, probably since the device has 5103 * completed the command before we won abitration, 5104 * send a M_ABORT message without IDENTIFY. 5105 * According to the specs, the device must just 5106 * disconnect the BUS and not abort any task. 5107 */ 5108 if (!i) { 5109 np->abrt_msg[0] = M_ABORT; 5110 np->abrt_tbl.size = 1; 5111 break; 5112 } 5113 5114 /* 5115 * We have some task to abort. 5116 * Set the IDENTIFY(lun) 5117 */ 5118 np->abrt_msg[0] = M_IDENTIFY | cp->lun; 5119 5120 /* 5121 * If we want to abort an untagged command, we 5122 * will send an IDENTIFY + M_ABORT. 5123 * Otherwise (tagged command), we will send 5124 * an IDENTIFY + task attributes + ABORT TAG. 5125 */ 5126 if (cp->tag == NO_TAG) { 5127 np->abrt_msg[1] = M_ABORT; 5128 np->abrt_tbl.size = 2; 5129 } 5130 else { 5131 np->abrt_msg[1] = cp->scsi_smsg[1]; 5132 np->abrt_msg[2] = cp->scsi_smsg[2]; 5133 np->abrt_msg[3] = M_ABORT_TAG; 5134 np->abrt_tbl.size = 4; 5135 } 5136 /* 5137 * Keep track of software timeout condition, since the 5138 * peripheral driver may not count retries on abort 5139 * conditions not due to timeout. 5140 */ 5141 if (cp->to_abort == 2) 5142 sym_set_cam_status(cp->cam_ccb, CAM_CMD_TIMEOUT); 5143 cp->to_abort = 0; /* We donnot expect to fail here */ 5144 break; 5145 5146 /* 5147 * The target has accepted our message and switched 5148 * to BUS FREE phase as we expected. 5149 */ 5150 case SIR_ABORT_SENT: 5151 target = (INB (nc_sdid) & 0xf); 5152 tp = &np->target[target]; 5153 5154 /* 5155 ** If we didn't abort anything, leave here. 5156 */ 5157 if (np->abrt_msg[0] == M_ABORT) 5158 break; 5159 5160 /* 5161 * If we sent a M_RESET, then a hardware reset has 5162 * been performed by the target. 5163 * - Reset everything to async 8 bit 5164 * - Tell ourself to negotiate next time :-) 5165 * - Prepare to clear all disconnected CCBs for 5166 * this target from our task list (lun=task=-1) 5167 */ 5168 lun = -1; 5169 task = -1; 5170 if (np->abrt_msg[0] == M_RESET) { 5171 tp->head.sval = 0; 5172 tp->head.wval = np->rv_scntl3; 5173 tp->head.uval = 0; 5174 tp->tinfo.current.period = 0; 5175 tp->tinfo.current.offset = 0; 5176 tp->tinfo.current.width = BUS_8_BIT; 5177 tp->tinfo.current.options = 0; 5178 } 5179 5180 /* 5181 * Otherwise, check for the LUN and TASK(s) 5182 * concerned by the cancellation. 5183 * If it is not ABORT_TAG then it is CLEAR_QUEUE 5184 * or an ABORT message :-) 5185 */ 5186 else { 5187 lun = np->abrt_msg[0] & 0x3f; 5188 if (np->abrt_msg[1] == M_ABORT_TAG) 5189 task = np->abrt_msg[2]; 5190 } 5191 5192 /* 5193 * Complete all the CCBs the device should have 5194 * aborted due to our 'kiss of death' message. 5195 */ 5196 i = (INL (nc_scratcha) - np->squeue_ba) / 4; 5197 (void) sym_dequeue_from_squeue(np, i, target, lun, -1); 5198 (void) sym_clear_tasks(np, CAM_REQ_ABORTED, target, lun, task); 5199 sym_flush_comp_queue(np, 0); 5200 5201 /* 5202 * If we sent a BDR, make uper layer aware of that. 5203 */ 5204 if (np->abrt_msg[0] == M_RESET) 5205 xpt_async(AC_SENT_BDR, np->path, NULL); 5206 break; 5207 } 5208 5209 /* 5210 * Print to the log the message we intend to send. 5211 */ 5212 if (num == SIR_TARGET_SELECTED) { 5213 PRINT_TARGET(np, target); 5214 sym_printl_hex("control msgout:", np->abrt_msg, 5215 np->abrt_tbl.size); 5216 np->abrt_tbl.size = cpu_to_scr(np->abrt_tbl.size); 5217 } 5218 5219 /* 5220 * Let the SCRIPTS processor continue. 5221 */ 5222 OUTONB_STD (); 5223 } 5224 5225 /* 5226 * Gerard's alchemy:) that deals with with the data 5227 * pointer for both MDP and the residual calculation. 5228 * 5229 * I didn't want to bloat the code by more than 200 5230 * lignes for the handling of both MDP and the residual. 5231 * This has been achieved by using a data pointer 5232 * representation consisting in an index in the data 5233 * array (dp_sg) and a negative offset (dp_ofs) that 5234 * have the following meaning: 5235 * 5236 * - dp_sg = SYM_CONF_MAX_SG 5237 * we are at the end of the data script. 5238 * - dp_sg < SYM_CONF_MAX_SG 5239 * dp_sg points to the next entry of the scatter array 5240 * we want to transfer. 5241 * - dp_ofs < 0 5242 * dp_ofs represents the residual of bytes of the 5243 * previous entry scatter entry we will send first. 5244 * - dp_ofs = 0 5245 * no residual to send first. 5246 * 5247 * The function sym_evaluate_dp() accepts an arbitray 5248 * offset (basically from the MDP message) and returns 5249 * the corresponding values of dp_sg and dp_ofs. 5250 */ 5251 static int sym_evaluate_dp(hcb_p np, ccb_p cp, u32 scr, int *ofs) 5252 { 5253 u32 dp_scr; 5254 int dp_ofs, dp_sg, dp_sgmin; 5255 int tmp; 5256 struct sym_pmc *pm; 5257 5258 /* 5259 * Compute the resulted data pointer in term of a script 5260 * address within some DATA script and a signed byte offset. 5261 */ 5262 dp_scr = scr; 5263 dp_ofs = *ofs; 5264 if (dp_scr == SCRIPTA_BA (np, pm0_data)) 5265 pm = &cp->phys.pm0; 5266 else if (dp_scr == SCRIPTA_BA (np, pm1_data)) 5267 pm = &cp->phys.pm1; 5268 else 5269 pm = NULL; 5270 5271 if (pm) { 5272 dp_scr = scr_to_cpu(pm->ret); 5273 dp_ofs -= scr_to_cpu(pm->sg.size); 5274 } 5275 5276 /* 5277 * If we are auto-sensing, then we are done. 5278 */ 5279 if (cp->host_flags & HF_SENSE) { 5280 *ofs = dp_ofs; 5281 return 0; 5282 } 5283 5284 /* 5285 * Deduce the index of the sg entry. 5286 * Keep track of the index of the first valid entry. 5287 * If result is dp_sg = SYM_CONF_MAX_SG, then we are at the 5288 * end of the data. 5289 */ 5290 tmp = scr_to_cpu(cp->phys.head.goalp); 5291 dp_sg = SYM_CONF_MAX_SG; 5292 if (dp_scr != tmp) 5293 dp_sg -= (tmp - 8 - (int)dp_scr) / (2*4); 5294 dp_sgmin = SYM_CONF_MAX_SG - cp->segments; 5295 5296 /* 5297 * Move to the sg entry the data pointer belongs to. 5298 * 5299 * If we are inside the data area, we expect result to be: 5300 * 5301 * Either, 5302 * dp_ofs = 0 and dp_sg is the index of the sg entry 5303 * the data pointer belongs to (or the end of the data) 5304 * Or, 5305 * dp_ofs < 0 and dp_sg is the index of the sg entry 5306 * the data pointer belongs to + 1. 5307 */ 5308 if (dp_ofs < 0) { 5309 int n; 5310 while (dp_sg > dp_sgmin) { 5311 --dp_sg; 5312 tmp = scr_to_cpu(cp->phys.data[dp_sg].size); 5313 n = dp_ofs + (tmp & 0xffffff); 5314 if (n > 0) { 5315 ++dp_sg; 5316 break; 5317 } 5318 dp_ofs = n; 5319 } 5320 } 5321 else if (dp_ofs > 0) { 5322 while (dp_sg < SYM_CONF_MAX_SG) { 5323 tmp = scr_to_cpu(cp->phys.data[dp_sg].size); 5324 dp_ofs -= (tmp & 0xffffff); 5325 ++dp_sg; 5326 if (dp_ofs <= 0) 5327 break; 5328 } 5329 } 5330 5331 /* 5332 * Make sure the data pointer is inside the data area. 5333 * If not, return some error. 5334 */ 5335 if (dp_sg < dp_sgmin || (dp_sg == dp_sgmin && dp_ofs < 0)) 5336 goto out_err; 5337 else if (dp_sg > SYM_CONF_MAX_SG || 5338 (dp_sg == SYM_CONF_MAX_SG && dp_ofs > 0)) 5339 goto out_err; 5340 5341 /* 5342 * Save the extreme pointer if needed. 5343 */ 5344 if (dp_sg > cp->ext_sg || 5345 (dp_sg == cp->ext_sg && dp_ofs > cp->ext_ofs)) { 5346 cp->ext_sg = dp_sg; 5347 cp->ext_ofs = dp_ofs; 5348 } 5349 5350 /* 5351 * Return data. 5352 */ 5353 *ofs = dp_ofs; 5354 return dp_sg; 5355 5356 out_err: 5357 return -1; 5358 } 5359 5360 /* 5361 * chip handler for MODIFY DATA POINTER MESSAGE 5362 * 5363 * We also call this function on IGNORE WIDE RESIDUE 5364 * messages that do not match a SWIDE full condition. 5365 * Btw, we assume in that situation that such a message 5366 * is equivalent to a MODIFY DATA POINTER (offset=-1). 5367 */ 5368 static void sym_modify_dp(hcb_p np, ccb_p cp, int ofs) 5369 { 5370 int dp_ofs = ofs; 5371 u32 dp_scr = INL (nc_temp); 5372 u32 dp_ret; 5373 u32 tmp; 5374 u_char hflags; 5375 int dp_sg; 5376 struct sym_pmc *pm; 5377 5378 /* 5379 * Not supported for auto-sense. 5380 */ 5381 if (cp->host_flags & HF_SENSE) 5382 goto out_reject; 5383 5384 /* 5385 * Apply our alchemy:) (see comments in sym_evaluate_dp()), 5386 * to the resulted data pointer. 5387 */ 5388 dp_sg = sym_evaluate_dp(np, cp, dp_scr, &dp_ofs); 5389 if (dp_sg < 0) 5390 goto out_reject; 5391 5392 /* 5393 * And our alchemy:) allows to easily calculate the data 5394 * script address we want to return for the next data phase. 5395 */ 5396 dp_ret = cpu_to_scr(cp->phys.head.goalp); 5397 dp_ret = dp_ret - 8 - (SYM_CONF_MAX_SG - dp_sg) * (2*4); 5398 5399 /* 5400 * If offset / scatter entry is zero we donnot need 5401 * a context for the new current data pointer. 5402 */ 5403 if (dp_ofs == 0) { 5404 dp_scr = dp_ret; 5405 goto out_ok; 5406 } 5407 5408 /* 5409 * Get a context for the new current data pointer. 5410 */ 5411 hflags = INB (HF_PRT); 5412 5413 if (hflags & HF_DP_SAVED) 5414 hflags ^= HF_ACT_PM; 5415 5416 if (!(hflags & HF_ACT_PM)) { 5417 pm = &cp->phys.pm0; 5418 dp_scr = SCRIPTA_BA (np, pm0_data); 5419 } 5420 else { 5421 pm = &cp->phys.pm1; 5422 dp_scr = SCRIPTA_BA (np, pm1_data); 5423 } 5424 5425 hflags &= ~(HF_DP_SAVED); 5426 5427 OUTB (HF_PRT, hflags); 5428 5429 /* 5430 * Set up the new current data pointer. 5431 * ofs < 0 there, and for the next data phase, we 5432 * want to transfer part of the data of the sg entry 5433 * corresponding to index dp_sg-1 prior to returning 5434 * to the main data script. 5435 */ 5436 pm->ret = cpu_to_scr(dp_ret); 5437 tmp = scr_to_cpu(cp->phys.data[dp_sg-1].addr); 5438 tmp += scr_to_cpu(cp->phys.data[dp_sg-1].size) + dp_ofs; 5439 pm->sg.addr = cpu_to_scr(tmp); 5440 pm->sg.size = cpu_to_scr(-dp_ofs); 5441 5442 out_ok: 5443 OUTL (nc_temp, dp_scr); 5444 OUTL_DSP (SCRIPTA_BA (np, clrack)); 5445 return; 5446 5447 out_reject: 5448 OUTL_DSP (SCRIPTB_BA (np, msg_bad)); 5449 } 5450 5451 /* 5452 * chip calculation of the data residual. 5453 * 5454 * As I used to say, the requirement of data residual 5455 * in SCSI is broken, useless and cannot be achieved 5456 * without huge complexity. 5457 * But most OSes and even the official CAM require it. 5458 * When stupidity happens to be so widely spread inside 5459 * a community, it gets hard to convince. 5460 * 5461 * Anyway, I don't care, since I am not going to use 5462 * any software that considers this data residual as 5463 * a relevant information. :) 5464 */ 5465 static int sym_compute_residual(hcb_p np, ccb_p cp) 5466 { 5467 int dp_sg, dp_sgmin, resid = 0; 5468 int dp_ofs = 0; 5469 5470 /* 5471 * Check for some data lost or just thrown away. 5472 * We are not required to be quite accurate in this 5473 * situation. Btw, if we are odd for output and the 5474 * device claims some more data, it may well happen 5475 * than our residual be zero. :-) 5476 */ 5477 if (cp->xerr_status & (XE_EXTRA_DATA|XE_SODL_UNRUN|XE_SWIDE_OVRUN)) { 5478 if (cp->xerr_status & XE_EXTRA_DATA) 5479 resid -= cp->extra_bytes; 5480 if (cp->xerr_status & XE_SODL_UNRUN) 5481 ++resid; 5482 if (cp->xerr_status & XE_SWIDE_OVRUN) 5483 --resid; 5484 } 5485 5486 /* 5487 * If all data has been transferred, 5488 * there is no residual. 5489 */ 5490 if (cp->phys.head.lastp == cp->phys.head.goalp) 5491 return resid; 5492 5493 /* 5494 * If no data transfer occurs, or if the data 5495 * pointer is weird, return full residual. 5496 */ 5497 if (cp->startp == cp->phys.head.lastp || 5498 sym_evaluate_dp(np, cp, scr_to_cpu(cp->phys.head.lastp), 5499 &dp_ofs) < 0) { 5500 return cp->data_len; 5501 } 5502 5503 /* 5504 * If we were auto-sensing, then we are done. 5505 */ 5506 if (cp->host_flags & HF_SENSE) { 5507 return -dp_ofs; 5508 } 5509 5510 /* 5511 * We are now full comfortable in the computation 5512 * of the data residual (2's complement). 5513 */ 5514 dp_sgmin = SYM_CONF_MAX_SG - cp->segments; 5515 resid = -cp->ext_ofs; 5516 for (dp_sg = cp->ext_sg; dp_sg < SYM_CONF_MAX_SG; ++dp_sg) { 5517 u_int tmp = scr_to_cpu(cp->phys.data[dp_sg].size); 5518 resid += (tmp & 0xffffff); 5519 } 5520 5521 /* 5522 * Hopefully, the result is not too wrong. 5523 */ 5524 return resid; 5525 } 5526 5527 /* 5528 * Print out the content of a SCSI message. 5529 */ 5530 static int sym_show_msg (u_char * msg) 5531 { 5532 u_char i; 5533 printf ("%x",*msg); 5534 if (*msg==M_EXTENDED) { 5535 for (i=1;i<8;i++) { 5536 if (i-1>msg[1]) break; 5537 printf ("-%x",msg[i]); 5538 } 5539 return (i+1); 5540 } else if ((*msg & 0xf0) == 0x20) { 5541 printf ("-%x",msg[1]); 5542 return (2); 5543 } 5544 return (1); 5545 } 5546 5547 static void sym_print_msg (ccb_p cp, char *label, u_char *msg) 5548 { 5549 PRINT_ADDR(cp); 5550 if (label) 5551 printf ("%s: ", label); 5552 5553 (void) sym_show_msg (msg); 5554 printf (".\n"); 5555 } 5556 5557 /* 5558 * Negotiation for WIDE and SYNCHRONOUS DATA TRANSFER. 5559 * 5560 * When we try to negotiate, we append the negotiation message 5561 * to the identify and (maybe) simple tag message. 5562 * The host status field is set to HS_NEGOTIATE to mark this 5563 * situation. 5564 * 5565 * If the target doesn't answer this message immediately 5566 * (as required by the standard), the SIR_NEGO_FAILED interrupt 5567 * will be raised eventually. 5568 * The handler removes the HS_NEGOTIATE status, and sets the 5569 * negotiated value to the default (async / nowide). 5570 * 5571 * If we receive a matching answer immediately, we check it 5572 * for validity, and set the values. 5573 * 5574 * If we receive a Reject message immediately, we assume the 5575 * negotiation has failed, and fall back to standard values. 5576 * 5577 * If we receive a negotiation message while not in HS_NEGOTIATE 5578 * state, it's a target initiated negotiation. We prepare a 5579 * (hopefully) valid answer, set our parameters, and send back 5580 * this answer to the target. 5581 * 5582 * If the target doesn't fetch the answer (no message out phase), 5583 * we assume the negotiation has failed, and fall back to default 5584 * settings (SIR_NEGO_PROTO interrupt). 5585 * 5586 * When we set the values, we adjust them in all ccbs belonging 5587 * to this target, in the controller's register, and in the "phys" 5588 * field of the controller's struct sym_hcb. 5589 */ 5590 5591 /* 5592 * chip handler for SYNCHRONOUS DATA TRANSFER REQUEST (SDTR) message. 5593 */ 5594 static void sym_sync_nego(hcb_p np, tcb_p tp, ccb_p cp) 5595 { 5596 u_char chg, ofs, per, fak, div; 5597 int req = 1; 5598 5599 /* 5600 * Synchronous request message received. 5601 */ 5602 if (DEBUG_FLAGS & DEBUG_NEGO) { 5603 sym_print_msg(cp, "sync msgin", np->msgin); 5604 } 5605 5606 /* 5607 * request or answer ? 5608 */ 5609 if (INB (HS_PRT) == HS_NEGOTIATE) { 5610 OUTB (HS_PRT, HS_BUSY); 5611 if (cp->nego_status && cp->nego_status != NS_SYNC) 5612 goto reject_it; 5613 req = 0; 5614 } 5615 5616 /* 5617 * get requested values. 5618 */ 5619 chg = 0; 5620 per = np->msgin[3]; 5621 ofs = np->msgin[4]; 5622 5623 /* 5624 * check values against our limits. 5625 */ 5626 if (ofs) { 5627 if (ofs > np->maxoffs) 5628 {chg = 1; ofs = np->maxoffs;} 5629 if (req) { 5630 if (ofs > tp->tinfo.user.offset) 5631 {chg = 1; ofs = tp->tinfo.user.offset;} 5632 } 5633 } 5634 5635 if (ofs) { 5636 if (per < np->minsync) 5637 {chg = 1; per = np->minsync;} 5638 if (req) { 5639 if (per < tp->tinfo.user.period) 5640 {chg = 1; per = tp->tinfo.user.period;} 5641 } 5642 } 5643 5644 div = fak = 0; 5645 if (ofs && sym_getsync(np, 0, per, &div, &fak) < 0) 5646 goto reject_it; 5647 5648 if (DEBUG_FLAGS & DEBUG_NEGO) { 5649 PRINT_ADDR(cp); 5650 printf ("sdtr: ofs=%d per=%d div=%d fak=%d chg=%d.\n", 5651 ofs, per, div, fak, chg); 5652 } 5653 5654 /* 5655 * This was an answer message 5656 */ 5657 if (req == 0) { 5658 if (chg) /* Answer wasn't acceptable. */ 5659 goto reject_it; 5660 sym_setsync (np, cp, ofs, per, div, fak); 5661 OUTL_DSP (SCRIPTA_BA (np, clrack)); 5662 return; 5663 } 5664 5665 /* 5666 * It was a request. Set value and 5667 * prepare an answer message 5668 */ 5669 sym_setsync (np, cp, ofs, per, div, fak); 5670 5671 np->msgout[0] = M_EXTENDED; 5672 np->msgout[1] = 3; 5673 np->msgout[2] = M_X_SYNC_REQ; 5674 np->msgout[3] = per; 5675 np->msgout[4] = ofs; 5676 5677 cp->nego_status = NS_SYNC; 5678 5679 if (DEBUG_FLAGS & DEBUG_NEGO) { 5680 sym_print_msg(cp, "sync msgout", np->msgout); 5681 } 5682 5683 np->msgin [0] = M_NOOP; 5684 5685 OUTL_DSP (SCRIPTB_BA (np, sdtr_resp)); 5686 return; 5687 reject_it: 5688 sym_setsync (np, cp, 0, 0, 0, 0); 5689 OUTL_DSP (SCRIPTB_BA (np, msg_bad)); 5690 } 5691 5692 /* 5693 * chip handler for PARALLEL PROTOCOL REQUEST (PPR) message. 5694 */ 5695 static void sym_ppr_nego(hcb_p np, tcb_p tp, ccb_p cp) 5696 { 5697 u_char chg, ofs, per, fak, dt, div, wide; 5698 int req = 1; 5699 5700 /* 5701 * Synchronous request message received. 5702 */ 5703 if (DEBUG_FLAGS & DEBUG_NEGO) { 5704 sym_print_msg(cp, "ppr msgin", np->msgin); 5705 } 5706 5707 /* 5708 * get requested values. 5709 */ 5710 chg = 0; 5711 per = np->msgin[3]; 5712 ofs = np->msgin[5]; 5713 wide = np->msgin[6]; 5714 dt = np->msgin[7] & PPR_OPT_DT; 5715 5716 /* 5717 * request or answer ? 5718 */ 5719 if (INB (HS_PRT) == HS_NEGOTIATE) { 5720 OUTB (HS_PRT, HS_BUSY); 5721 if (cp->nego_status && cp->nego_status != NS_PPR) 5722 goto reject_it; 5723 req = 0; 5724 } 5725 5726 /* 5727 * check values against our limits. 5728 */ 5729 if (wide > np->maxwide) 5730 {chg = 1; wide = np->maxwide;} 5731 if (!wide || !(np->features & FE_ULTRA3)) 5732 dt &= ~PPR_OPT_DT; 5733 if (req) { 5734 if (wide > tp->tinfo.user.width) 5735 {chg = 1; wide = tp->tinfo.user.width;} 5736 } 5737 5738 if (!(np->features & FE_U3EN)) /* Broken U3EN bit not supported */ 5739 dt &= ~PPR_OPT_DT; 5740 5741 if (dt != (np->msgin[7] & PPR_OPT_MASK)) chg = 1; 5742 5743 if (ofs) { 5744 if (dt) { 5745 if (ofs > np->maxoffs_dt) 5746 {chg = 1; ofs = np->maxoffs_dt;} 5747 } 5748 else if (ofs > np->maxoffs) 5749 {chg = 1; ofs = np->maxoffs;} 5750 if (req) { 5751 if (ofs > tp->tinfo.user.offset) 5752 {chg = 1; ofs = tp->tinfo.user.offset;} 5753 } 5754 } 5755 5756 if (ofs) { 5757 if (dt) { 5758 if (per < np->minsync_dt) 5759 {chg = 1; per = np->minsync_dt;} 5760 } 5761 else if (per < np->minsync) 5762 {chg = 1; per = np->minsync;} 5763 if (req) { 5764 if (per < tp->tinfo.user.period) 5765 {chg = 1; per = tp->tinfo.user.period;} 5766 } 5767 } 5768 5769 div = fak = 0; 5770 if (ofs && sym_getsync(np, dt, per, &div, &fak) < 0) 5771 goto reject_it; 5772 5773 if (DEBUG_FLAGS & DEBUG_NEGO) { 5774 PRINT_ADDR(cp); 5775 printf ("ppr: " 5776 "dt=%x ofs=%d per=%d wide=%d div=%d fak=%d chg=%d.\n", 5777 dt, ofs, per, wide, div, fak, chg); 5778 } 5779 5780 /* 5781 * It was an answer. 5782 */ 5783 if (req == 0) { 5784 if (chg) /* Answer wasn't acceptable */ 5785 goto reject_it; 5786 sym_setpprot (np, cp, dt, ofs, per, wide, div, fak); 5787 OUTL_DSP (SCRIPTA_BA (np, clrack)); 5788 return; 5789 } 5790 5791 /* 5792 * It was a request. Set value and 5793 * prepare an answer message 5794 */ 5795 sym_setpprot (np, cp, dt, ofs, per, wide, div, fak); 5796 5797 np->msgout[0] = M_EXTENDED; 5798 np->msgout[1] = 6; 5799 np->msgout[2] = M_X_PPR_REQ; 5800 np->msgout[3] = per; 5801 np->msgout[4] = 0; 5802 np->msgout[5] = ofs; 5803 np->msgout[6] = wide; 5804 np->msgout[7] = dt; 5805 5806 cp->nego_status = NS_PPR; 5807 5808 if (DEBUG_FLAGS & DEBUG_NEGO) { 5809 sym_print_msg(cp, "ppr msgout", np->msgout); 5810 } 5811 5812 np->msgin [0] = M_NOOP; 5813 5814 OUTL_DSP (SCRIPTB_BA (np, ppr_resp)); 5815 return; 5816 reject_it: 5817 sym_setpprot (np, cp, 0, 0, 0, 0, 0, 0); 5818 OUTL_DSP (SCRIPTB_BA (np, msg_bad)); 5819 /* 5820 * If it was a device response that should result in 5821 * ST, we may want to try a legacy negotiation later. 5822 */ 5823 if (!req && !dt) { 5824 tp->tinfo.goal.options = 0; 5825 tp->tinfo.goal.width = wide; 5826 tp->tinfo.goal.period = per; 5827 tp->tinfo.goal.offset = ofs; 5828 } 5829 } 5830 5831 /* 5832 * chip handler for WIDE DATA TRANSFER REQUEST (WDTR) message. 5833 */ 5834 static void sym_wide_nego(hcb_p np, tcb_p tp, ccb_p cp) 5835 { 5836 u_char chg, wide; 5837 int req = 1; 5838 5839 /* 5840 * Wide request message received. 5841 */ 5842 if (DEBUG_FLAGS & DEBUG_NEGO) { 5843 sym_print_msg(cp, "wide msgin", np->msgin); 5844 } 5845 5846 /* 5847 * Is it a request from the device? 5848 */ 5849 if (INB (HS_PRT) == HS_NEGOTIATE) { 5850 OUTB (HS_PRT, HS_BUSY); 5851 if (cp->nego_status && cp->nego_status != NS_WIDE) 5852 goto reject_it; 5853 req = 0; 5854 } 5855 5856 /* 5857 * get requested values. 5858 */ 5859 chg = 0; 5860 wide = np->msgin[3]; 5861 5862 /* 5863 * check values against driver limits. 5864 */ 5865 if (wide > np->maxwide) 5866 {chg = 1; wide = np->maxwide;} 5867 if (req) { 5868 if (wide > tp->tinfo.user.width) 5869 {chg = 1; wide = tp->tinfo.user.width;} 5870 } 5871 5872 if (DEBUG_FLAGS & DEBUG_NEGO) { 5873 PRINT_ADDR(cp); 5874 printf ("wdtr: wide=%d chg=%d.\n", wide, chg); 5875 } 5876 5877 /* 5878 * This was an answer message 5879 */ 5880 if (req == 0) { 5881 if (chg) /* Answer wasn't acceptable. */ 5882 goto reject_it; 5883 sym_setwide (np, cp, wide); 5884 5885 /* 5886 * Negotiate for SYNC immediately after WIDE response. 5887 * This allows to negotiate for both WIDE and SYNC on 5888 * a single SCSI command (Suggested by Justin Gibbs). 5889 */ 5890 if (tp->tinfo.goal.offset) { 5891 np->msgout[0] = M_EXTENDED; 5892 np->msgout[1] = 3; 5893 np->msgout[2] = M_X_SYNC_REQ; 5894 np->msgout[3] = tp->tinfo.goal.period; 5895 np->msgout[4] = tp->tinfo.goal.offset; 5896 5897 if (DEBUG_FLAGS & DEBUG_NEGO) { 5898 sym_print_msg(cp, "sync msgout", np->msgout); 5899 } 5900 5901 cp->nego_status = NS_SYNC; 5902 OUTB (HS_PRT, HS_NEGOTIATE); 5903 OUTL_DSP (SCRIPTB_BA (np, sdtr_resp)); 5904 return; 5905 } 5906 5907 OUTL_DSP (SCRIPTA_BA (np, clrack)); 5908 return; 5909 } 5910 5911 /* 5912 * It was a request, set value and 5913 * prepare an answer message 5914 */ 5915 sym_setwide (np, cp, wide); 5916 5917 np->msgout[0] = M_EXTENDED; 5918 np->msgout[1] = 2; 5919 np->msgout[2] = M_X_WIDE_REQ; 5920 np->msgout[3] = wide; 5921 5922 np->msgin [0] = M_NOOP; 5923 5924 cp->nego_status = NS_WIDE; 5925 5926 if (DEBUG_FLAGS & DEBUG_NEGO) { 5927 sym_print_msg(cp, "wide msgout", np->msgout); 5928 } 5929 5930 OUTL_DSP (SCRIPTB_BA (np, wdtr_resp)); 5931 return; 5932 reject_it: 5933 OUTL_DSP (SCRIPTB_BA (np, msg_bad)); 5934 } 5935 5936 /* 5937 * Reset SYNC or WIDE to default settings. 5938 * 5939 * Called when a negotiation does not succeed either 5940 * on rejection or on protocol error. 5941 * 5942 * If it was a PPR that made problems, we may want to 5943 * try a legacy negotiation later. 5944 */ 5945 static void sym_nego_default(hcb_p np, tcb_p tp, ccb_p cp) 5946 { 5947 /* 5948 * any error in negotiation: 5949 * fall back to default mode. 5950 */ 5951 switch (cp->nego_status) { 5952 case NS_PPR: 5953 #if 0 5954 sym_setpprot (np, cp, 0, 0, 0, 0, 0, 0); 5955 #else 5956 tp->tinfo.goal.options = 0; 5957 if (tp->tinfo.goal.period < np->minsync) 5958 tp->tinfo.goal.period = np->minsync; 5959 if (tp->tinfo.goal.offset > np->maxoffs) 5960 tp->tinfo.goal.offset = np->maxoffs; 5961 #endif 5962 break; 5963 case NS_SYNC: 5964 sym_setsync (np, cp, 0, 0, 0, 0); 5965 break; 5966 case NS_WIDE: 5967 sym_setwide (np, cp, 0); 5968 break; 5969 } 5970 np->msgin [0] = M_NOOP; 5971 np->msgout[0] = M_NOOP; 5972 cp->nego_status = 0; 5973 } 5974 5975 /* 5976 * chip handler for MESSAGE REJECT received in response to 5977 * a WIDE or SYNCHRONOUS negotiation. 5978 */ 5979 static void sym_nego_rejected(hcb_p np, tcb_p tp, ccb_p cp) 5980 { 5981 sym_nego_default(np, tp, cp); 5982 OUTB (HS_PRT, HS_BUSY); 5983 } 5984 5985 /* 5986 * chip exception handler for programmed interrupts. 5987 */ 5988 static void sym_int_sir (hcb_p np) 5989 { 5990 u_char num = INB (nc_dsps); 5991 u32 dsa = INL (nc_dsa); 5992 ccb_p cp = sym_ccb_from_dsa(np, dsa); 5993 u_char target = INB (nc_sdid) & 0x0f; 5994 tcb_p tp = &np->target[target]; 5995 int tmp; 5996 5997 SYM_LOCK_ASSERT(MA_OWNED); 5998 5999 if (DEBUG_FLAGS & DEBUG_TINY) printf ("I#%d", num); 6000 6001 switch (num) { 6002 /* 6003 * Command has been completed with error condition 6004 * or has been auto-sensed. 6005 */ 6006 case SIR_COMPLETE_ERROR: 6007 sym_complete_error(np, cp); 6008 return; 6009 /* 6010 * The C code is currently trying to recover from something. 6011 * Typically, user want to abort some command. 6012 */ 6013 case SIR_SCRIPT_STOPPED: 6014 case SIR_TARGET_SELECTED: 6015 case SIR_ABORT_SENT: 6016 sym_sir_task_recovery(np, num); 6017 return; 6018 /* 6019 * The device didn't go to MSG OUT phase after having 6020 * been selected with ATN. We donnot want to handle 6021 * that. 6022 */ 6023 case SIR_SEL_ATN_NO_MSG_OUT: 6024 printf ("%s:%d: No MSG OUT phase after selection with ATN.\n", 6025 sym_name (np), target); 6026 goto out_stuck; 6027 /* 6028 * The device didn't switch to MSG IN phase after 6029 * having reseleted the initiator. 6030 */ 6031 case SIR_RESEL_NO_MSG_IN: 6032 printf ("%s:%d: No MSG IN phase after reselection.\n", 6033 sym_name (np), target); 6034 goto out_stuck; 6035 /* 6036 * After reselection, the device sent a message that wasn't 6037 * an IDENTIFY. 6038 */ 6039 case SIR_RESEL_NO_IDENTIFY: 6040 printf ("%s:%d: No IDENTIFY after reselection.\n", 6041 sym_name (np), target); 6042 goto out_stuck; 6043 /* 6044 * The device reselected a LUN we donnot know about. 6045 */ 6046 case SIR_RESEL_BAD_LUN: 6047 np->msgout[0] = M_RESET; 6048 goto out; 6049 /* 6050 * The device reselected for an untagged nexus and we 6051 * haven't any. 6052 */ 6053 case SIR_RESEL_BAD_I_T_L: 6054 np->msgout[0] = M_ABORT; 6055 goto out; 6056 /* 6057 * The device reselected for a tagged nexus that we donnot 6058 * have. 6059 */ 6060 case SIR_RESEL_BAD_I_T_L_Q: 6061 np->msgout[0] = M_ABORT_TAG; 6062 goto out; 6063 /* 6064 * The SCRIPTS let us know that the device has grabbed 6065 * our message and will abort the job. 6066 */ 6067 case SIR_RESEL_ABORTED: 6068 np->lastmsg = np->msgout[0]; 6069 np->msgout[0] = M_NOOP; 6070 printf ("%s:%d: message %x sent on bad reselection.\n", 6071 sym_name (np), target, np->lastmsg); 6072 goto out; 6073 /* 6074 * The SCRIPTS let us know that a message has been 6075 * successfully sent to the device. 6076 */ 6077 case SIR_MSG_OUT_DONE: 6078 np->lastmsg = np->msgout[0]; 6079 np->msgout[0] = M_NOOP; 6080 /* Should we really care of that */ 6081 if (np->lastmsg == M_PARITY || np->lastmsg == M_ID_ERROR) { 6082 if (cp) { 6083 cp->xerr_status &= ~XE_PARITY_ERR; 6084 if (!cp->xerr_status) 6085 OUTOFFB (HF_PRT, HF_EXT_ERR); 6086 } 6087 } 6088 goto out; 6089 /* 6090 * The device didn't send a GOOD SCSI status. 6091 * We may have some work to do prior to allow 6092 * the SCRIPTS processor to continue. 6093 */ 6094 case SIR_BAD_SCSI_STATUS: 6095 if (!cp) 6096 goto out; 6097 sym_sir_bad_scsi_status(np, cp); 6098 return; 6099 /* 6100 * We are asked by the SCRIPTS to prepare a 6101 * REJECT message. 6102 */ 6103 case SIR_REJECT_TO_SEND: 6104 sym_print_msg(cp, "M_REJECT to send for ", np->msgin); 6105 np->msgout[0] = M_REJECT; 6106 goto out; 6107 /* 6108 * We have been ODD at the end of a DATA IN 6109 * transfer and the device didn't send a 6110 * IGNORE WIDE RESIDUE message. 6111 * It is a data overrun condition. 6112 */ 6113 case SIR_SWIDE_OVERRUN: 6114 if (cp) { 6115 OUTONB (HF_PRT, HF_EXT_ERR); 6116 cp->xerr_status |= XE_SWIDE_OVRUN; 6117 } 6118 goto out; 6119 /* 6120 * We have been ODD at the end of a DATA OUT 6121 * transfer. 6122 * It is a data underrun condition. 6123 */ 6124 case SIR_SODL_UNDERRUN: 6125 if (cp) { 6126 OUTONB (HF_PRT, HF_EXT_ERR); 6127 cp->xerr_status |= XE_SODL_UNRUN; 6128 } 6129 goto out; 6130 /* 6131 * The device wants us to transfer more data than 6132 * expected or in the wrong direction. 6133 * The number of extra bytes is in scratcha. 6134 * It is a data overrun condition. 6135 */ 6136 case SIR_DATA_OVERRUN: 6137 if (cp) { 6138 OUTONB (HF_PRT, HF_EXT_ERR); 6139 cp->xerr_status |= XE_EXTRA_DATA; 6140 cp->extra_bytes += INL (nc_scratcha); 6141 } 6142 goto out; 6143 /* 6144 * The device switched to an illegal phase (4/5). 6145 */ 6146 case SIR_BAD_PHASE: 6147 if (cp) { 6148 OUTONB (HF_PRT, HF_EXT_ERR); 6149 cp->xerr_status |= XE_BAD_PHASE; 6150 } 6151 goto out; 6152 /* 6153 * We received a message. 6154 */ 6155 case SIR_MSG_RECEIVED: 6156 if (!cp) 6157 goto out_stuck; 6158 switch (np->msgin [0]) { 6159 /* 6160 * We received an extended message. 6161 * We handle MODIFY DATA POINTER, SDTR, WDTR 6162 * and reject all other extended messages. 6163 */ 6164 case M_EXTENDED: 6165 switch (np->msgin [2]) { 6166 case M_X_MODIFY_DP: 6167 if (DEBUG_FLAGS & DEBUG_POINTER) 6168 sym_print_msg(cp,"modify DP",np->msgin); 6169 tmp = (np->msgin[3]<<24) + (np->msgin[4]<<16) + 6170 (np->msgin[5]<<8) + (np->msgin[6]); 6171 sym_modify_dp(np, cp, tmp); 6172 return; 6173 case M_X_SYNC_REQ: 6174 sym_sync_nego(np, tp, cp); 6175 return; 6176 case M_X_PPR_REQ: 6177 sym_ppr_nego(np, tp, cp); 6178 return; 6179 case M_X_WIDE_REQ: 6180 sym_wide_nego(np, tp, cp); 6181 return; 6182 default: 6183 goto out_reject; 6184 } 6185 break; 6186 /* 6187 * We received a 1/2 byte message not handled from SCRIPTS. 6188 * We are only expecting MESSAGE REJECT and IGNORE WIDE 6189 * RESIDUE messages that haven't been anticipated by 6190 * SCRIPTS on SWIDE full condition. Unanticipated IGNORE 6191 * WIDE RESIDUE messages are aliased as MODIFY DP (-1). 6192 */ 6193 case M_IGN_RESIDUE: 6194 if (DEBUG_FLAGS & DEBUG_POINTER) 6195 sym_print_msg(cp,"ign wide residue", np->msgin); 6196 sym_modify_dp(np, cp, -1); 6197 return; 6198 case M_REJECT: 6199 if (INB (HS_PRT) == HS_NEGOTIATE) 6200 sym_nego_rejected(np, tp, cp); 6201 else { 6202 PRINT_ADDR(cp); 6203 printf ("M_REJECT received (%x:%x).\n", 6204 scr_to_cpu(np->lastmsg), np->msgout[0]); 6205 } 6206 goto out_clrack; 6207 break; 6208 default: 6209 goto out_reject; 6210 } 6211 break; 6212 /* 6213 * We received an unknown message. 6214 * Ignore all MSG IN phases and reject it. 6215 */ 6216 case SIR_MSG_WEIRD: 6217 sym_print_msg(cp, "WEIRD message received", np->msgin); 6218 OUTL_DSP (SCRIPTB_BA (np, msg_weird)); 6219 return; 6220 /* 6221 * Negotiation failed. 6222 * Target does not send us the reply. 6223 * Remove the HS_NEGOTIATE status. 6224 */ 6225 case SIR_NEGO_FAILED: 6226 OUTB (HS_PRT, HS_BUSY); 6227 /* 6228 * Negotiation failed. 6229 * Target does not want answer message. 6230 */ 6231 case SIR_NEGO_PROTO: 6232 sym_nego_default(np, tp, cp); 6233 goto out; 6234 } 6235 6236 out: 6237 OUTONB_STD (); 6238 return; 6239 out_reject: 6240 OUTL_DSP (SCRIPTB_BA (np, msg_bad)); 6241 return; 6242 out_clrack: 6243 OUTL_DSP (SCRIPTA_BA (np, clrack)); 6244 return; 6245 out_stuck: 6246 return; 6247 } 6248 6249 /* 6250 * Acquire a control block 6251 */ 6252 static ccb_p sym_get_ccb (hcb_p np, u_char tn, u_char ln, u_char tag_order) 6253 { 6254 tcb_p tp = &np->target[tn]; 6255 lcb_p lp = sym_lp(tp, ln); 6256 u_short tag = NO_TAG; 6257 SYM_QUEHEAD *qp; 6258 ccb_p cp = (ccb_p) NULL; 6259 6260 /* 6261 * Look for a free CCB 6262 */ 6263 if (sym_que_empty(&np->free_ccbq)) 6264 goto out; 6265 qp = sym_remque_head(&np->free_ccbq); 6266 if (!qp) 6267 goto out; 6268 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 6269 6270 /* 6271 * If the LCB is not yet available and the LUN 6272 * has been probed ok, try to allocate the LCB. 6273 */ 6274 if (!lp && sym_is_bit(tp->lun_map, ln)) { 6275 lp = sym_alloc_lcb(np, tn, ln); 6276 if (!lp) 6277 goto out_free; 6278 } 6279 6280 /* 6281 * If the LCB is not available here, then the 6282 * logical unit is not yet discovered. For those 6283 * ones only accept 1 SCSI IO per logical unit, 6284 * since we cannot allow disconnections. 6285 */ 6286 if (!lp) { 6287 if (!sym_is_bit(tp->busy0_map, ln)) 6288 sym_set_bit(tp->busy0_map, ln); 6289 else 6290 goto out_free; 6291 } else { 6292 /* 6293 * If we have been asked for a tagged command. 6294 */ 6295 if (tag_order) { 6296 /* 6297 * Debugging purpose. 6298 */ 6299 assert(lp->busy_itl == 0); 6300 /* 6301 * Allocate resources for tags if not yet. 6302 */ 6303 if (!lp->cb_tags) { 6304 sym_alloc_lcb_tags(np, tn, ln); 6305 if (!lp->cb_tags) 6306 goto out_free; 6307 } 6308 /* 6309 * Get a tag for this SCSI IO and set up 6310 * the CCB bus address for reselection, 6311 * and count it for this LUN. 6312 * Toggle reselect path to tagged. 6313 */ 6314 if (lp->busy_itlq < SYM_CONF_MAX_TASK) { 6315 tag = lp->cb_tags[lp->ia_tag]; 6316 if (++lp->ia_tag == SYM_CONF_MAX_TASK) 6317 lp->ia_tag = 0; 6318 lp->itlq_tbl[tag] = cpu_to_scr(cp->ccb_ba); 6319 ++lp->busy_itlq; 6320 lp->head.resel_sa = 6321 cpu_to_scr(SCRIPTA_BA (np, resel_tag)); 6322 } 6323 else 6324 goto out_free; 6325 } 6326 /* 6327 * This command will not be tagged. 6328 * If we already have either a tagged or untagged 6329 * one, refuse to overlap this untagged one. 6330 */ 6331 else { 6332 /* 6333 * Debugging purpose. 6334 */ 6335 assert(lp->busy_itl == 0 && lp->busy_itlq == 0); 6336 /* 6337 * Count this nexus for this LUN. 6338 * Set up the CCB bus address for reselection. 6339 * Toggle reselect path to untagged. 6340 */ 6341 if (++lp->busy_itl == 1) { 6342 lp->head.itl_task_sa = cpu_to_scr(cp->ccb_ba); 6343 lp->head.resel_sa = 6344 cpu_to_scr(SCRIPTA_BA (np, resel_no_tag)); 6345 } 6346 else 6347 goto out_free; 6348 } 6349 } 6350 /* 6351 * Put the CCB into the busy queue. 6352 */ 6353 sym_insque_tail(&cp->link_ccbq, &np->busy_ccbq); 6354 6355 /* 6356 * Remember all informations needed to free this CCB. 6357 */ 6358 cp->to_abort = 0; 6359 cp->tag = tag; 6360 cp->target = tn; 6361 cp->lun = ln; 6362 6363 if (DEBUG_FLAGS & DEBUG_TAGS) { 6364 PRINT_LUN(np, tn, ln); 6365 printf ("ccb @%p using tag %d.\n", cp, tag); 6366 } 6367 6368 out: 6369 return cp; 6370 out_free: 6371 sym_insque_head(&cp->link_ccbq, &np->free_ccbq); 6372 return NULL; 6373 } 6374 6375 /* 6376 * Release one control block 6377 */ 6378 static void sym_free_ccb(hcb_p np, ccb_p cp) 6379 { 6380 tcb_p tp = &np->target[cp->target]; 6381 lcb_p lp = sym_lp(tp, cp->lun); 6382 6383 if (DEBUG_FLAGS & DEBUG_TAGS) { 6384 PRINT_LUN(np, cp->target, cp->lun); 6385 printf ("ccb @%p freeing tag %d.\n", cp, cp->tag); 6386 } 6387 6388 /* 6389 * If LCB available, 6390 */ 6391 if (lp) { 6392 /* 6393 * If tagged, release the tag, set the relect path 6394 */ 6395 if (cp->tag != NO_TAG) { 6396 /* 6397 * Free the tag value. 6398 */ 6399 lp->cb_tags[lp->if_tag] = cp->tag; 6400 if (++lp->if_tag == SYM_CONF_MAX_TASK) 6401 lp->if_tag = 0; 6402 /* 6403 * Make the reselect path invalid, 6404 * and uncount this CCB. 6405 */ 6406 lp->itlq_tbl[cp->tag] = cpu_to_scr(np->bad_itlq_ba); 6407 --lp->busy_itlq; 6408 } else { /* Untagged */ 6409 /* 6410 * Make the reselect path invalid, 6411 * and uncount this CCB. 6412 */ 6413 lp->head.itl_task_sa = cpu_to_scr(np->bad_itl_ba); 6414 --lp->busy_itl; 6415 } 6416 /* 6417 * If no JOB active, make the LUN reselect path invalid. 6418 */ 6419 if (lp->busy_itlq == 0 && lp->busy_itl == 0) 6420 lp->head.resel_sa = 6421 cpu_to_scr(SCRIPTB_BA (np, resel_bad_lun)); 6422 } 6423 /* 6424 * Otherwise, we only accept 1 IO per LUN. 6425 * Clear the bit that keeps track of this IO. 6426 */ 6427 else 6428 sym_clr_bit(tp->busy0_map, cp->lun); 6429 6430 /* 6431 * We donnot queue more than 1 ccb per target 6432 * with negotiation at any time. If this ccb was 6433 * used for negotiation, clear this info in the tcb. 6434 */ 6435 if (cp == tp->nego_cp) 6436 tp->nego_cp = NULL; 6437 6438 #ifdef SYM_CONF_IARB_SUPPORT 6439 /* 6440 * If we just complete the last queued CCB, 6441 * clear this info that is no longer relevant. 6442 */ 6443 if (cp == np->last_cp) 6444 np->last_cp = NULL; 6445 #endif 6446 6447 /* 6448 * Unmap user data from DMA map if needed. 6449 */ 6450 if (cp->dmamapped) { 6451 bus_dmamap_unload(np->data_dmat, cp->dmamap); 6452 cp->dmamapped = 0; 6453 } 6454 6455 /* 6456 * Make this CCB available. 6457 */ 6458 cp->cam_ccb = NULL; 6459 cp->host_status = HS_IDLE; 6460 sym_remque(&cp->link_ccbq); 6461 sym_insque_head(&cp->link_ccbq, &np->free_ccbq); 6462 } 6463 6464 /* 6465 * Allocate a CCB from memory and initialize its fixed part. 6466 */ 6467 static ccb_p sym_alloc_ccb(hcb_p np) 6468 { 6469 ccb_p cp = NULL; 6470 int hcode; 6471 6472 SYM_LOCK_ASSERT(MA_NOTOWNED); 6473 6474 /* 6475 * Prevent from allocating more CCBs than we can 6476 * queue to the controller. 6477 */ 6478 if (np->actccbs >= SYM_CONF_MAX_START) 6479 return NULL; 6480 6481 /* 6482 * Allocate memory for this CCB. 6483 */ 6484 cp = sym_calloc_dma(sizeof(struct sym_ccb), "CCB"); 6485 if (!cp) 6486 return NULL; 6487 6488 /* 6489 * Allocate a bounce buffer for sense data. 6490 */ 6491 cp->sns_bbuf = sym_calloc_dma(SYM_SNS_BBUF_LEN, "SNS_BBUF"); 6492 if (!cp->sns_bbuf) 6493 goto out_free; 6494 6495 /* 6496 * Allocate a map for the DMA of user data. 6497 */ 6498 if (bus_dmamap_create(np->data_dmat, 0, &cp->dmamap)) 6499 goto out_free; 6500 /* 6501 * Count it. 6502 */ 6503 np->actccbs++; 6504 6505 /* 6506 * Initialize the callout. 6507 */ 6508 callout_init(&cp->ch, 1); 6509 6510 /* 6511 * Compute the bus address of this ccb. 6512 */ 6513 cp->ccb_ba = vtobus(cp); 6514 6515 /* 6516 * Insert this ccb into the hashed list. 6517 */ 6518 hcode = CCB_HASH_CODE(cp->ccb_ba); 6519 cp->link_ccbh = np->ccbh[hcode]; 6520 np->ccbh[hcode] = cp; 6521 6522 /* 6523 * Initialize the start and restart actions. 6524 */ 6525 cp->phys.head.go.start = cpu_to_scr(SCRIPTA_BA (np, idle)); 6526 cp->phys.head.go.restart = cpu_to_scr(SCRIPTB_BA (np, bad_i_t_l)); 6527 6528 /* 6529 * Initilialyze some other fields. 6530 */ 6531 cp->phys.smsg_ext.addr = cpu_to_scr(HCB_BA(np, msgin[2])); 6532 6533 /* 6534 * Chain into free ccb queue. 6535 */ 6536 sym_insque_head(&cp->link_ccbq, &np->free_ccbq); 6537 6538 return cp; 6539 out_free: 6540 if (cp->sns_bbuf) 6541 sym_mfree_dma(cp->sns_bbuf, SYM_SNS_BBUF_LEN, "SNS_BBUF"); 6542 sym_mfree_dma(cp, sizeof(*cp), "CCB"); 6543 return NULL; 6544 } 6545 6546 /* 6547 * Look up a CCB from a DSA value. 6548 */ 6549 static ccb_p sym_ccb_from_dsa(hcb_p np, u32 dsa) 6550 { 6551 int hcode; 6552 ccb_p cp; 6553 6554 hcode = CCB_HASH_CODE(dsa); 6555 cp = np->ccbh[hcode]; 6556 while (cp) { 6557 if (cp->ccb_ba == dsa) 6558 break; 6559 cp = cp->link_ccbh; 6560 } 6561 6562 return cp; 6563 } 6564 6565 /* 6566 * Lun control block allocation and initialization. 6567 */ 6568 static lcb_p sym_alloc_lcb (hcb_p np, u_char tn, u_char ln) 6569 { 6570 tcb_p tp = &np->target[tn]; 6571 lcb_p lp = sym_lp(tp, ln); 6572 6573 /* 6574 * Already done, just return. 6575 */ 6576 if (lp) 6577 return lp; 6578 /* 6579 * Check against some race. 6580 */ 6581 assert(!sym_is_bit(tp->busy0_map, ln)); 6582 6583 /* 6584 * Allocate the LCB bus address array. 6585 * Compute the bus address of this table. 6586 */ 6587 if (ln && !tp->luntbl) { 6588 int i; 6589 6590 tp->luntbl = sym_calloc_dma(256, "LUNTBL"); 6591 if (!tp->luntbl) 6592 goto fail; 6593 for (i = 0 ; i < 64 ; i++) 6594 tp->luntbl[i] = cpu_to_scr(vtobus(&np->badlun_sa)); 6595 tp->head.luntbl_sa = cpu_to_scr(vtobus(tp->luntbl)); 6596 } 6597 6598 /* 6599 * Allocate the table of pointers for LUN(s) > 0, if needed. 6600 */ 6601 if (ln && !tp->lunmp) { 6602 tp->lunmp = sym_calloc(SYM_CONF_MAX_LUN * sizeof(lcb_p), 6603 "LUNMP"); 6604 if (!tp->lunmp) 6605 goto fail; 6606 } 6607 6608 /* 6609 * Allocate the lcb. 6610 * Make it available to the chip. 6611 */ 6612 lp = sym_calloc_dma(sizeof(struct sym_lcb), "LCB"); 6613 if (!lp) 6614 goto fail; 6615 if (ln) { 6616 tp->lunmp[ln] = lp; 6617 tp->luntbl[ln] = cpu_to_scr(vtobus(lp)); 6618 } 6619 else { 6620 tp->lun0p = lp; 6621 tp->head.lun0_sa = cpu_to_scr(vtobus(lp)); 6622 } 6623 6624 /* 6625 * Let the itl task point to error handling. 6626 */ 6627 lp->head.itl_task_sa = cpu_to_scr(np->bad_itl_ba); 6628 6629 /* 6630 * Set the reselect pattern to our default. :) 6631 */ 6632 lp->head.resel_sa = cpu_to_scr(SCRIPTB_BA (np, resel_bad_lun)); 6633 6634 /* 6635 * Set user capabilities. 6636 */ 6637 lp->user_flags = tp->usrflags & (SYM_DISC_ENABLED | SYM_TAGS_ENABLED); 6638 6639 fail: 6640 return lp; 6641 } 6642 6643 /* 6644 * Allocate LCB resources for tagged command queuing. 6645 */ 6646 static void sym_alloc_lcb_tags (hcb_p np, u_char tn, u_char ln) 6647 { 6648 tcb_p tp = &np->target[tn]; 6649 lcb_p lp = sym_lp(tp, ln); 6650 int i; 6651 6652 /* 6653 * If LCB not available, try to allocate it. 6654 */ 6655 if (!lp && !(lp = sym_alloc_lcb(np, tn, ln))) 6656 return; 6657 6658 /* 6659 * Allocate the task table and and the tag allocation 6660 * circular buffer. We want both or none. 6661 */ 6662 lp->itlq_tbl = sym_calloc_dma(SYM_CONF_MAX_TASK*4, "ITLQ_TBL"); 6663 if (!lp->itlq_tbl) 6664 return; 6665 lp->cb_tags = sym_calloc(SYM_CONF_MAX_TASK, "CB_TAGS"); 6666 if (!lp->cb_tags) { 6667 sym_mfree_dma(lp->itlq_tbl, SYM_CONF_MAX_TASK*4, "ITLQ_TBL"); 6668 lp->itlq_tbl = NULL; 6669 return; 6670 } 6671 6672 /* 6673 * Initialize the task table with invalid entries. 6674 */ 6675 for (i = 0 ; i < SYM_CONF_MAX_TASK ; i++) 6676 lp->itlq_tbl[i] = cpu_to_scr(np->notask_ba); 6677 6678 /* 6679 * Fill up the tag buffer with tag numbers. 6680 */ 6681 for (i = 0 ; i < SYM_CONF_MAX_TASK ; i++) 6682 lp->cb_tags[i] = i; 6683 6684 /* 6685 * Make the task table available to SCRIPTS, 6686 * And accept tagged commands now. 6687 */ 6688 lp->head.itlq_tbl_sa = cpu_to_scr(vtobus(lp->itlq_tbl)); 6689 } 6690 6691 /* 6692 * Test the pci bus snoop logic :-( 6693 * 6694 * Has to be called with interrupts disabled. 6695 */ 6696 #ifndef SYM_CONF_IOMAPPED 6697 static int sym_regtest (hcb_p np) 6698 { 6699 register volatile u32 data; 6700 /* 6701 * chip registers may NOT be cached. 6702 * write 0xffffffff to a read only register area, 6703 * and try to read it back. 6704 */ 6705 data = 0xffffffff; 6706 OUTL_OFF(offsetof(struct sym_reg, nc_dstat), data); 6707 data = INL_OFF(offsetof(struct sym_reg, nc_dstat)); 6708 #if 1 6709 if (data == 0xffffffff) { 6710 #else 6711 if ((data & 0xe2f0fffd) != 0x02000080) { 6712 #endif 6713 printf ("CACHE TEST FAILED: reg dstat-sstat2 readback %x.\n", 6714 (unsigned) data); 6715 return (0x10); 6716 } 6717 return (0); 6718 } 6719 #endif 6720 6721 static int sym_snooptest (hcb_p np) 6722 { 6723 u32 sym_rd, sym_wr, sym_bk, host_rd, host_wr, pc, dstat; 6724 int i, err=0; 6725 #ifndef SYM_CONF_IOMAPPED 6726 err |= sym_regtest (np); 6727 if (err) return (err); 6728 #endif 6729 restart_test: 6730 /* 6731 * Enable Master Parity Checking as we intend 6732 * to enable it for normal operations. 6733 */ 6734 OUTB (nc_ctest4, (np->rv_ctest4 & MPEE)); 6735 /* 6736 * init 6737 */ 6738 pc = SCRIPTB0_BA (np, snooptest); 6739 host_wr = 1; 6740 sym_wr = 2; 6741 /* 6742 * Set memory and register. 6743 */ 6744 np->cache = cpu_to_scr(host_wr); 6745 OUTL (nc_temp, sym_wr); 6746 /* 6747 * Start script (exchange values) 6748 */ 6749 OUTL (nc_dsa, np->hcb_ba); 6750 OUTL_DSP (pc); 6751 /* 6752 * Wait 'til done (with timeout) 6753 */ 6754 for (i=0; i<SYM_SNOOP_TIMEOUT; i++) 6755 if (INB(nc_istat) & (INTF|SIP|DIP)) 6756 break; 6757 if (i>=SYM_SNOOP_TIMEOUT) { 6758 printf ("CACHE TEST FAILED: timeout.\n"); 6759 return (0x20); 6760 } 6761 /* 6762 * Check for fatal DMA errors. 6763 */ 6764 dstat = INB (nc_dstat); 6765 #if 1 /* Band aiding for broken hardwares that fail PCI parity */ 6766 if ((dstat & MDPE) && (np->rv_ctest4 & MPEE)) { 6767 printf ("%s: PCI DATA PARITY ERROR DETECTED - " 6768 "DISABLING MASTER DATA PARITY CHECKING.\n", 6769 sym_name(np)); 6770 np->rv_ctest4 &= ~MPEE; 6771 goto restart_test; 6772 } 6773 #endif 6774 if (dstat & (MDPE|BF|IID)) { 6775 printf ("CACHE TEST FAILED: DMA error (dstat=0x%02x).", dstat); 6776 return (0x80); 6777 } 6778 /* 6779 * Save termination position. 6780 */ 6781 pc = INL (nc_dsp); 6782 /* 6783 * Read memory and register. 6784 */ 6785 host_rd = scr_to_cpu(np->cache); 6786 sym_rd = INL (nc_scratcha); 6787 sym_bk = INL (nc_temp); 6788 6789 /* 6790 * Check termination position. 6791 */ 6792 if (pc != SCRIPTB0_BA (np, snoopend)+8) { 6793 printf ("CACHE TEST FAILED: script execution failed.\n"); 6794 printf ("start=%08lx, pc=%08lx, end=%08lx\n", 6795 (u_long) SCRIPTB0_BA (np, snooptest), (u_long) pc, 6796 (u_long) SCRIPTB0_BA (np, snoopend) +8); 6797 return (0x40); 6798 } 6799 /* 6800 * Show results. 6801 */ 6802 if (host_wr != sym_rd) { 6803 printf ("CACHE TEST FAILED: host wrote %d, chip read %d.\n", 6804 (int) host_wr, (int) sym_rd); 6805 err |= 1; 6806 } 6807 if (host_rd != sym_wr) { 6808 printf ("CACHE TEST FAILED: chip wrote %d, host read %d.\n", 6809 (int) sym_wr, (int) host_rd); 6810 err |= 2; 6811 } 6812 if (sym_bk != sym_wr) { 6813 printf ("CACHE TEST FAILED: chip wrote %d, read back %d.\n", 6814 (int) sym_wr, (int) sym_bk); 6815 err |= 4; 6816 } 6817 6818 return (err); 6819 } 6820 6821 /* 6822 * Determine the chip's clock frequency. 6823 * 6824 * This is essential for the negotiation of the synchronous 6825 * transfer rate. 6826 * 6827 * Note: we have to return the correct value. 6828 * THERE IS NO SAFE DEFAULT VALUE. 6829 * 6830 * Most NCR/SYMBIOS boards are delivered with a 40 Mhz clock. 6831 * 53C860 and 53C875 rev. 1 support fast20 transfers but 6832 * do not have a clock doubler and so are provided with a 6833 * 80 MHz clock. All other fast20 boards incorporate a doubler 6834 * and so should be delivered with a 40 MHz clock. 6835 * The recent fast40 chips (895/896/895A/1010) use a 40 Mhz base 6836 * clock and provide a clock quadrupler (160 Mhz). 6837 */ 6838 6839 /* 6840 * Select SCSI clock frequency 6841 */ 6842 static void sym_selectclock(hcb_p np, u_char scntl3) 6843 { 6844 /* 6845 * If multiplier not present or not selected, leave here. 6846 */ 6847 if (np->multiplier <= 1) { 6848 OUTB(nc_scntl3, scntl3); 6849 return; 6850 } 6851 6852 if (sym_verbose >= 2) 6853 printf ("%s: enabling clock multiplier\n", sym_name(np)); 6854 6855 OUTB(nc_stest1, DBLEN); /* Enable clock multiplier */ 6856 /* 6857 * Wait for the LCKFRQ bit to be set if supported by the chip. 6858 * Otherwise wait 20 micro-seconds. 6859 */ 6860 if (np->features & FE_LCKFRQ) { 6861 int i = 20; 6862 while (!(INB(nc_stest4) & LCKFRQ) && --i > 0) 6863 UDELAY (20); 6864 if (!i) 6865 printf("%s: the chip cannot lock the frequency\n", 6866 sym_name(np)); 6867 } else 6868 UDELAY (20); 6869 OUTB(nc_stest3, HSC); /* Halt the scsi clock */ 6870 OUTB(nc_scntl3, scntl3); 6871 OUTB(nc_stest1, (DBLEN|DBLSEL));/* Select clock multiplier */ 6872 OUTB(nc_stest3, 0x00); /* Restart scsi clock */ 6873 } 6874 6875 /* 6876 * calculate SCSI clock frequency (in KHz) 6877 */ 6878 static unsigned getfreq (hcb_p np, int gen) 6879 { 6880 unsigned int ms = 0; 6881 unsigned int f; 6882 6883 /* 6884 * Measure GEN timer delay in order 6885 * to calculate SCSI clock frequency 6886 * 6887 * This code will never execute too 6888 * many loop iterations (if DELAY is 6889 * reasonably correct). It could get 6890 * too low a delay (too high a freq.) 6891 * if the CPU is slow executing the 6892 * loop for some reason (an NMI, for 6893 * example). For this reason we will 6894 * if multiple measurements are to be 6895 * performed trust the higher delay 6896 * (lower frequency returned). 6897 */ 6898 OUTW (nc_sien , 0); /* mask all scsi interrupts */ 6899 (void) INW (nc_sist); /* clear pending scsi interrupt */ 6900 OUTB (nc_dien , 0); /* mask all dma interrupts */ 6901 (void) INW (nc_sist); /* another one, just to be sure :) */ 6902 OUTB (nc_scntl3, 4); /* set pre-scaler to divide by 3 */ 6903 OUTB (nc_stime1, 0); /* disable general purpose timer */ 6904 OUTB (nc_stime1, gen); /* set to nominal delay of 1<<gen * 125us */ 6905 while (!(INW(nc_sist) & GEN) && ms++ < 100000) 6906 UDELAY (1000); /* count ms */ 6907 OUTB (nc_stime1, 0); /* disable general purpose timer */ 6908 /* 6909 * set prescaler to divide by whatever 0 means 6910 * 0 ought to choose divide by 2, but appears 6911 * to set divide by 3.5 mode in my 53c810 ... 6912 */ 6913 OUTB (nc_scntl3, 0); 6914 6915 /* 6916 * adjust for prescaler, and convert into KHz 6917 */ 6918 f = ms ? ((1 << gen) * 4340) / ms : 0; 6919 6920 if (sym_verbose >= 2) 6921 printf ("%s: Delay (GEN=%d): %u msec, %u KHz\n", 6922 sym_name(np), gen, ms, f); 6923 6924 return f; 6925 } 6926 6927 static unsigned sym_getfreq (hcb_p np) 6928 { 6929 u_int f1, f2; 6930 int gen = 11; 6931 6932 (void) getfreq (np, gen); /* throw away first result */ 6933 f1 = getfreq (np, gen); 6934 f2 = getfreq (np, gen); 6935 if (f1 > f2) f1 = f2; /* trust lower result */ 6936 return f1; 6937 } 6938 6939 /* 6940 * Get/probe chip SCSI clock frequency 6941 */ 6942 static void sym_getclock (hcb_p np, int mult) 6943 { 6944 unsigned char scntl3 = np->sv_scntl3; 6945 unsigned char stest1 = np->sv_stest1; 6946 unsigned f1; 6947 6948 /* 6949 * For the C10 core, assume 40 MHz. 6950 */ 6951 if (np->features & FE_C10) { 6952 np->multiplier = mult; 6953 np->clock_khz = 40000 * mult; 6954 return; 6955 } 6956 6957 np->multiplier = 1; 6958 f1 = 40000; 6959 /* 6960 * True with 875/895/896/895A with clock multiplier selected 6961 */ 6962 if (mult > 1 && (stest1 & (DBLEN+DBLSEL)) == DBLEN+DBLSEL) { 6963 if (sym_verbose >= 2) 6964 printf ("%s: clock multiplier found\n", sym_name(np)); 6965 np->multiplier = mult; 6966 } 6967 6968 /* 6969 * If multiplier not found or scntl3 not 7,5,3, 6970 * reset chip and get frequency from general purpose timer. 6971 * Otherwise trust scntl3 BIOS setting. 6972 */ 6973 if (np->multiplier != mult || (scntl3 & 7) < 3 || !(scntl3 & 1)) { 6974 OUTB (nc_stest1, 0); /* make sure doubler is OFF */ 6975 f1 = sym_getfreq (np); 6976 6977 if (sym_verbose) 6978 printf ("%s: chip clock is %uKHz\n", sym_name(np), f1); 6979 6980 if (f1 < 45000) f1 = 40000; 6981 else if (f1 < 55000) f1 = 50000; 6982 else f1 = 80000; 6983 6984 if (f1 < 80000 && mult > 1) { 6985 if (sym_verbose >= 2) 6986 printf ("%s: clock multiplier assumed\n", 6987 sym_name(np)); 6988 np->multiplier = mult; 6989 } 6990 } else { 6991 if ((scntl3 & 7) == 3) f1 = 40000; 6992 else if ((scntl3 & 7) == 5) f1 = 80000; 6993 else f1 = 160000; 6994 6995 f1 /= np->multiplier; 6996 } 6997 6998 /* 6999 * Compute controller synchronous parameters. 7000 */ 7001 f1 *= np->multiplier; 7002 np->clock_khz = f1; 7003 } 7004 7005 /* 7006 * Get/probe PCI clock frequency 7007 */ 7008 static int sym_getpciclock (hcb_p np) 7009 { 7010 int f = 0; 7011 7012 /* 7013 * For the C1010-33, this doesn't work. 7014 * For the C1010-66, this will be tested when I'll have 7015 * such a beast to play with. 7016 */ 7017 if (!(np->features & FE_C10)) { 7018 OUTB (nc_stest1, SCLK); /* Use the PCI clock as SCSI clock */ 7019 f = (int) sym_getfreq (np); 7020 OUTB (nc_stest1, 0); 7021 } 7022 np->pciclk_khz = f; 7023 7024 return f; 7025 } 7026 7027 /*============= DRIVER ACTION/COMPLETION ====================*/ 7028 7029 /* 7030 * Print something that tells about extended errors. 7031 */ 7032 static void sym_print_xerr(ccb_p cp, int x_status) 7033 { 7034 if (x_status & XE_PARITY_ERR) { 7035 PRINT_ADDR(cp); 7036 printf ("unrecovered SCSI parity error.\n"); 7037 } 7038 if (x_status & XE_EXTRA_DATA) { 7039 PRINT_ADDR(cp); 7040 printf ("extraneous data discarded.\n"); 7041 } 7042 if (x_status & XE_BAD_PHASE) { 7043 PRINT_ADDR(cp); 7044 printf ("illegal scsi phase (4/5).\n"); 7045 } 7046 if (x_status & XE_SODL_UNRUN) { 7047 PRINT_ADDR(cp); 7048 printf ("ODD transfer in DATA OUT phase.\n"); 7049 } 7050 if (x_status & XE_SWIDE_OVRUN) { 7051 PRINT_ADDR(cp); 7052 printf ("ODD transfer in DATA IN phase.\n"); 7053 } 7054 } 7055 7056 /* 7057 * Choose the more appropriate CAM status if 7058 * the IO encountered an extended error. 7059 */ 7060 static int sym_xerr_cam_status(int cam_status, int x_status) 7061 { 7062 if (x_status) { 7063 if (x_status & XE_PARITY_ERR) 7064 cam_status = CAM_UNCOR_PARITY; 7065 else if (x_status &(XE_EXTRA_DATA|XE_SODL_UNRUN|XE_SWIDE_OVRUN)) 7066 cam_status = CAM_DATA_RUN_ERR; 7067 else if (x_status & XE_BAD_PHASE) 7068 cam_status = CAM_REQ_CMP_ERR; 7069 else 7070 cam_status = CAM_REQ_CMP_ERR; 7071 } 7072 return cam_status; 7073 } 7074 7075 /* 7076 * Complete execution of a SCSI command with extented 7077 * error, SCSI status error, or having been auto-sensed. 7078 * 7079 * The SCRIPTS processor is not running there, so we 7080 * can safely access IO registers and remove JOBs from 7081 * the START queue. 7082 * SCRATCHA is assumed to have been loaded with STARTPOS 7083 * before the SCRIPTS called the C code. 7084 */ 7085 static void sym_complete_error (hcb_p np, ccb_p cp) 7086 { 7087 struct ccb_scsiio *csio; 7088 u_int cam_status; 7089 int i, sense_returned; 7090 7091 SYM_LOCK_ASSERT(MA_OWNED); 7092 7093 /* 7094 * Paranoid check. :) 7095 */ 7096 if (!cp || !cp->cam_ccb) 7097 return; 7098 7099 if (DEBUG_FLAGS & (DEBUG_TINY|DEBUG_RESULT)) { 7100 printf ("CCB=%lx STAT=%x/%x/%x DEV=%d/%d\n", (unsigned long)cp, 7101 cp->host_status, cp->ssss_status, cp->host_flags, 7102 cp->target, cp->lun); 7103 MDELAY(100); 7104 } 7105 7106 /* 7107 * Get CAM command pointer. 7108 */ 7109 csio = &cp->cam_ccb->csio; 7110 7111 /* 7112 * Check for extended errors. 7113 */ 7114 if (cp->xerr_status) { 7115 if (sym_verbose) 7116 sym_print_xerr(cp, cp->xerr_status); 7117 if (cp->host_status == HS_COMPLETE) 7118 cp->host_status = HS_COMP_ERR; 7119 } 7120 7121 /* 7122 * Calculate the residual. 7123 */ 7124 csio->sense_resid = 0; 7125 csio->resid = sym_compute_residual(np, cp); 7126 7127 if (!SYM_CONF_RESIDUAL_SUPPORT) {/* If user does not want residuals */ 7128 csio->resid = 0; /* throw them away. :) */ 7129 cp->sv_resid = 0; 7130 } 7131 7132 if (cp->host_flags & HF_SENSE) { /* Auto sense */ 7133 csio->scsi_status = cp->sv_scsi_status; /* Restore status */ 7134 csio->sense_resid = csio->resid; /* Swap residuals */ 7135 csio->resid = cp->sv_resid; 7136 cp->sv_resid = 0; 7137 if (sym_verbose && cp->sv_xerr_status) 7138 sym_print_xerr(cp, cp->sv_xerr_status); 7139 if (cp->host_status == HS_COMPLETE && 7140 cp->ssss_status == S_GOOD && 7141 cp->xerr_status == 0) { 7142 cam_status = sym_xerr_cam_status(CAM_SCSI_STATUS_ERROR, 7143 cp->sv_xerr_status); 7144 cam_status |= CAM_AUTOSNS_VALID; 7145 /* 7146 * Bounce back the sense data to user and 7147 * fix the residual. 7148 */ 7149 bzero(&csio->sense_data, sizeof(csio->sense_data)); 7150 sense_returned = SYM_SNS_BBUF_LEN - csio->sense_resid; 7151 if (sense_returned < csio->sense_len) 7152 csio->sense_resid = csio->sense_len - 7153 sense_returned; 7154 else 7155 csio->sense_resid = 0; 7156 bcopy(cp->sns_bbuf, &csio->sense_data, 7157 MIN(csio->sense_len, sense_returned)); 7158 #if 0 7159 /* 7160 * If the device reports a UNIT ATTENTION condition 7161 * due to a RESET condition, we should consider all 7162 * disconnect CCBs for this unit as aborted. 7163 */ 7164 if (1) { 7165 u_char *p; 7166 p = (u_char *) csio->sense_data; 7167 if (p[0]==0x70 && p[2]==0x6 && p[12]==0x29) 7168 sym_clear_tasks(np, CAM_REQ_ABORTED, 7169 cp->target,cp->lun, -1); 7170 } 7171 #endif 7172 } 7173 else 7174 cam_status = CAM_AUTOSENSE_FAIL; 7175 } 7176 else if (cp->host_status == HS_COMPLETE) { /* Bad SCSI status */ 7177 csio->scsi_status = cp->ssss_status; 7178 cam_status = CAM_SCSI_STATUS_ERROR; 7179 } 7180 else if (cp->host_status == HS_SEL_TIMEOUT) /* Selection timeout */ 7181 cam_status = CAM_SEL_TIMEOUT; 7182 else if (cp->host_status == HS_UNEXPECTED) /* Unexpected BUS FREE*/ 7183 cam_status = CAM_UNEXP_BUSFREE; 7184 else { /* Extended error */ 7185 if (sym_verbose) { 7186 PRINT_ADDR(cp); 7187 printf ("COMMAND FAILED (%x %x %x).\n", 7188 cp->host_status, cp->ssss_status, 7189 cp->xerr_status); 7190 } 7191 csio->scsi_status = cp->ssss_status; 7192 /* 7193 * Set the most appropriate value for CAM status. 7194 */ 7195 cam_status = sym_xerr_cam_status(CAM_REQ_CMP_ERR, 7196 cp->xerr_status); 7197 } 7198 7199 /* 7200 * Dequeue all queued CCBs for that device 7201 * not yet started by SCRIPTS. 7202 */ 7203 i = (INL (nc_scratcha) - np->squeue_ba) / 4; 7204 (void) sym_dequeue_from_squeue(np, i, cp->target, cp->lun, -1); 7205 7206 /* 7207 * Restart the SCRIPTS processor. 7208 */ 7209 OUTL_DSP (SCRIPTA_BA (np, start)); 7210 7211 /* 7212 * Synchronize DMA map if needed. 7213 */ 7214 if (cp->dmamapped) { 7215 bus_dmamap_sync(np->data_dmat, cp->dmamap, 7216 (cp->dmamapped == SYM_DMA_READ ? 7217 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 7218 } 7219 /* 7220 * Add this one to the COMP queue. 7221 * Complete all those commands with either error 7222 * or requeue condition. 7223 */ 7224 sym_set_cam_status((union ccb *) csio, cam_status); 7225 sym_remque(&cp->link_ccbq); 7226 sym_insque_head(&cp->link_ccbq, &np->comp_ccbq); 7227 sym_flush_comp_queue(np, 0); 7228 } 7229 7230 /* 7231 * Complete execution of a successful SCSI command. 7232 * 7233 * Only successful commands go to the DONE queue, 7234 * since we need to have the SCRIPTS processor 7235 * stopped on any error condition. 7236 * The SCRIPTS processor is running while we are 7237 * completing successful commands. 7238 */ 7239 static void sym_complete_ok (hcb_p np, ccb_p cp) 7240 { 7241 struct ccb_scsiio *csio; 7242 tcb_p tp; 7243 lcb_p lp; 7244 7245 SYM_LOCK_ASSERT(MA_OWNED); 7246 7247 /* 7248 * Paranoid check. :) 7249 */ 7250 if (!cp || !cp->cam_ccb) 7251 return; 7252 assert (cp->host_status == HS_COMPLETE); 7253 7254 /* 7255 * Get command, target and lun pointers. 7256 */ 7257 csio = &cp->cam_ccb->csio; 7258 tp = &np->target[cp->target]; 7259 lp = sym_lp(tp, cp->lun); 7260 7261 /* 7262 * Assume device discovered on first success. 7263 */ 7264 if (!lp) 7265 sym_set_bit(tp->lun_map, cp->lun); 7266 7267 /* 7268 * If all data have been transferred, given than no 7269 * extended error did occur, there is no residual. 7270 */ 7271 csio->resid = 0; 7272 if (cp->phys.head.lastp != cp->phys.head.goalp) 7273 csio->resid = sym_compute_residual(np, cp); 7274 7275 /* 7276 * Wrong transfer residuals may be worse than just always 7277 * returning zero. User can disable this feature from 7278 * sym_conf.h. Residual support is enabled by default. 7279 */ 7280 if (!SYM_CONF_RESIDUAL_SUPPORT) 7281 csio->resid = 0; 7282 7283 /* 7284 * Synchronize DMA map if needed. 7285 */ 7286 if (cp->dmamapped) { 7287 bus_dmamap_sync(np->data_dmat, cp->dmamap, 7288 (cp->dmamapped == SYM_DMA_READ ? 7289 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 7290 } 7291 /* 7292 * Set status and complete the command. 7293 */ 7294 csio->scsi_status = cp->ssss_status; 7295 sym_set_cam_status((union ccb *) csio, CAM_REQ_CMP); 7296 sym_xpt_done(np, (union ccb *) csio, cp); 7297 sym_free_ccb(np, cp); 7298 } 7299 7300 /* 7301 * Our callout handler 7302 */ 7303 static void sym_callout(void *arg) 7304 { 7305 union ccb *ccb = (union ccb *) arg; 7306 hcb_p np = ccb->ccb_h.sym_hcb_ptr; 7307 7308 /* 7309 * Check that the CAM CCB is still queued. 7310 */ 7311 if (!np) 7312 return; 7313 7314 SYM_LOCK(); 7315 7316 switch(ccb->ccb_h.func_code) { 7317 case XPT_SCSI_IO: 7318 (void) sym_abort_scsiio(np, ccb, 1); 7319 break; 7320 default: 7321 break; 7322 } 7323 7324 SYM_UNLOCK(); 7325 } 7326 7327 /* 7328 * Abort an SCSI IO. 7329 */ 7330 static int sym_abort_scsiio(hcb_p np, union ccb *ccb, int timed_out) 7331 { 7332 ccb_p cp; 7333 SYM_QUEHEAD *qp; 7334 7335 SYM_LOCK_ASSERT(MA_OWNED); 7336 7337 /* 7338 * Look up our CCB control block. 7339 */ 7340 cp = NULL; 7341 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) { 7342 ccb_p cp2 = sym_que_entry(qp, struct sym_ccb, link_ccbq); 7343 if (cp2->cam_ccb == ccb) { 7344 cp = cp2; 7345 break; 7346 } 7347 } 7348 if (!cp || cp->host_status == HS_WAIT) 7349 return -1; 7350 7351 /* 7352 * If a previous abort didn't succeed in time, 7353 * perform a BUS reset. 7354 */ 7355 if (cp->to_abort) { 7356 sym_reset_scsi_bus(np, 1); 7357 return 0; 7358 } 7359 7360 /* 7361 * Mark the CCB for abort and allow time for. 7362 */ 7363 cp->to_abort = timed_out ? 2 : 1; 7364 callout_reset(&cp->ch, 10 * hz, sym_callout, (caddr_t) ccb); 7365 7366 /* 7367 * Tell the SCRIPTS processor to stop and synchronize with us. 7368 */ 7369 np->istat_sem = SEM; 7370 OUTB (nc_istat, SIGP|SEM); 7371 return 0; 7372 } 7373 7374 /* 7375 * Reset a SCSI device (all LUNs of a target). 7376 */ 7377 static void sym_reset_dev(hcb_p np, union ccb *ccb) 7378 { 7379 tcb_p tp; 7380 struct ccb_hdr *ccb_h = &ccb->ccb_h; 7381 7382 SYM_LOCK_ASSERT(MA_OWNED); 7383 7384 if (ccb_h->target_id == np->myaddr || 7385 ccb_h->target_id >= SYM_CONF_MAX_TARGET || 7386 ccb_h->target_lun >= SYM_CONF_MAX_LUN) { 7387 sym_xpt_done2(np, ccb, CAM_DEV_NOT_THERE); 7388 return; 7389 } 7390 7391 tp = &np->target[ccb_h->target_id]; 7392 7393 tp->to_reset = 1; 7394 sym_xpt_done2(np, ccb, CAM_REQ_CMP); 7395 7396 np->istat_sem = SEM; 7397 OUTB (nc_istat, SIGP|SEM); 7398 } 7399 7400 /* 7401 * SIM action entry point. 7402 */ 7403 static void sym_action(struct cam_sim *sim, union ccb *ccb) 7404 { 7405 hcb_p np; 7406 tcb_p tp; 7407 lcb_p lp; 7408 ccb_p cp; 7409 int tmp; 7410 u_char idmsg, *msgptr; 7411 u_int msglen; 7412 struct ccb_scsiio *csio; 7413 struct ccb_hdr *ccb_h; 7414 7415 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("sym_action\n")); 7416 7417 /* 7418 * Retrieve our controller data structure. 7419 */ 7420 np = (hcb_p) cam_sim_softc(sim); 7421 7422 SYM_LOCK_ASSERT(MA_OWNED); 7423 7424 /* 7425 * The common case is SCSI IO. 7426 * We deal with other ones elsewhere. 7427 */ 7428 if (ccb->ccb_h.func_code != XPT_SCSI_IO) { 7429 sym_action2(sim, ccb); 7430 return; 7431 } 7432 csio = &ccb->csio; 7433 ccb_h = &csio->ccb_h; 7434 7435 /* 7436 * Work around races. 7437 */ 7438 if ((ccb_h->status & CAM_STATUS_MASK) != CAM_REQ_INPROG) { 7439 xpt_done(ccb); 7440 return; 7441 } 7442 7443 /* 7444 * Minimal checkings, so that we will not 7445 * go outside our tables. 7446 */ 7447 if (ccb_h->target_id == np->myaddr || 7448 ccb_h->target_id >= SYM_CONF_MAX_TARGET || 7449 ccb_h->target_lun >= SYM_CONF_MAX_LUN) { 7450 sym_xpt_done2(np, ccb, CAM_DEV_NOT_THERE); 7451 return; 7452 } 7453 7454 /* 7455 * Retrieve the target and lun descriptors. 7456 */ 7457 tp = &np->target[ccb_h->target_id]; 7458 lp = sym_lp(tp, ccb_h->target_lun); 7459 7460 /* 7461 * Complete the 1st INQUIRY command with error 7462 * condition if the device is flagged NOSCAN 7463 * at BOOT in the NVRAM. This may speed up 7464 * the boot and maintain coherency with BIOS 7465 * device numbering. Clearing the flag allows 7466 * user to rescan skipped devices later. 7467 * We also return error for devices not flagged 7468 * for SCAN LUNS in the NVRAM since some mono-lun 7469 * devices behave badly when asked for some non 7470 * zero LUN. Btw, this is an absolute hack.:-) 7471 */ 7472 if (!(ccb_h->flags & CAM_CDB_PHYS) && 7473 (0x12 == ((ccb_h->flags & CAM_CDB_POINTER) ? 7474 csio->cdb_io.cdb_ptr[0] : csio->cdb_io.cdb_bytes[0]))) { 7475 if ((tp->usrflags & SYM_SCAN_BOOT_DISABLED) || 7476 ((tp->usrflags & SYM_SCAN_LUNS_DISABLED) && 7477 ccb_h->target_lun != 0)) { 7478 tp->usrflags &= ~SYM_SCAN_BOOT_DISABLED; 7479 sym_xpt_done2(np, ccb, CAM_DEV_NOT_THERE); 7480 return; 7481 } 7482 } 7483 7484 /* 7485 * Get a control block for this IO. 7486 */ 7487 tmp = ((ccb_h->flags & CAM_TAG_ACTION_VALID) != 0); 7488 cp = sym_get_ccb(np, ccb_h->target_id, ccb_h->target_lun, tmp); 7489 if (!cp) { 7490 sym_xpt_done2(np, ccb, CAM_RESRC_UNAVAIL); 7491 return; 7492 } 7493 7494 /* 7495 * Keep track of the IO in our CCB. 7496 */ 7497 cp->cam_ccb = ccb; 7498 7499 /* 7500 * Build the IDENTIFY message. 7501 */ 7502 idmsg = M_IDENTIFY | cp->lun; 7503 if (cp->tag != NO_TAG || (lp && (lp->current_flags & SYM_DISC_ENABLED))) 7504 idmsg |= 0x40; 7505 7506 msgptr = cp->scsi_smsg; 7507 msglen = 0; 7508 msgptr[msglen++] = idmsg; 7509 7510 /* 7511 * Build the tag message if present. 7512 */ 7513 if (cp->tag != NO_TAG) { 7514 u_char order = csio->tag_action; 7515 7516 switch(order) { 7517 case M_ORDERED_TAG: 7518 break; 7519 case M_HEAD_TAG: 7520 break; 7521 default: 7522 order = M_SIMPLE_TAG; 7523 } 7524 msgptr[msglen++] = order; 7525 7526 /* 7527 * For less than 128 tags, actual tags are numbered 7528 * 1,3,5,..2*MAXTAGS+1,since we may have to deal 7529 * with devices that have problems with #TAG 0 or too 7530 * great #TAG numbers. For more tags (up to 256), 7531 * we use directly our tag number. 7532 */ 7533 #if SYM_CONF_MAX_TASK > (512/4) 7534 msgptr[msglen++] = cp->tag; 7535 #else 7536 msgptr[msglen++] = (cp->tag << 1) + 1; 7537 #endif 7538 } 7539 7540 /* 7541 * Build a negotiation message if needed. 7542 * (nego_status is filled by sym_prepare_nego()) 7543 */ 7544 cp->nego_status = 0; 7545 if (tp->tinfo.current.width != tp->tinfo.goal.width || 7546 tp->tinfo.current.period != tp->tinfo.goal.period || 7547 tp->tinfo.current.offset != tp->tinfo.goal.offset || 7548 tp->tinfo.current.options != tp->tinfo.goal.options) { 7549 if (!tp->nego_cp && lp) 7550 msglen += sym_prepare_nego(np, cp, 0, msgptr + msglen); 7551 } 7552 7553 /* 7554 * Fill in our ccb 7555 */ 7556 7557 /* 7558 * Startqueue 7559 */ 7560 cp->phys.head.go.start = cpu_to_scr(SCRIPTA_BA (np, select)); 7561 cp->phys.head.go.restart = cpu_to_scr(SCRIPTA_BA (np, resel_dsa)); 7562 7563 /* 7564 * select 7565 */ 7566 cp->phys.select.sel_id = cp->target; 7567 cp->phys.select.sel_scntl3 = tp->head.wval; 7568 cp->phys.select.sel_sxfer = tp->head.sval; 7569 cp->phys.select.sel_scntl4 = tp->head.uval; 7570 7571 /* 7572 * message 7573 */ 7574 cp->phys.smsg.addr = cpu_to_scr(CCB_BA (cp, scsi_smsg)); 7575 cp->phys.smsg.size = cpu_to_scr(msglen); 7576 7577 /* 7578 * command 7579 */ 7580 if (sym_setup_cdb(np, csio, cp) < 0) { 7581 sym_xpt_done(np, ccb, cp); 7582 sym_free_ccb(np, cp); 7583 return; 7584 } 7585 7586 /* 7587 * status 7588 */ 7589 #if 0 /* Provision */ 7590 cp->actualquirks = tp->quirks; 7591 #endif 7592 cp->actualquirks = SYM_QUIRK_AUTOSAVE; 7593 cp->host_status = cp->nego_status ? HS_NEGOTIATE : HS_BUSY; 7594 cp->ssss_status = S_ILLEGAL; 7595 cp->xerr_status = 0; 7596 cp->host_flags = 0; 7597 cp->extra_bytes = 0; 7598 7599 /* 7600 * extreme data pointer. 7601 * shall be positive, so -1 is lower than lowest.:) 7602 */ 7603 cp->ext_sg = -1; 7604 cp->ext_ofs = 0; 7605 7606 /* 7607 * Build the data descriptor block 7608 * and start the IO. 7609 */ 7610 sym_setup_data_and_start(np, csio, cp); 7611 } 7612 7613 /* 7614 * Setup buffers and pointers that address the CDB. 7615 * I bet, physical CDBs will never be used on the planet, 7616 * since they can be bounced without significant overhead. 7617 */ 7618 static int sym_setup_cdb(hcb_p np, struct ccb_scsiio *csio, ccb_p cp) 7619 { 7620 struct ccb_hdr *ccb_h; 7621 u32 cmd_ba; 7622 int cmd_len; 7623 7624 SYM_LOCK_ASSERT(MA_OWNED); 7625 7626 ccb_h = &csio->ccb_h; 7627 7628 /* 7629 * CDB is 16 bytes max. 7630 */ 7631 if (csio->cdb_len > sizeof(cp->cdb_buf)) { 7632 sym_set_cam_status(cp->cam_ccb, CAM_REQ_INVALID); 7633 return -1; 7634 } 7635 cmd_len = csio->cdb_len; 7636 7637 if (ccb_h->flags & CAM_CDB_POINTER) { 7638 /* CDB is a pointer */ 7639 if (!(ccb_h->flags & CAM_CDB_PHYS)) { 7640 /* CDB pointer is virtual */ 7641 bcopy(csio->cdb_io.cdb_ptr, cp->cdb_buf, cmd_len); 7642 cmd_ba = CCB_BA (cp, cdb_buf[0]); 7643 } else { 7644 /* CDB pointer is physical */ 7645 #if 0 7646 cmd_ba = ((u32)csio->cdb_io.cdb_ptr) & 0xffffffff; 7647 #else 7648 sym_set_cam_status(cp->cam_ccb, CAM_REQ_INVALID); 7649 return -1; 7650 #endif 7651 } 7652 } else { 7653 /* CDB is in the CAM ccb (buffer) */ 7654 bcopy(csio->cdb_io.cdb_bytes, cp->cdb_buf, cmd_len); 7655 cmd_ba = CCB_BA (cp, cdb_buf[0]); 7656 } 7657 7658 cp->phys.cmd.addr = cpu_to_scr(cmd_ba); 7659 cp->phys.cmd.size = cpu_to_scr(cmd_len); 7660 7661 return 0; 7662 } 7663 7664 /* 7665 * Set up data pointers used by SCRIPTS. 7666 */ 7667 static void __inline 7668 sym_setup_data_pointers(hcb_p np, ccb_p cp, int dir) 7669 { 7670 u32 lastp, goalp; 7671 7672 SYM_LOCK_ASSERT(MA_OWNED); 7673 7674 /* 7675 * No segments means no data. 7676 */ 7677 if (!cp->segments) 7678 dir = CAM_DIR_NONE; 7679 7680 /* 7681 * Set the data pointer. 7682 */ 7683 switch(dir) { 7684 case CAM_DIR_OUT: 7685 goalp = SCRIPTA_BA (np, data_out2) + 8; 7686 lastp = goalp - 8 - (cp->segments * (2*4)); 7687 break; 7688 case CAM_DIR_IN: 7689 cp->host_flags |= HF_DATA_IN; 7690 goalp = SCRIPTA_BA (np, data_in2) + 8; 7691 lastp = goalp - 8 - (cp->segments * (2*4)); 7692 break; 7693 case CAM_DIR_NONE: 7694 default: 7695 lastp = goalp = SCRIPTB_BA (np, no_data); 7696 break; 7697 } 7698 7699 cp->phys.head.lastp = cpu_to_scr(lastp); 7700 cp->phys.head.goalp = cpu_to_scr(goalp); 7701 cp->phys.head.savep = cpu_to_scr(lastp); 7702 cp->startp = cp->phys.head.savep; 7703 } 7704 7705 /* 7706 * Call back routine for the DMA map service. 7707 * If bounce buffers are used (why ?), we may sleep and then 7708 * be called there in another context. 7709 */ 7710 static void 7711 sym_execute_ccb(void *arg, bus_dma_segment_t *psegs, int nsegs, int error) 7712 { 7713 ccb_p cp; 7714 hcb_p np; 7715 union ccb *ccb; 7716 7717 cp = (ccb_p) arg; 7718 ccb = cp->cam_ccb; 7719 np = (hcb_p) cp->arg; 7720 7721 SYM_LOCK_ASSERT(MA_OWNED); 7722 7723 /* 7724 * Deal with weird races. 7725 */ 7726 if (sym_get_cam_status(ccb) != CAM_REQ_INPROG) 7727 goto out_abort; 7728 7729 /* 7730 * Deal with weird errors. 7731 */ 7732 if (error) { 7733 cp->dmamapped = 0; 7734 sym_set_cam_status(cp->cam_ccb, CAM_REQ_ABORTED); 7735 goto out_abort; 7736 } 7737 7738 /* 7739 * Build the data descriptor for the chip. 7740 */ 7741 if (nsegs) { 7742 int retv; 7743 /* 896 rev 1 requires to be careful about boundaries */ 7744 if (np->device_id == PCI_ID_SYM53C896 && np->revision_id <= 1) 7745 retv = sym_scatter_sg_physical(np, cp, psegs, nsegs); 7746 else 7747 retv = sym_fast_scatter_sg_physical(np,cp, psegs,nsegs); 7748 if (retv < 0) { 7749 sym_set_cam_status(cp->cam_ccb, CAM_REQ_TOO_BIG); 7750 goto out_abort; 7751 } 7752 } 7753 7754 /* 7755 * Synchronize the DMA map only if we have 7756 * actually mapped the data. 7757 */ 7758 if (cp->dmamapped) { 7759 bus_dmamap_sync(np->data_dmat, cp->dmamap, 7760 (cp->dmamapped == SYM_DMA_READ ? 7761 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 7762 } 7763 7764 /* 7765 * Set host status to busy state. 7766 * May have been set back to HS_WAIT to avoid a race. 7767 */ 7768 cp->host_status = cp->nego_status ? HS_NEGOTIATE : HS_BUSY; 7769 7770 /* 7771 * Set data pointers. 7772 */ 7773 sym_setup_data_pointers(np, cp, (ccb->ccb_h.flags & CAM_DIR_MASK)); 7774 7775 /* 7776 * Enqueue this IO in our pending queue. 7777 */ 7778 sym_enqueue_cam_ccb(cp); 7779 7780 /* 7781 * When `#ifed 1', the code below makes the driver 7782 * panic on the first attempt to write to a SCSI device. 7783 * It is the first test we want to do after a driver 7784 * change that does not seem obviously safe. :) 7785 */ 7786 #if 0 7787 switch (cp->cdb_buf[0]) { 7788 case 0x0A: case 0x2A: case 0xAA: 7789 panic("XXXXXXXXXXXXX WRITE NOT YET ALLOWED XXXXXXXXXXXXXX\n"); 7790 MDELAY(10000); 7791 break; 7792 default: 7793 break; 7794 } 7795 #endif 7796 /* 7797 * Activate this job. 7798 */ 7799 sym_put_start_queue(np, cp); 7800 return; 7801 out_abort: 7802 sym_xpt_done(np, ccb, cp); 7803 sym_free_ccb(np, cp); 7804 } 7805 7806 /* 7807 * How complex it gets to deal with the data in CAM. 7808 * The Bus Dma stuff makes things still more complex. 7809 */ 7810 static void 7811 sym_setup_data_and_start(hcb_p np, struct ccb_scsiio *csio, ccb_p cp) 7812 { 7813 struct ccb_hdr *ccb_h; 7814 int dir, retv; 7815 7816 SYM_LOCK_ASSERT(MA_OWNED); 7817 7818 ccb_h = &csio->ccb_h; 7819 7820 /* 7821 * Now deal with the data. 7822 */ 7823 cp->data_len = csio->dxfer_len; 7824 cp->arg = np; 7825 7826 /* 7827 * No direction means no data. 7828 */ 7829 dir = (ccb_h->flags & CAM_DIR_MASK); 7830 if (dir == CAM_DIR_NONE) { 7831 sym_execute_ccb(cp, NULL, 0, 0); 7832 return; 7833 } 7834 7835 cp->dmamapped = (dir == CAM_DIR_IN) ? SYM_DMA_READ : SYM_DMA_WRITE; 7836 retv = bus_dmamap_load_ccb(np->data_dmat, cp->dmamap, 7837 (union ccb *)csio, sym_execute_ccb, cp, 0); 7838 if (retv == EINPROGRESS) { 7839 cp->host_status = HS_WAIT; 7840 xpt_freeze_simq(np->sim, 1); 7841 csio->ccb_h.status |= CAM_RELEASE_SIMQ; 7842 } 7843 } 7844 7845 /* 7846 * Move the scatter list to our data block. 7847 */ 7848 static int 7849 sym_fast_scatter_sg_physical(hcb_p np, ccb_p cp, 7850 bus_dma_segment_t *psegs, int nsegs) 7851 { 7852 struct sym_tblmove *data; 7853 bus_dma_segment_t *psegs2; 7854 7855 SYM_LOCK_ASSERT(MA_OWNED); 7856 7857 if (nsegs > SYM_CONF_MAX_SG) 7858 return -1; 7859 7860 data = &cp->phys.data[SYM_CONF_MAX_SG-1]; 7861 psegs2 = &psegs[nsegs-1]; 7862 cp->segments = nsegs; 7863 7864 while (1) { 7865 data->addr = cpu_to_scr(psegs2->ds_addr); 7866 data->size = cpu_to_scr(psegs2->ds_len); 7867 if (DEBUG_FLAGS & DEBUG_SCATTER) { 7868 printf ("%s scatter: paddr=%lx len=%ld\n", 7869 sym_name(np), (long) psegs2->ds_addr, 7870 (long) psegs2->ds_len); 7871 } 7872 if (psegs2 != psegs) { 7873 --data; 7874 --psegs2; 7875 continue; 7876 } 7877 break; 7878 } 7879 return 0; 7880 } 7881 7882 /* 7883 * Scatter a SG list with physical addresses into bus addressable chunks. 7884 */ 7885 static int 7886 sym_scatter_sg_physical(hcb_p np, ccb_p cp, bus_dma_segment_t *psegs, int nsegs) 7887 { 7888 u_long ps, pe, pn; 7889 u_long k; 7890 int s, t; 7891 7892 SYM_LOCK_ASSERT(MA_OWNED); 7893 7894 s = SYM_CONF_MAX_SG - 1; 7895 t = nsegs - 1; 7896 ps = psegs[t].ds_addr; 7897 pe = ps + psegs[t].ds_len; 7898 7899 while (s >= 0) { 7900 pn = rounddown2(pe - 1, SYM_CONF_DMA_BOUNDARY); 7901 if (pn <= ps) 7902 pn = ps; 7903 k = pe - pn; 7904 if (DEBUG_FLAGS & DEBUG_SCATTER) { 7905 printf ("%s scatter: paddr=%lx len=%ld\n", 7906 sym_name(np), pn, k); 7907 } 7908 cp->phys.data[s].addr = cpu_to_scr(pn); 7909 cp->phys.data[s].size = cpu_to_scr(k); 7910 --s; 7911 if (pn == ps) { 7912 if (--t < 0) 7913 break; 7914 ps = psegs[t].ds_addr; 7915 pe = ps + psegs[t].ds_len; 7916 } 7917 else 7918 pe = pn; 7919 } 7920 7921 cp->segments = SYM_CONF_MAX_SG - 1 - s; 7922 7923 return t >= 0 ? -1 : 0; 7924 } 7925 7926 /* 7927 * SIM action for non performance critical stuff. 7928 */ 7929 static void sym_action2(struct cam_sim *sim, union ccb *ccb) 7930 { 7931 union ccb *abort_ccb; 7932 struct ccb_hdr *ccb_h; 7933 struct ccb_pathinq *cpi; 7934 struct ccb_trans_settings *cts; 7935 struct sym_trans *tip; 7936 hcb_p np; 7937 tcb_p tp; 7938 lcb_p lp; 7939 u_char dflags; 7940 7941 /* 7942 * Retrieve our controller data structure. 7943 */ 7944 np = (hcb_p) cam_sim_softc(sim); 7945 7946 SYM_LOCK_ASSERT(MA_OWNED); 7947 7948 ccb_h = &ccb->ccb_h; 7949 7950 switch (ccb_h->func_code) { 7951 case XPT_SET_TRAN_SETTINGS: 7952 cts = &ccb->cts; 7953 tp = &np->target[ccb_h->target_id]; 7954 7955 /* 7956 * Update SPI transport settings in TARGET control block. 7957 * Update SCSI device settings in LUN control block. 7958 */ 7959 lp = sym_lp(tp, ccb_h->target_lun); 7960 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) { 7961 sym_update_trans(np, &tp->tinfo.goal, cts); 7962 if (lp) 7963 sym_update_dflags(np, &lp->current_flags, cts); 7964 } 7965 if (cts->type == CTS_TYPE_USER_SETTINGS) { 7966 sym_update_trans(np, &tp->tinfo.user, cts); 7967 if (lp) 7968 sym_update_dflags(np, &lp->user_flags, cts); 7969 } 7970 7971 sym_xpt_done2(np, ccb, CAM_REQ_CMP); 7972 break; 7973 case XPT_GET_TRAN_SETTINGS: 7974 cts = &ccb->cts; 7975 tp = &np->target[ccb_h->target_id]; 7976 lp = sym_lp(tp, ccb_h->target_lun); 7977 7978 #define cts__scsi (&cts->proto_specific.scsi) 7979 #define cts__spi (&cts->xport_specific.spi) 7980 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) { 7981 tip = &tp->tinfo.current; 7982 dflags = lp ? lp->current_flags : 0; 7983 } 7984 else { 7985 tip = &tp->tinfo.user; 7986 dflags = lp ? lp->user_flags : tp->usrflags; 7987 } 7988 7989 cts->protocol = PROTO_SCSI; 7990 cts->transport = XPORT_SPI; 7991 cts->protocol_version = tip->scsi_version; 7992 cts->transport_version = tip->spi_version; 7993 7994 cts__spi->sync_period = tip->period; 7995 cts__spi->sync_offset = tip->offset; 7996 cts__spi->bus_width = tip->width; 7997 cts__spi->ppr_options = tip->options; 7998 7999 cts__spi->valid = CTS_SPI_VALID_SYNC_RATE 8000 | CTS_SPI_VALID_SYNC_OFFSET 8001 | CTS_SPI_VALID_BUS_WIDTH 8002 | CTS_SPI_VALID_PPR_OPTIONS; 8003 8004 cts__spi->flags &= ~CTS_SPI_FLAGS_DISC_ENB; 8005 if (dflags & SYM_DISC_ENABLED) 8006 cts__spi->flags |= CTS_SPI_FLAGS_DISC_ENB; 8007 cts__spi->valid |= CTS_SPI_VALID_DISC; 8008 8009 cts__scsi->flags &= ~CTS_SCSI_FLAGS_TAG_ENB; 8010 if (dflags & SYM_TAGS_ENABLED) 8011 cts__scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB; 8012 cts__scsi->valid |= CTS_SCSI_VALID_TQ; 8013 #undef cts__spi 8014 #undef cts__scsi 8015 sym_xpt_done2(np, ccb, CAM_REQ_CMP); 8016 break; 8017 case XPT_CALC_GEOMETRY: 8018 cam_calc_geometry(&ccb->ccg, /*extended*/1); 8019 sym_xpt_done2(np, ccb, CAM_REQ_CMP); 8020 break; 8021 case XPT_PATH_INQ: 8022 cpi = &ccb->cpi; 8023 cpi->version_num = 1; 8024 cpi->hba_inquiry = PI_MDP_ABLE|PI_SDTR_ABLE|PI_TAG_ABLE; 8025 if ((np->features & FE_WIDE) != 0) 8026 cpi->hba_inquiry |= PI_WIDE_16; 8027 cpi->target_sprt = 0; 8028 cpi->hba_misc = PIM_UNMAPPED; 8029 if (np->usrflags & SYM_SCAN_TARGETS_HILO) 8030 cpi->hba_misc |= PIM_SCANHILO; 8031 if (np->usrflags & SYM_AVOID_BUS_RESET) 8032 cpi->hba_misc |= PIM_NOBUSRESET; 8033 cpi->hba_eng_cnt = 0; 8034 cpi->max_target = (np->features & FE_WIDE) ? 15 : 7; 8035 /* Semantic problem:)LUN number max = max number of LUNs - 1 */ 8036 cpi->max_lun = SYM_CONF_MAX_LUN-1; 8037 if (SYM_SETUP_MAX_LUN < SYM_CONF_MAX_LUN) 8038 cpi->max_lun = SYM_SETUP_MAX_LUN-1; 8039 cpi->bus_id = cam_sim_bus(sim); 8040 cpi->initiator_id = np->myaddr; 8041 cpi->base_transfer_speed = 3300; 8042 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 8043 strlcpy(cpi->hba_vid, "Symbios", HBA_IDLEN); 8044 strlcpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 8045 cpi->unit_number = cam_sim_unit(sim); 8046 8047 cpi->protocol = PROTO_SCSI; 8048 cpi->protocol_version = SCSI_REV_2; 8049 cpi->transport = XPORT_SPI; 8050 cpi->transport_version = 2; 8051 cpi->xport_specific.spi.ppr_options = SID_SPI_CLOCK_ST; 8052 if (np->features & FE_ULTRA3) { 8053 cpi->transport_version = 3; 8054 cpi->xport_specific.spi.ppr_options = 8055 SID_SPI_CLOCK_DT_ST; 8056 } 8057 cpi->maxio = SYM_CONF_MAX_SG * PAGE_SIZE; 8058 sym_xpt_done2(np, ccb, CAM_REQ_CMP); 8059 break; 8060 case XPT_ABORT: 8061 abort_ccb = ccb->cab.abort_ccb; 8062 switch(abort_ccb->ccb_h.func_code) { 8063 case XPT_SCSI_IO: 8064 if (sym_abort_scsiio(np, abort_ccb, 0) == 0) { 8065 sym_xpt_done2(np, ccb, CAM_REQ_CMP); 8066 break; 8067 } 8068 default: 8069 sym_xpt_done2(np, ccb, CAM_UA_ABORT); 8070 break; 8071 } 8072 break; 8073 case XPT_RESET_DEV: 8074 sym_reset_dev(np, ccb); 8075 break; 8076 case XPT_RESET_BUS: 8077 sym_reset_scsi_bus(np, 0); 8078 if (sym_verbose) { 8079 xpt_print_path(np->path); 8080 printf("SCSI BUS reset delivered.\n"); 8081 } 8082 sym_init (np, 1); 8083 sym_xpt_done2(np, ccb, CAM_REQ_CMP); 8084 break; 8085 case XPT_TERM_IO: 8086 default: 8087 sym_xpt_done2(np, ccb, CAM_REQ_INVALID); 8088 break; 8089 } 8090 } 8091 8092 /* 8093 * Asynchronous notification handler. 8094 */ 8095 static void 8096 sym_async(void *cb_arg, u32 code, struct cam_path *path, void *args __unused) 8097 { 8098 hcb_p np; 8099 struct cam_sim *sim; 8100 u_int tn; 8101 tcb_p tp; 8102 8103 sim = (struct cam_sim *) cb_arg; 8104 np = (hcb_p) cam_sim_softc(sim); 8105 8106 SYM_LOCK_ASSERT(MA_OWNED); 8107 8108 switch (code) { 8109 case AC_LOST_DEVICE: 8110 tn = xpt_path_target_id(path); 8111 if (tn >= SYM_CONF_MAX_TARGET) 8112 break; 8113 8114 tp = &np->target[tn]; 8115 8116 tp->to_reset = 0; 8117 tp->head.sval = 0; 8118 tp->head.wval = np->rv_scntl3; 8119 tp->head.uval = 0; 8120 8121 tp->tinfo.current.period = tp->tinfo.goal.period = 0; 8122 tp->tinfo.current.offset = tp->tinfo.goal.offset = 0; 8123 tp->tinfo.current.width = tp->tinfo.goal.width = BUS_8_BIT; 8124 tp->tinfo.current.options = tp->tinfo.goal.options = 0; 8125 8126 break; 8127 default: 8128 break; 8129 } 8130 } 8131 8132 /* 8133 * Update transfer settings of a target. 8134 */ 8135 static void sym_update_trans(hcb_p np, struct sym_trans *tip, 8136 struct ccb_trans_settings *cts) 8137 { 8138 8139 SYM_LOCK_ASSERT(MA_OWNED); 8140 8141 /* 8142 * Update the infos. 8143 */ 8144 #define cts__spi (&cts->xport_specific.spi) 8145 if ((cts__spi->valid & CTS_SPI_VALID_BUS_WIDTH) != 0) 8146 tip->width = cts__spi->bus_width; 8147 if ((cts__spi->valid & CTS_SPI_VALID_SYNC_OFFSET) != 0) 8148 tip->offset = cts__spi->sync_offset; 8149 if ((cts__spi->valid & CTS_SPI_VALID_SYNC_RATE) != 0) 8150 tip->period = cts__spi->sync_period; 8151 if ((cts__spi->valid & CTS_SPI_VALID_PPR_OPTIONS) != 0) 8152 tip->options = (cts__spi->ppr_options & PPR_OPT_DT); 8153 if (cts->protocol_version != PROTO_VERSION_UNSPECIFIED && 8154 cts->protocol_version != PROTO_VERSION_UNKNOWN) 8155 tip->scsi_version = cts->protocol_version; 8156 if (cts->transport_version != XPORT_VERSION_UNSPECIFIED && 8157 cts->transport_version != XPORT_VERSION_UNKNOWN) 8158 tip->spi_version = cts->transport_version; 8159 #undef cts__spi 8160 /* 8161 * Scale against driver configuration limits. 8162 */ 8163 if (tip->width > SYM_SETUP_MAX_WIDE) tip->width = SYM_SETUP_MAX_WIDE; 8164 if (tip->period && tip->offset) { 8165 if (tip->offset > SYM_SETUP_MAX_OFFS) tip->offset = SYM_SETUP_MAX_OFFS; 8166 if (tip->period < SYM_SETUP_MIN_SYNC) tip->period = SYM_SETUP_MIN_SYNC; 8167 } else { 8168 tip->offset = 0; 8169 tip->period = 0; 8170 } 8171 8172 /* 8173 * Scale against actual controller BUS width. 8174 */ 8175 if (tip->width > np->maxwide) 8176 tip->width = np->maxwide; 8177 8178 /* 8179 * Only accept DT if controller supports and SYNC/WIDE asked. 8180 */ 8181 if (!((np->features & (FE_C10|FE_ULTRA3)) == (FE_C10|FE_ULTRA3)) || 8182 !(tip->width == BUS_16_BIT && tip->offset)) { 8183 tip->options &= ~PPR_OPT_DT; 8184 } 8185 8186 /* 8187 * Scale period factor and offset against controller limits. 8188 */ 8189 if (tip->offset && tip->period) { 8190 if (tip->options & PPR_OPT_DT) { 8191 if (tip->period < np->minsync_dt) 8192 tip->period = np->minsync_dt; 8193 if (tip->period > np->maxsync_dt) 8194 tip->period = np->maxsync_dt; 8195 if (tip->offset > np->maxoffs_dt) 8196 tip->offset = np->maxoffs_dt; 8197 } 8198 else { 8199 if (tip->period < np->minsync) 8200 tip->period = np->minsync; 8201 if (tip->period > np->maxsync) 8202 tip->period = np->maxsync; 8203 if (tip->offset > np->maxoffs) 8204 tip->offset = np->maxoffs; 8205 } 8206 } 8207 } 8208 8209 /* 8210 * Update flags for a device (logical unit). 8211 */ 8212 static void 8213 sym_update_dflags(hcb_p np, u_char *flags, struct ccb_trans_settings *cts) 8214 { 8215 8216 SYM_LOCK_ASSERT(MA_OWNED); 8217 8218 #define cts__scsi (&cts->proto_specific.scsi) 8219 #define cts__spi (&cts->xport_specific.spi) 8220 if ((cts__spi->valid & CTS_SPI_VALID_DISC) != 0) { 8221 if ((cts__spi->flags & CTS_SPI_FLAGS_DISC_ENB) != 0) 8222 *flags |= SYM_DISC_ENABLED; 8223 else 8224 *flags &= ~SYM_DISC_ENABLED; 8225 } 8226 8227 if ((cts__scsi->valid & CTS_SCSI_VALID_TQ) != 0) { 8228 if ((cts__scsi->flags & CTS_SCSI_FLAGS_TAG_ENB) != 0) 8229 *flags |= SYM_TAGS_ENABLED; 8230 else 8231 *flags &= ~SYM_TAGS_ENABLED; 8232 } 8233 #undef cts__spi 8234 #undef cts__scsi 8235 } 8236 8237 /*============= DRIVER INITIALISATION ==================*/ 8238 8239 static device_method_t sym_pci_methods[] = { 8240 DEVMETHOD(device_probe, sym_pci_probe), 8241 DEVMETHOD(device_attach, sym_pci_attach), 8242 DEVMETHOD_END 8243 }; 8244 8245 static driver_t sym_pci_driver = { 8246 "sym", 8247 sym_pci_methods, 8248 1 /* no softc */ 8249 }; 8250 8251 static devclass_t sym_devclass; 8252 8253 DRIVER_MODULE(sym, pci, sym_pci_driver, sym_devclass, NULL, NULL); 8254 MODULE_DEPEND(sym, cam, 1, 1, 1); 8255 MODULE_DEPEND(sym, pci, 1, 1, 1); 8256 8257 static const struct sym_pci_chip sym_pci_dev_table[] = { 8258 {PCI_ID_SYM53C810, 0x0f, "810", 4, 8, 4, 64, 8259 FE_ERL} 8260 , 8261 #ifdef SYM_DEBUG_GENERIC_SUPPORT 8262 {PCI_ID_SYM53C810, 0xff, "810a", 4, 8, 4, 1, 8263 FE_BOF} 8264 , 8265 #else 8266 {PCI_ID_SYM53C810, 0xff, "810a", 4, 8, 4, 1, 8267 FE_CACHE_SET|FE_LDSTR|FE_PFEN|FE_BOF} 8268 , 8269 #endif 8270 {PCI_ID_SYM53C815, 0xff, "815", 4, 8, 4, 64, 8271 FE_BOF|FE_ERL} 8272 , 8273 {PCI_ID_SYM53C825, 0x0f, "825", 6, 8, 4, 64, 8274 FE_WIDE|FE_BOF|FE_ERL|FE_DIFF} 8275 , 8276 {PCI_ID_SYM53C825, 0xff, "825a", 6, 8, 4, 2, 8277 FE_WIDE|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM|FE_DIFF} 8278 , 8279 {PCI_ID_SYM53C860, 0xff, "860", 4, 8, 5, 1, 8280 FE_ULTRA|FE_CLK80|FE_CACHE_SET|FE_BOF|FE_LDSTR|FE_PFEN} 8281 , 8282 {PCI_ID_SYM53C875, 0x01, "875", 6, 16, 5, 2, 8283 FE_WIDE|FE_ULTRA|FE_CLK80|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 8284 FE_RAM|FE_DIFF} 8285 , 8286 {PCI_ID_SYM53C875, 0xff, "875", 6, 16, 5, 2, 8287 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 8288 FE_RAM|FE_DIFF} 8289 , 8290 {PCI_ID_SYM53C875_2, 0xff, "875", 6, 16, 5, 2, 8291 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 8292 FE_RAM|FE_DIFF} 8293 , 8294 {PCI_ID_SYM53C885, 0xff, "885", 6, 16, 5, 2, 8295 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 8296 FE_RAM|FE_DIFF} 8297 , 8298 #ifdef SYM_DEBUG_GENERIC_SUPPORT 8299 {PCI_ID_SYM53C895, 0xff, "895", 6, 31, 7, 2, 8300 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS| 8301 FE_RAM|FE_LCKFRQ} 8302 , 8303 #else 8304 {PCI_ID_SYM53C895, 0xff, "895", 6, 31, 7, 2, 8305 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 8306 FE_RAM|FE_LCKFRQ} 8307 , 8308 #endif 8309 {PCI_ID_SYM53C896, 0xff, "896", 6, 31, 7, 4, 8310 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 8311 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_LCKFRQ} 8312 , 8313 {PCI_ID_SYM53C895A, 0xff, "895a", 6, 31, 7, 4, 8314 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 8315 FE_RAM|FE_RAM8K|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_LCKFRQ} 8316 , 8317 {PCI_ID_LSI53C1010, 0x00, "1010-33", 6, 31, 7, 8, 8318 FE_WIDE|FE_ULTRA3|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFBC|FE_LDSTR|FE_PFEN| 8319 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_CRC| 8320 FE_C10} 8321 , 8322 {PCI_ID_LSI53C1010, 0xff, "1010-33", 6, 31, 7, 8, 8323 FE_WIDE|FE_ULTRA3|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFBC|FE_LDSTR|FE_PFEN| 8324 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_CRC| 8325 FE_C10|FE_U3EN} 8326 , 8327 {PCI_ID_LSI53C1010_2, 0xff, "1010-66", 6, 31, 7, 8, 8328 FE_WIDE|FE_ULTRA3|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFBC|FE_LDSTR|FE_PFEN| 8329 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_66MHZ|FE_CRC| 8330 FE_C10|FE_U3EN} 8331 , 8332 {PCI_ID_LSI53C1510D, 0xff, "1510d", 6, 31, 7, 4, 8333 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 8334 FE_RAM|FE_IO256|FE_LEDC} 8335 }; 8336 8337 /* 8338 * Look up the chip table. 8339 * 8340 * Return a pointer to the chip entry if found, 8341 * zero otherwise. 8342 */ 8343 static const struct sym_pci_chip * 8344 sym_find_pci_chip(device_t dev) 8345 { 8346 const struct sym_pci_chip *chip; 8347 int i; 8348 u_short device_id; 8349 u_char revision; 8350 8351 if (pci_get_vendor(dev) != PCI_VENDOR_NCR) 8352 return NULL; 8353 8354 device_id = pci_get_device(dev); 8355 revision = pci_get_revid(dev); 8356 8357 for (i = 0; i < nitems(sym_pci_dev_table); i++) { 8358 chip = &sym_pci_dev_table[i]; 8359 if (device_id != chip->device_id) 8360 continue; 8361 if (revision > chip->revision_id) 8362 continue; 8363 return chip; 8364 } 8365 8366 return NULL; 8367 } 8368 8369 /* 8370 * Tell upper layer if the chip is supported. 8371 */ 8372 static int 8373 sym_pci_probe(device_t dev) 8374 { 8375 const struct sym_pci_chip *chip; 8376 8377 chip = sym_find_pci_chip(dev); 8378 if (chip && sym_find_firmware(chip)) { 8379 device_set_desc(dev, chip->name); 8380 return BUS_PROBE_DEFAULT; 8381 } 8382 return ENXIO; 8383 } 8384 8385 /* 8386 * Attach a sym53c8xx device. 8387 */ 8388 static int 8389 sym_pci_attach(device_t dev) 8390 { 8391 const struct sym_pci_chip *chip; 8392 u_short command; 8393 u_char cachelnsz; 8394 struct sym_hcb *np = NULL; 8395 struct sym_nvram nvram; 8396 const struct sym_fw *fw = NULL; 8397 int i; 8398 bus_dma_tag_t bus_dmat; 8399 8400 bus_dmat = bus_get_dma_tag(dev); 8401 8402 /* 8403 * Only probed devices should be attached. 8404 * We just enjoy being paranoid. :) 8405 */ 8406 chip = sym_find_pci_chip(dev); 8407 if (chip == NULL || (fw = sym_find_firmware(chip)) == NULL) 8408 return (ENXIO); 8409 8410 /* 8411 * Allocate immediately the host control block, 8412 * since we are only expecting to succeed. :) 8413 * We keep track in the HCB of all the resources that 8414 * are to be released on error. 8415 */ 8416 np = __sym_calloc_dma(bus_dmat, sizeof(*np), "HCB"); 8417 if (np) 8418 np->bus_dmat = bus_dmat; 8419 else 8420 return (ENXIO); 8421 device_set_softc(dev, np); 8422 8423 SYM_LOCK_INIT(); 8424 8425 /* 8426 * Copy some useful infos to the HCB. 8427 */ 8428 np->hcb_ba = vtobus(np); 8429 np->verbose = bootverbose; 8430 np->device = dev; 8431 np->device_id = pci_get_device(dev); 8432 np->revision_id = pci_get_revid(dev); 8433 np->features = chip->features; 8434 np->clock_divn = chip->nr_divisor; 8435 np->maxoffs = chip->offset_max; 8436 np->maxburst = chip->burst_max; 8437 np->scripta_sz = fw->a_size; 8438 np->scriptb_sz = fw->b_size; 8439 np->fw_setup = fw->setup; 8440 np->fw_patch = fw->patch; 8441 np->fw_name = fw->name; 8442 8443 #ifdef __amd64__ 8444 np->target = sym_calloc_dma(SYM_CONF_MAX_TARGET * sizeof(*(np->target)), 8445 "TARGET"); 8446 if (!np->target) 8447 goto attach_failed; 8448 #endif 8449 8450 /* 8451 * Initialize the CCB free and busy queues. 8452 */ 8453 sym_que_init(&np->free_ccbq); 8454 sym_que_init(&np->busy_ccbq); 8455 sym_que_init(&np->comp_ccbq); 8456 sym_que_init(&np->cam_ccbq); 8457 8458 /* 8459 * Allocate a tag for the DMA of user data. 8460 */ 8461 if (bus_dma_tag_create(np->bus_dmat, 1, SYM_CONF_DMA_BOUNDARY, 8462 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 8463 BUS_SPACE_MAXSIZE_32BIT, SYM_CONF_MAX_SG, SYM_CONF_DMA_BOUNDARY, 8464 0, busdma_lock_mutex, &np->mtx, &np->data_dmat)) { 8465 device_printf(dev, "failed to create DMA tag.\n"); 8466 goto attach_failed; 8467 } 8468 8469 /* 8470 * Read and apply some fix-ups to the PCI COMMAND 8471 * register. We want the chip to be enabled for: 8472 * - BUS mastering 8473 * - PCI parity checking (reporting would also be fine) 8474 * - Write And Invalidate. 8475 */ 8476 command = pci_read_config(dev, PCIR_COMMAND, 2); 8477 command |= PCIM_CMD_BUSMASTEREN | PCIM_CMD_PERRESPEN | 8478 PCIM_CMD_MWRICEN; 8479 pci_write_config(dev, PCIR_COMMAND, command, 2); 8480 8481 /* 8482 * Let the device know about the cache line size, 8483 * if it doesn't yet. 8484 */ 8485 cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 8486 if (!cachelnsz) { 8487 cachelnsz = 8; 8488 pci_write_config(dev, PCIR_CACHELNSZ, cachelnsz, 1); 8489 } 8490 8491 /* 8492 * Alloc/get/map/retrieve everything that deals with MMIO. 8493 */ 8494 i = SYM_PCI_MMIO; 8495 np->mmio_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &i, 8496 RF_ACTIVE); 8497 if (!np->mmio_res) { 8498 device_printf(dev, "failed to allocate MMIO resources\n"); 8499 goto attach_failed; 8500 } 8501 np->mmio_ba = rman_get_start(np->mmio_res); 8502 8503 /* 8504 * Allocate the IRQ. 8505 */ 8506 i = 0; 8507 np->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, 8508 RF_ACTIVE | RF_SHAREABLE); 8509 if (!np->irq_res) { 8510 device_printf(dev, "failed to allocate IRQ resource\n"); 8511 goto attach_failed; 8512 } 8513 8514 #ifdef SYM_CONF_IOMAPPED 8515 /* 8516 * User want us to use normal IO with PCI. 8517 * Alloc/get/map/retrieve everything that deals with IO. 8518 */ 8519 i = SYM_PCI_IO; 8520 np->io_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &i, RF_ACTIVE); 8521 if (!np->io_res) { 8522 device_printf(dev, "failed to allocate IO resources\n"); 8523 goto attach_failed; 8524 } 8525 8526 #endif /* SYM_CONF_IOMAPPED */ 8527 8528 /* 8529 * If the chip has RAM. 8530 * Alloc/get/map/retrieve the corresponding resources. 8531 */ 8532 if (np->features & (FE_RAM|FE_RAM8K)) { 8533 int regs_id = SYM_PCI_RAM; 8534 if (np->features & FE_64BIT) 8535 regs_id = SYM_PCI_RAM64; 8536 np->ram_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 8537 ®s_id, RF_ACTIVE); 8538 if (!np->ram_res) { 8539 device_printf(dev,"failed to allocate RAM resources\n"); 8540 goto attach_failed; 8541 } 8542 np->ram_id = regs_id; 8543 np->ram_ba = rman_get_start(np->ram_res); 8544 } 8545 8546 /* 8547 * Save setting of some IO registers, so we will 8548 * be able to probe specific implementations. 8549 */ 8550 sym_save_initial_setting (np); 8551 8552 /* 8553 * Reset the chip now, since it has been reported 8554 * that SCSI clock calibration may not work properly 8555 * if the chip is currently active. 8556 */ 8557 sym_chip_reset (np); 8558 8559 /* 8560 * Try to read the user set-up. 8561 */ 8562 (void) sym_read_nvram(np, &nvram); 8563 8564 /* 8565 * Prepare controller and devices settings, according 8566 * to chip features, user set-up and driver set-up. 8567 */ 8568 (void) sym_prepare_setting(np, &nvram); 8569 8570 /* 8571 * Check the PCI clock frequency. 8572 * Must be performed after prepare_setting since it destroys 8573 * STEST1 that is used to probe for the clock doubler. 8574 */ 8575 i = sym_getpciclock(np); 8576 if (i > 37000) 8577 device_printf(dev, "PCI BUS clock seems too high: %u KHz.\n",i); 8578 8579 /* 8580 * Allocate the start queue. 8581 */ 8582 np->squeue = (u32 *) sym_calloc_dma(sizeof(u32)*(MAX_QUEUE*2),"SQUEUE"); 8583 if (!np->squeue) 8584 goto attach_failed; 8585 np->squeue_ba = vtobus(np->squeue); 8586 8587 /* 8588 * Allocate the done queue. 8589 */ 8590 np->dqueue = (u32 *) sym_calloc_dma(sizeof(u32)*(MAX_QUEUE*2),"DQUEUE"); 8591 if (!np->dqueue) 8592 goto attach_failed; 8593 np->dqueue_ba = vtobus(np->dqueue); 8594 8595 /* 8596 * Allocate the target bus address array. 8597 */ 8598 np->targtbl = (u32 *) sym_calloc_dma(256, "TARGTBL"); 8599 if (!np->targtbl) 8600 goto attach_failed; 8601 np->targtbl_ba = vtobus(np->targtbl); 8602 8603 /* 8604 * Allocate SCRIPTS areas. 8605 */ 8606 np->scripta0 = sym_calloc_dma(np->scripta_sz, "SCRIPTA0"); 8607 np->scriptb0 = sym_calloc_dma(np->scriptb_sz, "SCRIPTB0"); 8608 if (!np->scripta0 || !np->scriptb0) 8609 goto attach_failed; 8610 8611 /* 8612 * Allocate the CCBs. We need at least ONE. 8613 */ 8614 for (i = 0; sym_alloc_ccb(np) != NULL; i++) 8615 ; 8616 if (i < 1) 8617 goto attach_failed; 8618 8619 /* 8620 * Calculate BUS addresses where we are going 8621 * to load the SCRIPTS. 8622 */ 8623 np->scripta_ba = vtobus(np->scripta0); 8624 np->scriptb_ba = vtobus(np->scriptb0); 8625 np->scriptb0_ba = np->scriptb_ba; 8626 8627 if (np->ram_ba) { 8628 np->scripta_ba = np->ram_ba; 8629 if (np->features & FE_RAM8K) { 8630 np->ram_ws = 8192; 8631 np->scriptb_ba = np->scripta_ba + 4096; 8632 #ifdef __LP64__ 8633 np->scr_ram_seg = cpu_to_scr(np->scripta_ba >> 32); 8634 #endif 8635 } 8636 else 8637 np->ram_ws = 4096; 8638 } 8639 8640 /* 8641 * Copy scripts to controller instance. 8642 */ 8643 bcopy(fw->a_base, np->scripta0, np->scripta_sz); 8644 bcopy(fw->b_base, np->scriptb0, np->scriptb_sz); 8645 8646 /* 8647 * Setup variable parts in scripts and compute 8648 * scripts bus addresses used from the C code. 8649 */ 8650 np->fw_setup(np, fw); 8651 8652 /* 8653 * Bind SCRIPTS with physical addresses usable by the 8654 * SCRIPTS processor (as seen from the BUS = BUS addresses). 8655 */ 8656 sym_fw_bind_script(np, (u32 *) np->scripta0, np->scripta_sz); 8657 sym_fw_bind_script(np, (u32 *) np->scriptb0, np->scriptb_sz); 8658 8659 #ifdef SYM_CONF_IARB_SUPPORT 8660 /* 8661 * If user wants IARB to be set when we win arbitration 8662 * and have other jobs, compute the max number of consecutive 8663 * settings of IARB hints before we leave devices a chance to 8664 * arbitrate for reselection. 8665 */ 8666 #ifdef SYM_SETUP_IARB_MAX 8667 np->iarb_max = SYM_SETUP_IARB_MAX; 8668 #else 8669 np->iarb_max = 4; 8670 #endif 8671 #endif 8672 8673 /* 8674 * Prepare the idle and invalid task actions. 8675 */ 8676 np->idletask.start = cpu_to_scr(SCRIPTA_BA (np, idle)); 8677 np->idletask.restart = cpu_to_scr(SCRIPTB_BA (np, bad_i_t_l)); 8678 np->idletask_ba = vtobus(&np->idletask); 8679 8680 np->notask.start = cpu_to_scr(SCRIPTA_BA (np, idle)); 8681 np->notask.restart = cpu_to_scr(SCRIPTB_BA (np, bad_i_t_l)); 8682 np->notask_ba = vtobus(&np->notask); 8683 8684 np->bad_itl.start = cpu_to_scr(SCRIPTA_BA (np, idle)); 8685 np->bad_itl.restart = cpu_to_scr(SCRIPTB_BA (np, bad_i_t_l)); 8686 np->bad_itl_ba = vtobus(&np->bad_itl); 8687 8688 np->bad_itlq.start = cpu_to_scr(SCRIPTA_BA (np, idle)); 8689 np->bad_itlq.restart = cpu_to_scr(SCRIPTB_BA (np,bad_i_t_l_q)); 8690 np->bad_itlq_ba = vtobus(&np->bad_itlq); 8691 8692 /* 8693 * Allocate and prepare the lun JUMP table that is used 8694 * for a target prior the probing of devices (bad lun table). 8695 * A private table will be allocated for the target on the 8696 * first INQUIRY response received. 8697 */ 8698 np->badluntbl = sym_calloc_dma(256, "BADLUNTBL"); 8699 if (!np->badluntbl) 8700 goto attach_failed; 8701 8702 np->badlun_sa = cpu_to_scr(SCRIPTB_BA (np, resel_bad_lun)); 8703 for (i = 0 ; i < 64 ; i++) /* 64 luns/target, no less */ 8704 np->badluntbl[i] = cpu_to_scr(vtobus(&np->badlun_sa)); 8705 8706 /* 8707 * Prepare the bus address array that contains the bus 8708 * address of each target control block. 8709 * For now, assume all logical units are wrong. :) 8710 */ 8711 for (i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) { 8712 np->targtbl[i] = cpu_to_scr(vtobus(&np->target[i])); 8713 np->target[i].head.luntbl_sa = 8714 cpu_to_scr(vtobus(np->badluntbl)); 8715 np->target[i].head.lun0_sa = 8716 cpu_to_scr(vtobus(&np->badlun_sa)); 8717 } 8718 8719 /* 8720 * Now check the cache handling of the pci chipset. 8721 */ 8722 if (sym_snooptest (np)) { 8723 device_printf(dev, "CACHE INCORRECTLY CONFIGURED.\n"); 8724 goto attach_failed; 8725 } 8726 8727 /* 8728 * Now deal with CAM. 8729 * Hopefully, we will succeed with that one.:) 8730 */ 8731 if (!sym_cam_attach(np)) 8732 goto attach_failed; 8733 8734 /* 8735 * Sigh! we are done. 8736 */ 8737 return 0; 8738 8739 /* 8740 * We have failed. 8741 * We will try to free all the resources we have 8742 * allocated, but if we are a boot device, this 8743 * will not help that much.;) 8744 */ 8745 attach_failed: 8746 if (np) 8747 sym_pci_free(np); 8748 return ENXIO; 8749 } 8750 8751 /* 8752 * Free everything that have been allocated for this device. 8753 */ 8754 static void sym_pci_free(hcb_p np) 8755 { 8756 SYM_QUEHEAD *qp; 8757 ccb_p cp; 8758 tcb_p tp; 8759 lcb_p lp; 8760 int target, lun; 8761 8762 /* 8763 * First free CAM resources. 8764 */ 8765 sym_cam_free(np); 8766 8767 /* 8768 * Now every should be quiet for us to 8769 * free other resources. 8770 */ 8771 if (np->ram_res) 8772 bus_release_resource(np->device, SYS_RES_MEMORY, 8773 np->ram_id, np->ram_res); 8774 if (np->mmio_res) 8775 bus_release_resource(np->device, SYS_RES_MEMORY, 8776 SYM_PCI_MMIO, np->mmio_res); 8777 if (np->io_res) 8778 bus_release_resource(np->device, SYS_RES_IOPORT, 8779 SYM_PCI_IO, np->io_res); 8780 if (np->irq_res) 8781 bus_release_resource(np->device, SYS_RES_IRQ, 8782 0, np->irq_res); 8783 8784 if (np->scriptb0) 8785 sym_mfree_dma(np->scriptb0, np->scriptb_sz, "SCRIPTB0"); 8786 if (np->scripta0) 8787 sym_mfree_dma(np->scripta0, np->scripta_sz, "SCRIPTA0"); 8788 if (np->squeue) 8789 sym_mfree_dma(np->squeue, sizeof(u32)*(MAX_QUEUE*2), "SQUEUE"); 8790 if (np->dqueue) 8791 sym_mfree_dma(np->dqueue, sizeof(u32)*(MAX_QUEUE*2), "DQUEUE"); 8792 8793 while ((qp = sym_remque_head(&np->free_ccbq)) != NULL) { 8794 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 8795 bus_dmamap_destroy(np->data_dmat, cp->dmamap); 8796 sym_mfree_dma(cp->sns_bbuf, SYM_SNS_BBUF_LEN, "SNS_BBUF"); 8797 sym_mfree_dma(cp, sizeof(*cp), "CCB"); 8798 } 8799 8800 if (np->badluntbl) 8801 sym_mfree_dma(np->badluntbl, 256,"BADLUNTBL"); 8802 8803 for (target = 0; target < SYM_CONF_MAX_TARGET ; target++) { 8804 tp = &np->target[target]; 8805 for (lun = 0 ; lun < SYM_CONF_MAX_LUN ; lun++) { 8806 lp = sym_lp(tp, lun); 8807 if (!lp) 8808 continue; 8809 if (lp->itlq_tbl) 8810 sym_mfree_dma(lp->itlq_tbl, SYM_CONF_MAX_TASK*4, 8811 "ITLQ_TBL"); 8812 if (lp->cb_tags) 8813 sym_mfree(lp->cb_tags, SYM_CONF_MAX_TASK, 8814 "CB_TAGS"); 8815 sym_mfree_dma(lp, sizeof(*lp), "LCB"); 8816 } 8817 #if SYM_CONF_MAX_LUN > 1 8818 if (tp->lunmp) 8819 sym_mfree(tp->lunmp, SYM_CONF_MAX_LUN*sizeof(lcb_p), 8820 "LUNMP"); 8821 #endif 8822 } 8823 #ifdef __amd64__ 8824 if (np->target) 8825 sym_mfree_dma(np->target, 8826 SYM_CONF_MAX_TARGET * sizeof(*(np->target)), "TARGET"); 8827 #endif 8828 if (np->targtbl) 8829 sym_mfree_dma(np->targtbl, 256, "TARGTBL"); 8830 if (np->data_dmat) 8831 bus_dma_tag_destroy(np->data_dmat); 8832 if (SYM_LOCK_INITIALIZED() != 0) 8833 SYM_LOCK_DESTROY(); 8834 device_set_softc(np->device, NULL); 8835 sym_mfree_dma(np, sizeof(*np), "HCB"); 8836 } 8837 8838 /* 8839 * Allocate CAM resources and register a bus to CAM. 8840 */ 8841 static int sym_cam_attach(hcb_p np) 8842 { 8843 struct cam_devq *devq = NULL; 8844 struct cam_sim *sim = NULL; 8845 struct cam_path *path = NULL; 8846 int err; 8847 8848 /* 8849 * Establish our interrupt handler. 8850 */ 8851 err = bus_setup_intr(np->device, np->irq_res, 8852 INTR_ENTROPY | INTR_MPSAFE | INTR_TYPE_CAM, 8853 NULL, sym_intr, np, &np->intr); 8854 if (err) { 8855 device_printf(np->device, "bus_setup_intr() failed: %d\n", 8856 err); 8857 goto fail; 8858 } 8859 8860 /* 8861 * Create the device queue for our sym SIM. 8862 */ 8863 devq = cam_simq_alloc(SYM_CONF_MAX_START); 8864 if (!devq) 8865 goto fail; 8866 8867 /* 8868 * Construct our SIM entry. 8869 */ 8870 sim = cam_sim_alloc(sym_action, sym_poll, "sym", np, 8871 device_get_unit(np->device), 8872 &np->mtx, 1, SYM_SETUP_MAX_TAG, devq); 8873 if (!sim) 8874 goto fail; 8875 8876 SYM_LOCK(); 8877 8878 if (xpt_bus_register(sim, np->device, 0) != CAM_SUCCESS) 8879 goto fail; 8880 np->sim = sim; 8881 sim = NULL; 8882 8883 if (xpt_create_path(&path, NULL, 8884 cam_sim_path(np->sim), CAM_TARGET_WILDCARD, 8885 CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 8886 goto fail; 8887 } 8888 np->path = path; 8889 8890 /* 8891 * Establish our async notification handler. 8892 */ 8893 if (xpt_register_async(AC_LOST_DEVICE, sym_async, np->sim, path) != 8894 CAM_REQ_CMP) 8895 goto fail; 8896 8897 /* 8898 * Start the chip now, without resetting the BUS, since 8899 * it seems that this must stay under control of CAM. 8900 * With LVD/SE capable chips and BUS in SE mode, we may 8901 * get a spurious SMBC interrupt. 8902 */ 8903 sym_init (np, 0); 8904 8905 SYM_UNLOCK(); 8906 8907 return 1; 8908 fail: 8909 if (sim) 8910 cam_sim_free(sim, FALSE); 8911 if (devq) 8912 cam_simq_free(devq); 8913 8914 SYM_UNLOCK(); 8915 8916 sym_cam_free(np); 8917 8918 return 0; 8919 } 8920 8921 /* 8922 * Free everything that deals with CAM. 8923 */ 8924 static void sym_cam_free(hcb_p np) 8925 { 8926 8927 SYM_LOCK_ASSERT(MA_NOTOWNED); 8928 8929 if (np->intr) { 8930 bus_teardown_intr(np->device, np->irq_res, np->intr); 8931 np->intr = NULL; 8932 } 8933 8934 SYM_LOCK(); 8935 8936 if (np->sim) { 8937 xpt_bus_deregister(cam_sim_path(np->sim)); 8938 cam_sim_free(np->sim, /*free_devq*/ TRUE); 8939 np->sim = NULL; 8940 } 8941 if (np->path) { 8942 xpt_free_path(np->path); 8943 np->path = NULL; 8944 } 8945 8946 SYM_UNLOCK(); 8947 } 8948 8949 /*============ OPTIONNAL NVRAM SUPPORT =================*/ 8950 8951 /* 8952 * Get host setup from NVRAM. 8953 */ 8954 static void sym_nvram_setup_host (hcb_p np, struct sym_nvram *nvram) 8955 { 8956 #ifdef SYM_CONF_NVRAM_SUPPORT 8957 /* 8958 * Get parity checking, host ID, verbose mode 8959 * and miscellaneous host flags from NVRAM. 8960 */ 8961 switch(nvram->type) { 8962 case SYM_SYMBIOS_NVRAM: 8963 if (!(nvram->data.Symbios.flags & SYMBIOS_PARITY_ENABLE)) 8964 np->rv_scntl0 &= ~0x0a; 8965 np->myaddr = nvram->data.Symbios.host_id & 0x0f; 8966 if (nvram->data.Symbios.flags & SYMBIOS_VERBOSE_MSGS) 8967 np->verbose += 1; 8968 if (nvram->data.Symbios.flags1 & SYMBIOS_SCAN_HI_LO) 8969 np->usrflags |= SYM_SCAN_TARGETS_HILO; 8970 if (nvram->data.Symbios.flags2 & SYMBIOS_AVOID_BUS_RESET) 8971 np->usrflags |= SYM_AVOID_BUS_RESET; 8972 break; 8973 case SYM_TEKRAM_NVRAM: 8974 np->myaddr = nvram->data.Tekram.host_id & 0x0f; 8975 break; 8976 default: 8977 break; 8978 } 8979 #endif 8980 } 8981 8982 /* 8983 * Get target setup from NVRAM. 8984 */ 8985 #ifdef SYM_CONF_NVRAM_SUPPORT 8986 static void sym_Symbios_setup_target(hcb_p np,int target, Symbios_nvram *nvram); 8987 static void sym_Tekram_setup_target(hcb_p np,int target, Tekram_nvram *nvram); 8988 #endif 8989 8990 static void 8991 sym_nvram_setup_target (hcb_p np, int target, struct sym_nvram *nvp) 8992 { 8993 #ifdef SYM_CONF_NVRAM_SUPPORT 8994 switch(nvp->type) { 8995 case SYM_SYMBIOS_NVRAM: 8996 sym_Symbios_setup_target (np, target, &nvp->data.Symbios); 8997 break; 8998 case SYM_TEKRAM_NVRAM: 8999 sym_Tekram_setup_target (np, target, &nvp->data.Tekram); 9000 break; 9001 default: 9002 break; 9003 } 9004 #endif 9005 } 9006 9007 #ifdef SYM_CONF_NVRAM_SUPPORT 9008 /* 9009 * Get target set-up from Symbios format NVRAM. 9010 */ 9011 static void 9012 sym_Symbios_setup_target(hcb_p np, int target, Symbios_nvram *nvram) 9013 { 9014 tcb_p tp = &np->target[target]; 9015 Symbios_target *tn = &nvram->target[target]; 9016 9017 tp->tinfo.user.period = tn->sync_period ? (tn->sync_period + 3) / 4 : 0; 9018 tp->tinfo.user.width = tn->bus_width == 0x10 ? BUS_16_BIT : BUS_8_BIT; 9019 tp->usrtags = 9020 (tn->flags & SYMBIOS_QUEUE_TAGS_ENABLED)? SYM_SETUP_MAX_TAG : 0; 9021 9022 if (!(tn->flags & SYMBIOS_DISCONNECT_ENABLE)) 9023 tp->usrflags &= ~SYM_DISC_ENABLED; 9024 if (!(tn->flags & SYMBIOS_SCAN_AT_BOOT_TIME)) 9025 tp->usrflags |= SYM_SCAN_BOOT_DISABLED; 9026 if (!(tn->flags & SYMBIOS_SCAN_LUNS)) 9027 tp->usrflags |= SYM_SCAN_LUNS_DISABLED; 9028 } 9029 9030 /* 9031 * Get target set-up from Tekram format NVRAM. 9032 */ 9033 static void 9034 sym_Tekram_setup_target(hcb_p np, int target, Tekram_nvram *nvram) 9035 { 9036 tcb_p tp = &np->target[target]; 9037 struct Tekram_target *tn = &nvram->target[target]; 9038 int i; 9039 9040 if (tn->flags & TEKRAM_SYNC_NEGO) { 9041 i = tn->sync_index & 0xf; 9042 tp->tinfo.user.period = Tekram_sync[i]; 9043 } 9044 9045 tp->tinfo.user.width = 9046 (tn->flags & TEKRAM_WIDE_NEGO) ? BUS_16_BIT : BUS_8_BIT; 9047 9048 if (tn->flags & TEKRAM_TAGGED_COMMANDS) { 9049 tp->usrtags = 2 << nvram->max_tags_index; 9050 } 9051 9052 if (tn->flags & TEKRAM_DISCONNECT_ENABLE) 9053 tp->usrflags |= SYM_DISC_ENABLED; 9054 9055 /* If any device does not support parity, we will not use this option */ 9056 if (!(tn->flags & TEKRAM_PARITY_CHECK)) 9057 np->rv_scntl0 &= ~0x0a; /* SCSI parity checking disabled */ 9058 } 9059 9060 #ifdef SYM_CONF_DEBUG_NVRAM 9061 /* 9062 * Dump Symbios format NVRAM for debugging purpose. 9063 */ 9064 static void sym_display_Symbios_nvram(hcb_p np, Symbios_nvram *nvram) 9065 { 9066 int i; 9067 9068 /* display Symbios nvram host data */ 9069 printf("%s: HOST ID=%d%s%s%s%s%s%s\n", 9070 sym_name(np), nvram->host_id & 0x0f, 9071 (nvram->flags & SYMBIOS_SCAM_ENABLE) ? " SCAM" :"", 9072 (nvram->flags & SYMBIOS_PARITY_ENABLE) ? " PARITY" :"", 9073 (nvram->flags & SYMBIOS_VERBOSE_MSGS) ? " VERBOSE" :"", 9074 (nvram->flags & SYMBIOS_CHS_MAPPING) ? " CHS_ALT" :"", 9075 (nvram->flags2 & SYMBIOS_AVOID_BUS_RESET)?" NO_RESET" :"", 9076 (nvram->flags1 & SYMBIOS_SCAN_HI_LO) ? " HI_LO" :""); 9077 9078 /* display Symbios nvram drive data */ 9079 for (i = 0 ; i < 15 ; i++) { 9080 struct Symbios_target *tn = &nvram->target[i]; 9081 printf("%s-%d:%s%s%s%s WIDTH=%d SYNC=%d TMO=%d\n", 9082 sym_name(np), i, 9083 (tn->flags & SYMBIOS_DISCONNECT_ENABLE) ? " DISC" : "", 9084 (tn->flags & SYMBIOS_SCAN_AT_BOOT_TIME) ? " SCAN_BOOT" : "", 9085 (tn->flags & SYMBIOS_SCAN_LUNS) ? " SCAN_LUNS" : "", 9086 (tn->flags & SYMBIOS_QUEUE_TAGS_ENABLED)? " TCQ" : "", 9087 tn->bus_width, 9088 tn->sync_period / 4, 9089 tn->timeout); 9090 } 9091 } 9092 9093 /* 9094 * Dump TEKRAM format NVRAM for debugging purpose. 9095 */ 9096 static const u_char Tekram_boot_delay[7] = {3, 5, 10, 20, 30, 60, 120}; 9097 static void sym_display_Tekram_nvram(hcb_p np, Tekram_nvram *nvram) 9098 { 9099 int i, tags, boot_delay; 9100 char *rem; 9101 9102 /* display Tekram nvram host data */ 9103 tags = 2 << nvram->max_tags_index; 9104 boot_delay = 0; 9105 if (nvram->boot_delay_index < 6) 9106 boot_delay = Tekram_boot_delay[nvram->boot_delay_index]; 9107 switch((nvram->flags & TEKRAM_REMOVABLE_FLAGS) >> 6) { 9108 default: 9109 case 0: rem = ""; break; 9110 case 1: rem = " REMOVABLE=boot device"; break; 9111 case 2: rem = " REMOVABLE=all"; break; 9112 } 9113 9114 printf("%s: HOST ID=%d%s%s%s%s%s%s%s%s%s BOOT DELAY=%d tags=%d\n", 9115 sym_name(np), nvram->host_id & 0x0f, 9116 (nvram->flags1 & SYMBIOS_SCAM_ENABLE) ? " SCAM" :"", 9117 (nvram->flags & TEKRAM_MORE_THAN_2_DRIVES) ? " >2DRIVES" :"", 9118 (nvram->flags & TEKRAM_DRIVES_SUP_1GB) ? " >1GB" :"", 9119 (nvram->flags & TEKRAM_RESET_ON_POWER_ON) ? " RESET" :"", 9120 (nvram->flags & TEKRAM_ACTIVE_NEGATION) ? " ACT_NEG" :"", 9121 (nvram->flags & TEKRAM_IMMEDIATE_SEEK) ? " IMM_SEEK" :"", 9122 (nvram->flags & TEKRAM_SCAN_LUNS) ? " SCAN_LUNS" :"", 9123 (nvram->flags1 & TEKRAM_F2_F6_ENABLED) ? " F2_F6" :"", 9124 rem, boot_delay, tags); 9125 9126 /* display Tekram nvram drive data */ 9127 for (i = 0; i <= 15; i++) { 9128 int sync, j; 9129 struct Tekram_target *tn = &nvram->target[i]; 9130 j = tn->sync_index & 0xf; 9131 sync = Tekram_sync[j]; 9132 printf("%s-%d:%s%s%s%s%s%s PERIOD=%d\n", 9133 sym_name(np), i, 9134 (tn->flags & TEKRAM_PARITY_CHECK) ? " PARITY" : "", 9135 (tn->flags & TEKRAM_SYNC_NEGO) ? " SYNC" : "", 9136 (tn->flags & TEKRAM_DISCONNECT_ENABLE) ? " DISC" : "", 9137 (tn->flags & TEKRAM_START_CMD) ? " START" : "", 9138 (tn->flags & TEKRAM_TAGGED_COMMANDS) ? " TCQ" : "", 9139 (tn->flags & TEKRAM_WIDE_NEGO) ? " WIDE" : "", 9140 sync); 9141 } 9142 } 9143 #endif /* SYM_CONF_DEBUG_NVRAM */ 9144 #endif /* SYM_CONF_NVRAM_SUPPORT */ 9145 9146 /* 9147 * Try reading Symbios or Tekram NVRAM 9148 */ 9149 #ifdef SYM_CONF_NVRAM_SUPPORT 9150 static int sym_read_Symbios_nvram (hcb_p np, Symbios_nvram *nvram); 9151 static int sym_read_Tekram_nvram (hcb_p np, Tekram_nvram *nvram); 9152 #endif 9153 9154 static int sym_read_nvram(hcb_p np, struct sym_nvram *nvp) 9155 { 9156 #ifdef SYM_CONF_NVRAM_SUPPORT 9157 /* 9158 * Try to read SYMBIOS nvram. 9159 * Try to read TEKRAM nvram if Symbios nvram not found. 9160 */ 9161 if (SYM_SETUP_SYMBIOS_NVRAM && 9162 !sym_read_Symbios_nvram (np, &nvp->data.Symbios)) { 9163 nvp->type = SYM_SYMBIOS_NVRAM; 9164 #ifdef SYM_CONF_DEBUG_NVRAM 9165 sym_display_Symbios_nvram(np, &nvp->data.Symbios); 9166 #endif 9167 } 9168 else if (SYM_SETUP_TEKRAM_NVRAM && 9169 !sym_read_Tekram_nvram (np, &nvp->data.Tekram)) { 9170 nvp->type = SYM_TEKRAM_NVRAM; 9171 #ifdef SYM_CONF_DEBUG_NVRAM 9172 sym_display_Tekram_nvram(np, &nvp->data.Tekram); 9173 #endif 9174 } 9175 else 9176 nvp->type = 0; 9177 #else 9178 nvp->type = 0; 9179 #endif 9180 return nvp->type; 9181 } 9182 9183 #ifdef SYM_CONF_NVRAM_SUPPORT 9184 /* 9185 * 24C16 EEPROM reading. 9186 * 9187 * GPOI0 - data in/data out 9188 * GPIO1 - clock 9189 * Symbios NVRAM wiring now also used by Tekram. 9190 */ 9191 9192 #define SET_BIT 0 9193 #define CLR_BIT 1 9194 #define SET_CLK 2 9195 #define CLR_CLK 3 9196 9197 /* 9198 * Set/clear data/clock bit in GPIO0 9199 */ 9200 static void S24C16_set_bit(hcb_p np, u_char write_bit, u_char *gpreg, 9201 int bit_mode) 9202 { 9203 UDELAY (5); 9204 switch (bit_mode){ 9205 case SET_BIT: 9206 *gpreg |= write_bit; 9207 break; 9208 case CLR_BIT: 9209 *gpreg &= 0xfe; 9210 break; 9211 case SET_CLK: 9212 *gpreg |= 0x02; 9213 break; 9214 case CLR_CLK: 9215 *gpreg &= 0xfd; 9216 break; 9217 9218 } 9219 OUTB (nc_gpreg, *gpreg); 9220 UDELAY (5); 9221 } 9222 9223 /* 9224 * Send START condition to NVRAM to wake it up. 9225 */ 9226 static void S24C16_start(hcb_p np, u_char *gpreg) 9227 { 9228 S24C16_set_bit(np, 1, gpreg, SET_BIT); 9229 S24C16_set_bit(np, 0, gpreg, SET_CLK); 9230 S24C16_set_bit(np, 0, gpreg, CLR_BIT); 9231 S24C16_set_bit(np, 0, gpreg, CLR_CLK); 9232 } 9233 9234 /* 9235 * Send STOP condition to NVRAM - puts NVRAM to sleep... ZZzzzz!! 9236 */ 9237 static void S24C16_stop(hcb_p np, u_char *gpreg) 9238 { 9239 S24C16_set_bit(np, 0, gpreg, SET_CLK); 9240 S24C16_set_bit(np, 1, gpreg, SET_BIT); 9241 } 9242 9243 /* 9244 * Read or write a bit to the NVRAM, 9245 * read if GPIO0 input else write if GPIO0 output 9246 */ 9247 static void S24C16_do_bit(hcb_p np, u_char *read_bit, u_char write_bit, 9248 u_char *gpreg) 9249 { 9250 S24C16_set_bit(np, write_bit, gpreg, SET_BIT); 9251 S24C16_set_bit(np, 0, gpreg, SET_CLK); 9252 if (read_bit) 9253 *read_bit = INB (nc_gpreg); 9254 S24C16_set_bit(np, 0, gpreg, CLR_CLK); 9255 S24C16_set_bit(np, 0, gpreg, CLR_BIT); 9256 } 9257 9258 /* 9259 * Output an ACK to the NVRAM after reading, 9260 * change GPIO0 to output and when done back to an input 9261 */ 9262 static void S24C16_write_ack(hcb_p np, u_char write_bit, u_char *gpreg, 9263 u_char *gpcntl) 9264 { 9265 OUTB (nc_gpcntl, *gpcntl & 0xfe); 9266 S24C16_do_bit(np, 0, write_bit, gpreg); 9267 OUTB (nc_gpcntl, *gpcntl); 9268 } 9269 9270 /* 9271 * Input an ACK from NVRAM after writing, 9272 * change GPIO0 to input and when done back to an output 9273 */ 9274 static void S24C16_read_ack(hcb_p np, u_char *read_bit, u_char *gpreg, 9275 u_char *gpcntl) 9276 { 9277 OUTB (nc_gpcntl, *gpcntl | 0x01); 9278 S24C16_do_bit(np, read_bit, 1, gpreg); 9279 OUTB (nc_gpcntl, *gpcntl); 9280 } 9281 9282 /* 9283 * WRITE a byte to the NVRAM and then get an ACK to see it was accepted OK, 9284 * GPIO0 must already be set as an output 9285 */ 9286 static void S24C16_write_byte(hcb_p np, u_char *ack_data, u_char write_data, 9287 u_char *gpreg, u_char *gpcntl) 9288 { 9289 int x; 9290 9291 for (x = 0; x < 8; x++) 9292 S24C16_do_bit(np, 0, (write_data >> (7 - x)) & 0x01, gpreg); 9293 9294 S24C16_read_ack(np, ack_data, gpreg, gpcntl); 9295 } 9296 9297 /* 9298 * READ a byte from the NVRAM and then send an ACK to say we have got it, 9299 * GPIO0 must already be set as an input 9300 */ 9301 static void S24C16_read_byte(hcb_p np, u_char *read_data, u_char ack_data, 9302 u_char *gpreg, u_char *gpcntl) 9303 { 9304 int x; 9305 u_char read_bit; 9306 9307 *read_data = 0; 9308 for (x = 0; x < 8; x++) { 9309 S24C16_do_bit(np, &read_bit, 1, gpreg); 9310 *read_data |= ((read_bit & 0x01) << (7 - x)); 9311 } 9312 9313 S24C16_write_ack(np, ack_data, gpreg, gpcntl); 9314 } 9315 9316 /* 9317 * Read 'len' bytes starting at 'offset'. 9318 */ 9319 static int sym_read_S24C16_nvram (hcb_p np, int offset, u_char *data, int len) 9320 { 9321 u_char gpcntl, gpreg; 9322 u_char old_gpcntl, old_gpreg; 9323 u_char ack_data; 9324 int retv = 1; 9325 int x; 9326 9327 /* save current state of GPCNTL and GPREG */ 9328 old_gpreg = INB (nc_gpreg); 9329 old_gpcntl = INB (nc_gpcntl); 9330 gpcntl = old_gpcntl & 0x1c; 9331 9332 /* set up GPREG & GPCNTL to set GPIO0 and GPIO1 in to known state */ 9333 OUTB (nc_gpreg, old_gpreg); 9334 OUTB (nc_gpcntl, gpcntl); 9335 9336 /* this is to set NVRAM into a known state with GPIO0/1 both low */ 9337 gpreg = old_gpreg; 9338 S24C16_set_bit(np, 0, &gpreg, CLR_CLK); 9339 S24C16_set_bit(np, 0, &gpreg, CLR_BIT); 9340 9341 /* now set NVRAM inactive with GPIO0/1 both high */ 9342 S24C16_stop(np, &gpreg); 9343 9344 /* activate NVRAM */ 9345 S24C16_start(np, &gpreg); 9346 9347 /* write device code and random address MSB */ 9348 S24C16_write_byte(np, &ack_data, 9349 0xa0 | ((offset >> 7) & 0x0e), &gpreg, &gpcntl); 9350 if (ack_data & 0x01) 9351 goto out; 9352 9353 /* write random address LSB */ 9354 S24C16_write_byte(np, &ack_data, 9355 offset & 0xff, &gpreg, &gpcntl); 9356 if (ack_data & 0x01) 9357 goto out; 9358 9359 /* regenerate START state to set up for reading */ 9360 S24C16_start(np, &gpreg); 9361 9362 /* rewrite device code and address MSB with read bit set (lsb = 0x01) */ 9363 S24C16_write_byte(np, &ack_data, 9364 0xa1 | ((offset >> 7) & 0x0e), &gpreg, &gpcntl); 9365 if (ack_data & 0x01) 9366 goto out; 9367 9368 /* now set up GPIO0 for inputting data */ 9369 gpcntl |= 0x01; 9370 OUTB (nc_gpcntl, gpcntl); 9371 9372 /* input all requested data - only part of total NVRAM */ 9373 for (x = 0; x < len; x++) 9374 S24C16_read_byte(np, &data[x], (x == (len-1)), &gpreg, &gpcntl); 9375 9376 /* finally put NVRAM back in inactive mode */ 9377 gpcntl &= 0xfe; 9378 OUTB (nc_gpcntl, gpcntl); 9379 S24C16_stop(np, &gpreg); 9380 retv = 0; 9381 out: 9382 /* return GPIO0/1 to original states after having accessed NVRAM */ 9383 OUTB (nc_gpcntl, old_gpcntl); 9384 OUTB (nc_gpreg, old_gpreg); 9385 9386 return retv; 9387 } 9388 9389 #undef SET_BIT /* 0 */ 9390 #undef CLR_BIT /* 1 */ 9391 #undef SET_CLK /* 2 */ 9392 #undef CLR_CLK /* 3 */ 9393 9394 /* 9395 * Try reading Symbios NVRAM. 9396 * Return 0 if OK. 9397 */ 9398 static int sym_read_Symbios_nvram (hcb_p np, Symbios_nvram *nvram) 9399 { 9400 static u_char Symbios_trailer[6] = {0xfe, 0xfe, 0, 0, 0, 0}; 9401 u_char *data = (u_char *) nvram; 9402 int len = sizeof(*nvram); 9403 u_short csum; 9404 int x; 9405 9406 /* probe the 24c16 and read the SYMBIOS 24c16 area */ 9407 if (sym_read_S24C16_nvram (np, SYMBIOS_NVRAM_ADDRESS, data, len)) 9408 return 1; 9409 9410 /* check valid NVRAM signature, verify byte count and checksum */ 9411 if (nvram->type != 0 || 9412 bcmp(nvram->trailer, Symbios_trailer, 6) || 9413 nvram->byte_count != len - 12) 9414 return 1; 9415 9416 /* verify checksum */ 9417 for (x = 6, csum = 0; x < len - 6; x++) 9418 csum += data[x]; 9419 if (csum != nvram->checksum) 9420 return 1; 9421 9422 return 0; 9423 } 9424 9425 /* 9426 * 93C46 EEPROM reading. 9427 * 9428 * GPOI0 - data in 9429 * GPIO1 - data out 9430 * GPIO2 - clock 9431 * GPIO4 - chip select 9432 * 9433 * Used by Tekram. 9434 */ 9435 9436 /* 9437 * Pulse clock bit in GPIO0 9438 */ 9439 static void T93C46_Clk(hcb_p np, u_char *gpreg) 9440 { 9441 OUTB (nc_gpreg, *gpreg | 0x04); 9442 UDELAY (2); 9443 OUTB (nc_gpreg, *gpreg); 9444 } 9445 9446 /* 9447 * Read bit from NVRAM 9448 */ 9449 static void T93C46_Read_Bit(hcb_p np, u_char *read_bit, u_char *gpreg) 9450 { 9451 UDELAY (2); 9452 T93C46_Clk(np, gpreg); 9453 *read_bit = INB (nc_gpreg); 9454 } 9455 9456 /* 9457 * Write bit to GPIO0 9458 */ 9459 static void T93C46_Write_Bit(hcb_p np, u_char write_bit, u_char *gpreg) 9460 { 9461 if (write_bit & 0x01) 9462 *gpreg |= 0x02; 9463 else 9464 *gpreg &= 0xfd; 9465 9466 *gpreg |= 0x10; 9467 9468 OUTB (nc_gpreg, *gpreg); 9469 UDELAY (2); 9470 9471 T93C46_Clk(np, gpreg); 9472 } 9473 9474 /* 9475 * Send STOP condition to NVRAM - puts NVRAM to sleep... ZZZzzz!! 9476 */ 9477 static void T93C46_Stop(hcb_p np, u_char *gpreg) 9478 { 9479 *gpreg &= 0xef; 9480 OUTB (nc_gpreg, *gpreg); 9481 UDELAY (2); 9482 9483 T93C46_Clk(np, gpreg); 9484 } 9485 9486 /* 9487 * Send read command and address to NVRAM 9488 */ 9489 static void T93C46_Send_Command(hcb_p np, u_short write_data, 9490 u_char *read_bit, u_char *gpreg) 9491 { 9492 int x; 9493 9494 /* send 9 bits, start bit (1), command (2), address (6) */ 9495 for (x = 0; x < 9; x++) 9496 T93C46_Write_Bit(np, (u_char) (write_data >> (8 - x)), gpreg); 9497 9498 *read_bit = INB (nc_gpreg); 9499 } 9500 9501 /* 9502 * READ 2 bytes from the NVRAM 9503 */ 9504 static void T93C46_Read_Word(hcb_p np, u_short *nvram_data, u_char *gpreg) 9505 { 9506 int x; 9507 u_char read_bit; 9508 9509 *nvram_data = 0; 9510 for (x = 0; x < 16; x++) { 9511 T93C46_Read_Bit(np, &read_bit, gpreg); 9512 9513 if (read_bit & 0x01) 9514 *nvram_data |= (0x01 << (15 - x)); 9515 else 9516 *nvram_data &= ~(0x01 << (15 - x)); 9517 } 9518 } 9519 9520 /* 9521 * Read Tekram NvRAM data. 9522 */ 9523 static int T93C46_Read_Data(hcb_p np, u_short *data,int len,u_char *gpreg) 9524 { 9525 u_char read_bit; 9526 int x; 9527 9528 for (x = 0; x < len; x++) { 9529 9530 /* output read command and address */ 9531 T93C46_Send_Command(np, 0x180 | x, &read_bit, gpreg); 9532 if (read_bit & 0x01) 9533 return 1; /* Bad */ 9534 T93C46_Read_Word(np, &data[x], gpreg); 9535 T93C46_Stop(np, gpreg); 9536 } 9537 9538 return 0; 9539 } 9540 9541 /* 9542 * Try reading 93C46 Tekram NVRAM. 9543 */ 9544 static int sym_read_T93C46_nvram (hcb_p np, Tekram_nvram *nvram) 9545 { 9546 u_char gpcntl, gpreg; 9547 u_char old_gpcntl, old_gpreg; 9548 int retv = 1; 9549 9550 /* save current state of GPCNTL and GPREG */ 9551 old_gpreg = INB (nc_gpreg); 9552 old_gpcntl = INB (nc_gpcntl); 9553 9554 /* set up GPREG & GPCNTL to set GPIO0/1/2/4 in to known state, 0 in, 9555 1/2/4 out */ 9556 gpreg = old_gpreg & 0xe9; 9557 OUTB (nc_gpreg, gpreg); 9558 gpcntl = (old_gpcntl & 0xe9) | 0x09; 9559 OUTB (nc_gpcntl, gpcntl); 9560 9561 /* input all of NVRAM, 64 words */ 9562 retv = T93C46_Read_Data(np, (u_short *) nvram, 9563 sizeof(*nvram) / sizeof(short), &gpreg); 9564 9565 /* return GPIO0/1/2/4 to original states after having accessed NVRAM */ 9566 OUTB (nc_gpcntl, old_gpcntl); 9567 OUTB (nc_gpreg, old_gpreg); 9568 9569 return retv; 9570 } 9571 9572 /* 9573 * Try reading Tekram NVRAM. 9574 * Return 0 if OK. 9575 */ 9576 static int sym_read_Tekram_nvram (hcb_p np, Tekram_nvram *nvram) 9577 { 9578 u_char *data = (u_char *) nvram; 9579 int len = sizeof(*nvram); 9580 u_short csum; 9581 int x; 9582 9583 switch (np->device_id) { 9584 case PCI_ID_SYM53C885: 9585 case PCI_ID_SYM53C895: 9586 case PCI_ID_SYM53C896: 9587 x = sym_read_S24C16_nvram(np, TEKRAM_24C16_NVRAM_ADDRESS, 9588 data, len); 9589 break; 9590 case PCI_ID_SYM53C875: 9591 x = sym_read_S24C16_nvram(np, TEKRAM_24C16_NVRAM_ADDRESS, 9592 data, len); 9593 if (!x) 9594 break; 9595 default: 9596 x = sym_read_T93C46_nvram(np, nvram); 9597 break; 9598 } 9599 if (x) 9600 return 1; 9601 9602 /* verify checksum */ 9603 for (x = 0, csum = 0; x < len - 1; x += 2) 9604 csum += data[x] + (data[x+1] << 8); 9605 if (csum != 0x1234) 9606 return 1; 9607 9608 return 0; 9609 } 9610 9611 #endif /* SYM_CONF_NVRAM_SUPPORT */ 9612