1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2012-2016 Ruslan Bukin <br@bsdpad.com> 5 * Copyright (c) 2023-2024 Florian Walpen <dev@submerge.ch> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * RME HDSP driver for FreeBSD. 32 * Supported cards: HDSP 9632, HDSP 9652. 33 */ 34 35 #include <sys/types.h> 36 #include <sys/sysctl.h> 37 38 #include <dev/sound/pcm/sound.h> 39 #include <dev/sound/pci/hdsp.h> 40 41 #include <dev/pci/pcireg.h> 42 #include <dev/pci/pcivar.h> 43 44 #include <mixer_if.h> 45 46 static bool hdsp_unified_pcm = false; 47 48 static SYSCTL_NODE(_hw, OID_AUTO, hdsp, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 49 "PCI HDSP"); 50 51 SYSCTL_BOOL(_hw_hdsp, OID_AUTO, unified_pcm, CTLFLAG_RWTUN, 52 &hdsp_unified_pcm, 0, "Combine physical ports in one unified pcm device"); 53 54 static struct hdsp_clock_source hdsp_clock_source_table_9632[] = { 55 { "internal", HDSP_CLOCK_INTERNAL }, 56 { "adat", HDSP_CLOCK_ADAT1 }, 57 { "spdif", HDSP_CLOCK_SPDIF }, 58 { "word", HDSP_CLOCK_WORD }, 59 { NULL, HDSP_CLOCK_INTERNAL } 60 }; 61 62 static struct hdsp_clock_source hdsp_clock_source_table_9652[] = { 63 { "internal", HDSP_CLOCK_INTERNAL }, 64 { "adat1", HDSP_CLOCK_ADAT1 }, 65 { "adat2", HDSP_CLOCK_ADAT2 }, 66 { "adat3", HDSP_CLOCK_ADAT3 }, 67 { "spdif", HDSP_CLOCK_SPDIF }, 68 { "word", HDSP_CLOCK_WORD }, 69 { "adat_sync", HDSP_CLOCK_ADAT_SYNC }, 70 { NULL, HDSP_CLOCK_INTERNAL } 71 }; 72 73 static struct hdsp_channel chan_map_9632[] = { 74 { HDSP_CHAN_9632_ADAT, "adat" }, 75 { HDSP_CHAN_9632_SPDIF, "s/pdif" }, 76 { HDSP_CHAN_9632_LINE, "line" }, 77 { HDSP_CHAN_9632_EXT, "ext" }, 78 { 0, NULL }, 79 }; 80 81 static struct hdsp_channel chan_map_9632_uni[] = { 82 { HDSP_CHAN_9632_ALL, "all" }, 83 { 0, NULL }, 84 }; 85 86 static struct hdsp_channel chan_map_9652[] = { 87 { HDSP_CHAN_9652_ADAT1, "adat1" }, 88 { HDSP_CHAN_9652_ADAT2, "adat2" }, 89 { HDSP_CHAN_9652_ADAT3, "adat3" }, 90 { HDSP_CHAN_9652_SPDIF, "s/pdif" }, 91 { 0, NULL }, 92 }; 93 94 static struct hdsp_channel chan_map_9652_uni[] = { 95 { HDSP_CHAN_9652_ALL, "all" }, 96 { 0, NULL }, 97 }; 98 99 static void 100 hdsp_intr(void *p) 101 { 102 struct sc_pcminfo *scp; 103 struct sc_info *sc; 104 device_t *devlist; 105 int devcount; 106 int status; 107 int err; 108 int i; 109 110 sc = (struct sc_info *)p; 111 112 snd_mtxlock(sc->lock); 113 114 status = hdsp_read_1(sc, HDSP_STATUS_REG); 115 if (status & HDSP_AUDIO_IRQ_PENDING) { 116 if ((err = device_get_children(sc->dev, &devlist, &devcount)) != 0) 117 return; 118 119 for (i = 0; i < devcount; i++) { 120 scp = device_get_ivars(devlist[i]); 121 if (scp->ih != NULL) 122 scp->ih(scp); 123 } 124 125 hdsp_write_1(sc, HDSP_INTERRUPT_ACK, 0); 126 free(devlist, M_TEMP); 127 } 128 129 snd_mtxunlock(sc->lock); 130 } 131 132 static void 133 hdsp_dmapsetmap(void *arg, bus_dma_segment_t *segs, int nseg, int error) 134 { 135 #if 0 136 device_printf(sc->dev, "hdsp_dmapsetmap()\n"); 137 #endif 138 } 139 140 static int 141 hdsp_alloc_resources(struct sc_info *sc) 142 { 143 144 /* Allocate resource. */ 145 sc->csid = PCIR_BAR(0); 146 sc->cs = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 147 &sc->csid, RF_ACTIVE); 148 149 if (!sc->cs) { 150 device_printf(sc->dev, "Unable to map SYS_RES_MEMORY.\n"); 151 return (ENXIO); 152 } 153 154 sc->cst = rman_get_bustag(sc->cs); 155 sc->csh = rman_get_bushandle(sc->cs); 156 157 /* Allocate interrupt resource. */ 158 sc->irqid = 0; 159 sc->irq = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &sc->irqid, 160 RF_ACTIVE | RF_SHAREABLE); 161 162 if (!sc->irq || 163 bus_setup_intr(sc->dev, sc->irq, INTR_MPSAFE | INTR_TYPE_AV, 164 NULL, hdsp_intr, sc, &sc->ih)) { 165 device_printf(sc->dev, "Unable to alloc interrupt resource.\n"); 166 return (ENXIO); 167 } 168 169 /* Allocate DMA resources. */ 170 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(sc->dev), 171 /*alignment*/4, 172 /*boundary*/0, 173 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 174 /*highaddr*/BUS_SPACE_MAXADDR, 175 /*filter*/NULL, 176 /*filterarg*/NULL, 177 /*maxsize*/2 * HDSP_DMASEGSIZE, 178 /*nsegments*/2, 179 /*maxsegsz*/HDSP_DMASEGSIZE, 180 /*flags*/0, 181 /*lockfunc*/NULL, 182 /*lockarg*/NULL, 183 /*dmatag*/&sc->dmat) != 0) { 184 device_printf(sc->dev, "Unable to create dma tag.\n"); 185 return (ENXIO); 186 } 187 188 sc->bufsize = HDSP_DMASEGSIZE; 189 190 /* pbuf (play buffer). */ 191 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->pbuf, BUS_DMA_WAITOK, 192 &sc->pmap)) { 193 device_printf(sc->dev, "Can't alloc pbuf.\n"); 194 return (ENXIO); 195 } 196 197 if (bus_dmamap_load(sc->dmat, sc->pmap, sc->pbuf, sc->bufsize, 198 hdsp_dmapsetmap, sc, BUS_DMA_NOWAIT)) { 199 device_printf(sc->dev, "Can't load pbuf.\n"); 200 return (ENXIO); 201 } 202 203 /* rbuf (rec buffer). */ 204 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->rbuf, BUS_DMA_WAITOK, 205 &sc->rmap)) { 206 device_printf(sc->dev, "Can't alloc rbuf.\n"); 207 return (ENXIO); 208 } 209 210 if (bus_dmamap_load(sc->dmat, sc->rmap, sc->rbuf, sc->bufsize, 211 hdsp_dmapsetmap, sc, BUS_DMA_NOWAIT)) { 212 device_printf(sc->dev, "Can't load rbuf.\n"); 213 return (ENXIO); 214 } 215 216 bzero(sc->pbuf, sc->bufsize); 217 bzero(sc->rbuf, sc->bufsize); 218 219 return (0); 220 } 221 222 static void 223 hdsp_map_dmabuf(struct sc_info *sc) 224 { 225 uint32_t paddr, raddr; 226 227 paddr = vtophys(sc->pbuf); 228 raddr = vtophys(sc->rbuf); 229 230 hdsp_write_4(sc, HDSP_PAGE_ADDR_BUF_OUT, paddr); 231 hdsp_write_4(sc, HDSP_PAGE_ADDR_BUF_IN, raddr); 232 } 233 234 static int 235 hdsp_sysctl_sample_rate(SYSCTL_HANDLER_ARGS) 236 { 237 struct sc_info *sc = oidp->oid_arg1; 238 int error; 239 unsigned int speed, multiplier; 240 241 speed = sc->force_speed; 242 243 /* Process sysctl (unsigned) integer request. */ 244 error = sysctl_handle_int(oidp, &speed, 0, req); 245 if (error != 0 || req->newptr == NULL) 246 return (error); 247 248 /* Speed from 32000 to 192000, 0 falls back to pcm speed setting. */ 249 sc->force_speed = 0; 250 if (speed > 0) { 251 multiplier = 1; 252 if ((speed > (96000 + 128000) / 2) && sc->type == HDSP_9632) 253 multiplier = 4; 254 else if (speed > (48000 + 64000) / 2) 255 multiplier = 2; 256 257 if (speed < ((32000 + 44100) / 2) * multiplier) 258 sc->force_speed = 32000 * multiplier; 259 else if (speed < ((44100 + 48000) / 2) * multiplier) 260 sc->force_speed = 44100 * multiplier; 261 else 262 sc->force_speed = 48000 * multiplier; 263 } 264 265 return (0); 266 } 267 268 269 static int 270 hdsp_sysctl_period(SYSCTL_HANDLER_ARGS) 271 { 272 struct sc_info *sc = oidp->oid_arg1; 273 int error; 274 unsigned int period; 275 276 period = sc->force_period; 277 278 /* Process sysctl (unsigned) integer request. */ 279 error = sysctl_handle_int(oidp, &period, 0, req); 280 if (error != 0 || req->newptr == NULL) 281 return (error); 282 283 /* Period is from 2^5 to 2^14, 0 falls back to pcm latency settings. */ 284 sc->force_period = 0; 285 if (period > 0) { 286 sc->force_period = 32; 287 while (sc->force_period < period && sc->force_period < 4096) 288 sc->force_period <<= 1; 289 } 290 291 return (0); 292 } 293 294 static uint32_t 295 hdsp_control_clock_preference(enum hdsp_clock_type type) 296 { 297 switch (type) { 298 case HDSP_CLOCK_INTERNAL: 299 return (HDSP_CONTROL_MASTER); 300 case HDSP_CLOCK_ADAT1: 301 return (HDSP_CONTROL_CLOCK(0)); 302 case HDSP_CLOCK_ADAT2: 303 return (HDSP_CONTROL_CLOCK(1)); 304 case HDSP_CLOCK_ADAT3: 305 return (HDSP_CONTROL_CLOCK(2)); 306 case HDSP_CLOCK_SPDIF: 307 return (HDSP_CONTROL_CLOCK(3)); 308 case HDSP_CLOCK_WORD: 309 return (HDSP_CONTROL_CLOCK(4)); 310 case HDSP_CLOCK_ADAT_SYNC: 311 return (HDSP_CONTROL_CLOCK(5)); 312 default: 313 return (HDSP_CONTROL_MASTER); 314 } 315 } 316 317 static int 318 hdsp_sysctl_clock_preference(SYSCTL_HANDLER_ARGS) 319 { 320 struct sc_info *sc; 321 struct hdsp_clock_source *clock_table, *clock; 322 char buf[16] = "invalid"; 323 int error; 324 uint32_t control; 325 326 sc = oidp->oid_arg1; 327 328 /* Select sync ports table for device type. */ 329 if (sc->type == HDSP_9632) 330 clock_table = hdsp_clock_source_table_9632; 331 else if (sc->type == HDSP_9652) 332 clock_table = hdsp_clock_source_table_9652; 333 else 334 return (ENXIO); 335 336 /* Extract preferred clock source from control register. */ 337 control = sc->ctrl_register & HDSP_CONTROL_CLOCK_MASK; 338 for (clock = clock_table; clock->name != NULL; ++clock) { 339 if (hdsp_control_clock_preference(clock->type) == control) 340 break; 341 } 342 if (clock->name != NULL) 343 strlcpy(buf, clock->name, sizeof(buf)); 344 345 /* Process sysctl string request. */ 346 error = sysctl_handle_string(oidp, buf, sizeof(buf), req); 347 if (error != 0 || req->newptr == NULL) 348 return (error); 349 350 /* Find clock source matching the sysctl string. */ 351 for (clock = clock_table; clock->name != NULL; ++clock) { 352 if (strncasecmp(buf, clock->name, sizeof(buf)) == 0) 353 break; 354 } 355 356 /* Set preferred clock source in control register. */ 357 if (clock->name != NULL) { 358 control = hdsp_control_clock_preference(clock->type); 359 control &= HDSP_CONTROL_CLOCK_MASK; 360 snd_mtxlock(sc->lock); 361 sc->ctrl_register &= ~HDSP_CONTROL_CLOCK_MASK; 362 sc->ctrl_register |= control; 363 hdsp_write_4(sc, HDSP_CONTROL_REG, sc->ctrl_register); 364 snd_mtxunlock(sc->lock); 365 } 366 return (0); 367 } 368 369 static uint32_t 370 hdsp_status2_clock_source(enum hdsp_clock_type type) 371 { 372 switch (type) { 373 case HDSP_CLOCK_INTERNAL: 374 return (0); 375 case HDSP_CLOCK_ADAT1: 376 return (HDSP_STATUS2_CLOCK(0)); 377 case HDSP_CLOCK_ADAT2: 378 return (HDSP_STATUS2_CLOCK(1)); 379 case HDSP_CLOCK_ADAT3: 380 return (HDSP_STATUS2_CLOCK(2)); 381 case HDSP_CLOCK_SPDIF: 382 return (HDSP_STATUS2_CLOCK(3)); 383 case HDSP_CLOCK_WORD: 384 return (HDSP_STATUS2_CLOCK(4)); 385 case HDSP_CLOCK_ADAT_SYNC: 386 return (HDSP_STATUS2_CLOCK(5)); 387 default: 388 return (0); 389 } 390 } 391 392 static int 393 hdsp_sysctl_clock_source(SYSCTL_HANDLER_ARGS) 394 { 395 struct sc_info *sc; 396 struct hdsp_clock_source *clock_table, *clock; 397 char buf[16] = "invalid"; 398 uint32_t status2; 399 400 sc = oidp->oid_arg1; 401 402 /* Select sync ports table for device type. */ 403 if (sc->type == HDSP_9632) 404 clock_table = hdsp_clock_source_table_9632; 405 else if (sc->type == HDSP_9652) 406 clock_table = hdsp_clock_source_table_9652; 407 else 408 return (ENXIO); 409 410 /* Read current (autosync) clock source from status2 register. */ 411 snd_mtxlock(sc->lock); 412 status2 = hdsp_read_4(sc, HDSP_STATUS2_REG); 413 status2 &= HDSP_STATUS2_CLOCK_MASK; 414 snd_mtxunlock(sc->lock); 415 416 /* Translate status2 register value to clock source. */ 417 for (clock = clock_table; clock->name != NULL; ++clock) { 418 /* In clock master mode, override with internal clock source. */ 419 if (sc->ctrl_register & HDSP_CONTROL_MASTER) { 420 if (clock->type == HDSP_CLOCK_INTERNAL) 421 break; 422 } else if (hdsp_status2_clock_source(clock->type) == status2) 423 break; 424 } 425 426 /* Process sysctl string request. */ 427 if (clock->name != NULL) 428 strlcpy(buf, clock->name, sizeof(buf)); 429 return (sysctl_handle_string(oidp, buf, sizeof(buf), req)); 430 } 431 432 static int 433 hdsp_sysctl_clock_list(SYSCTL_HANDLER_ARGS) 434 { 435 struct sc_info *sc; 436 struct hdsp_clock_source *clock_table, *clock; 437 char buf[256]; 438 int n; 439 440 sc = oidp->oid_arg1; 441 n = 0; 442 443 /* Select clock source table for device type. */ 444 if (sc->type == HDSP_9632) 445 clock_table = hdsp_clock_source_table_9632; 446 else if (sc->type == HDSP_9652) 447 clock_table = hdsp_clock_source_table_9652; 448 else 449 return (ENXIO); 450 451 /* List available clock sources. */ 452 buf[0] = 0; 453 for (clock = clock_table; clock->name != NULL; ++clock) { 454 if (n > 0) 455 n += strlcpy(buf + n, ",", sizeof(buf) - n); 456 n += strlcpy(buf + n, clock->name, sizeof(buf) - n); 457 } 458 return (sysctl_handle_string(oidp, buf, sizeof(buf), req)); 459 } 460 461 static bool 462 hdsp_clock_source_locked(enum hdsp_clock_type type, uint32_t status, 463 uint32_t status2) 464 { 465 switch (type) { 466 case HDSP_CLOCK_INTERNAL: 467 return (true); 468 case HDSP_CLOCK_ADAT1: 469 return ((status >> 3) & 0x01); 470 case HDSP_CLOCK_ADAT2: 471 return ((status >> 2) & 0x01); 472 case HDSP_CLOCK_ADAT3: 473 return ((status >> 1) & 0x01); 474 case HDSP_CLOCK_SPDIF: 475 return (!((status >> 25) & 0x01)); 476 case HDSP_CLOCK_WORD: 477 return ((status2 >> 3) & 0x01); 478 case HDSP_CLOCK_ADAT_SYNC: 479 return ((status >> 5) & 0x01); 480 default: 481 return (false); 482 } 483 } 484 485 static bool 486 hdsp_clock_source_synced(enum hdsp_clock_type type, uint32_t status, 487 uint32_t status2) 488 { 489 switch (type) { 490 case HDSP_CLOCK_INTERNAL: 491 return (true); 492 case HDSP_CLOCK_ADAT1: 493 return ((status >> 18) & 0x01); 494 case HDSP_CLOCK_ADAT2: 495 return ((status >> 17) & 0x01); 496 case HDSP_CLOCK_ADAT3: 497 return ((status >> 16) & 0x01); 498 case HDSP_CLOCK_SPDIF: 499 return (((status >> 4) & 0x01) && !((status >> 25) & 0x01)); 500 case HDSP_CLOCK_WORD: 501 return ((status2 >> 4) & 0x01); 502 case HDSP_CLOCK_ADAT_SYNC: 503 return ((status >> 27) & 0x01); 504 default: 505 return (false); 506 } 507 } 508 509 static int 510 hdsp_sysctl_sync_status(SYSCTL_HANDLER_ARGS) 511 { 512 struct sc_info *sc; 513 struct hdsp_clock_source *clock_table, *clock; 514 char buf[256]; 515 char *state; 516 int n; 517 uint32_t status, status2; 518 519 sc = oidp->oid_arg1; 520 n = 0; 521 522 /* Select sync ports table for device type. */ 523 if (sc->type == HDSP_9632) 524 clock_table = hdsp_clock_source_table_9632; 525 else if (sc->type == HDSP_9652) 526 clock_table = hdsp_clock_source_table_9652; 527 else 528 return (ENXIO); 529 530 /* Read current lock and sync bits from status registers. */ 531 snd_mtxlock(sc->lock); 532 status = hdsp_read_4(sc, HDSP_STATUS_REG); 533 status2 = hdsp_read_4(sc, HDSP_STATUS2_REG); 534 snd_mtxunlock(sc->lock); 535 536 /* List clock sources with lock and sync state. */ 537 for (clock = clock_table; clock->name != NULL; ++clock) { 538 if (clock->type == HDSP_CLOCK_INTERNAL) 539 continue; 540 if (n > 0) 541 n += strlcpy(buf + n, ",", sizeof(buf) - n); 542 state = "none"; 543 if (hdsp_clock_source_locked(clock->type, status, status2)) { 544 if (hdsp_clock_source_synced(clock->type, status, 545 status2)) 546 state = "sync"; 547 else 548 state = "lock"; 549 } 550 n += snprintf(buf + n, sizeof(buf) - n, "%s(%s)", 551 clock->name, state); 552 } 553 return (sysctl_handle_string(oidp, buf, sizeof(buf), req)); 554 } 555 556 static int 557 hdsp_probe(device_t dev) 558 { 559 uint32_t rev; 560 561 if (pci_get_vendor(dev) == PCI_VENDOR_XILINX && 562 pci_get_device(dev) == PCI_DEVICE_XILINX_HDSP) { 563 rev = pci_get_revid(dev); 564 switch (rev) { 565 case PCI_REVISION_9632: 566 device_set_desc(dev, "RME HDSP 9632"); 567 return (0); 568 case PCI_REVISION_9652: 569 device_set_desc(dev, "RME HDSP 9652"); 570 return (0); 571 } 572 } 573 574 return (ENXIO); 575 } 576 577 static int 578 hdsp_init(struct sc_info *sc) 579 { 580 unsigned mixer_controls; 581 582 /* Set latency. */ 583 sc->period = 256; 584 /* 585 * The pcm channel latency settings propagate unreliable blocksizes, 586 * different for recording and playback, and skewed due to rounding 587 * and total buffer size limits. 588 * Force period to a consistent default until these issues are fixed. 589 */ 590 sc->force_period = 256; 591 sc->ctrl_register = hdsp_encode_latency(2); 592 593 /* Set rate. */ 594 sc->speed = HDSP_SPEED_DEFAULT; 595 sc->force_speed = 0; 596 sc->ctrl_register &= ~HDSP_FREQ_MASK; 597 sc->ctrl_register |= HDSP_FREQ_MASK_DEFAULT; 598 599 /* Set internal clock source (master). */ 600 sc->ctrl_register &= ~HDSP_CONTROL_CLOCK_MASK; 601 sc->ctrl_register |= HDSP_CONTROL_MASTER; 602 603 /* SPDIF from coax in, line out. */ 604 sc->ctrl_register &= ~HDSP_CONTROL_SPDIF_COAX; 605 sc->ctrl_register |= HDSP_CONTROL_SPDIF_COAX; 606 sc->ctrl_register &= ~HDSP_CONTROL_LINE_OUT; 607 sc->ctrl_register |= HDSP_CONTROL_LINE_OUT; 608 609 hdsp_write_4(sc, HDSP_CONTROL_REG, sc->ctrl_register); 610 611 if (sc->type == HDSP_9652) 612 hdsp_write_4(sc, HDSP_CONTROL2_REG, HDSP_CONTROL2_9652_MIXER); 613 else 614 hdsp_write_4(sc, HDSP_CONTROL2_REG, 0); 615 616 switch (sc->type) { 617 case HDSP_9632: 618 /* Mixer matrix is 2 source rows (input, playback) per output. */ 619 mixer_controls = 2 * HDSP_MIX_SLOTS_9632 * HDSP_MIX_SLOTS_9632; 620 break; 621 case HDSP_9652: 622 /* Mixer matrix is 2 source rows (input, playback) per output. */ 623 mixer_controls = 2 * HDSP_MIX_SLOTS_9652 * HDSP_MIX_SLOTS_9652; 624 break; 625 default: 626 return (ENXIO); 627 } 628 629 /* Initialize mixer matrix by silencing all controls. */ 630 for (unsigned offset = 0; offset < mixer_controls * 2; offset += 4) { 631 /* Only accepts 4 byte values, pairs of 16 bit volume controls. */ 632 hdsp_write_4(sc, HDSP_MIXER_BASE + offset, 633 (HDSP_MIN_GAIN << 16) | HDSP_MIN_GAIN); 634 } 635 636 /* Reset pointer, rewrite frequency (same register) for 9632. */ 637 hdsp_write_4(sc, HDSP_RESET_POINTER, 0); 638 if (sc->type == HDSP_9632) { 639 /* Set DDS value. */ 640 hdsp_write_4(sc, HDSP_FREQ_REG, hdsp_freq_reg_value(sc->speed)); 641 } 642 643 return (0); 644 } 645 646 static int 647 hdsp_attach(device_t dev) 648 { 649 struct hdsp_channel *chan_map; 650 struct sc_pcminfo *scp; 651 struct sc_info *sc; 652 uint32_t rev; 653 int i, err; 654 655 #if 0 656 device_printf(dev, "hdsp_attach()\n"); 657 #endif 658 659 sc = device_get_softc(dev); 660 sc->lock = snd_mtxcreate(device_get_nameunit(dev), 661 "snd_hdsp softc"); 662 sc->dev = dev; 663 664 pci_enable_busmaster(dev); 665 rev = pci_get_revid(dev); 666 switch (rev) { 667 case PCI_REVISION_9632: 668 sc->type = HDSP_9632; 669 chan_map = hdsp_unified_pcm ? chan_map_9632_uni : chan_map_9632; 670 break; 671 case PCI_REVISION_9652: 672 sc->type = HDSP_9652; 673 chan_map = hdsp_unified_pcm ? chan_map_9652_uni : chan_map_9652; 674 break; 675 default: 676 return (ENXIO); 677 } 678 679 /* Allocate resources. */ 680 err = hdsp_alloc_resources(sc); 681 if (err) { 682 device_printf(dev, "Unable to allocate system resources.\n"); 683 return (ENXIO); 684 } 685 686 if (hdsp_init(sc) != 0) 687 return (ENXIO); 688 689 for (i = 0; i < HDSP_MAX_CHANS && chan_map[i].descr != NULL; i++) { 690 scp = malloc(sizeof(struct sc_pcminfo), M_DEVBUF, M_NOWAIT | M_ZERO); 691 scp->hc = &chan_map[i]; 692 scp->sc = sc; 693 scp->dev = device_add_child(dev, "pcm", -1); 694 device_set_ivars(scp->dev, scp); 695 } 696 697 hdsp_map_dmabuf(sc); 698 699 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 700 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 701 "sync_status", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 702 sc, 0, hdsp_sysctl_sync_status, "A", 703 "List clock source signal lock and sync status"); 704 705 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 706 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 707 "clock_source", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 708 sc, 0, hdsp_sysctl_clock_source, "A", 709 "Currently effective clock source"); 710 711 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 712 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 713 "clock_preference", CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, 714 sc, 0, hdsp_sysctl_clock_preference, "A", 715 "Set 'internal' (master) or preferred autosync clock source"); 716 717 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 718 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 719 "clock_list", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 720 sc, 0, hdsp_sysctl_clock_list, "A", 721 "List of supported clock sources"); 722 723 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 724 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 725 "period", CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE, 726 sc, 0, hdsp_sysctl_period, "A", 727 "Force period of samples per interrupt (32, 64, ... 4096)"); 728 729 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 730 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 731 "sample_rate", CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE, 732 sc, 0, hdsp_sysctl_sample_rate, "A", 733 "Force sample rate (32000, 44100, 48000, ... 192000)"); 734 735 return (bus_generic_attach(dev)); 736 } 737 738 static void 739 hdsp_dmafree(struct sc_info *sc) 740 { 741 742 bus_dmamap_unload(sc->dmat, sc->rmap); 743 bus_dmamap_unload(sc->dmat, sc->pmap); 744 bus_dmamem_free(sc->dmat, sc->rbuf, sc->rmap); 745 bus_dmamem_free(sc->dmat, sc->pbuf, sc->pmap); 746 sc->rbuf = sc->pbuf = NULL; 747 } 748 749 static int 750 hdsp_detach(device_t dev) 751 { 752 struct sc_info *sc; 753 int err; 754 755 sc = device_get_softc(dev); 756 if (sc == NULL) { 757 device_printf(dev,"Can't detach: softc is null.\n"); 758 return (0); 759 } 760 761 err = device_delete_children(dev); 762 if (err) 763 return (err); 764 765 hdsp_dmafree(sc); 766 767 if (sc->ih) 768 bus_teardown_intr(dev, sc->irq, sc->ih); 769 if (sc->dmat) 770 bus_dma_tag_destroy(sc->dmat); 771 if (sc->irq) 772 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 773 if (sc->cs) 774 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), sc->cs); 775 if (sc->lock) 776 snd_mtxfree(sc->lock); 777 778 return (0); 779 } 780 781 static device_method_t hdsp_methods[] = { 782 DEVMETHOD(device_probe, hdsp_probe), 783 DEVMETHOD(device_attach, hdsp_attach), 784 DEVMETHOD(device_detach, hdsp_detach), 785 { 0, 0 } 786 }; 787 788 static driver_t hdsp_driver = { 789 "hdsp", 790 hdsp_methods, 791 PCM_SOFTC_SIZE, 792 }; 793 794 DRIVER_MODULE(snd_hdsp, pci, hdsp_driver, 0, 0); 795