1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2008 Benno Rice. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 /* 29 * Driver for SMSC LAN91C111, may work for older variants. 30 */ 31 32 #ifdef HAVE_KERNEL_OPTION_HEADERS 33 #include "opt_device_polling.h" 34 #endif 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/errno.h> 39 #include <sys/kernel.h> 40 #include <sys/sockio.h> 41 #include <sys/malloc.h> 42 #include <sys/mbuf.h> 43 #include <sys/queue.h> 44 #include <sys/socket.h> 45 #include <sys/syslog.h> 46 #include <sys/taskqueue.h> 47 48 #include <sys/module.h> 49 #include <sys/bus.h> 50 51 #include <machine/bus.h> 52 #include <machine/resource.h> 53 #include <sys/rman.h> 54 55 #include <net/ethernet.h> 56 #include <net/if.h> 57 #include <net/if_var.h> 58 #include <net/if_arp.h> 59 #include <net/if_dl.h> 60 #include <net/if_types.h> 61 #include <net/if_mib.h> 62 #include <net/if_media.h> 63 64 #ifdef INET 65 #include <netinet/in.h> 66 #include <netinet/in_systm.h> 67 #include <netinet/in_var.h> 68 #include <netinet/ip.h> 69 #endif 70 71 #include <net/bpf.h> 72 #include <net/bpfdesc.h> 73 74 #include <dev/smc/if_smcreg.h> 75 #include <dev/smc/if_smcvar.h> 76 77 #include <dev/mii/mii.h> 78 #include <dev/mii/mii_bitbang.h> 79 #include <dev/mii/miivar.h> 80 81 #include "miibus_if.h" 82 83 #define SMC_LOCK(sc) mtx_lock(&(sc)->smc_mtx) 84 #define SMC_UNLOCK(sc) mtx_unlock(&(sc)->smc_mtx) 85 #define SMC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->smc_mtx, MA_OWNED) 86 87 #define SMC_INTR_PRIORITY 0 88 #define SMC_RX_PRIORITY 5 89 #define SMC_TX_PRIORITY 10 90 91 static const char *smc_chip_ids[16] = { 92 NULL, NULL, NULL, 93 /* 3 */ "SMSC LAN91C90 or LAN91C92", 94 /* 4 */ "SMSC LAN91C94", 95 /* 5 */ "SMSC LAN91C95", 96 /* 6 */ "SMSC LAN91C96", 97 /* 7 */ "SMSC LAN91C100", 98 /* 8 */ "SMSC LAN91C100FD", 99 /* 9 */ "SMSC LAN91C110FD or LAN91C111FD", 100 NULL, NULL, NULL, 101 NULL, NULL, NULL 102 }; 103 104 static void smc_init(void *); 105 static void smc_start(if_t); 106 static void smc_stop(struct smc_softc *); 107 static int smc_ioctl(if_t, u_long, caddr_t); 108 109 static void smc_init_locked(struct smc_softc *); 110 static void smc_start_locked(if_t); 111 static void smc_reset(struct smc_softc *); 112 static int smc_mii_ifmedia_upd(if_t); 113 static void smc_mii_ifmedia_sts(if_t, struct ifmediareq *); 114 static void smc_mii_tick(void *); 115 static void smc_mii_mediachg(struct smc_softc *); 116 static int smc_mii_mediaioctl(struct smc_softc *, struct ifreq *, u_long); 117 118 static void smc_task_intr(void *, int); 119 static void smc_task_rx(void *, int); 120 static void smc_task_tx(void *, int); 121 122 static driver_filter_t smc_intr; 123 static callout_func_t smc_watchdog; 124 #ifdef DEVICE_POLLING 125 static poll_handler_t smc_poll; 126 #endif 127 128 /* 129 * MII bit-bang glue 130 */ 131 static uint32_t smc_mii_bitbang_read(device_t); 132 static void smc_mii_bitbang_write(device_t, uint32_t); 133 134 static const struct mii_bitbang_ops smc_mii_bitbang_ops = { 135 smc_mii_bitbang_read, 136 smc_mii_bitbang_write, 137 { 138 MGMT_MDO, /* MII_BIT_MDO */ 139 MGMT_MDI, /* MII_BIT_MDI */ 140 MGMT_MCLK, /* MII_BIT_MDC */ 141 MGMT_MDOE, /* MII_BIT_DIR_HOST_PHY */ 142 0, /* MII_BIT_DIR_PHY_HOST */ 143 } 144 }; 145 146 static __inline void 147 smc_select_bank(struct smc_softc *sc, uint16_t bank) 148 { 149 150 bus_barrier(sc->smc_reg, BSR, 2, 151 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 152 bus_write_2(sc->smc_reg, BSR, bank & BSR_BANK_MASK); 153 bus_barrier(sc->smc_reg, BSR, 2, 154 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 155 } 156 157 /* Never call this when not in bank 2. */ 158 static __inline void 159 smc_mmu_wait(struct smc_softc *sc) 160 { 161 162 KASSERT((bus_read_2(sc->smc_reg, BSR) & 163 BSR_BANK_MASK) == 2, ("%s: smc_mmu_wait called when not in bank 2", 164 device_get_nameunit(sc->smc_dev))); 165 while (bus_read_2(sc->smc_reg, MMUCR) & MMUCR_BUSY) 166 ; 167 } 168 169 static __inline uint8_t 170 smc_read_1(struct smc_softc *sc, bus_size_t offset) 171 { 172 173 return (bus_read_1(sc->smc_reg, offset)); 174 } 175 176 static __inline void 177 smc_write_1(struct smc_softc *sc, bus_size_t offset, uint8_t val) 178 { 179 180 bus_write_1(sc->smc_reg, offset, val); 181 } 182 183 static __inline uint16_t 184 smc_read_2(struct smc_softc *sc, bus_size_t offset) 185 { 186 187 return (bus_read_2(sc->smc_reg, offset)); 188 } 189 190 static __inline void 191 smc_write_2(struct smc_softc *sc, bus_size_t offset, uint16_t val) 192 { 193 194 bus_write_2(sc->smc_reg, offset, val); 195 } 196 197 static __inline void 198 smc_read_multi_2(struct smc_softc *sc, bus_size_t offset, uint16_t *datap, 199 bus_size_t count) 200 { 201 202 bus_read_multi_2(sc->smc_reg, offset, datap, count); 203 } 204 205 static __inline void 206 smc_write_multi_2(struct smc_softc *sc, bus_size_t offset, uint16_t *datap, 207 bus_size_t count) 208 { 209 210 bus_write_multi_2(sc->smc_reg, offset, datap, count); 211 } 212 213 static __inline void 214 smc_barrier(struct smc_softc *sc, bus_size_t offset, bus_size_t length, 215 int flags) 216 { 217 218 bus_barrier(sc->smc_reg, offset, length, flags); 219 } 220 221 int 222 smc_probe(device_t dev) 223 { 224 int rid, type, error; 225 uint16_t val; 226 struct smc_softc *sc; 227 struct resource *reg; 228 229 sc = device_get_softc(dev); 230 rid = 0; 231 type = SYS_RES_IOPORT; 232 error = 0; 233 234 if (sc->smc_usemem) 235 type = SYS_RES_MEMORY; 236 237 reg = bus_alloc_resource_anywhere(dev, type, &rid, 16, RF_ACTIVE); 238 if (reg == NULL) { 239 if (bootverbose) 240 device_printf(dev, 241 "could not allocate I/O resource for probe\n"); 242 return (ENXIO); 243 } 244 245 /* Check for the identification value in the BSR. */ 246 val = bus_read_2(reg, BSR); 247 if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) { 248 if (bootverbose) 249 device_printf(dev, "identification value not in BSR\n"); 250 error = ENXIO; 251 goto done; 252 } 253 254 /* 255 * Try switching banks and make sure we still get the identification 256 * value. 257 */ 258 bus_write_2(reg, BSR, 0); 259 val = bus_read_2(reg, BSR); 260 if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) { 261 if (bootverbose) 262 device_printf(dev, 263 "identification value not in BSR after write\n"); 264 error = ENXIO; 265 goto done; 266 } 267 268 #if 0 269 /* Check the BAR. */ 270 bus_write_2(reg, BSR, 1); 271 val = bus_read_2(reg, BAR); 272 val = BAR_ADDRESS(val); 273 if (rman_get_start(reg) != val) { 274 if (bootverbose) 275 device_printf(dev, "BAR address %x does not match " 276 "I/O resource address %lx\n", val, 277 rman_get_start(reg)); 278 error = ENXIO; 279 goto done; 280 } 281 #endif 282 283 /* Compare REV against known chip revisions. */ 284 bus_write_2(reg, BSR, 3); 285 val = bus_read_2(reg, REV); 286 val = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT; 287 if (smc_chip_ids[val] == NULL) { 288 if (bootverbose) 289 device_printf(dev, "Unknown chip revision: %d\n", val); 290 error = ENXIO; 291 goto done; 292 } 293 294 device_set_desc(dev, smc_chip_ids[val]); 295 296 done: 297 bus_release_resource(dev, type, rid, reg); 298 return (error); 299 } 300 301 int 302 smc_attach(device_t dev) 303 { 304 int type, error; 305 uint16_t val; 306 u_char eaddr[ETHER_ADDR_LEN]; 307 struct smc_softc *sc; 308 if_t ifp; 309 310 sc = device_get_softc(dev); 311 error = 0; 312 313 sc->smc_dev = dev; 314 315 ifp = sc->smc_ifp = if_alloc(IFT_ETHER); 316 317 mtx_init(&sc->smc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 318 319 /* Set up watchdog callout. */ 320 callout_init_mtx(&sc->smc_watchdog, &sc->smc_mtx, 0); 321 322 type = SYS_RES_IOPORT; 323 if (sc->smc_usemem) 324 type = SYS_RES_MEMORY; 325 326 sc->smc_reg_rid = 0; 327 sc->smc_reg = bus_alloc_resource_anywhere(dev, type, &sc->smc_reg_rid, 328 16, RF_ACTIVE); 329 if (sc->smc_reg == NULL) { 330 error = ENXIO; 331 goto done; 332 } 333 334 sc->smc_irq = bus_alloc_resource_anywhere(dev, SYS_RES_IRQ, 335 &sc->smc_irq_rid, 1, RF_ACTIVE | RF_SHAREABLE); 336 if (sc->smc_irq == NULL) { 337 error = ENXIO; 338 goto done; 339 } 340 341 SMC_LOCK(sc); 342 smc_reset(sc); 343 SMC_UNLOCK(sc); 344 345 smc_select_bank(sc, 3); 346 val = smc_read_2(sc, REV); 347 sc->smc_chip = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT; 348 sc->smc_rev = (val * REV_REV_MASK) >> REV_REV_SHIFT; 349 if (bootverbose) 350 device_printf(dev, "revision %x\n", sc->smc_rev); 351 352 callout_init_mtx(&sc->smc_mii_tick_ch, &sc->smc_mtx, 353 CALLOUT_RETURNUNLOCKED); 354 if (sc->smc_chip >= REV_CHIP_91110FD) { 355 (void)mii_attach(dev, &sc->smc_miibus, ifp, 356 smc_mii_ifmedia_upd, smc_mii_ifmedia_sts, BMSR_DEFCAPMASK, 357 MII_PHY_ANY, MII_OFFSET_ANY, 0); 358 if (sc->smc_miibus != NULL) { 359 sc->smc_mii_tick = smc_mii_tick; 360 sc->smc_mii_mediachg = smc_mii_mediachg; 361 sc->smc_mii_mediaioctl = smc_mii_mediaioctl; 362 } 363 } 364 365 smc_select_bank(sc, 1); 366 eaddr[0] = smc_read_1(sc, IAR0); 367 eaddr[1] = smc_read_1(sc, IAR1); 368 eaddr[2] = smc_read_1(sc, IAR2); 369 eaddr[3] = smc_read_1(sc, IAR3); 370 eaddr[4] = smc_read_1(sc, IAR4); 371 eaddr[5] = smc_read_1(sc, IAR5); 372 373 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 374 if_setsoftc(ifp, sc); 375 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 376 if_setinitfn(ifp, smc_init); 377 if_setioctlfn(ifp, smc_ioctl); 378 if_setstartfn(ifp, smc_start); 379 if_setsendqlen(ifp, ifqmaxlen); 380 if_setsendqready(ifp); 381 382 if_setcapabilities(ifp, if_getcapenable(ifp) ); 383 384 #ifdef DEVICE_POLLING 385 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0); 386 #endif 387 388 ether_ifattach(ifp, eaddr); 389 390 /* Set up taskqueue */ 391 TASK_INIT(&sc->smc_intr, SMC_INTR_PRIORITY, smc_task_intr, ifp); 392 NET_TASK_INIT(&sc->smc_rx, SMC_RX_PRIORITY, smc_task_rx, ifp); 393 TASK_INIT(&sc->smc_tx, SMC_TX_PRIORITY, smc_task_tx, ifp); 394 sc->smc_tq = taskqueue_create_fast("smc_taskq", M_NOWAIT, 395 taskqueue_thread_enqueue, &sc->smc_tq); 396 taskqueue_start_threads(&sc->smc_tq, 1, PI_NET, "%s taskq", 397 device_get_nameunit(sc->smc_dev)); 398 399 /* Mask all interrupts. */ 400 sc->smc_mask = 0; 401 smc_write_1(sc, MSK, 0); 402 403 /* Wire up interrupt */ 404 error = bus_setup_intr(dev, sc->smc_irq, 405 INTR_TYPE_NET|INTR_MPSAFE, smc_intr, NULL, sc, &sc->smc_ih); 406 if (error != 0) 407 goto done; 408 409 done: 410 if (error != 0) 411 smc_detach(dev); 412 return (error); 413 } 414 415 int 416 smc_detach(device_t dev) 417 { 418 int type; 419 struct smc_softc *sc; 420 421 sc = device_get_softc(dev); 422 SMC_LOCK(sc); 423 smc_stop(sc); 424 SMC_UNLOCK(sc); 425 426 if (sc->smc_ifp != NULL) { 427 ether_ifdetach(sc->smc_ifp); 428 } 429 430 callout_drain(&sc->smc_watchdog); 431 callout_drain(&sc->smc_mii_tick_ch); 432 433 #ifdef DEVICE_POLLING 434 if (sc->smc_if_getcapenable(ifp) & IFCAP_POLLING) 435 ether_poll_deregister(sc->smc_ifp); 436 #endif 437 438 if (sc->smc_ih != NULL) 439 bus_teardown_intr(sc->smc_dev, sc->smc_irq, sc->smc_ih); 440 441 if (sc->smc_tq != NULL) { 442 taskqueue_drain(sc->smc_tq, &sc->smc_intr); 443 taskqueue_drain(sc->smc_tq, &sc->smc_rx); 444 taskqueue_drain(sc->smc_tq, &sc->smc_tx); 445 taskqueue_free(sc->smc_tq); 446 sc->smc_tq = NULL; 447 } 448 449 if (sc->smc_ifp != NULL) { 450 if_free(sc->smc_ifp); 451 } 452 453 bus_generic_detach(sc->smc_dev); 454 455 if (sc->smc_reg != NULL) { 456 type = SYS_RES_IOPORT; 457 if (sc->smc_usemem) 458 type = SYS_RES_MEMORY; 459 460 bus_release_resource(sc->smc_dev, type, sc->smc_reg_rid, 461 sc->smc_reg); 462 } 463 464 if (sc->smc_irq != NULL) 465 bus_release_resource(sc->smc_dev, SYS_RES_IRQ, sc->smc_irq_rid, 466 sc->smc_irq); 467 468 if (mtx_initialized(&sc->smc_mtx)) 469 mtx_destroy(&sc->smc_mtx); 470 471 return (0); 472 } 473 474 static device_method_t smc_methods[] = { 475 /* Device interface */ 476 DEVMETHOD(device_attach, smc_attach), 477 DEVMETHOD(device_detach, smc_detach), 478 479 /* MII interface */ 480 DEVMETHOD(miibus_readreg, smc_miibus_readreg), 481 DEVMETHOD(miibus_writereg, smc_miibus_writereg), 482 DEVMETHOD(miibus_statchg, smc_miibus_statchg), 483 { 0, 0 } 484 }; 485 486 driver_t smc_driver = { 487 "smc", 488 smc_methods, 489 sizeof(struct smc_softc), 490 }; 491 492 DRIVER_MODULE(miibus, smc, miibus_driver, 0, 0); 493 494 static void 495 smc_start(if_t ifp) 496 { 497 struct smc_softc *sc; 498 499 sc = if_getsoftc(ifp); 500 SMC_LOCK(sc); 501 smc_start_locked(ifp); 502 SMC_UNLOCK(sc); 503 } 504 505 static void 506 smc_start_locked(if_t ifp) 507 { 508 struct smc_softc *sc; 509 struct mbuf *m; 510 u_int len, npages, spin_count; 511 512 sc = if_getsoftc(ifp); 513 SMC_ASSERT_LOCKED(sc); 514 515 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 516 return; 517 if (if_sendq_empty(ifp)) 518 return; 519 520 /* 521 * Grab the next packet. If it's too big, drop it. 522 */ 523 m = if_dequeue(ifp); 524 len = m_length(m, NULL); 525 len += (len & 1); 526 if (len > ETHER_MAX_LEN - ETHER_CRC_LEN) { 527 if_printf(ifp, "large packet discarded\n"); 528 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 529 m_freem(m); 530 return; /* XXX readcheck? */ 531 } 532 533 /* 534 * Flag that we're busy. 535 */ 536 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 537 sc->smc_pending = m; 538 539 /* 540 * Work out how many 256 byte "pages" we need. We have to include the 541 * control data for the packet in this calculation. 542 */ 543 npages = (len + PKT_CTRL_DATA_LEN) >> 8; 544 if (npages == 0) 545 npages = 1; 546 547 /* 548 * Request memory. 549 */ 550 smc_select_bank(sc, 2); 551 smc_mmu_wait(sc); 552 smc_write_2(sc, MMUCR, MMUCR_CMD_TX_ALLOC | npages); 553 554 /* 555 * Spin briefly to see if the allocation succeeds. 556 */ 557 spin_count = TX_ALLOC_WAIT_TIME; 558 do { 559 if (smc_read_1(sc, IST) & ALLOC_INT) { 560 smc_write_1(sc, ACK, ALLOC_INT); 561 break; 562 } 563 } while (--spin_count); 564 565 /* 566 * If the allocation is taking too long, unmask the alloc interrupt 567 * and wait. 568 */ 569 if (spin_count == 0) { 570 sc->smc_mask |= ALLOC_INT; 571 if ((if_getcapenable(ifp) & IFCAP_POLLING) == 0) 572 smc_write_1(sc, MSK, sc->smc_mask); 573 return; 574 } 575 576 taskqueue_enqueue(sc->smc_tq, &sc->smc_tx); 577 } 578 579 static void 580 smc_task_tx(void *context, int pending) 581 { 582 if_t ifp; 583 struct smc_softc *sc; 584 struct mbuf *m, *m0; 585 u_int packet, len; 586 int last_len; 587 uint8_t *data; 588 589 (void)pending; 590 ifp = (if_t)context; 591 sc = if_getsoftc(ifp); 592 593 SMC_LOCK(sc); 594 595 if (sc->smc_pending == NULL) { 596 SMC_UNLOCK(sc); 597 goto next_packet; 598 } 599 600 m = m0 = sc->smc_pending; 601 sc->smc_pending = NULL; 602 smc_select_bank(sc, 2); 603 604 /* 605 * Check the allocation result. 606 */ 607 packet = smc_read_1(sc, ARR); 608 609 /* 610 * If the allocation failed, requeue the packet and retry. 611 */ 612 if (packet & ARR_FAILED) { 613 if_sendq_prepend(ifp, m); 614 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 615 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 616 smc_start_locked(ifp); 617 SMC_UNLOCK(sc); 618 return; 619 } 620 621 /* 622 * Tell the device to write to our packet number. 623 */ 624 smc_write_1(sc, PNR, packet); 625 smc_write_2(sc, PTR, 0 | PTR_AUTO_INCR); 626 627 /* 628 * Tell the device how long the packet is (including control data). 629 */ 630 len = m_length(m, 0); 631 len += PKT_CTRL_DATA_LEN; 632 smc_write_2(sc, DATA0, 0); 633 smc_write_2(sc, DATA0, len); 634 635 /* 636 * Push the data out to the device. 637 */ 638 data = NULL; 639 last_len = 0; 640 for (; m != NULL; m = m->m_next) { 641 data = mtod(m, uint8_t *); 642 smc_write_multi_2(sc, DATA0, (uint16_t *)data, m->m_len / 2); 643 last_len = m->m_len; 644 } 645 646 /* 647 * Push out the control byte and and the odd byte if needed. 648 */ 649 if ((len & 1) != 0 && data != NULL) 650 smc_write_2(sc, DATA0, (CTRL_ODD << 8) | data[last_len - 1]); 651 else 652 smc_write_2(sc, DATA0, 0); 653 654 /* 655 * Unmask the TX empty interrupt. 656 */ 657 sc->smc_mask |= TX_EMPTY_INT; 658 if ((if_getcapenable(ifp) & IFCAP_POLLING) == 0) 659 smc_write_1(sc, MSK, sc->smc_mask); 660 661 /* 662 * Enqueue the packet. 663 */ 664 smc_mmu_wait(sc); 665 smc_write_2(sc, MMUCR, MMUCR_CMD_ENQUEUE); 666 callout_reset(&sc->smc_watchdog, hz * 2, smc_watchdog, sc); 667 668 /* 669 * Finish up. 670 */ 671 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 672 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 673 SMC_UNLOCK(sc); 674 BPF_MTAP(ifp, m0); 675 m_freem(m0); 676 677 next_packet: 678 /* 679 * See if there's anything else to do. 680 */ 681 smc_start(ifp); 682 } 683 684 static void 685 smc_task_rx(void *context, int pending) 686 { 687 u_int packet, status, len; 688 uint8_t *data; 689 if_t ifp; 690 struct smc_softc *sc; 691 struct mbuf *m, *mhead, *mtail; 692 693 (void)pending; 694 ifp = (if_t)context; 695 sc = if_getsoftc(ifp); 696 mhead = mtail = NULL; 697 698 SMC_LOCK(sc); 699 700 packet = smc_read_1(sc, FIFO_RX); 701 while ((packet & FIFO_EMPTY) == 0) { 702 /* 703 * Grab an mbuf and attach a cluster. 704 */ 705 MGETHDR(m, M_NOWAIT, MT_DATA); 706 if (m == NULL) { 707 break; 708 } 709 if (!(MCLGET(m, M_NOWAIT))) { 710 m_freem(m); 711 break; 712 } 713 714 /* 715 * Point to the start of the packet. 716 */ 717 smc_select_bank(sc, 2); 718 smc_write_1(sc, PNR, packet); 719 smc_write_2(sc, PTR, 0 | PTR_READ | PTR_RCV | PTR_AUTO_INCR); 720 721 /* 722 * Grab status and packet length. 723 */ 724 status = smc_read_2(sc, DATA0); 725 len = smc_read_2(sc, DATA0) & RX_LEN_MASK; 726 len -= 6; 727 if (status & RX_ODDFRM) 728 len += 1; 729 730 /* 731 * Check for errors. 732 */ 733 if (status & (RX_TOOSHORT | RX_TOOLNG | RX_BADCRC | RX_ALGNERR)) { 734 smc_mmu_wait(sc); 735 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE); 736 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 737 m_freem(m); 738 break; 739 } 740 741 /* 742 * Set the mbuf up the way we want it. 743 */ 744 m->m_pkthdr.rcvif = ifp; 745 m->m_pkthdr.len = m->m_len = len + 2; /* XXX: Is this right? */ 746 m_adj(m, ETHER_ALIGN); 747 748 /* 749 * Pull the packet out of the device. Make sure we're in the 750 * right bank first as things may have changed while we were 751 * allocating our mbuf. 752 */ 753 smc_select_bank(sc, 2); 754 smc_write_1(sc, PNR, packet); 755 smc_write_2(sc, PTR, 4 | PTR_READ | PTR_RCV | PTR_AUTO_INCR); 756 data = mtod(m, uint8_t *); 757 smc_read_multi_2(sc, DATA0, (uint16_t *)data, len >> 1); 758 if (len & 1) { 759 data += len & ~1; 760 *data = smc_read_1(sc, DATA0); 761 } 762 763 /* 764 * Tell the device we're done. 765 */ 766 smc_mmu_wait(sc); 767 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE); 768 if (m == NULL) { 769 break; 770 } 771 772 if (mhead == NULL) { 773 mhead = mtail = m; 774 m->m_next = NULL; 775 } else { 776 mtail->m_next = m; 777 mtail = m; 778 } 779 packet = smc_read_1(sc, FIFO_RX); 780 } 781 782 sc->smc_mask |= RCV_INT; 783 if ((if_getcapenable(ifp) & IFCAP_POLLING) == 0) 784 smc_write_1(sc, MSK, sc->smc_mask); 785 786 SMC_UNLOCK(sc); 787 788 while (mhead != NULL) { 789 m = mhead; 790 mhead = mhead->m_next; 791 m->m_next = NULL; 792 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 793 if_input(ifp, m); 794 } 795 } 796 797 #ifdef DEVICE_POLLING 798 static int 799 smc_poll(if_t ifp, enum poll_cmd cmd, int count) 800 { 801 struct smc_softc *sc; 802 803 sc = if_getsoftc(ifp); 804 805 SMC_LOCK(sc); 806 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 807 SMC_UNLOCK(sc); 808 return (0); 809 } 810 SMC_UNLOCK(sc); 811 812 if (cmd == POLL_AND_CHECK_STATUS) 813 taskqueue_enqueue(sc->smc_tq, &sc->smc_intr); 814 return (0); 815 } 816 #endif 817 818 static int 819 smc_intr(void *context) 820 { 821 struct smc_softc *sc; 822 uint32_t curbank; 823 824 sc = (struct smc_softc *)context; 825 826 /* 827 * Save current bank and restore later in this function 828 */ 829 curbank = (smc_read_2(sc, BSR) & BSR_BANK_MASK); 830 831 /* 832 * Block interrupts in order to let smc_task_intr to kick in 833 */ 834 smc_select_bank(sc, 2); 835 smc_write_1(sc, MSK, 0); 836 837 /* Restore bank */ 838 smc_select_bank(sc, curbank); 839 840 taskqueue_enqueue(sc->smc_tq, &sc->smc_intr); 841 return (FILTER_HANDLED); 842 } 843 844 static void 845 smc_task_intr(void *context, int pending) 846 { 847 struct smc_softc *sc; 848 if_t ifp; 849 u_int status, packet, counter, tcr; 850 851 (void)pending; 852 ifp = (if_t)context; 853 sc = if_getsoftc(ifp); 854 855 SMC_LOCK(sc); 856 857 smc_select_bank(sc, 2); 858 859 /* 860 * Find out what interrupts are flagged. 861 */ 862 status = smc_read_1(sc, IST) & sc->smc_mask; 863 864 /* 865 * Transmit error 866 */ 867 if (status & TX_INT) { 868 /* 869 * Kill off the packet if there is one and re-enable transmit. 870 */ 871 packet = smc_read_1(sc, FIFO_TX); 872 if ((packet & FIFO_EMPTY) == 0) { 873 callout_stop(&sc->smc_watchdog); 874 smc_select_bank(sc, 2); 875 smc_write_1(sc, PNR, packet); 876 smc_write_2(sc, PTR, 0 | PTR_READ | 877 PTR_AUTO_INCR); 878 smc_select_bank(sc, 0); 879 tcr = smc_read_2(sc, EPHSR); 880 #if 0 881 if ((tcr & EPHSR_TX_SUC) == 0) 882 device_printf(sc->smc_dev, 883 "bad packet\n"); 884 #endif 885 smc_select_bank(sc, 2); 886 smc_mmu_wait(sc); 887 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE_PKT); 888 889 smc_select_bank(sc, 0); 890 tcr = smc_read_2(sc, TCR); 891 tcr |= TCR_TXENA | TCR_PAD_EN; 892 smc_write_2(sc, TCR, tcr); 893 smc_select_bank(sc, 2); 894 taskqueue_enqueue(sc->smc_tq, &sc->smc_tx); 895 } 896 897 /* 898 * Ack the interrupt. 899 */ 900 smc_write_1(sc, ACK, TX_INT); 901 } 902 903 /* 904 * Receive 905 */ 906 if (status & RCV_INT) { 907 smc_write_1(sc, ACK, RCV_INT); 908 sc->smc_mask &= ~RCV_INT; 909 taskqueue_enqueue(sc->smc_tq, &sc->smc_rx); 910 } 911 912 /* 913 * Allocation 914 */ 915 if (status & ALLOC_INT) { 916 smc_write_1(sc, ACK, ALLOC_INT); 917 sc->smc_mask &= ~ALLOC_INT; 918 taskqueue_enqueue(sc->smc_tq, &sc->smc_tx); 919 } 920 921 /* 922 * Receive overrun 923 */ 924 if (status & RX_OVRN_INT) { 925 smc_write_1(sc, ACK, RX_OVRN_INT); 926 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 927 } 928 929 /* 930 * Transmit empty 931 */ 932 if (status & TX_EMPTY_INT) { 933 smc_write_1(sc, ACK, TX_EMPTY_INT); 934 sc->smc_mask &= ~TX_EMPTY_INT; 935 callout_stop(&sc->smc_watchdog); 936 937 /* 938 * Update collision stats. 939 */ 940 smc_select_bank(sc, 0); 941 counter = smc_read_2(sc, ECR); 942 smc_select_bank(sc, 2); 943 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 944 ((counter & ECR_SNGLCOL_MASK) >> ECR_SNGLCOL_SHIFT) + 945 ((counter & ECR_MULCOL_MASK) >> ECR_MULCOL_SHIFT)); 946 947 /* 948 * See if there are any packets to transmit. 949 */ 950 taskqueue_enqueue(sc->smc_tq, &sc->smc_tx); 951 } 952 953 /* 954 * Update the interrupt mask. 955 */ 956 smc_select_bank(sc, 2); 957 if ((if_getcapenable(ifp) & IFCAP_POLLING) == 0) 958 smc_write_1(sc, MSK, sc->smc_mask); 959 960 SMC_UNLOCK(sc); 961 } 962 963 static uint32_t 964 smc_mii_bitbang_read(device_t dev) 965 { 966 struct smc_softc *sc; 967 uint32_t val; 968 969 sc = device_get_softc(dev); 970 971 SMC_ASSERT_LOCKED(sc); 972 KASSERT((smc_read_2(sc, BSR) & BSR_BANK_MASK) == 3, 973 ("%s: smc_mii_bitbang_read called with bank %d (!= 3)", 974 device_get_nameunit(sc->smc_dev), 975 smc_read_2(sc, BSR) & BSR_BANK_MASK)); 976 977 val = smc_read_2(sc, MGMT); 978 smc_barrier(sc, MGMT, 2, 979 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 980 981 return (val); 982 } 983 984 static void 985 smc_mii_bitbang_write(device_t dev, uint32_t val) 986 { 987 struct smc_softc *sc; 988 989 sc = device_get_softc(dev); 990 991 SMC_ASSERT_LOCKED(sc); 992 KASSERT((smc_read_2(sc, BSR) & BSR_BANK_MASK) == 3, 993 ("%s: smc_mii_bitbang_write called with bank %d (!= 3)", 994 device_get_nameunit(sc->smc_dev), 995 smc_read_2(sc, BSR) & BSR_BANK_MASK)); 996 997 smc_write_2(sc, MGMT, val); 998 smc_barrier(sc, MGMT, 2, 999 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1000 } 1001 1002 int 1003 smc_miibus_readreg(device_t dev, int phy, int reg) 1004 { 1005 struct smc_softc *sc; 1006 int val; 1007 1008 sc = device_get_softc(dev); 1009 1010 SMC_LOCK(sc); 1011 1012 smc_select_bank(sc, 3); 1013 1014 val = mii_bitbang_readreg(dev, &smc_mii_bitbang_ops, phy, reg); 1015 1016 SMC_UNLOCK(sc); 1017 return (val); 1018 } 1019 1020 int 1021 smc_miibus_writereg(device_t dev, int phy, int reg, int data) 1022 { 1023 struct smc_softc *sc; 1024 1025 sc = device_get_softc(dev); 1026 1027 SMC_LOCK(sc); 1028 1029 smc_select_bank(sc, 3); 1030 1031 mii_bitbang_writereg(dev, &smc_mii_bitbang_ops, phy, reg, data); 1032 1033 SMC_UNLOCK(sc); 1034 return (0); 1035 } 1036 1037 void 1038 smc_miibus_statchg(device_t dev) 1039 { 1040 struct smc_softc *sc; 1041 struct mii_data *mii; 1042 uint16_t tcr; 1043 1044 sc = device_get_softc(dev); 1045 mii = device_get_softc(sc->smc_miibus); 1046 1047 SMC_LOCK(sc); 1048 1049 smc_select_bank(sc, 0); 1050 tcr = smc_read_2(sc, TCR); 1051 1052 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 1053 tcr |= TCR_SWFDUP; 1054 else 1055 tcr &= ~TCR_SWFDUP; 1056 1057 smc_write_2(sc, TCR, tcr); 1058 1059 SMC_UNLOCK(sc); 1060 } 1061 1062 static int 1063 smc_mii_ifmedia_upd(if_t ifp) 1064 { 1065 struct smc_softc *sc; 1066 struct mii_data *mii; 1067 1068 sc = if_getsoftc(ifp); 1069 if (sc->smc_miibus == NULL) 1070 return (ENXIO); 1071 1072 mii = device_get_softc(sc->smc_miibus); 1073 return (mii_mediachg(mii)); 1074 } 1075 1076 static void 1077 smc_mii_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 1078 { 1079 struct smc_softc *sc; 1080 struct mii_data *mii; 1081 1082 sc = if_getsoftc(ifp); 1083 if (sc->smc_miibus == NULL) 1084 return; 1085 1086 mii = device_get_softc(sc->smc_miibus); 1087 mii_pollstat(mii); 1088 ifmr->ifm_active = mii->mii_media_active; 1089 ifmr->ifm_status = mii->mii_media_status; 1090 } 1091 1092 static void 1093 smc_mii_tick(void *context) 1094 { 1095 struct smc_softc *sc; 1096 1097 sc = (struct smc_softc *)context; 1098 1099 if (sc->smc_miibus == NULL) 1100 return; 1101 1102 SMC_UNLOCK(sc); 1103 1104 mii_tick(device_get_softc(sc->smc_miibus)); 1105 callout_reset(&sc->smc_mii_tick_ch, hz, smc_mii_tick, sc); 1106 } 1107 1108 static void 1109 smc_mii_mediachg(struct smc_softc *sc) 1110 { 1111 1112 if (sc->smc_miibus == NULL) 1113 return; 1114 mii_mediachg(device_get_softc(sc->smc_miibus)); 1115 } 1116 1117 static int 1118 smc_mii_mediaioctl(struct smc_softc *sc, struct ifreq *ifr, u_long command) 1119 { 1120 struct mii_data *mii; 1121 1122 if (sc->smc_miibus == NULL) 1123 return (EINVAL); 1124 1125 mii = device_get_softc(sc->smc_miibus); 1126 return (ifmedia_ioctl(sc->smc_ifp, ifr, &mii->mii_media, command)); 1127 } 1128 1129 static void 1130 smc_reset(struct smc_softc *sc) 1131 { 1132 u_int ctr; 1133 1134 SMC_ASSERT_LOCKED(sc); 1135 1136 smc_select_bank(sc, 2); 1137 1138 /* 1139 * Mask all interrupts. 1140 */ 1141 smc_write_1(sc, MSK, 0); 1142 1143 /* 1144 * Tell the device to reset. 1145 */ 1146 smc_select_bank(sc, 0); 1147 smc_write_2(sc, RCR, RCR_SOFT_RST); 1148 1149 /* 1150 * Set up the configuration register. 1151 */ 1152 smc_select_bank(sc, 1); 1153 smc_write_2(sc, CR, CR_EPH_POWER_EN); 1154 DELAY(1); 1155 1156 /* 1157 * Turn off transmit and receive. 1158 */ 1159 smc_select_bank(sc, 0); 1160 smc_write_2(sc, TCR, 0); 1161 smc_write_2(sc, RCR, 0); 1162 1163 /* 1164 * Set up the control register. 1165 */ 1166 smc_select_bank(sc, 1); 1167 ctr = smc_read_2(sc, CTRL); 1168 ctr |= CTRL_LE_ENABLE | CTRL_AUTO_RELEASE; 1169 smc_write_2(sc, CTRL, ctr); 1170 1171 /* 1172 * Reset the MMU. 1173 */ 1174 smc_select_bank(sc, 2); 1175 smc_mmu_wait(sc); 1176 smc_write_2(sc, MMUCR, MMUCR_CMD_MMU_RESET); 1177 } 1178 1179 static void 1180 smc_enable(struct smc_softc *sc) 1181 { 1182 if_t ifp; 1183 1184 SMC_ASSERT_LOCKED(sc); 1185 ifp = sc->smc_ifp; 1186 1187 /* 1188 * Set up the receive/PHY control register. 1189 */ 1190 smc_select_bank(sc, 0); 1191 smc_write_2(sc, RPCR, RPCR_ANEG | (RPCR_LED_LINK_ANY << RPCR_LSA_SHIFT) 1192 | (RPCR_LED_ACT_ANY << RPCR_LSB_SHIFT)); 1193 1194 /* 1195 * Set up the transmit and receive control registers. 1196 */ 1197 smc_write_2(sc, TCR, TCR_TXENA | TCR_PAD_EN); 1198 smc_write_2(sc, RCR, RCR_RXEN | RCR_STRIP_CRC); 1199 1200 /* 1201 * Set up the interrupt mask. 1202 */ 1203 smc_select_bank(sc, 2); 1204 sc->smc_mask = EPH_INT | RX_OVRN_INT | RCV_INT | TX_INT; 1205 if ((if_getcapenable(ifp) & IFCAP_POLLING) != 0) 1206 smc_write_1(sc, MSK, sc->smc_mask); 1207 } 1208 1209 static void 1210 smc_stop(struct smc_softc *sc) 1211 { 1212 1213 SMC_ASSERT_LOCKED(sc); 1214 1215 /* 1216 * Turn off callouts. 1217 */ 1218 callout_stop(&sc->smc_watchdog); 1219 callout_stop(&sc->smc_mii_tick_ch); 1220 1221 /* 1222 * Mask all interrupts. 1223 */ 1224 smc_select_bank(sc, 2); 1225 sc->smc_mask = 0; 1226 smc_write_1(sc, MSK, 0); 1227 #ifdef DEVICE_POLLING 1228 ether_poll_deregister(sc->smc_ifp); 1229 if_setcapenablebit(ifp, 0, IFCAP_POLLING); 1230 #endif 1231 1232 /* 1233 * Disable transmit and receive. 1234 */ 1235 smc_select_bank(sc, 0); 1236 smc_write_2(sc, TCR, 0); 1237 smc_write_2(sc, RCR, 0); 1238 1239 if_setdrvflagbits(sc->smc_ifp, 0, IFF_DRV_RUNNING); 1240 } 1241 1242 static void 1243 smc_watchdog(void *arg) 1244 { 1245 struct smc_softc *sc; 1246 1247 sc = (struct smc_softc *)arg; 1248 device_printf(sc->smc_dev, "watchdog timeout\n"); 1249 taskqueue_enqueue(sc->smc_tq, &sc->smc_intr); 1250 } 1251 1252 static void 1253 smc_init(void *context) 1254 { 1255 struct smc_softc *sc; 1256 1257 sc = (struct smc_softc *)context; 1258 SMC_LOCK(sc); 1259 smc_init_locked(sc); 1260 SMC_UNLOCK(sc); 1261 } 1262 1263 static void 1264 smc_init_locked(struct smc_softc *sc) 1265 { 1266 if_t ifp; 1267 1268 SMC_ASSERT_LOCKED(sc); 1269 ifp = sc->smc_ifp; 1270 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1271 return; 1272 1273 smc_reset(sc); 1274 smc_enable(sc); 1275 1276 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 1277 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1278 1279 smc_start_locked(ifp); 1280 1281 if (sc->smc_mii_tick != NULL) 1282 callout_reset(&sc->smc_mii_tick_ch, hz, sc->smc_mii_tick, sc); 1283 1284 #ifdef DEVICE_POLLING 1285 SMC_UNLOCK(sc); 1286 ether_poll_register(smc_poll, ifp); 1287 SMC_LOCK(sc); 1288 if_setcapenablebit(ifp, IFCAP_POLLING, 0); 1289 #endif 1290 } 1291 1292 static int 1293 smc_ioctl(if_t ifp, u_long cmd, caddr_t data) 1294 { 1295 struct smc_softc *sc; 1296 int error; 1297 1298 sc = if_getsoftc(ifp); 1299 error = 0; 1300 1301 switch (cmd) { 1302 case SIOCSIFFLAGS: 1303 if ((if_getflags(ifp) & IFF_UP) == 0 && 1304 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1305 SMC_LOCK(sc); 1306 smc_stop(sc); 1307 SMC_UNLOCK(sc); 1308 } else { 1309 smc_init(sc); 1310 if (sc->smc_mii_mediachg != NULL) 1311 sc->smc_mii_mediachg(sc); 1312 } 1313 break; 1314 1315 case SIOCADDMULTI: 1316 case SIOCDELMULTI: 1317 /* XXX 1318 SMC_LOCK(sc); 1319 smc_setmcast(sc); 1320 SMC_UNLOCK(sc); 1321 */ 1322 error = EINVAL; 1323 break; 1324 1325 case SIOCGIFMEDIA: 1326 case SIOCSIFMEDIA: 1327 if (sc->smc_mii_mediaioctl == NULL) { 1328 error = EINVAL; 1329 break; 1330 } 1331 sc->smc_mii_mediaioctl(sc, (struct ifreq *)data, cmd); 1332 break; 1333 1334 default: 1335 error = ether_ioctl(ifp, cmd, data); 1336 break; 1337 } 1338 1339 return (error); 1340 } 1341