1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008 Benno Rice. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * Driver for SMSC LAN91C111, may work for older variants. 32 */ 33 34 #ifdef HAVE_KERNEL_OPTION_HEADERS 35 #include "opt_device_polling.h" 36 #endif 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/errno.h> 41 #include <sys/kernel.h> 42 #include <sys/sockio.h> 43 #include <sys/malloc.h> 44 #include <sys/mbuf.h> 45 #include <sys/queue.h> 46 #include <sys/socket.h> 47 #include <sys/syslog.h> 48 #include <sys/taskqueue.h> 49 50 #include <sys/module.h> 51 #include <sys/bus.h> 52 53 #include <machine/bus.h> 54 #include <machine/resource.h> 55 #include <sys/rman.h> 56 57 #include <net/ethernet.h> 58 #include <net/if.h> 59 #include <net/if_var.h> 60 #include <net/if_arp.h> 61 #include <net/if_dl.h> 62 #include <net/if_types.h> 63 #include <net/if_mib.h> 64 #include <net/if_media.h> 65 66 #ifdef INET 67 #include <netinet/in.h> 68 #include <netinet/in_systm.h> 69 #include <netinet/in_var.h> 70 #include <netinet/ip.h> 71 #endif 72 73 #include <net/bpf.h> 74 #include <net/bpfdesc.h> 75 76 #include <dev/smc/if_smcreg.h> 77 #include <dev/smc/if_smcvar.h> 78 79 #include <dev/mii/mii.h> 80 #include <dev/mii/mii_bitbang.h> 81 #include <dev/mii/miivar.h> 82 83 #include "miibus_if.h" 84 85 #define SMC_LOCK(sc) mtx_lock(&(sc)->smc_mtx) 86 #define SMC_UNLOCK(sc) mtx_unlock(&(sc)->smc_mtx) 87 #define SMC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->smc_mtx, MA_OWNED) 88 89 #define SMC_INTR_PRIORITY 0 90 #define SMC_RX_PRIORITY 5 91 #define SMC_TX_PRIORITY 10 92 93 devclass_t smc_devclass; 94 95 static const char *smc_chip_ids[16] = { 96 NULL, NULL, NULL, 97 /* 3 */ "SMSC LAN91C90 or LAN91C92", 98 /* 4 */ "SMSC LAN91C94", 99 /* 5 */ "SMSC LAN91C95", 100 /* 6 */ "SMSC LAN91C96", 101 /* 7 */ "SMSC LAN91C100", 102 /* 8 */ "SMSC LAN91C100FD", 103 /* 9 */ "SMSC LAN91C110FD or LAN91C111FD", 104 NULL, NULL, NULL, 105 NULL, NULL, NULL 106 }; 107 108 static void smc_init(void *); 109 static void smc_start(struct ifnet *); 110 static void smc_stop(struct smc_softc *); 111 static int smc_ioctl(struct ifnet *, u_long, caddr_t); 112 113 static void smc_init_locked(struct smc_softc *); 114 static void smc_start_locked(struct ifnet *); 115 static void smc_reset(struct smc_softc *); 116 static int smc_mii_ifmedia_upd(struct ifnet *); 117 static void smc_mii_ifmedia_sts(struct ifnet *, struct ifmediareq *); 118 static void smc_mii_tick(void *); 119 static void smc_mii_mediachg(struct smc_softc *); 120 static int smc_mii_mediaioctl(struct smc_softc *, struct ifreq *, u_long); 121 122 static void smc_task_intr(void *, int); 123 static void smc_task_rx(void *, int); 124 static void smc_task_tx(void *, int); 125 126 static driver_filter_t smc_intr; 127 static callout_func_t smc_watchdog; 128 #ifdef DEVICE_POLLING 129 static poll_handler_t smc_poll; 130 #endif 131 132 /* 133 * MII bit-bang glue 134 */ 135 static uint32_t smc_mii_bitbang_read(device_t); 136 static void smc_mii_bitbang_write(device_t, uint32_t); 137 138 static const struct mii_bitbang_ops smc_mii_bitbang_ops = { 139 smc_mii_bitbang_read, 140 smc_mii_bitbang_write, 141 { 142 MGMT_MDO, /* MII_BIT_MDO */ 143 MGMT_MDI, /* MII_BIT_MDI */ 144 MGMT_MCLK, /* MII_BIT_MDC */ 145 MGMT_MDOE, /* MII_BIT_DIR_HOST_PHY */ 146 0, /* MII_BIT_DIR_PHY_HOST */ 147 } 148 }; 149 150 static __inline void 151 smc_select_bank(struct smc_softc *sc, uint16_t bank) 152 { 153 154 bus_barrier(sc->smc_reg, BSR, 2, 155 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 156 bus_write_2(sc->smc_reg, BSR, bank & BSR_BANK_MASK); 157 bus_barrier(sc->smc_reg, BSR, 2, 158 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 159 } 160 161 /* Never call this when not in bank 2. */ 162 static __inline void 163 smc_mmu_wait(struct smc_softc *sc) 164 { 165 166 KASSERT((bus_read_2(sc->smc_reg, BSR) & 167 BSR_BANK_MASK) == 2, ("%s: smc_mmu_wait called when not in bank 2", 168 device_get_nameunit(sc->smc_dev))); 169 while (bus_read_2(sc->smc_reg, MMUCR) & MMUCR_BUSY) 170 ; 171 } 172 173 static __inline uint8_t 174 smc_read_1(struct smc_softc *sc, bus_size_t offset) 175 { 176 177 return (bus_read_1(sc->smc_reg, offset)); 178 } 179 180 static __inline void 181 smc_write_1(struct smc_softc *sc, bus_size_t offset, uint8_t val) 182 { 183 184 bus_write_1(sc->smc_reg, offset, val); 185 } 186 187 static __inline uint16_t 188 smc_read_2(struct smc_softc *sc, bus_size_t offset) 189 { 190 191 return (bus_read_2(sc->smc_reg, offset)); 192 } 193 194 static __inline void 195 smc_write_2(struct smc_softc *sc, bus_size_t offset, uint16_t val) 196 { 197 198 bus_write_2(sc->smc_reg, offset, val); 199 } 200 201 static __inline void 202 smc_read_multi_2(struct smc_softc *sc, bus_size_t offset, uint16_t *datap, 203 bus_size_t count) 204 { 205 206 bus_read_multi_2(sc->smc_reg, offset, datap, count); 207 } 208 209 static __inline void 210 smc_write_multi_2(struct smc_softc *sc, bus_size_t offset, uint16_t *datap, 211 bus_size_t count) 212 { 213 214 bus_write_multi_2(sc->smc_reg, offset, datap, count); 215 } 216 217 static __inline void 218 smc_barrier(struct smc_softc *sc, bus_size_t offset, bus_size_t length, 219 int flags) 220 { 221 222 bus_barrier(sc->smc_reg, offset, length, flags); 223 } 224 225 int 226 smc_probe(device_t dev) 227 { 228 int rid, type, error; 229 uint16_t val; 230 struct smc_softc *sc; 231 struct resource *reg; 232 233 sc = device_get_softc(dev); 234 rid = 0; 235 type = SYS_RES_IOPORT; 236 error = 0; 237 238 if (sc->smc_usemem) 239 type = SYS_RES_MEMORY; 240 241 reg = bus_alloc_resource_anywhere(dev, type, &rid, 16, RF_ACTIVE); 242 if (reg == NULL) { 243 if (bootverbose) 244 device_printf(dev, 245 "could not allocate I/O resource for probe\n"); 246 return (ENXIO); 247 } 248 249 /* Check for the identification value in the BSR. */ 250 val = bus_read_2(reg, BSR); 251 if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) { 252 if (bootverbose) 253 device_printf(dev, "identification value not in BSR\n"); 254 error = ENXIO; 255 goto done; 256 } 257 258 /* 259 * Try switching banks and make sure we still get the identification 260 * value. 261 */ 262 bus_write_2(reg, BSR, 0); 263 val = bus_read_2(reg, BSR); 264 if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) { 265 if (bootverbose) 266 device_printf(dev, 267 "identification value not in BSR after write\n"); 268 error = ENXIO; 269 goto done; 270 } 271 272 #if 0 273 /* Check the BAR. */ 274 bus_write_2(reg, BSR, 1); 275 val = bus_read_2(reg, BAR); 276 val = BAR_ADDRESS(val); 277 if (rman_get_start(reg) != val) { 278 if (bootverbose) 279 device_printf(dev, "BAR address %x does not match " 280 "I/O resource address %lx\n", val, 281 rman_get_start(reg)); 282 error = ENXIO; 283 goto done; 284 } 285 #endif 286 287 /* Compare REV against known chip revisions. */ 288 bus_write_2(reg, BSR, 3); 289 val = bus_read_2(reg, REV); 290 val = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT; 291 if (smc_chip_ids[val] == NULL) { 292 if (bootverbose) 293 device_printf(dev, "Unknown chip revision: %d\n", val); 294 error = ENXIO; 295 goto done; 296 } 297 298 device_set_desc(dev, smc_chip_ids[val]); 299 300 done: 301 bus_release_resource(dev, type, rid, reg); 302 return (error); 303 } 304 305 int 306 smc_attach(device_t dev) 307 { 308 int type, error; 309 uint16_t val; 310 u_char eaddr[ETHER_ADDR_LEN]; 311 struct smc_softc *sc; 312 struct ifnet *ifp; 313 314 sc = device_get_softc(dev); 315 error = 0; 316 317 sc->smc_dev = dev; 318 319 ifp = sc->smc_ifp = if_alloc(IFT_ETHER); 320 if (ifp == NULL) { 321 error = ENOSPC; 322 goto done; 323 } 324 325 mtx_init(&sc->smc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 326 327 /* Set up watchdog callout. */ 328 callout_init_mtx(&sc->smc_watchdog, &sc->smc_mtx, 0); 329 330 type = SYS_RES_IOPORT; 331 if (sc->smc_usemem) 332 type = SYS_RES_MEMORY; 333 334 sc->smc_reg_rid = 0; 335 sc->smc_reg = bus_alloc_resource_anywhere(dev, type, &sc->smc_reg_rid, 336 16, RF_ACTIVE); 337 if (sc->smc_reg == NULL) { 338 error = ENXIO; 339 goto done; 340 } 341 342 sc->smc_irq = bus_alloc_resource_anywhere(dev, SYS_RES_IRQ, 343 &sc->smc_irq_rid, 1, RF_ACTIVE | RF_SHAREABLE); 344 if (sc->smc_irq == NULL) { 345 error = ENXIO; 346 goto done; 347 } 348 349 SMC_LOCK(sc); 350 smc_reset(sc); 351 SMC_UNLOCK(sc); 352 353 smc_select_bank(sc, 3); 354 val = smc_read_2(sc, REV); 355 sc->smc_chip = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT; 356 sc->smc_rev = (val * REV_REV_MASK) >> REV_REV_SHIFT; 357 if (bootverbose) 358 device_printf(dev, "revision %x\n", sc->smc_rev); 359 360 callout_init_mtx(&sc->smc_mii_tick_ch, &sc->smc_mtx, 361 CALLOUT_RETURNUNLOCKED); 362 if (sc->smc_chip >= REV_CHIP_91110FD) { 363 (void)mii_attach(dev, &sc->smc_miibus, ifp, 364 smc_mii_ifmedia_upd, smc_mii_ifmedia_sts, BMSR_DEFCAPMASK, 365 MII_PHY_ANY, MII_OFFSET_ANY, 0); 366 if (sc->smc_miibus != NULL) { 367 sc->smc_mii_tick = smc_mii_tick; 368 sc->smc_mii_mediachg = smc_mii_mediachg; 369 sc->smc_mii_mediaioctl = smc_mii_mediaioctl; 370 } 371 } 372 373 smc_select_bank(sc, 1); 374 eaddr[0] = smc_read_1(sc, IAR0); 375 eaddr[1] = smc_read_1(sc, IAR1); 376 eaddr[2] = smc_read_1(sc, IAR2); 377 eaddr[3] = smc_read_1(sc, IAR3); 378 eaddr[4] = smc_read_1(sc, IAR4); 379 eaddr[5] = smc_read_1(sc, IAR5); 380 381 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 382 ifp->if_softc = sc; 383 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 384 ifp->if_init = smc_init; 385 ifp->if_ioctl = smc_ioctl; 386 ifp->if_start = smc_start; 387 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 388 IFQ_SET_READY(&ifp->if_snd); 389 390 ifp->if_capabilities = ifp->if_capenable = 0; 391 392 #ifdef DEVICE_POLLING 393 ifp->if_capabilities |= IFCAP_POLLING; 394 #endif 395 396 ether_ifattach(ifp, eaddr); 397 398 /* Set up taskqueue */ 399 TASK_INIT(&sc->smc_intr, SMC_INTR_PRIORITY, smc_task_intr, ifp); 400 NET_TASK_INIT(&sc->smc_rx, SMC_RX_PRIORITY, smc_task_rx, ifp); 401 TASK_INIT(&sc->smc_tx, SMC_TX_PRIORITY, smc_task_tx, ifp); 402 sc->smc_tq = taskqueue_create_fast("smc_taskq", M_NOWAIT, 403 taskqueue_thread_enqueue, &sc->smc_tq); 404 taskqueue_start_threads(&sc->smc_tq, 1, PI_NET, "%s taskq", 405 device_get_nameunit(sc->smc_dev)); 406 407 /* Mask all interrupts. */ 408 sc->smc_mask = 0; 409 smc_write_1(sc, MSK, 0); 410 411 /* Wire up interrupt */ 412 error = bus_setup_intr(dev, sc->smc_irq, 413 INTR_TYPE_NET|INTR_MPSAFE, smc_intr, NULL, sc, &sc->smc_ih); 414 if (error != 0) 415 goto done; 416 417 done: 418 if (error != 0) 419 smc_detach(dev); 420 return (error); 421 } 422 423 int 424 smc_detach(device_t dev) 425 { 426 int type; 427 struct smc_softc *sc; 428 429 sc = device_get_softc(dev); 430 SMC_LOCK(sc); 431 smc_stop(sc); 432 SMC_UNLOCK(sc); 433 434 if (sc->smc_ifp != NULL) { 435 ether_ifdetach(sc->smc_ifp); 436 } 437 438 callout_drain(&sc->smc_watchdog); 439 callout_drain(&sc->smc_mii_tick_ch); 440 441 #ifdef DEVICE_POLLING 442 if (sc->smc_ifp->if_capenable & IFCAP_POLLING) 443 ether_poll_deregister(sc->smc_ifp); 444 #endif 445 446 if (sc->smc_ih != NULL) 447 bus_teardown_intr(sc->smc_dev, sc->smc_irq, sc->smc_ih); 448 449 if (sc->smc_tq != NULL) { 450 taskqueue_drain(sc->smc_tq, &sc->smc_intr); 451 taskqueue_drain(sc->smc_tq, &sc->smc_rx); 452 taskqueue_drain(sc->smc_tq, &sc->smc_tx); 453 taskqueue_free(sc->smc_tq); 454 sc->smc_tq = NULL; 455 } 456 457 if (sc->smc_ifp != NULL) { 458 if_free(sc->smc_ifp); 459 } 460 461 if (sc->smc_miibus != NULL) { 462 device_delete_child(sc->smc_dev, sc->smc_miibus); 463 bus_generic_detach(sc->smc_dev); 464 } 465 466 if (sc->smc_reg != NULL) { 467 type = SYS_RES_IOPORT; 468 if (sc->smc_usemem) 469 type = SYS_RES_MEMORY; 470 471 bus_release_resource(sc->smc_dev, type, sc->smc_reg_rid, 472 sc->smc_reg); 473 } 474 475 if (sc->smc_irq != NULL) 476 bus_release_resource(sc->smc_dev, SYS_RES_IRQ, sc->smc_irq_rid, 477 sc->smc_irq); 478 479 if (mtx_initialized(&sc->smc_mtx)) 480 mtx_destroy(&sc->smc_mtx); 481 482 return (0); 483 } 484 485 static device_method_t smc_methods[] = { 486 /* Device interface */ 487 DEVMETHOD(device_attach, smc_attach), 488 DEVMETHOD(device_detach, smc_detach), 489 490 /* MII interface */ 491 DEVMETHOD(miibus_readreg, smc_miibus_readreg), 492 DEVMETHOD(miibus_writereg, smc_miibus_writereg), 493 DEVMETHOD(miibus_statchg, smc_miibus_statchg), 494 { 0, 0 } 495 }; 496 497 driver_t smc_driver = { 498 "smc", 499 smc_methods, 500 sizeof(struct smc_softc), 501 }; 502 503 DRIVER_MODULE(miibus, smc, miibus_driver, miibus_devclass, 0, 0); 504 505 static void 506 smc_start(struct ifnet *ifp) 507 { 508 struct smc_softc *sc; 509 510 sc = ifp->if_softc; 511 SMC_LOCK(sc); 512 smc_start_locked(ifp); 513 SMC_UNLOCK(sc); 514 } 515 516 static void 517 smc_start_locked(struct ifnet *ifp) 518 { 519 struct smc_softc *sc; 520 struct mbuf *m; 521 u_int len, npages, spin_count; 522 523 sc = ifp->if_softc; 524 SMC_ASSERT_LOCKED(sc); 525 526 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 527 return; 528 if (IFQ_IS_EMPTY(&ifp->if_snd)) 529 return; 530 531 /* 532 * Grab the next packet. If it's too big, drop it. 533 */ 534 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 535 len = m_length(m, NULL); 536 len += (len & 1); 537 if (len > ETHER_MAX_LEN - ETHER_CRC_LEN) { 538 if_printf(ifp, "large packet discarded\n"); 539 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 540 m_freem(m); 541 return; /* XXX readcheck? */ 542 } 543 544 /* 545 * Flag that we're busy. 546 */ 547 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 548 sc->smc_pending = m; 549 550 /* 551 * Work out how many 256 byte "pages" we need. We have to include the 552 * control data for the packet in this calculation. 553 */ 554 npages = (len + PKT_CTRL_DATA_LEN) >> 8; 555 if (npages == 0) 556 npages = 1; 557 558 /* 559 * Request memory. 560 */ 561 smc_select_bank(sc, 2); 562 smc_mmu_wait(sc); 563 smc_write_2(sc, MMUCR, MMUCR_CMD_TX_ALLOC | npages); 564 565 /* 566 * Spin briefly to see if the allocation succeeds. 567 */ 568 spin_count = TX_ALLOC_WAIT_TIME; 569 do { 570 if (smc_read_1(sc, IST) & ALLOC_INT) { 571 smc_write_1(sc, ACK, ALLOC_INT); 572 break; 573 } 574 } while (--spin_count); 575 576 /* 577 * If the allocation is taking too long, unmask the alloc interrupt 578 * and wait. 579 */ 580 if (spin_count == 0) { 581 sc->smc_mask |= ALLOC_INT; 582 if ((ifp->if_capenable & IFCAP_POLLING) == 0) 583 smc_write_1(sc, MSK, sc->smc_mask); 584 return; 585 } 586 587 taskqueue_enqueue(sc->smc_tq, &sc->smc_tx); 588 } 589 590 static void 591 smc_task_tx(void *context, int pending) 592 { 593 struct ifnet *ifp; 594 struct smc_softc *sc; 595 struct mbuf *m, *m0; 596 u_int packet, len; 597 int last_len; 598 uint8_t *data; 599 600 (void)pending; 601 ifp = (struct ifnet *)context; 602 sc = ifp->if_softc; 603 604 SMC_LOCK(sc); 605 606 if (sc->smc_pending == NULL) { 607 SMC_UNLOCK(sc); 608 goto next_packet; 609 } 610 611 m = m0 = sc->smc_pending; 612 sc->smc_pending = NULL; 613 smc_select_bank(sc, 2); 614 615 /* 616 * Check the allocation result. 617 */ 618 packet = smc_read_1(sc, ARR); 619 620 /* 621 * If the allocation failed, requeue the packet and retry. 622 */ 623 if (packet & ARR_FAILED) { 624 IFQ_DRV_PREPEND(&ifp->if_snd, m); 625 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 626 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 627 smc_start_locked(ifp); 628 SMC_UNLOCK(sc); 629 return; 630 } 631 632 /* 633 * Tell the device to write to our packet number. 634 */ 635 smc_write_1(sc, PNR, packet); 636 smc_write_2(sc, PTR, 0 | PTR_AUTO_INCR); 637 638 /* 639 * Tell the device how long the packet is (including control data). 640 */ 641 len = m_length(m, 0); 642 len += PKT_CTRL_DATA_LEN; 643 smc_write_2(sc, DATA0, 0); 644 smc_write_2(sc, DATA0, len); 645 646 /* 647 * Push the data out to the device. 648 */ 649 data = NULL; 650 last_len = 0; 651 for (; m != NULL; m = m->m_next) { 652 data = mtod(m, uint8_t *); 653 smc_write_multi_2(sc, DATA0, (uint16_t *)data, m->m_len / 2); 654 last_len = m->m_len; 655 } 656 657 /* 658 * Push out the control byte and and the odd byte if needed. 659 */ 660 if ((len & 1) != 0 && data != NULL) 661 smc_write_2(sc, DATA0, (CTRL_ODD << 8) | data[last_len - 1]); 662 else 663 smc_write_2(sc, DATA0, 0); 664 665 /* 666 * Unmask the TX empty interrupt. 667 */ 668 sc->smc_mask |= TX_EMPTY_INT; 669 if ((ifp->if_capenable & IFCAP_POLLING) == 0) 670 smc_write_1(sc, MSK, sc->smc_mask); 671 672 /* 673 * Enqueue the packet. 674 */ 675 smc_mmu_wait(sc); 676 smc_write_2(sc, MMUCR, MMUCR_CMD_ENQUEUE); 677 callout_reset(&sc->smc_watchdog, hz * 2, smc_watchdog, sc); 678 679 /* 680 * Finish up. 681 */ 682 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 683 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 684 SMC_UNLOCK(sc); 685 BPF_MTAP(ifp, m0); 686 m_freem(m0); 687 688 next_packet: 689 /* 690 * See if there's anything else to do. 691 */ 692 smc_start(ifp); 693 } 694 695 static void 696 smc_task_rx(void *context, int pending) 697 { 698 u_int packet, status, len; 699 uint8_t *data; 700 struct ifnet *ifp; 701 struct smc_softc *sc; 702 struct mbuf *m, *mhead, *mtail; 703 704 (void)pending; 705 ifp = (struct ifnet *)context; 706 sc = ifp->if_softc; 707 mhead = mtail = NULL; 708 709 SMC_LOCK(sc); 710 711 packet = smc_read_1(sc, FIFO_RX); 712 while ((packet & FIFO_EMPTY) == 0) { 713 /* 714 * Grab an mbuf and attach a cluster. 715 */ 716 MGETHDR(m, M_NOWAIT, MT_DATA); 717 if (m == NULL) { 718 break; 719 } 720 if (!(MCLGET(m, M_NOWAIT))) { 721 m_freem(m); 722 break; 723 } 724 725 /* 726 * Point to the start of the packet. 727 */ 728 smc_select_bank(sc, 2); 729 smc_write_1(sc, PNR, packet); 730 smc_write_2(sc, PTR, 0 | PTR_READ | PTR_RCV | PTR_AUTO_INCR); 731 732 /* 733 * Grab status and packet length. 734 */ 735 status = smc_read_2(sc, DATA0); 736 len = smc_read_2(sc, DATA0) & RX_LEN_MASK; 737 len -= 6; 738 if (status & RX_ODDFRM) 739 len += 1; 740 741 /* 742 * Check for errors. 743 */ 744 if (status & (RX_TOOSHORT | RX_TOOLNG | RX_BADCRC | RX_ALGNERR)) { 745 smc_mmu_wait(sc); 746 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE); 747 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 748 m_freem(m); 749 break; 750 } 751 752 /* 753 * Set the mbuf up the way we want it. 754 */ 755 m->m_pkthdr.rcvif = ifp; 756 m->m_pkthdr.len = m->m_len = len + 2; /* XXX: Is this right? */ 757 m_adj(m, ETHER_ALIGN); 758 759 /* 760 * Pull the packet out of the device. Make sure we're in the 761 * right bank first as things may have changed while we were 762 * allocating our mbuf. 763 */ 764 smc_select_bank(sc, 2); 765 smc_write_1(sc, PNR, packet); 766 smc_write_2(sc, PTR, 4 | PTR_READ | PTR_RCV | PTR_AUTO_INCR); 767 data = mtod(m, uint8_t *); 768 smc_read_multi_2(sc, DATA0, (uint16_t *)data, len >> 1); 769 if (len & 1) { 770 data += len & ~1; 771 *data = smc_read_1(sc, DATA0); 772 } 773 774 /* 775 * Tell the device we're done. 776 */ 777 smc_mmu_wait(sc); 778 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE); 779 if (m == NULL) { 780 break; 781 } 782 783 if (mhead == NULL) { 784 mhead = mtail = m; 785 m->m_next = NULL; 786 } else { 787 mtail->m_next = m; 788 mtail = m; 789 } 790 packet = smc_read_1(sc, FIFO_RX); 791 } 792 793 sc->smc_mask |= RCV_INT; 794 if ((ifp->if_capenable & IFCAP_POLLING) == 0) 795 smc_write_1(sc, MSK, sc->smc_mask); 796 797 SMC_UNLOCK(sc); 798 799 while (mhead != NULL) { 800 m = mhead; 801 mhead = mhead->m_next; 802 m->m_next = NULL; 803 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 804 (*ifp->if_input)(ifp, m); 805 } 806 } 807 808 #ifdef DEVICE_POLLING 809 static int 810 smc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 811 { 812 struct smc_softc *sc; 813 814 sc = ifp->if_softc; 815 816 SMC_LOCK(sc); 817 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 818 SMC_UNLOCK(sc); 819 return (0); 820 } 821 SMC_UNLOCK(sc); 822 823 if (cmd == POLL_AND_CHECK_STATUS) 824 taskqueue_enqueue(sc->smc_tq, &sc->smc_intr); 825 return (0); 826 } 827 #endif 828 829 static int 830 smc_intr(void *context) 831 { 832 struct smc_softc *sc; 833 uint32_t curbank; 834 835 sc = (struct smc_softc *)context; 836 837 /* 838 * Save current bank and restore later in this function 839 */ 840 curbank = (smc_read_2(sc, BSR) & BSR_BANK_MASK); 841 842 /* 843 * Block interrupts in order to let smc_task_intr to kick in 844 */ 845 smc_select_bank(sc, 2); 846 smc_write_1(sc, MSK, 0); 847 848 /* Restore bank */ 849 smc_select_bank(sc, curbank); 850 851 taskqueue_enqueue(sc->smc_tq, &sc->smc_intr); 852 return (FILTER_HANDLED); 853 } 854 855 static void 856 smc_task_intr(void *context, int pending) 857 { 858 struct smc_softc *sc; 859 struct ifnet *ifp; 860 u_int status, packet, counter, tcr; 861 862 (void)pending; 863 ifp = (struct ifnet *)context; 864 sc = ifp->if_softc; 865 866 SMC_LOCK(sc); 867 868 smc_select_bank(sc, 2); 869 870 /* 871 * Find out what interrupts are flagged. 872 */ 873 status = smc_read_1(sc, IST) & sc->smc_mask; 874 875 /* 876 * Transmit error 877 */ 878 if (status & TX_INT) { 879 /* 880 * Kill off the packet if there is one and re-enable transmit. 881 */ 882 packet = smc_read_1(sc, FIFO_TX); 883 if ((packet & FIFO_EMPTY) == 0) { 884 callout_stop(&sc->smc_watchdog); 885 smc_select_bank(sc, 2); 886 smc_write_1(sc, PNR, packet); 887 smc_write_2(sc, PTR, 0 | PTR_READ | 888 PTR_AUTO_INCR); 889 smc_select_bank(sc, 0); 890 tcr = smc_read_2(sc, EPHSR); 891 #if 0 892 if ((tcr & EPHSR_TX_SUC) == 0) 893 device_printf(sc->smc_dev, 894 "bad packet\n"); 895 #endif 896 smc_select_bank(sc, 2); 897 smc_mmu_wait(sc); 898 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE_PKT); 899 900 smc_select_bank(sc, 0); 901 tcr = smc_read_2(sc, TCR); 902 tcr |= TCR_TXENA | TCR_PAD_EN; 903 smc_write_2(sc, TCR, tcr); 904 smc_select_bank(sc, 2); 905 taskqueue_enqueue(sc->smc_tq, &sc->smc_tx); 906 } 907 908 /* 909 * Ack the interrupt. 910 */ 911 smc_write_1(sc, ACK, TX_INT); 912 } 913 914 /* 915 * Receive 916 */ 917 if (status & RCV_INT) { 918 smc_write_1(sc, ACK, RCV_INT); 919 sc->smc_mask &= ~RCV_INT; 920 taskqueue_enqueue(sc->smc_tq, &sc->smc_rx); 921 } 922 923 /* 924 * Allocation 925 */ 926 if (status & ALLOC_INT) { 927 smc_write_1(sc, ACK, ALLOC_INT); 928 sc->smc_mask &= ~ALLOC_INT; 929 taskqueue_enqueue(sc->smc_tq, &sc->smc_tx); 930 } 931 932 /* 933 * Receive overrun 934 */ 935 if (status & RX_OVRN_INT) { 936 smc_write_1(sc, ACK, RX_OVRN_INT); 937 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 938 } 939 940 /* 941 * Transmit empty 942 */ 943 if (status & TX_EMPTY_INT) { 944 smc_write_1(sc, ACK, TX_EMPTY_INT); 945 sc->smc_mask &= ~TX_EMPTY_INT; 946 callout_stop(&sc->smc_watchdog); 947 948 /* 949 * Update collision stats. 950 */ 951 smc_select_bank(sc, 0); 952 counter = smc_read_2(sc, ECR); 953 smc_select_bank(sc, 2); 954 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 955 ((counter & ECR_SNGLCOL_MASK) >> ECR_SNGLCOL_SHIFT) + 956 ((counter & ECR_MULCOL_MASK) >> ECR_MULCOL_SHIFT)); 957 958 /* 959 * See if there are any packets to transmit. 960 */ 961 taskqueue_enqueue(sc->smc_tq, &sc->smc_tx); 962 } 963 964 /* 965 * Update the interrupt mask. 966 */ 967 smc_select_bank(sc, 2); 968 if ((ifp->if_capenable & IFCAP_POLLING) == 0) 969 smc_write_1(sc, MSK, sc->smc_mask); 970 971 SMC_UNLOCK(sc); 972 } 973 974 static uint32_t 975 smc_mii_bitbang_read(device_t dev) 976 { 977 struct smc_softc *sc; 978 uint32_t val; 979 980 sc = device_get_softc(dev); 981 982 SMC_ASSERT_LOCKED(sc); 983 KASSERT((smc_read_2(sc, BSR) & BSR_BANK_MASK) == 3, 984 ("%s: smc_mii_bitbang_read called with bank %d (!= 3)", 985 device_get_nameunit(sc->smc_dev), 986 smc_read_2(sc, BSR) & BSR_BANK_MASK)); 987 988 val = smc_read_2(sc, MGMT); 989 smc_barrier(sc, MGMT, 2, 990 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 991 992 return (val); 993 } 994 995 static void 996 smc_mii_bitbang_write(device_t dev, uint32_t val) 997 { 998 struct smc_softc *sc; 999 1000 sc = device_get_softc(dev); 1001 1002 SMC_ASSERT_LOCKED(sc); 1003 KASSERT((smc_read_2(sc, BSR) & BSR_BANK_MASK) == 3, 1004 ("%s: smc_mii_bitbang_write called with bank %d (!= 3)", 1005 device_get_nameunit(sc->smc_dev), 1006 smc_read_2(sc, BSR) & BSR_BANK_MASK)); 1007 1008 smc_write_2(sc, MGMT, val); 1009 smc_barrier(sc, MGMT, 2, 1010 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1011 } 1012 1013 int 1014 smc_miibus_readreg(device_t dev, int phy, int reg) 1015 { 1016 struct smc_softc *sc; 1017 int val; 1018 1019 sc = device_get_softc(dev); 1020 1021 SMC_LOCK(sc); 1022 1023 smc_select_bank(sc, 3); 1024 1025 val = mii_bitbang_readreg(dev, &smc_mii_bitbang_ops, phy, reg); 1026 1027 SMC_UNLOCK(sc); 1028 return (val); 1029 } 1030 1031 int 1032 smc_miibus_writereg(device_t dev, int phy, int reg, int data) 1033 { 1034 struct smc_softc *sc; 1035 1036 sc = device_get_softc(dev); 1037 1038 SMC_LOCK(sc); 1039 1040 smc_select_bank(sc, 3); 1041 1042 mii_bitbang_writereg(dev, &smc_mii_bitbang_ops, phy, reg, data); 1043 1044 SMC_UNLOCK(sc); 1045 return (0); 1046 } 1047 1048 void 1049 smc_miibus_statchg(device_t dev) 1050 { 1051 struct smc_softc *sc; 1052 struct mii_data *mii; 1053 uint16_t tcr; 1054 1055 sc = device_get_softc(dev); 1056 mii = device_get_softc(sc->smc_miibus); 1057 1058 SMC_LOCK(sc); 1059 1060 smc_select_bank(sc, 0); 1061 tcr = smc_read_2(sc, TCR); 1062 1063 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 1064 tcr |= TCR_SWFDUP; 1065 else 1066 tcr &= ~TCR_SWFDUP; 1067 1068 smc_write_2(sc, TCR, tcr); 1069 1070 SMC_UNLOCK(sc); 1071 } 1072 1073 static int 1074 smc_mii_ifmedia_upd(struct ifnet *ifp) 1075 { 1076 struct smc_softc *sc; 1077 struct mii_data *mii; 1078 1079 sc = ifp->if_softc; 1080 if (sc->smc_miibus == NULL) 1081 return (ENXIO); 1082 1083 mii = device_get_softc(sc->smc_miibus); 1084 return (mii_mediachg(mii)); 1085 } 1086 1087 static void 1088 smc_mii_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1089 { 1090 struct smc_softc *sc; 1091 struct mii_data *mii; 1092 1093 sc = ifp->if_softc; 1094 if (sc->smc_miibus == NULL) 1095 return; 1096 1097 mii = device_get_softc(sc->smc_miibus); 1098 mii_pollstat(mii); 1099 ifmr->ifm_active = mii->mii_media_active; 1100 ifmr->ifm_status = mii->mii_media_status; 1101 } 1102 1103 static void 1104 smc_mii_tick(void *context) 1105 { 1106 struct smc_softc *sc; 1107 1108 sc = (struct smc_softc *)context; 1109 1110 if (sc->smc_miibus == NULL) 1111 return; 1112 1113 SMC_UNLOCK(sc); 1114 1115 mii_tick(device_get_softc(sc->smc_miibus)); 1116 callout_reset(&sc->smc_mii_tick_ch, hz, smc_mii_tick, sc); 1117 } 1118 1119 static void 1120 smc_mii_mediachg(struct smc_softc *sc) 1121 { 1122 1123 if (sc->smc_miibus == NULL) 1124 return; 1125 mii_mediachg(device_get_softc(sc->smc_miibus)); 1126 } 1127 1128 static int 1129 smc_mii_mediaioctl(struct smc_softc *sc, struct ifreq *ifr, u_long command) 1130 { 1131 struct mii_data *mii; 1132 1133 if (sc->smc_miibus == NULL) 1134 return (EINVAL); 1135 1136 mii = device_get_softc(sc->smc_miibus); 1137 return (ifmedia_ioctl(sc->smc_ifp, ifr, &mii->mii_media, command)); 1138 } 1139 1140 static void 1141 smc_reset(struct smc_softc *sc) 1142 { 1143 u_int ctr; 1144 1145 SMC_ASSERT_LOCKED(sc); 1146 1147 smc_select_bank(sc, 2); 1148 1149 /* 1150 * Mask all interrupts. 1151 */ 1152 smc_write_1(sc, MSK, 0); 1153 1154 /* 1155 * Tell the device to reset. 1156 */ 1157 smc_select_bank(sc, 0); 1158 smc_write_2(sc, RCR, RCR_SOFT_RST); 1159 1160 /* 1161 * Set up the configuration register. 1162 */ 1163 smc_select_bank(sc, 1); 1164 smc_write_2(sc, CR, CR_EPH_POWER_EN); 1165 DELAY(1); 1166 1167 /* 1168 * Turn off transmit and receive. 1169 */ 1170 smc_select_bank(sc, 0); 1171 smc_write_2(sc, TCR, 0); 1172 smc_write_2(sc, RCR, 0); 1173 1174 /* 1175 * Set up the control register. 1176 */ 1177 smc_select_bank(sc, 1); 1178 ctr = smc_read_2(sc, CTR); 1179 ctr |= CTR_LE_ENABLE | CTR_AUTO_RELEASE; 1180 smc_write_2(sc, CTR, ctr); 1181 1182 /* 1183 * Reset the MMU. 1184 */ 1185 smc_select_bank(sc, 2); 1186 smc_mmu_wait(sc); 1187 smc_write_2(sc, MMUCR, MMUCR_CMD_MMU_RESET); 1188 } 1189 1190 static void 1191 smc_enable(struct smc_softc *sc) 1192 { 1193 struct ifnet *ifp; 1194 1195 SMC_ASSERT_LOCKED(sc); 1196 ifp = sc->smc_ifp; 1197 1198 /* 1199 * Set up the receive/PHY control register. 1200 */ 1201 smc_select_bank(sc, 0); 1202 smc_write_2(sc, RPCR, RPCR_ANEG | (RPCR_LED_LINK_ANY << RPCR_LSA_SHIFT) 1203 | (RPCR_LED_ACT_ANY << RPCR_LSB_SHIFT)); 1204 1205 /* 1206 * Set up the transmit and receive control registers. 1207 */ 1208 smc_write_2(sc, TCR, TCR_TXENA | TCR_PAD_EN); 1209 smc_write_2(sc, RCR, RCR_RXEN | RCR_STRIP_CRC); 1210 1211 /* 1212 * Set up the interrupt mask. 1213 */ 1214 smc_select_bank(sc, 2); 1215 sc->smc_mask = EPH_INT | RX_OVRN_INT | RCV_INT | TX_INT; 1216 if ((ifp->if_capenable & IFCAP_POLLING) != 0) 1217 smc_write_1(sc, MSK, sc->smc_mask); 1218 } 1219 1220 static void 1221 smc_stop(struct smc_softc *sc) 1222 { 1223 1224 SMC_ASSERT_LOCKED(sc); 1225 1226 /* 1227 * Turn off callouts. 1228 */ 1229 callout_stop(&sc->smc_watchdog); 1230 callout_stop(&sc->smc_mii_tick_ch); 1231 1232 /* 1233 * Mask all interrupts. 1234 */ 1235 smc_select_bank(sc, 2); 1236 sc->smc_mask = 0; 1237 smc_write_1(sc, MSK, 0); 1238 #ifdef DEVICE_POLLING 1239 ether_poll_deregister(sc->smc_ifp); 1240 sc->smc_ifp->if_capenable &= ~IFCAP_POLLING; 1241 #endif 1242 1243 /* 1244 * Disable transmit and receive. 1245 */ 1246 smc_select_bank(sc, 0); 1247 smc_write_2(sc, TCR, 0); 1248 smc_write_2(sc, RCR, 0); 1249 1250 sc->smc_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1251 } 1252 1253 static void 1254 smc_watchdog(void *arg) 1255 { 1256 struct smc_softc *sc; 1257 1258 sc = (struct smc_softc *)arg; 1259 device_printf(sc->smc_dev, "watchdog timeout\n"); 1260 taskqueue_enqueue(sc->smc_tq, &sc->smc_intr); 1261 } 1262 1263 static void 1264 smc_init(void *context) 1265 { 1266 struct smc_softc *sc; 1267 1268 sc = (struct smc_softc *)context; 1269 SMC_LOCK(sc); 1270 smc_init_locked(sc); 1271 SMC_UNLOCK(sc); 1272 } 1273 1274 static void 1275 smc_init_locked(struct smc_softc *sc) 1276 { 1277 struct ifnet *ifp; 1278 1279 SMC_ASSERT_LOCKED(sc); 1280 ifp = sc->smc_ifp; 1281 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1282 return; 1283 1284 smc_reset(sc); 1285 smc_enable(sc); 1286 1287 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1288 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1289 1290 smc_start_locked(ifp); 1291 1292 if (sc->smc_mii_tick != NULL) 1293 callout_reset(&sc->smc_mii_tick_ch, hz, sc->smc_mii_tick, sc); 1294 1295 #ifdef DEVICE_POLLING 1296 SMC_UNLOCK(sc); 1297 ether_poll_register(smc_poll, ifp); 1298 SMC_LOCK(sc); 1299 ifp->if_capenable |= IFCAP_POLLING; 1300 #endif 1301 } 1302 1303 static int 1304 smc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1305 { 1306 struct smc_softc *sc; 1307 int error; 1308 1309 sc = ifp->if_softc; 1310 error = 0; 1311 1312 switch (cmd) { 1313 case SIOCSIFFLAGS: 1314 if ((ifp->if_flags & IFF_UP) == 0 && 1315 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1316 SMC_LOCK(sc); 1317 smc_stop(sc); 1318 SMC_UNLOCK(sc); 1319 } else { 1320 smc_init(sc); 1321 if (sc->smc_mii_mediachg != NULL) 1322 sc->smc_mii_mediachg(sc); 1323 } 1324 break; 1325 1326 case SIOCADDMULTI: 1327 case SIOCDELMULTI: 1328 /* XXX 1329 SMC_LOCK(sc); 1330 smc_setmcast(sc); 1331 SMC_UNLOCK(sc); 1332 */ 1333 error = EINVAL; 1334 break; 1335 1336 case SIOCGIFMEDIA: 1337 case SIOCSIFMEDIA: 1338 if (sc->smc_mii_mediaioctl == NULL) { 1339 error = EINVAL; 1340 break; 1341 } 1342 sc->smc_mii_mediaioctl(sc, (struct ifreq *)data, cmd); 1343 break; 1344 1345 default: 1346 error = ether_ioctl(ifp, cmd, data); 1347 break; 1348 } 1349 1350 return (error); 1351 } 1352