1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008 Benno Rice. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * Driver for SMSC LAN91C111, may work for older variants. 32 */ 33 34 #ifdef HAVE_KERNEL_OPTION_HEADERS 35 #include "opt_device_polling.h" 36 #endif 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/errno.h> 41 #include <sys/kernel.h> 42 #include <sys/sockio.h> 43 #include <sys/malloc.h> 44 #include <sys/mbuf.h> 45 #include <sys/queue.h> 46 #include <sys/socket.h> 47 #include <sys/syslog.h> 48 #include <sys/taskqueue.h> 49 50 #include <sys/module.h> 51 #include <sys/bus.h> 52 53 #include <machine/bus.h> 54 #include <machine/resource.h> 55 #include <sys/rman.h> 56 57 #include <net/ethernet.h> 58 #include <net/if.h> 59 #include <net/if_var.h> 60 #include <net/if_arp.h> 61 #include <net/if_dl.h> 62 #include <net/if_types.h> 63 #include <net/if_mib.h> 64 #include <net/if_media.h> 65 66 #ifdef INET 67 #include <netinet/in.h> 68 #include <netinet/in_systm.h> 69 #include <netinet/in_var.h> 70 #include <netinet/ip.h> 71 #endif 72 73 #include <net/bpf.h> 74 #include <net/bpfdesc.h> 75 76 #include <dev/smc/if_smcreg.h> 77 #include <dev/smc/if_smcvar.h> 78 79 #include <dev/mii/mii.h> 80 #include <dev/mii/mii_bitbang.h> 81 #include <dev/mii/miivar.h> 82 83 #define SMC_LOCK(sc) mtx_lock(&(sc)->smc_mtx) 84 #define SMC_UNLOCK(sc) mtx_unlock(&(sc)->smc_mtx) 85 #define SMC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->smc_mtx, MA_OWNED) 86 87 #define SMC_INTR_PRIORITY 0 88 #define SMC_RX_PRIORITY 5 89 #define SMC_TX_PRIORITY 10 90 91 devclass_t smc_devclass; 92 93 static const char *smc_chip_ids[16] = { 94 NULL, NULL, NULL, 95 /* 3 */ "SMSC LAN91C90 or LAN91C92", 96 /* 4 */ "SMSC LAN91C94", 97 /* 5 */ "SMSC LAN91C95", 98 /* 6 */ "SMSC LAN91C96", 99 /* 7 */ "SMSC LAN91C100", 100 /* 8 */ "SMSC LAN91C100FD", 101 /* 9 */ "SMSC LAN91C110FD or LAN91C111FD", 102 NULL, NULL, NULL, 103 NULL, NULL, NULL 104 }; 105 106 static void smc_init(void *); 107 static void smc_start(struct ifnet *); 108 static void smc_stop(struct smc_softc *); 109 static int smc_ioctl(struct ifnet *, u_long, caddr_t); 110 111 static void smc_init_locked(struct smc_softc *); 112 static void smc_start_locked(struct ifnet *); 113 static void smc_reset(struct smc_softc *); 114 static int smc_mii_ifmedia_upd(struct ifnet *); 115 static void smc_mii_ifmedia_sts(struct ifnet *, struct ifmediareq *); 116 static void smc_mii_tick(void *); 117 static void smc_mii_mediachg(struct smc_softc *); 118 static int smc_mii_mediaioctl(struct smc_softc *, struct ifreq *, u_long); 119 120 static void smc_task_intr(void *, int); 121 static void smc_task_rx(void *, int); 122 static void smc_task_tx(void *, int); 123 124 static driver_filter_t smc_intr; 125 static timeout_t smc_watchdog; 126 #ifdef DEVICE_POLLING 127 static poll_handler_t smc_poll; 128 #endif 129 130 /* 131 * MII bit-bang glue 132 */ 133 static uint32_t smc_mii_bitbang_read(device_t); 134 static void smc_mii_bitbang_write(device_t, uint32_t); 135 136 static const struct mii_bitbang_ops smc_mii_bitbang_ops = { 137 smc_mii_bitbang_read, 138 smc_mii_bitbang_write, 139 { 140 MGMT_MDO, /* MII_BIT_MDO */ 141 MGMT_MDI, /* MII_BIT_MDI */ 142 MGMT_MCLK, /* MII_BIT_MDC */ 143 MGMT_MDOE, /* MII_BIT_DIR_HOST_PHY */ 144 0, /* MII_BIT_DIR_PHY_HOST */ 145 } 146 }; 147 148 static __inline void 149 smc_select_bank(struct smc_softc *sc, uint16_t bank) 150 { 151 152 bus_barrier(sc->smc_reg, BSR, 2, 153 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 154 bus_write_2(sc->smc_reg, BSR, bank & BSR_BANK_MASK); 155 bus_barrier(sc->smc_reg, BSR, 2, 156 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 157 } 158 159 /* Never call this when not in bank 2. */ 160 static __inline void 161 smc_mmu_wait(struct smc_softc *sc) 162 { 163 164 KASSERT((bus_read_2(sc->smc_reg, BSR) & 165 BSR_BANK_MASK) == 2, ("%s: smc_mmu_wait called when not in bank 2", 166 device_get_nameunit(sc->smc_dev))); 167 while (bus_read_2(sc->smc_reg, MMUCR) & MMUCR_BUSY) 168 ; 169 } 170 171 static __inline uint8_t 172 smc_read_1(struct smc_softc *sc, bus_size_t offset) 173 { 174 175 return (bus_read_1(sc->smc_reg, offset)); 176 } 177 178 static __inline void 179 smc_write_1(struct smc_softc *sc, bus_size_t offset, uint8_t val) 180 { 181 182 bus_write_1(sc->smc_reg, offset, val); 183 } 184 185 static __inline uint16_t 186 smc_read_2(struct smc_softc *sc, bus_size_t offset) 187 { 188 189 return (bus_read_2(sc->smc_reg, offset)); 190 } 191 192 static __inline void 193 smc_write_2(struct smc_softc *sc, bus_size_t offset, uint16_t val) 194 { 195 196 bus_write_2(sc->smc_reg, offset, val); 197 } 198 199 static __inline void 200 smc_read_multi_2(struct smc_softc *sc, bus_size_t offset, uint16_t *datap, 201 bus_size_t count) 202 { 203 204 bus_read_multi_2(sc->smc_reg, offset, datap, count); 205 } 206 207 static __inline void 208 smc_write_multi_2(struct smc_softc *sc, bus_size_t offset, uint16_t *datap, 209 bus_size_t count) 210 { 211 212 bus_write_multi_2(sc->smc_reg, offset, datap, count); 213 } 214 215 static __inline void 216 smc_barrier(struct smc_softc *sc, bus_size_t offset, bus_size_t length, 217 int flags) 218 { 219 220 bus_barrier(sc->smc_reg, offset, length, flags); 221 } 222 223 int 224 smc_probe(device_t dev) 225 { 226 int rid, type, error; 227 uint16_t val; 228 struct smc_softc *sc; 229 struct resource *reg; 230 231 sc = device_get_softc(dev); 232 rid = 0; 233 type = SYS_RES_IOPORT; 234 error = 0; 235 236 if (sc->smc_usemem) 237 type = SYS_RES_MEMORY; 238 239 reg = bus_alloc_resource_anywhere(dev, type, &rid, 16, RF_ACTIVE); 240 if (reg == NULL) { 241 if (bootverbose) 242 device_printf(dev, 243 "could not allocate I/O resource for probe\n"); 244 return (ENXIO); 245 } 246 247 /* Check for the identification value in the BSR. */ 248 val = bus_read_2(reg, BSR); 249 if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) { 250 if (bootverbose) 251 device_printf(dev, "identification value not in BSR\n"); 252 error = ENXIO; 253 goto done; 254 } 255 256 /* 257 * Try switching banks and make sure we still get the identification 258 * value. 259 */ 260 bus_write_2(reg, BSR, 0); 261 val = bus_read_2(reg, BSR); 262 if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) { 263 if (bootverbose) 264 device_printf(dev, 265 "identification value not in BSR after write\n"); 266 error = ENXIO; 267 goto done; 268 } 269 270 #if 0 271 /* Check the BAR. */ 272 bus_write_2(reg, BSR, 1); 273 val = bus_read_2(reg, BAR); 274 val = BAR_ADDRESS(val); 275 if (rman_get_start(reg) != val) { 276 if (bootverbose) 277 device_printf(dev, "BAR address %x does not match " 278 "I/O resource address %lx\n", val, 279 rman_get_start(reg)); 280 error = ENXIO; 281 goto done; 282 } 283 #endif 284 285 /* Compare REV against known chip revisions. */ 286 bus_write_2(reg, BSR, 3); 287 val = bus_read_2(reg, REV); 288 val = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT; 289 if (smc_chip_ids[val] == NULL) { 290 if (bootverbose) 291 device_printf(dev, "Unknown chip revision: %d\n", val); 292 error = ENXIO; 293 goto done; 294 } 295 296 device_set_desc(dev, smc_chip_ids[val]); 297 298 done: 299 bus_release_resource(dev, type, rid, reg); 300 return (error); 301 } 302 303 int 304 smc_attach(device_t dev) 305 { 306 int type, error; 307 uint16_t val; 308 u_char eaddr[ETHER_ADDR_LEN]; 309 struct smc_softc *sc; 310 struct ifnet *ifp; 311 312 sc = device_get_softc(dev); 313 error = 0; 314 315 sc->smc_dev = dev; 316 317 ifp = sc->smc_ifp = if_alloc(IFT_ETHER); 318 if (ifp == NULL) { 319 error = ENOSPC; 320 goto done; 321 } 322 323 mtx_init(&sc->smc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 324 325 /* Set up watchdog callout. */ 326 callout_init_mtx(&sc->smc_watchdog, &sc->smc_mtx, 0); 327 328 type = SYS_RES_IOPORT; 329 if (sc->smc_usemem) 330 type = SYS_RES_MEMORY; 331 332 sc->smc_reg_rid = 0; 333 sc->smc_reg = bus_alloc_resource_anywhere(dev, type, &sc->smc_reg_rid, 334 16, RF_ACTIVE); 335 if (sc->smc_reg == NULL) { 336 error = ENXIO; 337 goto done; 338 } 339 340 sc->smc_irq = bus_alloc_resource_anywhere(dev, SYS_RES_IRQ, 341 &sc->smc_irq_rid, 1, RF_ACTIVE | RF_SHAREABLE); 342 if (sc->smc_irq == NULL) { 343 error = ENXIO; 344 goto done; 345 } 346 347 SMC_LOCK(sc); 348 smc_reset(sc); 349 SMC_UNLOCK(sc); 350 351 smc_select_bank(sc, 3); 352 val = smc_read_2(sc, REV); 353 sc->smc_chip = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT; 354 sc->smc_rev = (val * REV_REV_MASK) >> REV_REV_SHIFT; 355 if (bootverbose) 356 device_printf(dev, "revision %x\n", sc->smc_rev); 357 358 callout_init_mtx(&sc->smc_mii_tick_ch, &sc->smc_mtx, 359 CALLOUT_RETURNUNLOCKED); 360 if (sc->smc_chip >= REV_CHIP_91110FD) { 361 (void)mii_attach(dev, &sc->smc_miibus, ifp, 362 smc_mii_ifmedia_upd, smc_mii_ifmedia_sts, BMSR_DEFCAPMASK, 363 MII_PHY_ANY, MII_OFFSET_ANY, 0); 364 if (sc->smc_miibus != NULL) { 365 sc->smc_mii_tick = smc_mii_tick; 366 sc->smc_mii_mediachg = smc_mii_mediachg; 367 sc->smc_mii_mediaioctl = smc_mii_mediaioctl; 368 } 369 } 370 371 smc_select_bank(sc, 1); 372 eaddr[0] = smc_read_1(sc, IAR0); 373 eaddr[1] = smc_read_1(sc, IAR1); 374 eaddr[2] = smc_read_1(sc, IAR2); 375 eaddr[3] = smc_read_1(sc, IAR3); 376 eaddr[4] = smc_read_1(sc, IAR4); 377 eaddr[5] = smc_read_1(sc, IAR5); 378 379 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 380 ifp->if_softc = sc; 381 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 382 ifp->if_init = smc_init; 383 ifp->if_ioctl = smc_ioctl; 384 ifp->if_start = smc_start; 385 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 386 IFQ_SET_READY(&ifp->if_snd); 387 388 ifp->if_capabilities = ifp->if_capenable = 0; 389 390 #ifdef DEVICE_POLLING 391 ifp->if_capabilities |= IFCAP_POLLING; 392 #endif 393 394 ether_ifattach(ifp, eaddr); 395 396 /* Set up taskqueue */ 397 TASK_INIT(&sc->smc_intr, SMC_INTR_PRIORITY, smc_task_intr, ifp); 398 TASK_INIT(&sc->smc_rx, SMC_RX_PRIORITY, smc_task_rx, ifp); 399 TASK_INIT(&sc->smc_tx, SMC_TX_PRIORITY, smc_task_tx, ifp); 400 sc->smc_tq = taskqueue_create_fast("smc_taskq", M_NOWAIT, 401 taskqueue_thread_enqueue, &sc->smc_tq); 402 taskqueue_start_threads(&sc->smc_tq, 1, PI_NET, "%s taskq", 403 device_get_nameunit(sc->smc_dev)); 404 405 /* Mask all interrupts. */ 406 sc->smc_mask = 0; 407 smc_write_1(sc, MSK, 0); 408 409 /* Wire up interrupt */ 410 error = bus_setup_intr(dev, sc->smc_irq, 411 INTR_TYPE_NET|INTR_MPSAFE, smc_intr, NULL, sc, &sc->smc_ih); 412 if (error != 0) 413 goto done; 414 415 done: 416 if (error != 0) 417 smc_detach(dev); 418 return (error); 419 } 420 421 int 422 smc_detach(device_t dev) 423 { 424 int type; 425 struct smc_softc *sc; 426 427 sc = device_get_softc(dev); 428 SMC_LOCK(sc); 429 smc_stop(sc); 430 SMC_UNLOCK(sc); 431 432 if (sc->smc_ifp != NULL) { 433 ether_ifdetach(sc->smc_ifp); 434 } 435 436 callout_drain(&sc->smc_watchdog); 437 callout_drain(&sc->smc_mii_tick_ch); 438 439 #ifdef DEVICE_POLLING 440 if (sc->smc_ifp->if_capenable & IFCAP_POLLING) 441 ether_poll_deregister(sc->smc_ifp); 442 #endif 443 444 if (sc->smc_ih != NULL) 445 bus_teardown_intr(sc->smc_dev, sc->smc_irq, sc->smc_ih); 446 447 if (sc->smc_tq != NULL) { 448 taskqueue_drain(sc->smc_tq, &sc->smc_intr); 449 taskqueue_drain(sc->smc_tq, &sc->smc_rx); 450 taskqueue_drain(sc->smc_tq, &sc->smc_tx); 451 taskqueue_free(sc->smc_tq); 452 sc->smc_tq = NULL; 453 } 454 455 if (sc->smc_ifp != NULL) { 456 if_free(sc->smc_ifp); 457 } 458 459 if (sc->smc_miibus != NULL) { 460 device_delete_child(sc->smc_dev, sc->smc_miibus); 461 bus_generic_detach(sc->smc_dev); 462 } 463 464 if (sc->smc_reg != NULL) { 465 type = SYS_RES_IOPORT; 466 if (sc->smc_usemem) 467 type = SYS_RES_MEMORY; 468 469 bus_release_resource(sc->smc_dev, type, sc->smc_reg_rid, 470 sc->smc_reg); 471 } 472 473 if (sc->smc_irq != NULL) 474 bus_release_resource(sc->smc_dev, SYS_RES_IRQ, sc->smc_irq_rid, 475 sc->smc_irq); 476 477 if (mtx_initialized(&sc->smc_mtx)) 478 mtx_destroy(&sc->smc_mtx); 479 480 return (0); 481 } 482 483 static void 484 smc_start(struct ifnet *ifp) 485 { 486 struct smc_softc *sc; 487 488 sc = ifp->if_softc; 489 SMC_LOCK(sc); 490 smc_start_locked(ifp); 491 SMC_UNLOCK(sc); 492 } 493 494 static void 495 smc_start_locked(struct ifnet *ifp) 496 { 497 struct smc_softc *sc; 498 struct mbuf *m; 499 u_int len, npages, spin_count; 500 501 sc = ifp->if_softc; 502 SMC_ASSERT_LOCKED(sc); 503 504 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 505 return; 506 if (IFQ_IS_EMPTY(&ifp->if_snd)) 507 return; 508 509 /* 510 * Grab the next packet. If it's too big, drop it. 511 */ 512 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 513 len = m_length(m, NULL); 514 len += (len & 1); 515 if (len > ETHER_MAX_LEN - ETHER_CRC_LEN) { 516 if_printf(ifp, "large packet discarded\n"); 517 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 518 m_freem(m); 519 return; /* XXX readcheck? */ 520 } 521 522 /* 523 * Flag that we're busy. 524 */ 525 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 526 sc->smc_pending = m; 527 528 /* 529 * Work out how many 256 byte "pages" we need. We have to include the 530 * control data for the packet in this calculation. 531 */ 532 npages = (len + PKT_CTRL_DATA_LEN) >> 8; 533 if (npages == 0) 534 npages = 1; 535 536 /* 537 * Request memory. 538 */ 539 smc_select_bank(sc, 2); 540 smc_mmu_wait(sc); 541 smc_write_2(sc, MMUCR, MMUCR_CMD_TX_ALLOC | npages); 542 543 /* 544 * Spin briefly to see if the allocation succeeds. 545 */ 546 spin_count = TX_ALLOC_WAIT_TIME; 547 do { 548 if (smc_read_1(sc, IST) & ALLOC_INT) { 549 smc_write_1(sc, ACK, ALLOC_INT); 550 break; 551 } 552 } while (--spin_count); 553 554 /* 555 * If the allocation is taking too long, unmask the alloc interrupt 556 * and wait. 557 */ 558 if (spin_count == 0) { 559 sc->smc_mask |= ALLOC_INT; 560 if ((ifp->if_capenable & IFCAP_POLLING) == 0) 561 smc_write_1(sc, MSK, sc->smc_mask); 562 return; 563 } 564 565 taskqueue_enqueue(sc->smc_tq, &sc->smc_tx); 566 } 567 568 static void 569 smc_task_tx(void *context, int pending) 570 { 571 struct ifnet *ifp; 572 struct smc_softc *sc; 573 struct mbuf *m, *m0; 574 u_int packet, len; 575 int last_len; 576 uint8_t *data; 577 578 (void)pending; 579 ifp = (struct ifnet *)context; 580 sc = ifp->if_softc; 581 582 SMC_LOCK(sc); 583 584 if (sc->smc_pending == NULL) { 585 SMC_UNLOCK(sc); 586 goto next_packet; 587 } 588 589 m = m0 = sc->smc_pending; 590 sc->smc_pending = NULL; 591 smc_select_bank(sc, 2); 592 593 /* 594 * Check the allocation result. 595 */ 596 packet = smc_read_1(sc, ARR); 597 598 /* 599 * If the allocation failed, requeue the packet and retry. 600 */ 601 if (packet & ARR_FAILED) { 602 IFQ_DRV_PREPEND(&ifp->if_snd, m); 603 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 604 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 605 smc_start_locked(ifp); 606 SMC_UNLOCK(sc); 607 return; 608 } 609 610 /* 611 * Tell the device to write to our packet number. 612 */ 613 smc_write_1(sc, PNR, packet); 614 smc_write_2(sc, PTR, 0 | PTR_AUTO_INCR); 615 616 /* 617 * Tell the device how long the packet is (including control data). 618 */ 619 len = m_length(m, 0); 620 len += PKT_CTRL_DATA_LEN; 621 smc_write_2(sc, DATA0, 0); 622 smc_write_2(sc, DATA0, len); 623 624 /* 625 * Push the data out to the device. 626 */ 627 data = NULL; 628 last_len = 0; 629 for (; m != NULL; m = m->m_next) { 630 data = mtod(m, uint8_t *); 631 smc_write_multi_2(sc, DATA0, (uint16_t *)data, m->m_len / 2); 632 last_len = m->m_len; 633 } 634 635 /* 636 * Push out the control byte and and the odd byte if needed. 637 */ 638 if ((len & 1) != 0 && data != NULL) 639 smc_write_2(sc, DATA0, (CTRL_ODD << 8) | data[last_len - 1]); 640 else 641 smc_write_2(sc, DATA0, 0); 642 643 /* 644 * Unmask the TX empty interrupt. 645 */ 646 sc->smc_mask |= TX_EMPTY_INT; 647 if ((ifp->if_capenable & IFCAP_POLLING) == 0) 648 smc_write_1(sc, MSK, sc->smc_mask); 649 650 /* 651 * Enqueue the packet. 652 */ 653 smc_mmu_wait(sc); 654 smc_write_2(sc, MMUCR, MMUCR_CMD_ENQUEUE); 655 callout_reset(&sc->smc_watchdog, hz * 2, smc_watchdog, sc); 656 657 /* 658 * Finish up. 659 */ 660 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 661 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 662 SMC_UNLOCK(sc); 663 BPF_MTAP(ifp, m0); 664 m_freem(m0); 665 666 next_packet: 667 /* 668 * See if there's anything else to do. 669 */ 670 smc_start(ifp); 671 } 672 673 static void 674 smc_task_rx(void *context, int pending) 675 { 676 u_int packet, status, len; 677 uint8_t *data; 678 struct ifnet *ifp; 679 struct smc_softc *sc; 680 struct mbuf *m, *mhead, *mtail; 681 682 (void)pending; 683 ifp = (struct ifnet *)context; 684 sc = ifp->if_softc; 685 mhead = mtail = NULL; 686 687 SMC_LOCK(sc); 688 689 packet = smc_read_1(sc, FIFO_RX); 690 while ((packet & FIFO_EMPTY) == 0) { 691 /* 692 * Grab an mbuf and attach a cluster. 693 */ 694 MGETHDR(m, M_NOWAIT, MT_DATA); 695 if (m == NULL) { 696 break; 697 } 698 if (!(MCLGET(m, M_NOWAIT))) { 699 m_freem(m); 700 break; 701 } 702 703 /* 704 * Point to the start of the packet. 705 */ 706 smc_select_bank(sc, 2); 707 smc_write_1(sc, PNR, packet); 708 smc_write_2(sc, PTR, 0 | PTR_READ | PTR_RCV | PTR_AUTO_INCR); 709 710 /* 711 * Grab status and packet length. 712 */ 713 status = smc_read_2(sc, DATA0); 714 len = smc_read_2(sc, DATA0) & RX_LEN_MASK; 715 len -= 6; 716 if (status & RX_ODDFRM) 717 len += 1; 718 719 /* 720 * Check for errors. 721 */ 722 if (status & (RX_TOOSHORT | RX_TOOLNG | RX_BADCRC | RX_ALGNERR)) { 723 smc_mmu_wait(sc); 724 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE); 725 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 726 m_freem(m); 727 break; 728 } 729 730 /* 731 * Set the mbuf up the way we want it. 732 */ 733 m->m_pkthdr.rcvif = ifp; 734 m->m_pkthdr.len = m->m_len = len + 2; /* XXX: Is this right? */ 735 m_adj(m, ETHER_ALIGN); 736 737 /* 738 * Pull the packet out of the device. Make sure we're in the 739 * right bank first as things may have changed while we were 740 * allocating our mbuf. 741 */ 742 smc_select_bank(sc, 2); 743 smc_write_1(sc, PNR, packet); 744 smc_write_2(sc, PTR, 4 | PTR_READ | PTR_RCV | PTR_AUTO_INCR); 745 data = mtod(m, uint8_t *); 746 smc_read_multi_2(sc, DATA0, (uint16_t *)data, len >> 1); 747 if (len & 1) { 748 data += len & ~1; 749 *data = smc_read_1(sc, DATA0); 750 } 751 752 /* 753 * Tell the device we're done. 754 */ 755 smc_mmu_wait(sc); 756 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE); 757 if (m == NULL) { 758 break; 759 } 760 761 if (mhead == NULL) { 762 mhead = mtail = m; 763 m->m_next = NULL; 764 } else { 765 mtail->m_next = m; 766 mtail = m; 767 } 768 packet = smc_read_1(sc, FIFO_RX); 769 } 770 771 sc->smc_mask |= RCV_INT; 772 if ((ifp->if_capenable & IFCAP_POLLING) == 0) 773 smc_write_1(sc, MSK, sc->smc_mask); 774 775 SMC_UNLOCK(sc); 776 777 while (mhead != NULL) { 778 m = mhead; 779 mhead = mhead->m_next; 780 m->m_next = NULL; 781 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 782 (*ifp->if_input)(ifp, m); 783 } 784 } 785 786 #ifdef DEVICE_POLLING 787 static int 788 smc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 789 { 790 struct smc_softc *sc; 791 792 sc = ifp->if_softc; 793 794 SMC_LOCK(sc); 795 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 796 SMC_UNLOCK(sc); 797 return (0); 798 } 799 SMC_UNLOCK(sc); 800 801 if (cmd == POLL_AND_CHECK_STATUS) 802 taskqueue_enqueue(sc->smc_tq, &sc->smc_intr); 803 return (0); 804 } 805 #endif 806 807 static int 808 smc_intr(void *context) 809 { 810 struct smc_softc *sc; 811 uint32_t curbank; 812 813 sc = (struct smc_softc *)context; 814 815 /* 816 * Save current bank and restore later in this function 817 */ 818 curbank = (smc_read_2(sc, BSR) & BSR_BANK_MASK); 819 820 /* 821 * Block interrupts in order to let smc_task_intr to kick in 822 */ 823 smc_select_bank(sc, 2); 824 smc_write_1(sc, MSK, 0); 825 826 /* Restore bank */ 827 smc_select_bank(sc, curbank); 828 829 taskqueue_enqueue(sc->smc_tq, &sc->smc_intr); 830 return (FILTER_HANDLED); 831 } 832 833 static void 834 smc_task_intr(void *context, int pending) 835 { 836 struct smc_softc *sc; 837 struct ifnet *ifp; 838 u_int status, packet, counter, tcr; 839 840 (void)pending; 841 ifp = (struct ifnet *)context; 842 sc = ifp->if_softc; 843 844 SMC_LOCK(sc); 845 846 smc_select_bank(sc, 2); 847 848 /* 849 * Find out what interrupts are flagged. 850 */ 851 status = smc_read_1(sc, IST) & sc->smc_mask; 852 853 /* 854 * Transmit error 855 */ 856 if (status & TX_INT) { 857 /* 858 * Kill off the packet if there is one and re-enable transmit. 859 */ 860 packet = smc_read_1(sc, FIFO_TX); 861 if ((packet & FIFO_EMPTY) == 0) { 862 callout_stop(&sc->smc_watchdog); 863 smc_select_bank(sc, 2); 864 smc_write_1(sc, PNR, packet); 865 smc_write_2(sc, PTR, 0 | PTR_READ | 866 PTR_AUTO_INCR); 867 smc_select_bank(sc, 0); 868 tcr = smc_read_2(sc, EPHSR); 869 #if 0 870 if ((tcr & EPHSR_TX_SUC) == 0) 871 device_printf(sc->smc_dev, 872 "bad packet\n"); 873 #endif 874 smc_select_bank(sc, 2); 875 smc_mmu_wait(sc); 876 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE_PKT); 877 878 smc_select_bank(sc, 0); 879 tcr = smc_read_2(sc, TCR); 880 tcr |= TCR_TXENA | TCR_PAD_EN; 881 smc_write_2(sc, TCR, tcr); 882 smc_select_bank(sc, 2); 883 taskqueue_enqueue(sc->smc_tq, &sc->smc_tx); 884 } 885 886 /* 887 * Ack the interrupt. 888 */ 889 smc_write_1(sc, ACK, TX_INT); 890 } 891 892 /* 893 * Receive 894 */ 895 if (status & RCV_INT) { 896 smc_write_1(sc, ACK, RCV_INT); 897 sc->smc_mask &= ~RCV_INT; 898 taskqueue_enqueue(sc->smc_tq, &sc->smc_rx); 899 } 900 901 /* 902 * Allocation 903 */ 904 if (status & ALLOC_INT) { 905 smc_write_1(sc, ACK, ALLOC_INT); 906 sc->smc_mask &= ~ALLOC_INT; 907 taskqueue_enqueue(sc->smc_tq, &sc->smc_tx); 908 } 909 910 /* 911 * Receive overrun 912 */ 913 if (status & RX_OVRN_INT) { 914 smc_write_1(sc, ACK, RX_OVRN_INT); 915 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 916 } 917 918 /* 919 * Transmit empty 920 */ 921 if (status & TX_EMPTY_INT) { 922 smc_write_1(sc, ACK, TX_EMPTY_INT); 923 sc->smc_mask &= ~TX_EMPTY_INT; 924 callout_stop(&sc->smc_watchdog); 925 926 /* 927 * Update collision stats. 928 */ 929 smc_select_bank(sc, 0); 930 counter = smc_read_2(sc, ECR); 931 smc_select_bank(sc, 2); 932 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 933 ((counter & ECR_SNGLCOL_MASK) >> ECR_SNGLCOL_SHIFT) + 934 ((counter & ECR_MULCOL_MASK) >> ECR_MULCOL_SHIFT)); 935 936 /* 937 * See if there are any packets to transmit. 938 */ 939 taskqueue_enqueue(sc->smc_tq, &sc->smc_tx); 940 } 941 942 /* 943 * Update the interrupt mask. 944 */ 945 smc_select_bank(sc, 2); 946 if ((ifp->if_capenable & IFCAP_POLLING) == 0) 947 smc_write_1(sc, MSK, sc->smc_mask); 948 949 SMC_UNLOCK(sc); 950 } 951 952 static uint32_t 953 smc_mii_bitbang_read(device_t dev) 954 { 955 struct smc_softc *sc; 956 uint32_t val; 957 958 sc = device_get_softc(dev); 959 960 SMC_ASSERT_LOCKED(sc); 961 KASSERT((smc_read_2(sc, BSR) & BSR_BANK_MASK) == 3, 962 ("%s: smc_mii_bitbang_read called with bank %d (!= 3)", 963 device_get_nameunit(sc->smc_dev), 964 smc_read_2(sc, BSR) & BSR_BANK_MASK)); 965 966 val = smc_read_2(sc, MGMT); 967 smc_barrier(sc, MGMT, 2, 968 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 969 970 return (val); 971 } 972 973 static void 974 smc_mii_bitbang_write(device_t dev, uint32_t val) 975 { 976 struct smc_softc *sc; 977 978 sc = device_get_softc(dev); 979 980 SMC_ASSERT_LOCKED(sc); 981 KASSERT((smc_read_2(sc, BSR) & BSR_BANK_MASK) == 3, 982 ("%s: smc_mii_bitbang_write called with bank %d (!= 3)", 983 device_get_nameunit(sc->smc_dev), 984 smc_read_2(sc, BSR) & BSR_BANK_MASK)); 985 986 smc_write_2(sc, MGMT, val); 987 smc_barrier(sc, MGMT, 2, 988 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 989 } 990 991 int 992 smc_miibus_readreg(device_t dev, int phy, int reg) 993 { 994 struct smc_softc *sc; 995 int val; 996 997 sc = device_get_softc(dev); 998 999 SMC_LOCK(sc); 1000 1001 smc_select_bank(sc, 3); 1002 1003 val = mii_bitbang_readreg(dev, &smc_mii_bitbang_ops, phy, reg); 1004 1005 SMC_UNLOCK(sc); 1006 return (val); 1007 } 1008 1009 int 1010 smc_miibus_writereg(device_t dev, int phy, int reg, int data) 1011 { 1012 struct smc_softc *sc; 1013 1014 sc = device_get_softc(dev); 1015 1016 SMC_LOCK(sc); 1017 1018 smc_select_bank(sc, 3); 1019 1020 mii_bitbang_writereg(dev, &smc_mii_bitbang_ops, phy, reg, data); 1021 1022 SMC_UNLOCK(sc); 1023 return (0); 1024 } 1025 1026 void 1027 smc_miibus_statchg(device_t dev) 1028 { 1029 struct smc_softc *sc; 1030 struct mii_data *mii; 1031 uint16_t tcr; 1032 1033 sc = device_get_softc(dev); 1034 mii = device_get_softc(sc->smc_miibus); 1035 1036 SMC_LOCK(sc); 1037 1038 smc_select_bank(sc, 0); 1039 tcr = smc_read_2(sc, TCR); 1040 1041 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 1042 tcr |= TCR_SWFDUP; 1043 else 1044 tcr &= ~TCR_SWFDUP; 1045 1046 smc_write_2(sc, TCR, tcr); 1047 1048 SMC_UNLOCK(sc); 1049 } 1050 1051 static int 1052 smc_mii_ifmedia_upd(struct ifnet *ifp) 1053 { 1054 struct smc_softc *sc; 1055 struct mii_data *mii; 1056 1057 sc = ifp->if_softc; 1058 if (sc->smc_miibus == NULL) 1059 return (ENXIO); 1060 1061 mii = device_get_softc(sc->smc_miibus); 1062 return (mii_mediachg(mii)); 1063 } 1064 1065 static void 1066 smc_mii_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1067 { 1068 struct smc_softc *sc; 1069 struct mii_data *mii; 1070 1071 sc = ifp->if_softc; 1072 if (sc->smc_miibus == NULL) 1073 return; 1074 1075 mii = device_get_softc(sc->smc_miibus); 1076 mii_pollstat(mii); 1077 ifmr->ifm_active = mii->mii_media_active; 1078 ifmr->ifm_status = mii->mii_media_status; 1079 } 1080 1081 static void 1082 smc_mii_tick(void *context) 1083 { 1084 struct smc_softc *sc; 1085 1086 sc = (struct smc_softc *)context; 1087 1088 if (sc->smc_miibus == NULL) 1089 return; 1090 1091 SMC_UNLOCK(sc); 1092 1093 mii_tick(device_get_softc(sc->smc_miibus)); 1094 callout_reset(&sc->smc_mii_tick_ch, hz, smc_mii_tick, sc); 1095 } 1096 1097 static void 1098 smc_mii_mediachg(struct smc_softc *sc) 1099 { 1100 1101 if (sc->smc_miibus == NULL) 1102 return; 1103 mii_mediachg(device_get_softc(sc->smc_miibus)); 1104 } 1105 1106 static int 1107 smc_mii_mediaioctl(struct smc_softc *sc, struct ifreq *ifr, u_long command) 1108 { 1109 struct mii_data *mii; 1110 1111 if (sc->smc_miibus == NULL) 1112 return (EINVAL); 1113 1114 mii = device_get_softc(sc->smc_miibus); 1115 return (ifmedia_ioctl(sc->smc_ifp, ifr, &mii->mii_media, command)); 1116 } 1117 1118 static void 1119 smc_reset(struct smc_softc *sc) 1120 { 1121 u_int ctr; 1122 1123 SMC_ASSERT_LOCKED(sc); 1124 1125 smc_select_bank(sc, 2); 1126 1127 /* 1128 * Mask all interrupts. 1129 */ 1130 smc_write_1(sc, MSK, 0); 1131 1132 /* 1133 * Tell the device to reset. 1134 */ 1135 smc_select_bank(sc, 0); 1136 smc_write_2(sc, RCR, RCR_SOFT_RST); 1137 1138 /* 1139 * Set up the configuration register. 1140 */ 1141 smc_select_bank(sc, 1); 1142 smc_write_2(sc, CR, CR_EPH_POWER_EN); 1143 DELAY(1); 1144 1145 /* 1146 * Turn off transmit and receive. 1147 */ 1148 smc_select_bank(sc, 0); 1149 smc_write_2(sc, TCR, 0); 1150 smc_write_2(sc, RCR, 0); 1151 1152 /* 1153 * Set up the control register. 1154 */ 1155 smc_select_bank(sc, 1); 1156 ctr = smc_read_2(sc, CTR); 1157 ctr |= CTR_LE_ENABLE | CTR_AUTO_RELEASE; 1158 smc_write_2(sc, CTR, ctr); 1159 1160 /* 1161 * Reset the MMU. 1162 */ 1163 smc_select_bank(sc, 2); 1164 smc_mmu_wait(sc); 1165 smc_write_2(sc, MMUCR, MMUCR_CMD_MMU_RESET); 1166 } 1167 1168 static void 1169 smc_enable(struct smc_softc *sc) 1170 { 1171 struct ifnet *ifp; 1172 1173 SMC_ASSERT_LOCKED(sc); 1174 ifp = sc->smc_ifp; 1175 1176 /* 1177 * Set up the receive/PHY control register. 1178 */ 1179 smc_select_bank(sc, 0); 1180 smc_write_2(sc, RPCR, RPCR_ANEG | (RPCR_LED_LINK_ANY << RPCR_LSA_SHIFT) 1181 | (RPCR_LED_ACT_ANY << RPCR_LSB_SHIFT)); 1182 1183 /* 1184 * Set up the transmit and receive control registers. 1185 */ 1186 smc_write_2(sc, TCR, TCR_TXENA | TCR_PAD_EN); 1187 smc_write_2(sc, RCR, RCR_RXEN | RCR_STRIP_CRC); 1188 1189 /* 1190 * Set up the interrupt mask. 1191 */ 1192 smc_select_bank(sc, 2); 1193 sc->smc_mask = EPH_INT | RX_OVRN_INT | RCV_INT | TX_INT; 1194 if ((ifp->if_capenable & IFCAP_POLLING) != 0) 1195 smc_write_1(sc, MSK, sc->smc_mask); 1196 } 1197 1198 static void 1199 smc_stop(struct smc_softc *sc) 1200 { 1201 1202 SMC_ASSERT_LOCKED(sc); 1203 1204 /* 1205 * Turn off callouts. 1206 */ 1207 callout_stop(&sc->smc_watchdog); 1208 callout_stop(&sc->smc_mii_tick_ch); 1209 1210 /* 1211 * Mask all interrupts. 1212 */ 1213 smc_select_bank(sc, 2); 1214 sc->smc_mask = 0; 1215 smc_write_1(sc, MSK, 0); 1216 #ifdef DEVICE_POLLING 1217 ether_poll_deregister(sc->smc_ifp); 1218 sc->smc_ifp->if_capenable &= ~IFCAP_POLLING; 1219 #endif 1220 1221 /* 1222 * Disable transmit and receive. 1223 */ 1224 smc_select_bank(sc, 0); 1225 smc_write_2(sc, TCR, 0); 1226 smc_write_2(sc, RCR, 0); 1227 1228 sc->smc_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1229 } 1230 1231 static void 1232 smc_watchdog(void *arg) 1233 { 1234 struct smc_softc *sc; 1235 1236 sc = (struct smc_softc *)arg; 1237 device_printf(sc->smc_dev, "watchdog timeout\n"); 1238 taskqueue_enqueue(sc->smc_tq, &sc->smc_intr); 1239 } 1240 1241 static void 1242 smc_init(void *context) 1243 { 1244 struct smc_softc *sc; 1245 1246 sc = (struct smc_softc *)context; 1247 SMC_LOCK(sc); 1248 smc_init_locked(sc); 1249 SMC_UNLOCK(sc); 1250 } 1251 1252 static void 1253 smc_init_locked(struct smc_softc *sc) 1254 { 1255 struct ifnet *ifp; 1256 1257 SMC_ASSERT_LOCKED(sc); 1258 ifp = sc->smc_ifp; 1259 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1260 return; 1261 1262 smc_reset(sc); 1263 smc_enable(sc); 1264 1265 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1266 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1267 1268 smc_start_locked(ifp); 1269 1270 if (sc->smc_mii_tick != NULL) 1271 callout_reset(&sc->smc_mii_tick_ch, hz, sc->smc_mii_tick, sc); 1272 1273 #ifdef DEVICE_POLLING 1274 SMC_UNLOCK(sc); 1275 ether_poll_register(smc_poll, ifp); 1276 SMC_LOCK(sc); 1277 ifp->if_capenable |= IFCAP_POLLING; 1278 #endif 1279 } 1280 1281 static int 1282 smc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1283 { 1284 struct smc_softc *sc; 1285 int error; 1286 1287 sc = ifp->if_softc; 1288 error = 0; 1289 1290 switch (cmd) { 1291 case SIOCSIFFLAGS: 1292 if ((ifp->if_flags & IFF_UP) == 0 && 1293 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1294 SMC_LOCK(sc); 1295 smc_stop(sc); 1296 SMC_UNLOCK(sc); 1297 } else { 1298 smc_init(sc); 1299 if (sc->smc_mii_mediachg != NULL) 1300 sc->smc_mii_mediachg(sc); 1301 } 1302 break; 1303 1304 case SIOCADDMULTI: 1305 case SIOCDELMULTI: 1306 /* XXX 1307 SMC_LOCK(sc); 1308 smc_setmcast(sc); 1309 SMC_UNLOCK(sc); 1310 */ 1311 error = EINVAL; 1312 break; 1313 1314 case SIOCGIFMEDIA: 1315 case SIOCSIFMEDIA: 1316 if (sc->smc_mii_mediaioctl == NULL) { 1317 error = EINVAL; 1318 break; 1319 } 1320 sc->smc_mii_mediaioctl(sc, (struct ifreq *)data, cmd); 1321 break; 1322 1323 default: 1324 error = ether_ioctl(ifp, cmd, data); 1325 break; 1326 } 1327 1328 return (error); 1329 } 1330