1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2008 Benno Rice. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 /* 29 * Driver for SMSC LAN91C111, may work for older variants. 30 */ 31 32 #ifdef HAVE_KERNEL_OPTION_HEADERS 33 #include "opt_device_polling.h" 34 #endif 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/errno.h> 39 #include <sys/kernel.h> 40 #include <sys/sockio.h> 41 #include <sys/malloc.h> 42 #include <sys/mbuf.h> 43 #include <sys/queue.h> 44 #include <sys/socket.h> 45 #include <sys/syslog.h> 46 #include <sys/taskqueue.h> 47 48 #include <sys/module.h> 49 #include <sys/bus.h> 50 51 #include <machine/bus.h> 52 #include <machine/resource.h> 53 #include <sys/rman.h> 54 55 #include <net/ethernet.h> 56 #include <net/if.h> 57 #include <net/if_var.h> 58 #include <net/if_arp.h> 59 #include <net/if_dl.h> 60 #include <net/if_types.h> 61 #include <net/if_mib.h> 62 #include <net/if_media.h> 63 64 #ifdef INET 65 #include <netinet/in.h> 66 #include <netinet/in_systm.h> 67 #include <netinet/in_var.h> 68 #include <netinet/ip.h> 69 #endif 70 71 #include <net/bpf.h> 72 #include <net/bpfdesc.h> 73 74 #include <dev/smc/if_smcreg.h> 75 #include <dev/smc/if_smcvar.h> 76 77 #include <dev/mii/mii.h> 78 #include <dev/mii/mii_bitbang.h> 79 #include <dev/mii/miivar.h> 80 81 #include "miibus_if.h" 82 83 #define SMC_LOCK(sc) mtx_lock(&(sc)->smc_mtx) 84 #define SMC_UNLOCK(sc) mtx_unlock(&(sc)->smc_mtx) 85 #define SMC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->smc_mtx, MA_OWNED) 86 87 #define SMC_INTR_PRIORITY 0 88 #define SMC_RX_PRIORITY 5 89 #define SMC_TX_PRIORITY 10 90 91 static const char *smc_chip_ids[16] = { 92 NULL, NULL, NULL, 93 /* 3 */ "SMSC LAN91C90 or LAN91C92", 94 /* 4 */ "SMSC LAN91C94", 95 /* 5 */ "SMSC LAN91C95", 96 /* 6 */ "SMSC LAN91C96", 97 /* 7 */ "SMSC LAN91C100", 98 /* 8 */ "SMSC LAN91C100FD", 99 /* 9 */ "SMSC LAN91C110FD or LAN91C111FD", 100 NULL, NULL, NULL, 101 NULL, NULL, NULL 102 }; 103 104 static void smc_init(void *); 105 static void smc_start(if_t); 106 static void smc_stop(struct smc_softc *); 107 static int smc_ioctl(if_t, u_long, caddr_t); 108 109 static void smc_init_locked(struct smc_softc *); 110 static void smc_start_locked(if_t); 111 static void smc_reset(struct smc_softc *); 112 static int smc_mii_ifmedia_upd(if_t); 113 static void smc_mii_ifmedia_sts(if_t, struct ifmediareq *); 114 static void smc_mii_tick(void *); 115 static void smc_mii_mediachg(struct smc_softc *); 116 static int smc_mii_mediaioctl(struct smc_softc *, struct ifreq *, u_long); 117 118 static void smc_task_intr(void *, int); 119 static void smc_task_rx(void *, int); 120 static void smc_task_tx(void *, int); 121 122 static driver_filter_t smc_intr; 123 static callout_func_t smc_watchdog; 124 #ifdef DEVICE_POLLING 125 static poll_handler_t smc_poll; 126 #endif 127 128 /* 129 * MII bit-bang glue 130 */ 131 static uint32_t smc_mii_bitbang_read(device_t); 132 static void smc_mii_bitbang_write(device_t, uint32_t); 133 134 static const struct mii_bitbang_ops smc_mii_bitbang_ops = { 135 smc_mii_bitbang_read, 136 smc_mii_bitbang_write, 137 { 138 MGMT_MDO, /* MII_BIT_MDO */ 139 MGMT_MDI, /* MII_BIT_MDI */ 140 MGMT_MCLK, /* MII_BIT_MDC */ 141 MGMT_MDOE, /* MII_BIT_DIR_HOST_PHY */ 142 0, /* MII_BIT_DIR_PHY_HOST */ 143 } 144 }; 145 146 static __inline void 147 smc_select_bank(struct smc_softc *sc, uint16_t bank) 148 { 149 150 bus_barrier(sc->smc_reg, BSR, 2, 151 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 152 bus_write_2(sc->smc_reg, BSR, bank & BSR_BANK_MASK); 153 bus_barrier(sc->smc_reg, BSR, 2, 154 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 155 } 156 157 /* Never call this when not in bank 2. */ 158 static __inline void 159 smc_mmu_wait(struct smc_softc *sc) 160 { 161 162 KASSERT((bus_read_2(sc->smc_reg, BSR) & 163 BSR_BANK_MASK) == 2, ("%s: smc_mmu_wait called when not in bank 2", 164 device_get_nameunit(sc->smc_dev))); 165 while (bus_read_2(sc->smc_reg, MMUCR) & MMUCR_BUSY) 166 ; 167 } 168 169 static __inline uint8_t 170 smc_read_1(struct smc_softc *sc, bus_size_t offset) 171 { 172 173 return (bus_read_1(sc->smc_reg, offset)); 174 } 175 176 static __inline void 177 smc_write_1(struct smc_softc *sc, bus_size_t offset, uint8_t val) 178 { 179 180 bus_write_1(sc->smc_reg, offset, val); 181 } 182 183 static __inline uint16_t 184 smc_read_2(struct smc_softc *sc, bus_size_t offset) 185 { 186 187 return (bus_read_2(sc->smc_reg, offset)); 188 } 189 190 static __inline void 191 smc_write_2(struct smc_softc *sc, bus_size_t offset, uint16_t val) 192 { 193 194 bus_write_2(sc->smc_reg, offset, val); 195 } 196 197 static __inline void 198 smc_read_multi_2(struct smc_softc *sc, bus_size_t offset, uint16_t *datap, 199 bus_size_t count) 200 { 201 202 bus_read_multi_2(sc->smc_reg, offset, datap, count); 203 } 204 205 static __inline void 206 smc_write_multi_2(struct smc_softc *sc, bus_size_t offset, uint16_t *datap, 207 bus_size_t count) 208 { 209 210 bus_write_multi_2(sc->smc_reg, offset, datap, count); 211 } 212 213 static __inline void 214 smc_barrier(struct smc_softc *sc, bus_size_t offset, bus_size_t length, 215 int flags) 216 { 217 218 bus_barrier(sc->smc_reg, offset, length, flags); 219 } 220 221 int 222 smc_probe(device_t dev) 223 { 224 int rid, type, error; 225 uint16_t val; 226 struct smc_softc *sc; 227 struct resource *reg; 228 229 sc = device_get_softc(dev); 230 rid = 0; 231 type = SYS_RES_IOPORT; 232 error = 0; 233 234 if (sc->smc_usemem) 235 type = SYS_RES_MEMORY; 236 237 reg = bus_alloc_resource_anywhere(dev, type, &rid, 16, RF_ACTIVE); 238 if (reg == NULL) { 239 if (bootverbose) 240 device_printf(dev, 241 "could not allocate I/O resource for probe\n"); 242 return (ENXIO); 243 } 244 245 /* Check for the identification value in the BSR. */ 246 val = bus_read_2(reg, BSR); 247 if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) { 248 if (bootverbose) 249 device_printf(dev, "identification value not in BSR\n"); 250 error = ENXIO; 251 goto done; 252 } 253 254 /* 255 * Try switching banks and make sure we still get the identification 256 * value. 257 */ 258 bus_write_2(reg, BSR, 0); 259 val = bus_read_2(reg, BSR); 260 if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) { 261 if (bootverbose) 262 device_printf(dev, 263 "identification value not in BSR after write\n"); 264 error = ENXIO; 265 goto done; 266 } 267 268 #if 0 269 /* Check the BAR. */ 270 bus_write_2(reg, BSR, 1); 271 val = bus_read_2(reg, BAR); 272 val = BAR_ADDRESS(val); 273 if (rman_get_start(reg) != val) { 274 if (bootverbose) 275 device_printf(dev, "BAR address %x does not match " 276 "I/O resource address %lx\n", val, 277 rman_get_start(reg)); 278 error = ENXIO; 279 goto done; 280 } 281 #endif 282 283 /* Compare REV against known chip revisions. */ 284 bus_write_2(reg, BSR, 3); 285 val = bus_read_2(reg, REV); 286 val = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT; 287 if (smc_chip_ids[val] == NULL) { 288 if (bootverbose) 289 device_printf(dev, "Unknown chip revision: %d\n", val); 290 error = ENXIO; 291 goto done; 292 } 293 294 device_set_desc(dev, smc_chip_ids[val]); 295 296 done: 297 bus_release_resource(dev, type, rid, reg); 298 return (error); 299 } 300 301 int 302 smc_attach(device_t dev) 303 { 304 int type, error; 305 uint16_t val; 306 u_char eaddr[ETHER_ADDR_LEN]; 307 struct smc_softc *sc; 308 if_t ifp; 309 310 sc = device_get_softc(dev); 311 error = 0; 312 313 sc->smc_dev = dev; 314 315 ifp = sc->smc_ifp = if_alloc(IFT_ETHER); 316 if (ifp == NULL) { 317 error = ENOSPC; 318 goto done; 319 } 320 321 mtx_init(&sc->smc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 322 323 /* Set up watchdog callout. */ 324 callout_init_mtx(&sc->smc_watchdog, &sc->smc_mtx, 0); 325 326 type = SYS_RES_IOPORT; 327 if (sc->smc_usemem) 328 type = SYS_RES_MEMORY; 329 330 sc->smc_reg_rid = 0; 331 sc->smc_reg = bus_alloc_resource_anywhere(dev, type, &sc->smc_reg_rid, 332 16, RF_ACTIVE); 333 if (sc->smc_reg == NULL) { 334 error = ENXIO; 335 goto done; 336 } 337 338 sc->smc_irq = bus_alloc_resource_anywhere(dev, SYS_RES_IRQ, 339 &sc->smc_irq_rid, 1, RF_ACTIVE | RF_SHAREABLE); 340 if (sc->smc_irq == NULL) { 341 error = ENXIO; 342 goto done; 343 } 344 345 SMC_LOCK(sc); 346 smc_reset(sc); 347 SMC_UNLOCK(sc); 348 349 smc_select_bank(sc, 3); 350 val = smc_read_2(sc, REV); 351 sc->smc_chip = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT; 352 sc->smc_rev = (val * REV_REV_MASK) >> REV_REV_SHIFT; 353 if (bootverbose) 354 device_printf(dev, "revision %x\n", sc->smc_rev); 355 356 callout_init_mtx(&sc->smc_mii_tick_ch, &sc->smc_mtx, 357 CALLOUT_RETURNUNLOCKED); 358 if (sc->smc_chip >= REV_CHIP_91110FD) { 359 (void)mii_attach(dev, &sc->smc_miibus, ifp, 360 smc_mii_ifmedia_upd, smc_mii_ifmedia_sts, BMSR_DEFCAPMASK, 361 MII_PHY_ANY, MII_OFFSET_ANY, 0); 362 if (sc->smc_miibus != NULL) { 363 sc->smc_mii_tick = smc_mii_tick; 364 sc->smc_mii_mediachg = smc_mii_mediachg; 365 sc->smc_mii_mediaioctl = smc_mii_mediaioctl; 366 } 367 } 368 369 smc_select_bank(sc, 1); 370 eaddr[0] = smc_read_1(sc, IAR0); 371 eaddr[1] = smc_read_1(sc, IAR1); 372 eaddr[2] = smc_read_1(sc, IAR2); 373 eaddr[3] = smc_read_1(sc, IAR3); 374 eaddr[4] = smc_read_1(sc, IAR4); 375 eaddr[5] = smc_read_1(sc, IAR5); 376 377 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 378 if_setsoftc(ifp, sc); 379 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 380 if_setinitfn(ifp, smc_init); 381 if_setioctlfn(ifp, smc_ioctl); 382 if_setstartfn(ifp, smc_start); 383 if_setsendqlen(ifp, ifqmaxlen); 384 if_setsendqready(ifp); 385 386 if_setcapabilities(ifp, if_getcapenable(ifp) ); 387 388 #ifdef DEVICE_POLLING 389 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0); 390 #endif 391 392 ether_ifattach(ifp, eaddr); 393 394 /* Set up taskqueue */ 395 TASK_INIT(&sc->smc_intr, SMC_INTR_PRIORITY, smc_task_intr, ifp); 396 NET_TASK_INIT(&sc->smc_rx, SMC_RX_PRIORITY, smc_task_rx, ifp); 397 TASK_INIT(&sc->smc_tx, SMC_TX_PRIORITY, smc_task_tx, ifp); 398 sc->smc_tq = taskqueue_create_fast("smc_taskq", M_NOWAIT, 399 taskqueue_thread_enqueue, &sc->smc_tq); 400 taskqueue_start_threads(&sc->smc_tq, 1, PI_NET, "%s taskq", 401 device_get_nameunit(sc->smc_dev)); 402 403 /* Mask all interrupts. */ 404 sc->smc_mask = 0; 405 smc_write_1(sc, MSK, 0); 406 407 /* Wire up interrupt */ 408 error = bus_setup_intr(dev, sc->smc_irq, 409 INTR_TYPE_NET|INTR_MPSAFE, smc_intr, NULL, sc, &sc->smc_ih); 410 if (error != 0) 411 goto done; 412 413 done: 414 if (error != 0) 415 smc_detach(dev); 416 return (error); 417 } 418 419 int 420 smc_detach(device_t dev) 421 { 422 int type; 423 struct smc_softc *sc; 424 425 sc = device_get_softc(dev); 426 SMC_LOCK(sc); 427 smc_stop(sc); 428 SMC_UNLOCK(sc); 429 430 if (sc->smc_ifp != NULL) { 431 ether_ifdetach(sc->smc_ifp); 432 } 433 434 callout_drain(&sc->smc_watchdog); 435 callout_drain(&sc->smc_mii_tick_ch); 436 437 #ifdef DEVICE_POLLING 438 if (sc->smc_if_getcapenable(ifp) & IFCAP_POLLING) 439 ether_poll_deregister(sc->smc_ifp); 440 #endif 441 442 if (sc->smc_ih != NULL) 443 bus_teardown_intr(sc->smc_dev, sc->smc_irq, sc->smc_ih); 444 445 if (sc->smc_tq != NULL) { 446 taskqueue_drain(sc->smc_tq, &sc->smc_intr); 447 taskqueue_drain(sc->smc_tq, &sc->smc_rx); 448 taskqueue_drain(sc->smc_tq, &sc->smc_tx); 449 taskqueue_free(sc->smc_tq); 450 sc->smc_tq = NULL; 451 } 452 453 if (sc->smc_ifp != NULL) { 454 if_free(sc->smc_ifp); 455 } 456 457 if (sc->smc_miibus != NULL) { 458 device_delete_child(sc->smc_dev, sc->smc_miibus); 459 bus_generic_detach(sc->smc_dev); 460 } 461 462 if (sc->smc_reg != NULL) { 463 type = SYS_RES_IOPORT; 464 if (sc->smc_usemem) 465 type = SYS_RES_MEMORY; 466 467 bus_release_resource(sc->smc_dev, type, sc->smc_reg_rid, 468 sc->smc_reg); 469 } 470 471 if (sc->smc_irq != NULL) 472 bus_release_resource(sc->smc_dev, SYS_RES_IRQ, sc->smc_irq_rid, 473 sc->smc_irq); 474 475 if (mtx_initialized(&sc->smc_mtx)) 476 mtx_destroy(&sc->smc_mtx); 477 478 return (0); 479 } 480 481 static device_method_t smc_methods[] = { 482 /* Device interface */ 483 DEVMETHOD(device_attach, smc_attach), 484 DEVMETHOD(device_detach, smc_detach), 485 486 /* MII interface */ 487 DEVMETHOD(miibus_readreg, smc_miibus_readreg), 488 DEVMETHOD(miibus_writereg, smc_miibus_writereg), 489 DEVMETHOD(miibus_statchg, smc_miibus_statchg), 490 { 0, 0 } 491 }; 492 493 driver_t smc_driver = { 494 "smc", 495 smc_methods, 496 sizeof(struct smc_softc), 497 }; 498 499 DRIVER_MODULE(miibus, smc, miibus_driver, 0, 0); 500 501 static void 502 smc_start(if_t ifp) 503 { 504 struct smc_softc *sc; 505 506 sc = if_getsoftc(ifp); 507 SMC_LOCK(sc); 508 smc_start_locked(ifp); 509 SMC_UNLOCK(sc); 510 } 511 512 static void 513 smc_start_locked(if_t ifp) 514 { 515 struct smc_softc *sc; 516 struct mbuf *m; 517 u_int len, npages, spin_count; 518 519 sc = if_getsoftc(ifp); 520 SMC_ASSERT_LOCKED(sc); 521 522 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 523 return; 524 if (if_sendq_empty(ifp)) 525 return; 526 527 /* 528 * Grab the next packet. If it's too big, drop it. 529 */ 530 m = if_dequeue(ifp); 531 len = m_length(m, NULL); 532 len += (len & 1); 533 if (len > ETHER_MAX_LEN - ETHER_CRC_LEN) { 534 if_printf(ifp, "large packet discarded\n"); 535 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 536 m_freem(m); 537 return; /* XXX readcheck? */ 538 } 539 540 /* 541 * Flag that we're busy. 542 */ 543 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 544 sc->smc_pending = m; 545 546 /* 547 * Work out how many 256 byte "pages" we need. We have to include the 548 * control data for the packet in this calculation. 549 */ 550 npages = (len + PKT_CTRL_DATA_LEN) >> 8; 551 if (npages == 0) 552 npages = 1; 553 554 /* 555 * Request memory. 556 */ 557 smc_select_bank(sc, 2); 558 smc_mmu_wait(sc); 559 smc_write_2(sc, MMUCR, MMUCR_CMD_TX_ALLOC | npages); 560 561 /* 562 * Spin briefly to see if the allocation succeeds. 563 */ 564 spin_count = TX_ALLOC_WAIT_TIME; 565 do { 566 if (smc_read_1(sc, IST) & ALLOC_INT) { 567 smc_write_1(sc, ACK, ALLOC_INT); 568 break; 569 } 570 } while (--spin_count); 571 572 /* 573 * If the allocation is taking too long, unmask the alloc interrupt 574 * and wait. 575 */ 576 if (spin_count == 0) { 577 sc->smc_mask |= ALLOC_INT; 578 if ((if_getcapenable(ifp) & IFCAP_POLLING) == 0) 579 smc_write_1(sc, MSK, sc->smc_mask); 580 return; 581 } 582 583 taskqueue_enqueue(sc->smc_tq, &sc->smc_tx); 584 } 585 586 static void 587 smc_task_tx(void *context, int pending) 588 { 589 if_t ifp; 590 struct smc_softc *sc; 591 struct mbuf *m, *m0; 592 u_int packet, len; 593 int last_len; 594 uint8_t *data; 595 596 (void)pending; 597 ifp = (if_t)context; 598 sc = if_getsoftc(ifp); 599 600 SMC_LOCK(sc); 601 602 if (sc->smc_pending == NULL) { 603 SMC_UNLOCK(sc); 604 goto next_packet; 605 } 606 607 m = m0 = sc->smc_pending; 608 sc->smc_pending = NULL; 609 smc_select_bank(sc, 2); 610 611 /* 612 * Check the allocation result. 613 */ 614 packet = smc_read_1(sc, ARR); 615 616 /* 617 * If the allocation failed, requeue the packet and retry. 618 */ 619 if (packet & ARR_FAILED) { 620 if_sendq_prepend(ifp, m); 621 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 622 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 623 smc_start_locked(ifp); 624 SMC_UNLOCK(sc); 625 return; 626 } 627 628 /* 629 * Tell the device to write to our packet number. 630 */ 631 smc_write_1(sc, PNR, packet); 632 smc_write_2(sc, PTR, 0 | PTR_AUTO_INCR); 633 634 /* 635 * Tell the device how long the packet is (including control data). 636 */ 637 len = m_length(m, 0); 638 len += PKT_CTRL_DATA_LEN; 639 smc_write_2(sc, DATA0, 0); 640 smc_write_2(sc, DATA0, len); 641 642 /* 643 * Push the data out to the device. 644 */ 645 data = NULL; 646 last_len = 0; 647 for (; m != NULL; m = m->m_next) { 648 data = mtod(m, uint8_t *); 649 smc_write_multi_2(sc, DATA0, (uint16_t *)data, m->m_len / 2); 650 last_len = m->m_len; 651 } 652 653 /* 654 * Push out the control byte and and the odd byte if needed. 655 */ 656 if ((len & 1) != 0 && data != NULL) 657 smc_write_2(sc, DATA0, (CTRL_ODD << 8) | data[last_len - 1]); 658 else 659 smc_write_2(sc, DATA0, 0); 660 661 /* 662 * Unmask the TX empty interrupt. 663 */ 664 sc->smc_mask |= TX_EMPTY_INT; 665 if ((if_getcapenable(ifp) & IFCAP_POLLING) == 0) 666 smc_write_1(sc, MSK, sc->smc_mask); 667 668 /* 669 * Enqueue the packet. 670 */ 671 smc_mmu_wait(sc); 672 smc_write_2(sc, MMUCR, MMUCR_CMD_ENQUEUE); 673 callout_reset(&sc->smc_watchdog, hz * 2, smc_watchdog, sc); 674 675 /* 676 * Finish up. 677 */ 678 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 679 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 680 SMC_UNLOCK(sc); 681 BPF_MTAP(ifp, m0); 682 m_freem(m0); 683 684 next_packet: 685 /* 686 * See if there's anything else to do. 687 */ 688 smc_start(ifp); 689 } 690 691 static void 692 smc_task_rx(void *context, int pending) 693 { 694 u_int packet, status, len; 695 uint8_t *data; 696 if_t ifp; 697 struct smc_softc *sc; 698 struct mbuf *m, *mhead, *mtail; 699 700 (void)pending; 701 ifp = (if_t)context; 702 sc = if_getsoftc(ifp); 703 mhead = mtail = NULL; 704 705 SMC_LOCK(sc); 706 707 packet = smc_read_1(sc, FIFO_RX); 708 while ((packet & FIFO_EMPTY) == 0) { 709 /* 710 * Grab an mbuf and attach a cluster. 711 */ 712 MGETHDR(m, M_NOWAIT, MT_DATA); 713 if (m == NULL) { 714 break; 715 } 716 if (!(MCLGET(m, M_NOWAIT))) { 717 m_freem(m); 718 break; 719 } 720 721 /* 722 * Point to the start of the packet. 723 */ 724 smc_select_bank(sc, 2); 725 smc_write_1(sc, PNR, packet); 726 smc_write_2(sc, PTR, 0 | PTR_READ | PTR_RCV | PTR_AUTO_INCR); 727 728 /* 729 * Grab status and packet length. 730 */ 731 status = smc_read_2(sc, DATA0); 732 len = smc_read_2(sc, DATA0) & RX_LEN_MASK; 733 len -= 6; 734 if (status & RX_ODDFRM) 735 len += 1; 736 737 /* 738 * Check for errors. 739 */ 740 if (status & (RX_TOOSHORT | RX_TOOLNG | RX_BADCRC | RX_ALGNERR)) { 741 smc_mmu_wait(sc); 742 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE); 743 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 744 m_freem(m); 745 break; 746 } 747 748 /* 749 * Set the mbuf up the way we want it. 750 */ 751 m->m_pkthdr.rcvif = ifp; 752 m->m_pkthdr.len = m->m_len = len + 2; /* XXX: Is this right? */ 753 m_adj(m, ETHER_ALIGN); 754 755 /* 756 * Pull the packet out of the device. Make sure we're in the 757 * right bank first as things may have changed while we were 758 * allocating our mbuf. 759 */ 760 smc_select_bank(sc, 2); 761 smc_write_1(sc, PNR, packet); 762 smc_write_2(sc, PTR, 4 | PTR_READ | PTR_RCV | PTR_AUTO_INCR); 763 data = mtod(m, uint8_t *); 764 smc_read_multi_2(sc, DATA0, (uint16_t *)data, len >> 1); 765 if (len & 1) { 766 data += len & ~1; 767 *data = smc_read_1(sc, DATA0); 768 } 769 770 /* 771 * Tell the device we're done. 772 */ 773 smc_mmu_wait(sc); 774 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE); 775 if (m == NULL) { 776 break; 777 } 778 779 if (mhead == NULL) { 780 mhead = mtail = m; 781 m->m_next = NULL; 782 } else { 783 mtail->m_next = m; 784 mtail = m; 785 } 786 packet = smc_read_1(sc, FIFO_RX); 787 } 788 789 sc->smc_mask |= RCV_INT; 790 if ((if_getcapenable(ifp) & IFCAP_POLLING) == 0) 791 smc_write_1(sc, MSK, sc->smc_mask); 792 793 SMC_UNLOCK(sc); 794 795 while (mhead != NULL) { 796 m = mhead; 797 mhead = mhead->m_next; 798 m->m_next = NULL; 799 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 800 if_input(ifp, m); 801 } 802 } 803 804 #ifdef DEVICE_POLLING 805 static int 806 smc_poll(if_t ifp, enum poll_cmd cmd, int count) 807 { 808 struct smc_softc *sc; 809 810 sc = if_getsoftc(ifp); 811 812 SMC_LOCK(sc); 813 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 814 SMC_UNLOCK(sc); 815 return (0); 816 } 817 SMC_UNLOCK(sc); 818 819 if (cmd == POLL_AND_CHECK_STATUS) 820 taskqueue_enqueue(sc->smc_tq, &sc->smc_intr); 821 return (0); 822 } 823 #endif 824 825 static int 826 smc_intr(void *context) 827 { 828 struct smc_softc *sc; 829 uint32_t curbank; 830 831 sc = (struct smc_softc *)context; 832 833 /* 834 * Save current bank and restore later in this function 835 */ 836 curbank = (smc_read_2(sc, BSR) & BSR_BANK_MASK); 837 838 /* 839 * Block interrupts in order to let smc_task_intr to kick in 840 */ 841 smc_select_bank(sc, 2); 842 smc_write_1(sc, MSK, 0); 843 844 /* Restore bank */ 845 smc_select_bank(sc, curbank); 846 847 taskqueue_enqueue(sc->smc_tq, &sc->smc_intr); 848 return (FILTER_HANDLED); 849 } 850 851 static void 852 smc_task_intr(void *context, int pending) 853 { 854 struct smc_softc *sc; 855 if_t ifp; 856 u_int status, packet, counter, tcr; 857 858 (void)pending; 859 ifp = (if_t)context; 860 sc = if_getsoftc(ifp); 861 862 SMC_LOCK(sc); 863 864 smc_select_bank(sc, 2); 865 866 /* 867 * Find out what interrupts are flagged. 868 */ 869 status = smc_read_1(sc, IST) & sc->smc_mask; 870 871 /* 872 * Transmit error 873 */ 874 if (status & TX_INT) { 875 /* 876 * Kill off the packet if there is one and re-enable transmit. 877 */ 878 packet = smc_read_1(sc, FIFO_TX); 879 if ((packet & FIFO_EMPTY) == 0) { 880 callout_stop(&sc->smc_watchdog); 881 smc_select_bank(sc, 2); 882 smc_write_1(sc, PNR, packet); 883 smc_write_2(sc, PTR, 0 | PTR_READ | 884 PTR_AUTO_INCR); 885 smc_select_bank(sc, 0); 886 tcr = smc_read_2(sc, EPHSR); 887 #if 0 888 if ((tcr & EPHSR_TX_SUC) == 0) 889 device_printf(sc->smc_dev, 890 "bad packet\n"); 891 #endif 892 smc_select_bank(sc, 2); 893 smc_mmu_wait(sc); 894 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE_PKT); 895 896 smc_select_bank(sc, 0); 897 tcr = smc_read_2(sc, TCR); 898 tcr |= TCR_TXENA | TCR_PAD_EN; 899 smc_write_2(sc, TCR, tcr); 900 smc_select_bank(sc, 2); 901 taskqueue_enqueue(sc->smc_tq, &sc->smc_tx); 902 } 903 904 /* 905 * Ack the interrupt. 906 */ 907 smc_write_1(sc, ACK, TX_INT); 908 } 909 910 /* 911 * Receive 912 */ 913 if (status & RCV_INT) { 914 smc_write_1(sc, ACK, RCV_INT); 915 sc->smc_mask &= ~RCV_INT; 916 taskqueue_enqueue(sc->smc_tq, &sc->smc_rx); 917 } 918 919 /* 920 * Allocation 921 */ 922 if (status & ALLOC_INT) { 923 smc_write_1(sc, ACK, ALLOC_INT); 924 sc->smc_mask &= ~ALLOC_INT; 925 taskqueue_enqueue(sc->smc_tq, &sc->smc_tx); 926 } 927 928 /* 929 * Receive overrun 930 */ 931 if (status & RX_OVRN_INT) { 932 smc_write_1(sc, ACK, RX_OVRN_INT); 933 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 934 } 935 936 /* 937 * Transmit empty 938 */ 939 if (status & TX_EMPTY_INT) { 940 smc_write_1(sc, ACK, TX_EMPTY_INT); 941 sc->smc_mask &= ~TX_EMPTY_INT; 942 callout_stop(&sc->smc_watchdog); 943 944 /* 945 * Update collision stats. 946 */ 947 smc_select_bank(sc, 0); 948 counter = smc_read_2(sc, ECR); 949 smc_select_bank(sc, 2); 950 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 951 ((counter & ECR_SNGLCOL_MASK) >> ECR_SNGLCOL_SHIFT) + 952 ((counter & ECR_MULCOL_MASK) >> ECR_MULCOL_SHIFT)); 953 954 /* 955 * See if there are any packets to transmit. 956 */ 957 taskqueue_enqueue(sc->smc_tq, &sc->smc_tx); 958 } 959 960 /* 961 * Update the interrupt mask. 962 */ 963 smc_select_bank(sc, 2); 964 if ((if_getcapenable(ifp) & IFCAP_POLLING) == 0) 965 smc_write_1(sc, MSK, sc->smc_mask); 966 967 SMC_UNLOCK(sc); 968 } 969 970 static uint32_t 971 smc_mii_bitbang_read(device_t dev) 972 { 973 struct smc_softc *sc; 974 uint32_t val; 975 976 sc = device_get_softc(dev); 977 978 SMC_ASSERT_LOCKED(sc); 979 KASSERT((smc_read_2(sc, BSR) & BSR_BANK_MASK) == 3, 980 ("%s: smc_mii_bitbang_read called with bank %d (!= 3)", 981 device_get_nameunit(sc->smc_dev), 982 smc_read_2(sc, BSR) & BSR_BANK_MASK)); 983 984 val = smc_read_2(sc, MGMT); 985 smc_barrier(sc, MGMT, 2, 986 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 987 988 return (val); 989 } 990 991 static void 992 smc_mii_bitbang_write(device_t dev, uint32_t val) 993 { 994 struct smc_softc *sc; 995 996 sc = device_get_softc(dev); 997 998 SMC_ASSERT_LOCKED(sc); 999 KASSERT((smc_read_2(sc, BSR) & BSR_BANK_MASK) == 3, 1000 ("%s: smc_mii_bitbang_write called with bank %d (!= 3)", 1001 device_get_nameunit(sc->smc_dev), 1002 smc_read_2(sc, BSR) & BSR_BANK_MASK)); 1003 1004 smc_write_2(sc, MGMT, val); 1005 smc_barrier(sc, MGMT, 2, 1006 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1007 } 1008 1009 int 1010 smc_miibus_readreg(device_t dev, int phy, int reg) 1011 { 1012 struct smc_softc *sc; 1013 int val; 1014 1015 sc = device_get_softc(dev); 1016 1017 SMC_LOCK(sc); 1018 1019 smc_select_bank(sc, 3); 1020 1021 val = mii_bitbang_readreg(dev, &smc_mii_bitbang_ops, phy, reg); 1022 1023 SMC_UNLOCK(sc); 1024 return (val); 1025 } 1026 1027 int 1028 smc_miibus_writereg(device_t dev, int phy, int reg, int data) 1029 { 1030 struct smc_softc *sc; 1031 1032 sc = device_get_softc(dev); 1033 1034 SMC_LOCK(sc); 1035 1036 smc_select_bank(sc, 3); 1037 1038 mii_bitbang_writereg(dev, &smc_mii_bitbang_ops, phy, reg, data); 1039 1040 SMC_UNLOCK(sc); 1041 return (0); 1042 } 1043 1044 void 1045 smc_miibus_statchg(device_t dev) 1046 { 1047 struct smc_softc *sc; 1048 struct mii_data *mii; 1049 uint16_t tcr; 1050 1051 sc = device_get_softc(dev); 1052 mii = device_get_softc(sc->smc_miibus); 1053 1054 SMC_LOCK(sc); 1055 1056 smc_select_bank(sc, 0); 1057 tcr = smc_read_2(sc, TCR); 1058 1059 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 1060 tcr |= TCR_SWFDUP; 1061 else 1062 tcr &= ~TCR_SWFDUP; 1063 1064 smc_write_2(sc, TCR, tcr); 1065 1066 SMC_UNLOCK(sc); 1067 } 1068 1069 static int 1070 smc_mii_ifmedia_upd(if_t ifp) 1071 { 1072 struct smc_softc *sc; 1073 struct mii_data *mii; 1074 1075 sc = if_getsoftc(ifp); 1076 if (sc->smc_miibus == NULL) 1077 return (ENXIO); 1078 1079 mii = device_get_softc(sc->smc_miibus); 1080 return (mii_mediachg(mii)); 1081 } 1082 1083 static void 1084 smc_mii_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 1085 { 1086 struct smc_softc *sc; 1087 struct mii_data *mii; 1088 1089 sc = if_getsoftc(ifp); 1090 if (sc->smc_miibus == NULL) 1091 return; 1092 1093 mii = device_get_softc(sc->smc_miibus); 1094 mii_pollstat(mii); 1095 ifmr->ifm_active = mii->mii_media_active; 1096 ifmr->ifm_status = mii->mii_media_status; 1097 } 1098 1099 static void 1100 smc_mii_tick(void *context) 1101 { 1102 struct smc_softc *sc; 1103 1104 sc = (struct smc_softc *)context; 1105 1106 if (sc->smc_miibus == NULL) 1107 return; 1108 1109 SMC_UNLOCK(sc); 1110 1111 mii_tick(device_get_softc(sc->smc_miibus)); 1112 callout_reset(&sc->smc_mii_tick_ch, hz, smc_mii_tick, sc); 1113 } 1114 1115 static void 1116 smc_mii_mediachg(struct smc_softc *sc) 1117 { 1118 1119 if (sc->smc_miibus == NULL) 1120 return; 1121 mii_mediachg(device_get_softc(sc->smc_miibus)); 1122 } 1123 1124 static int 1125 smc_mii_mediaioctl(struct smc_softc *sc, struct ifreq *ifr, u_long command) 1126 { 1127 struct mii_data *mii; 1128 1129 if (sc->smc_miibus == NULL) 1130 return (EINVAL); 1131 1132 mii = device_get_softc(sc->smc_miibus); 1133 return (ifmedia_ioctl(sc->smc_ifp, ifr, &mii->mii_media, command)); 1134 } 1135 1136 static void 1137 smc_reset(struct smc_softc *sc) 1138 { 1139 u_int ctr; 1140 1141 SMC_ASSERT_LOCKED(sc); 1142 1143 smc_select_bank(sc, 2); 1144 1145 /* 1146 * Mask all interrupts. 1147 */ 1148 smc_write_1(sc, MSK, 0); 1149 1150 /* 1151 * Tell the device to reset. 1152 */ 1153 smc_select_bank(sc, 0); 1154 smc_write_2(sc, RCR, RCR_SOFT_RST); 1155 1156 /* 1157 * Set up the configuration register. 1158 */ 1159 smc_select_bank(sc, 1); 1160 smc_write_2(sc, CR, CR_EPH_POWER_EN); 1161 DELAY(1); 1162 1163 /* 1164 * Turn off transmit and receive. 1165 */ 1166 smc_select_bank(sc, 0); 1167 smc_write_2(sc, TCR, 0); 1168 smc_write_2(sc, RCR, 0); 1169 1170 /* 1171 * Set up the control register. 1172 */ 1173 smc_select_bank(sc, 1); 1174 ctr = smc_read_2(sc, CTRL); 1175 ctr |= CTRL_LE_ENABLE | CTRL_AUTO_RELEASE; 1176 smc_write_2(sc, CTRL, ctr); 1177 1178 /* 1179 * Reset the MMU. 1180 */ 1181 smc_select_bank(sc, 2); 1182 smc_mmu_wait(sc); 1183 smc_write_2(sc, MMUCR, MMUCR_CMD_MMU_RESET); 1184 } 1185 1186 static void 1187 smc_enable(struct smc_softc *sc) 1188 { 1189 if_t ifp; 1190 1191 SMC_ASSERT_LOCKED(sc); 1192 ifp = sc->smc_ifp; 1193 1194 /* 1195 * Set up the receive/PHY control register. 1196 */ 1197 smc_select_bank(sc, 0); 1198 smc_write_2(sc, RPCR, RPCR_ANEG | (RPCR_LED_LINK_ANY << RPCR_LSA_SHIFT) 1199 | (RPCR_LED_ACT_ANY << RPCR_LSB_SHIFT)); 1200 1201 /* 1202 * Set up the transmit and receive control registers. 1203 */ 1204 smc_write_2(sc, TCR, TCR_TXENA | TCR_PAD_EN); 1205 smc_write_2(sc, RCR, RCR_RXEN | RCR_STRIP_CRC); 1206 1207 /* 1208 * Set up the interrupt mask. 1209 */ 1210 smc_select_bank(sc, 2); 1211 sc->smc_mask = EPH_INT | RX_OVRN_INT | RCV_INT | TX_INT; 1212 if ((if_getcapenable(ifp) & IFCAP_POLLING) != 0) 1213 smc_write_1(sc, MSK, sc->smc_mask); 1214 } 1215 1216 static void 1217 smc_stop(struct smc_softc *sc) 1218 { 1219 1220 SMC_ASSERT_LOCKED(sc); 1221 1222 /* 1223 * Turn off callouts. 1224 */ 1225 callout_stop(&sc->smc_watchdog); 1226 callout_stop(&sc->smc_mii_tick_ch); 1227 1228 /* 1229 * Mask all interrupts. 1230 */ 1231 smc_select_bank(sc, 2); 1232 sc->smc_mask = 0; 1233 smc_write_1(sc, MSK, 0); 1234 #ifdef DEVICE_POLLING 1235 ether_poll_deregister(sc->smc_ifp); 1236 if_setcapenablebit(ifp, 0, IFCAP_POLLING); 1237 #endif 1238 1239 /* 1240 * Disable transmit and receive. 1241 */ 1242 smc_select_bank(sc, 0); 1243 smc_write_2(sc, TCR, 0); 1244 smc_write_2(sc, RCR, 0); 1245 1246 if_setdrvflagbits(sc->smc_ifp, 0, IFF_DRV_RUNNING); 1247 } 1248 1249 static void 1250 smc_watchdog(void *arg) 1251 { 1252 struct smc_softc *sc; 1253 1254 sc = (struct smc_softc *)arg; 1255 device_printf(sc->smc_dev, "watchdog timeout\n"); 1256 taskqueue_enqueue(sc->smc_tq, &sc->smc_intr); 1257 } 1258 1259 static void 1260 smc_init(void *context) 1261 { 1262 struct smc_softc *sc; 1263 1264 sc = (struct smc_softc *)context; 1265 SMC_LOCK(sc); 1266 smc_init_locked(sc); 1267 SMC_UNLOCK(sc); 1268 } 1269 1270 static void 1271 smc_init_locked(struct smc_softc *sc) 1272 { 1273 if_t ifp; 1274 1275 SMC_ASSERT_LOCKED(sc); 1276 ifp = sc->smc_ifp; 1277 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1278 return; 1279 1280 smc_reset(sc); 1281 smc_enable(sc); 1282 1283 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 1284 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1285 1286 smc_start_locked(ifp); 1287 1288 if (sc->smc_mii_tick != NULL) 1289 callout_reset(&sc->smc_mii_tick_ch, hz, sc->smc_mii_tick, sc); 1290 1291 #ifdef DEVICE_POLLING 1292 SMC_UNLOCK(sc); 1293 ether_poll_register(smc_poll, ifp); 1294 SMC_LOCK(sc); 1295 if_setcapenablebit(ifp, IFCAP_POLLING, 0); 1296 #endif 1297 } 1298 1299 static int 1300 smc_ioctl(if_t ifp, u_long cmd, caddr_t data) 1301 { 1302 struct smc_softc *sc; 1303 int error; 1304 1305 sc = if_getsoftc(ifp); 1306 error = 0; 1307 1308 switch (cmd) { 1309 case SIOCSIFFLAGS: 1310 if ((if_getflags(ifp) & IFF_UP) == 0 && 1311 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1312 SMC_LOCK(sc); 1313 smc_stop(sc); 1314 SMC_UNLOCK(sc); 1315 } else { 1316 smc_init(sc); 1317 if (sc->smc_mii_mediachg != NULL) 1318 sc->smc_mii_mediachg(sc); 1319 } 1320 break; 1321 1322 case SIOCADDMULTI: 1323 case SIOCDELMULTI: 1324 /* XXX 1325 SMC_LOCK(sc); 1326 smc_setmcast(sc); 1327 SMC_UNLOCK(sc); 1328 */ 1329 error = EINVAL; 1330 break; 1331 1332 case SIOCGIFMEDIA: 1333 case SIOCSIFMEDIA: 1334 if (sc->smc_mii_mediaioctl == NULL) { 1335 error = EINVAL; 1336 break; 1337 } 1338 sc->smc_mii_mediaioctl(sc, (struct ifreq *)data, cmd); 1339 break; 1340 1341 default: 1342 error = ether_ioctl(ifp, cmd, data); 1343 break; 1344 } 1345 1346 return (error); 1347 } 1348