1694c6518SBenno Rice /*- 2269a0696SBenno Rice * Copyright (c) 2008 Benno Rice. All rights reserved. 3694c6518SBenno Rice * 4694c6518SBenno Rice * Redistribution and use in source and binary forms, with or without 5694c6518SBenno Rice * modification, are permitted provided that the following conditions 6694c6518SBenno Rice * are met: 7694c6518SBenno Rice * 1. Redistributions of source code must retain the above copyright 8694c6518SBenno Rice * notice, this list of conditions and the following disclaimer. 9694c6518SBenno Rice * 2. Redistributions in binary form must reproduce the above copyright 10694c6518SBenno Rice * notice, this list of conditions and the following disclaimer in the 11694c6518SBenno Rice * documentation and/or other materials provided with the distribution. 12694c6518SBenno Rice * 13694c6518SBenno Rice * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14694c6518SBenno Rice * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15694c6518SBenno Rice * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16694c6518SBenno Rice * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17694c6518SBenno Rice * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18694c6518SBenno Rice * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19694c6518SBenno Rice * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20694c6518SBenno Rice * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21694c6518SBenno Rice * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22694c6518SBenno Rice * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23694c6518SBenno Rice */ 24694c6518SBenno Rice 25694c6518SBenno Rice #include <sys/cdefs.h> 26694c6518SBenno Rice __FBSDID("$FreeBSD$"); 27694c6518SBenno Rice 28694c6518SBenno Rice /* 29694c6518SBenno Rice * Driver for SMSC LAN91C111, may work for older variants. 30694c6518SBenno Rice */ 31694c6518SBenno Rice 32694c6518SBenno Rice #ifdef HAVE_KERNEL_OPTION_HEADERS 33694c6518SBenno Rice #include "opt_device_polling.h" 34694c6518SBenno Rice #endif 35694c6518SBenno Rice 36694c6518SBenno Rice #include <sys/param.h> 37694c6518SBenno Rice #include <sys/systm.h> 38694c6518SBenno Rice #include <sys/errno.h> 39694c6518SBenno Rice #include <sys/kernel.h> 40694c6518SBenno Rice #include <sys/sockio.h> 41694c6518SBenno Rice #include <sys/malloc.h> 42694c6518SBenno Rice #include <sys/mbuf.h> 43694c6518SBenno Rice #include <sys/queue.h> 44694c6518SBenno Rice #include <sys/socket.h> 45694c6518SBenno Rice #include <sys/syslog.h> 46694c6518SBenno Rice #include <sys/taskqueue.h> 47694c6518SBenno Rice 48694c6518SBenno Rice #include <sys/module.h> 49694c6518SBenno Rice #include <sys/bus.h> 50694c6518SBenno Rice 51694c6518SBenno Rice #include <machine/bus.h> 52694c6518SBenno Rice #include <machine/resource.h> 53694c6518SBenno Rice #include <sys/rman.h> 54694c6518SBenno Rice 55694c6518SBenno Rice #include <net/ethernet.h> 56694c6518SBenno Rice #include <net/if.h> 5776039bc8SGleb Smirnoff #include <net/if_var.h> 58694c6518SBenno Rice #include <net/if_arp.h> 59694c6518SBenno Rice #include <net/if_dl.h> 60694c6518SBenno Rice #include <net/if_types.h> 61694c6518SBenno Rice #include <net/if_mib.h> 62694c6518SBenno Rice #include <net/if_media.h> 63694c6518SBenno Rice 64694c6518SBenno Rice #ifdef INET 65694c6518SBenno Rice #include <netinet/in.h> 66694c6518SBenno Rice #include <netinet/in_systm.h> 67694c6518SBenno Rice #include <netinet/in_var.h> 68694c6518SBenno Rice #include <netinet/ip.h> 69694c6518SBenno Rice #endif 70694c6518SBenno Rice 71694c6518SBenno Rice #include <net/bpf.h> 72694c6518SBenno Rice #include <net/bpfdesc.h> 73694c6518SBenno Rice 74694c6518SBenno Rice #include <dev/smc/if_smcreg.h> 75694c6518SBenno Rice #include <dev/smc/if_smcvar.h> 76694c6518SBenno Rice 77694c6518SBenno Rice #include <dev/mii/mii.h> 788c1093fcSMarius Strobl #include <dev/mii/mii_bitbang.h> 79694c6518SBenno Rice #include <dev/mii/miivar.h> 80694c6518SBenno Rice 813c463a49SBenno Rice #define SMC_LOCK(sc) mtx_lock(&(sc)->smc_mtx) 823c463a49SBenno Rice #define SMC_UNLOCK(sc) mtx_unlock(&(sc)->smc_mtx) 833c463a49SBenno Rice #define SMC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->smc_mtx, MA_OWNED) 843c463a49SBenno Rice 853c463a49SBenno Rice #define SMC_INTR_PRIORITY 0 863c463a49SBenno Rice #define SMC_RX_PRIORITY 5 873c463a49SBenno Rice #define SMC_TX_PRIORITY 10 883c463a49SBenno Rice 89694c6518SBenno Rice devclass_t smc_devclass; 90694c6518SBenno Rice 91694c6518SBenno Rice static const char *smc_chip_ids[16] = { 92694c6518SBenno Rice NULL, NULL, NULL, 93694c6518SBenno Rice /* 3 */ "SMSC LAN91C90 or LAN91C92", 94694c6518SBenno Rice /* 4 */ "SMSC LAN91C94", 95694c6518SBenno Rice /* 5 */ "SMSC LAN91C95", 96694c6518SBenno Rice /* 6 */ "SMSC LAN91C96", 97694c6518SBenno Rice /* 7 */ "SMSC LAN91C100", 98694c6518SBenno Rice /* 8 */ "SMSC LAN91C100FD", 99694c6518SBenno Rice /* 9 */ "SMSC LAN91C110FD or LAN91C111FD", 100694c6518SBenno Rice NULL, NULL, NULL, 101694c6518SBenno Rice NULL, NULL, NULL 102694c6518SBenno Rice }; 103694c6518SBenno Rice 104694c6518SBenno Rice static void smc_init(void *); 105694c6518SBenno Rice static void smc_start(struct ifnet *); 106764e058aSBenno Rice static void smc_stop(struct smc_softc *); 107694c6518SBenno Rice static int smc_ioctl(struct ifnet *, u_long, caddr_t); 108694c6518SBenno Rice 109694c6518SBenno Rice static void smc_init_locked(struct smc_softc *); 110694c6518SBenno Rice static void smc_start_locked(struct ifnet *); 111694c6518SBenno Rice static void smc_reset(struct smc_softc *); 112694c6518SBenno Rice static int smc_mii_ifmedia_upd(struct ifnet *); 113694c6518SBenno Rice static void smc_mii_ifmedia_sts(struct ifnet *, struct ifmediareq *); 114694c6518SBenno Rice static void smc_mii_tick(void *); 115694c6518SBenno Rice static void smc_mii_mediachg(struct smc_softc *); 116694c6518SBenno Rice static int smc_mii_mediaioctl(struct smc_softc *, struct ifreq *, u_long); 117694c6518SBenno Rice 1183c463a49SBenno Rice static void smc_task_intr(void *, int); 119694c6518SBenno Rice static void smc_task_rx(void *, int); 120694c6518SBenno Rice static void smc_task_tx(void *, int); 121694c6518SBenno Rice 122694c6518SBenno Rice static driver_filter_t smc_intr; 123694c6518SBenno Rice static timeout_t smc_watchdog; 124694c6518SBenno Rice #ifdef DEVICE_POLLING 125694c6518SBenno Rice static poll_handler_t smc_poll; 126694c6518SBenno Rice #endif 127694c6518SBenno Rice 1288c1093fcSMarius Strobl /* 1298c1093fcSMarius Strobl * MII bit-bang glue 1308c1093fcSMarius Strobl */ 1318c1093fcSMarius Strobl static uint32_t smc_mii_bitbang_read(device_t); 1328c1093fcSMarius Strobl static void smc_mii_bitbang_write(device_t, uint32_t); 1338c1093fcSMarius Strobl 1348c1093fcSMarius Strobl static const struct mii_bitbang_ops smc_mii_bitbang_ops = { 1358c1093fcSMarius Strobl smc_mii_bitbang_read, 1368c1093fcSMarius Strobl smc_mii_bitbang_write, 1378c1093fcSMarius Strobl { 1388c1093fcSMarius Strobl MGMT_MDO, /* MII_BIT_MDO */ 1398c1093fcSMarius Strobl MGMT_MDI, /* MII_BIT_MDI */ 1408c1093fcSMarius Strobl MGMT_MCLK, /* MII_BIT_MDC */ 1418c1093fcSMarius Strobl MGMT_MDOE, /* MII_BIT_DIR_HOST_PHY */ 1428c1093fcSMarius Strobl 0, /* MII_BIT_DIR_PHY_HOST */ 1438c1093fcSMarius Strobl } 1448c1093fcSMarius Strobl }; 1458c1093fcSMarius Strobl 146694c6518SBenno Rice static __inline void 147694c6518SBenno Rice smc_select_bank(struct smc_softc *sc, uint16_t bank) 148694c6518SBenno Rice { 149694c6518SBenno Rice 1508c1093fcSMarius Strobl bus_barrier(sc->smc_reg, BSR, 2, 1518c1093fcSMarius Strobl BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 152269a0696SBenno Rice bus_write_2(sc->smc_reg, BSR, bank & BSR_BANK_MASK); 1538c1093fcSMarius Strobl bus_barrier(sc->smc_reg, BSR, 2, 1548c1093fcSMarius Strobl BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 155694c6518SBenno Rice } 156694c6518SBenno Rice 157694c6518SBenno Rice /* Never call this when not in bank 2. */ 158694c6518SBenno Rice static __inline void 159694c6518SBenno Rice smc_mmu_wait(struct smc_softc *sc) 160694c6518SBenno Rice { 161694c6518SBenno Rice 162269a0696SBenno Rice KASSERT((bus_read_2(sc->smc_reg, BSR) & 163694c6518SBenno Rice BSR_BANK_MASK) == 2, ("%s: smc_mmu_wait called when not in bank 2", 164694c6518SBenno Rice device_get_nameunit(sc->smc_dev))); 165269a0696SBenno Rice while (bus_read_2(sc->smc_reg, MMUCR) & MMUCR_BUSY) 166694c6518SBenno Rice ; 167694c6518SBenno Rice } 168694c6518SBenno Rice 169694c6518SBenno Rice static __inline uint8_t 1708c1093fcSMarius Strobl smc_read_1(struct smc_softc *sc, bus_size_t offset) 171694c6518SBenno Rice { 172694c6518SBenno Rice 173269a0696SBenno Rice return (bus_read_1(sc->smc_reg, offset)); 174694c6518SBenno Rice } 175694c6518SBenno Rice 176694c6518SBenno Rice static __inline void 1778c1093fcSMarius Strobl smc_write_1(struct smc_softc *sc, bus_size_t offset, uint8_t val) 178694c6518SBenno Rice { 179694c6518SBenno Rice 180269a0696SBenno Rice bus_write_1(sc->smc_reg, offset, val); 181694c6518SBenno Rice } 182694c6518SBenno Rice 183694c6518SBenno Rice static __inline uint16_t 1848c1093fcSMarius Strobl smc_read_2(struct smc_softc *sc, bus_size_t offset) 185694c6518SBenno Rice { 186694c6518SBenno Rice 187269a0696SBenno Rice return (bus_read_2(sc->smc_reg, offset)); 188694c6518SBenno Rice } 189694c6518SBenno Rice 190694c6518SBenno Rice static __inline void 1918c1093fcSMarius Strobl smc_write_2(struct smc_softc *sc, bus_size_t offset, uint16_t val) 192694c6518SBenno Rice { 193694c6518SBenno Rice 194269a0696SBenno Rice bus_write_2(sc->smc_reg, offset, val); 195694c6518SBenno Rice } 196694c6518SBenno Rice 197694c6518SBenno Rice static __inline void 1988c1093fcSMarius Strobl smc_read_multi_2(struct smc_softc *sc, bus_size_t offset, uint16_t *datap, 199694c6518SBenno Rice bus_size_t count) 200694c6518SBenno Rice { 201694c6518SBenno Rice 202269a0696SBenno Rice bus_read_multi_2(sc->smc_reg, offset, datap, count); 203694c6518SBenno Rice } 204694c6518SBenno Rice 205694c6518SBenno Rice static __inline void 2068c1093fcSMarius Strobl smc_write_multi_2(struct smc_softc *sc, bus_size_t offset, uint16_t *datap, 207694c6518SBenno Rice bus_size_t count) 208694c6518SBenno Rice { 209694c6518SBenno Rice 210269a0696SBenno Rice bus_write_multi_2(sc->smc_reg, offset, datap, count); 211694c6518SBenno Rice } 212694c6518SBenno Rice 2138c1093fcSMarius Strobl static __inline void 2148c1093fcSMarius Strobl smc_barrier(struct smc_softc *sc, bus_size_t offset, bus_size_t length, 2158c1093fcSMarius Strobl int flags) 2168c1093fcSMarius Strobl { 2178c1093fcSMarius Strobl 2188c1093fcSMarius Strobl bus_barrier(sc->smc_reg, offset, length, flags); 2198c1093fcSMarius Strobl } 2208c1093fcSMarius Strobl 221694c6518SBenno Rice int 222694c6518SBenno Rice smc_probe(device_t dev) 223694c6518SBenno Rice { 224694c6518SBenno Rice int rid, type, error; 225694c6518SBenno Rice uint16_t val; 226694c6518SBenno Rice struct smc_softc *sc; 227694c6518SBenno Rice struct resource *reg; 228694c6518SBenno Rice 229694c6518SBenno Rice sc = device_get_softc(dev); 230694c6518SBenno Rice rid = 0; 231694c6518SBenno Rice type = SYS_RES_IOPORT; 232694c6518SBenno Rice error = 0; 233694c6518SBenno Rice 234694c6518SBenno Rice if (sc->smc_usemem) 235694c6518SBenno Rice type = SYS_RES_MEMORY; 236694c6518SBenno Rice 237*c47476d7SJustin Hibbits reg = bus_alloc_resource_anywhere(dev, type, &rid, 16, RF_ACTIVE); 238694c6518SBenno Rice if (reg == NULL) { 239694c6518SBenno Rice if (bootverbose) 240694c6518SBenno Rice device_printf(dev, 241694c6518SBenno Rice "could not allocate I/O resource for probe\n"); 242694c6518SBenno Rice return (ENXIO); 243694c6518SBenno Rice } 244694c6518SBenno Rice 245694c6518SBenno Rice /* Check for the identification value in the BSR. */ 246269a0696SBenno Rice val = bus_read_2(reg, BSR); 247694c6518SBenno Rice if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) { 248694c6518SBenno Rice if (bootverbose) 249694c6518SBenno Rice device_printf(dev, "identification value not in BSR\n"); 250694c6518SBenno Rice error = ENXIO; 251694c6518SBenno Rice goto done; 252694c6518SBenno Rice } 253694c6518SBenno Rice 254694c6518SBenno Rice /* 255694c6518SBenno Rice * Try switching banks and make sure we still get the identification 256694c6518SBenno Rice * value. 257694c6518SBenno Rice */ 258269a0696SBenno Rice bus_write_2(reg, BSR, 0); 259269a0696SBenno Rice val = bus_read_2(reg, BSR); 260694c6518SBenno Rice if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) { 261694c6518SBenno Rice if (bootverbose) 262694c6518SBenno Rice device_printf(dev, 263694c6518SBenno Rice "identification value not in BSR after write\n"); 264694c6518SBenno Rice error = ENXIO; 265694c6518SBenno Rice goto done; 266694c6518SBenno Rice } 267694c6518SBenno Rice 268694c6518SBenno Rice #if 0 269694c6518SBenno Rice /* Check the BAR. */ 270269a0696SBenno Rice bus_write_2(reg, BSR, 1); 271269a0696SBenno Rice val = bus_read_2(reg, BAR); 272694c6518SBenno Rice val = BAR_ADDRESS(val); 273694c6518SBenno Rice if (rman_get_start(reg) != val) { 274694c6518SBenno Rice if (bootverbose) 275694c6518SBenno Rice device_printf(dev, "BAR address %x does not match " 276694c6518SBenno Rice "I/O resource address %lx\n", val, 277694c6518SBenno Rice rman_get_start(reg)); 278694c6518SBenno Rice error = ENXIO; 279694c6518SBenno Rice goto done; 280694c6518SBenno Rice } 281694c6518SBenno Rice #endif 282694c6518SBenno Rice 283694c6518SBenno Rice /* Compare REV against known chip revisions. */ 284269a0696SBenno Rice bus_write_2(reg, BSR, 3); 285269a0696SBenno Rice val = bus_read_2(reg, REV); 286694c6518SBenno Rice val = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT; 287694c6518SBenno Rice if (smc_chip_ids[val] == NULL) { 288694c6518SBenno Rice if (bootverbose) 289694c6518SBenno Rice device_printf(dev, "Unknown chip revision: %d\n", val); 290694c6518SBenno Rice error = ENXIO; 291694c6518SBenno Rice goto done; 292694c6518SBenno Rice } 293694c6518SBenno Rice 294694c6518SBenno Rice device_set_desc(dev, smc_chip_ids[val]); 295694c6518SBenno Rice 296694c6518SBenno Rice done: 297694c6518SBenno Rice bus_release_resource(dev, type, rid, reg); 298694c6518SBenno Rice return (error); 299694c6518SBenno Rice } 300694c6518SBenno Rice 301694c6518SBenno Rice int 302694c6518SBenno Rice smc_attach(device_t dev) 303694c6518SBenno Rice { 304694c6518SBenno Rice int type, error; 305694c6518SBenno Rice uint16_t val; 306694c6518SBenno Rice u_char eaddr[ETHER_ADDR_LEN]; 307694c6518SBenno Rice struct smc_softc *sc; 308694c6518SBenno Rice struct ifnet *ifp; 309694c6518SBenno Rice 310694c6518SBenno Rice sc = device_get_softc(dev); 311694c6518SBenno Rice error = 0; 312694c6518SBenno Rice 313694c6518SBenno Rice sc->smc_dev = dev; 314694c6518SBenno Rice 315694c6518SBenno Rice ifp = sc->smc_ifp = if_alloc(IFT_ETHER); 316694c6518SBenno Rice if (ifp == NULL) { 317694c6518SBenno Rice error = ENOSPC; 318694c6518SBenno Rice goto done; 319694c6518SBenno Rice } 320694c6518SBenno Rice 3213c463a49SBenno Rice mtx_init(&sc->smc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 322694c6518SBenno Rice 3236e482159SBenno Rice /* Set up watchdog callout. */ 3246e482159SBenno Rice callout_init_mtx(&sc->smc_watchdog, &sc->smc_mtx, 0); 3256e482159SBenno Rice 326694c6518SBenno Rice type = SYS_RES_IOPORT; 327694c6518SBenno Rice if (sc->smc_usemem) 328694c6518SBenno Rice type = SYS_RES_MEMORY; 329694c6518SBenno Rice 330694c6518SBenno Rice sc->smc_reg_rid = 0; 331*c47476d7SJustin Hibbits sc->smc_reg = bus_alloc_resource_anywhere(dev, type, &sc->smc_reg_rid, 332694c6518SBenno Rice 16, RF_ACTIVE); 333694c6518SBenno Rice if (sc->smc_reg == NULL) { 334694c6518SBenno Rice error = ENXIO; 335694c6518SBenno Rice goto done; 336694c6518SBenno Rice } 337694c6518SBenno Rice 338*c47476d7SJustin Hibbits sc->smc_irq = bus_alloc_resource_anywhere(dev, SYS_RES_IRQ, 339*c47476d7SJustin Hibbits &sc->smc_irq_rid, 1, RF_ACTIVE | RF_SHAREABLE); 340694c6518SBenno Rice if (sc->smc_irq == NULL) { 341694c6518SBenno Rice error = ENXIO; 342694c6518SBenno Rice goto done; 343694c6518SBenno Rice } 344694c6518SBenno Rice 345694c6518SBenno Rice SMC_LOCK(sc); 346694c6518SBenno Rice smc_reset(sc); 347694c6518SBenno Rice SMC_UNLOCK(sc); 348694c6518SBenno Rice 349694c6518SBenno Rice smc_select_bank(sc, 3); 350694c6518SBenno Rice val = smc_read_2(sc, REV); 351694c6518SBenno Rice sc->smc_chip = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT; 352694c6518SBenno Rice sc->smc_rev = (val * REV_REV_MASK) >> REV_REV_SHIFT; 353694c6518SBenno Rice if (bootverbose) 354694c6518SBenno Rice device_printf(dev, "revision %x\n", sc->smc_rev); 355694c6518SBenno Rice 3566e482159SBenno Rice callout_init_mtx(&sc->smc_mii_tick_ch, &sc->smc_mtx, 3576e482159SBenno Rice CALLOUT_RETURNUNLOCKED); 358694c6518SBenno Rice if (sc->smc_chip >= REV_CHIP_91110FD) { 359d6c65d27SMarius Strobl (void)mii_attach(dev, &sc->smc_miibus, ifp, 360d6c65d27SMarius Strobl smc_mii_ifmedia_upd, smc_mii_ifmedia_sts, BMSR_DEFCAPMASK, 361d6c65d27SMarius Strobl MII_PHY_ANY, MII_OFFSET_ANY, 0); 362694c6518SBenno Rice if (sc->smc_miibus != NULL) { 363694c6518SBenno Rice sc->smc_mii_tick = smc_mii_tick; 364694c6518SBenno Rice sc->smc_mii_mediachg = smc_mii_mediachg; 365694c6518SBenno Rice sc->smc_mii_mediaioctl = smc_mii_mediaioctl; 366694c6518SBenno Rice } 367694c6518SBenno Rice } 368694c6518SBenno Rice 369694c6518SBenno Rice smc_select_bank(sc, 1); 370694c6518SBenno Rice eaddr[0] = smc_read_1(sc, IAR0); 371694c6518SBenno Rice eaddr[1] = smc_read_1(sc, IAR1); 372694c6518SBenno Rice eaddr[2] = smc_read_1(sc, IAR2); 373694c6518SBenno Rice eaddr[3] = smc_read_1(sc, IAR3); 374694c6518SBenno Rice eaddr[4] = smc_read_1(sc, IAR4); 375694c6518SBenno Rice eaddr[5] = smc_read_1(sc, IAR5); 376694c6518SBenno Rice 377694c6518SBenno Rice if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 378694c6518SBenno Rice ifp->if_softc = sc; 379694c6518SBenno Rice ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 380694c6518SBenno Rice ifp->if_init = smc_init; 381694c6518SBenno Rice ifp->if_ioctl = smc_ioctl; 382694c6518SBenno Rice ifp->if_start = smc_start; 383e50d35e6SMaxim Sobolev IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 384694c6518SBenno Rice IFQ_SET_READY(&ifp->if_snd); 385694c6518SBenno Rice 386694c6518SBenno Rice ifp->if_capabilities = ifp->if_capenable = 0; 387694c6518SBenno Rice 388694c6518SBenno Rice #ifdef DEVICE_POLLING 389694c6518SBenno Rice ifp->if_capabilities |= IFCAP_POLLING; 390694c6518SBenno Rice #endif 391694c6518SBenno Rice 392694c6518SBenno Rice ether_ifattach(ifp, eaddr); 393694c6518SBenno Rice 394694c6518SBenno Rice /* Set up taskqueue */ 3953c463a49SBenno Rice TASK_INIT(&sc->smc_intr, SMC_INTR_PRIORITY, smc_task_intr, ifp); 396694c6518SBenno Rice TASK_INIT(&sc->smc_rx, SMC_RX_PRIORITY, smc_task_rx, ifp); 397694c6518SBenno Rice TASK_INIT(&sc->smc_tx, SMC_TX_PRIORITY, smc_task_tx, ifp); 398694c6518SBenno Rice sc->smc_tq = taskqueue_create_fast("smc_taskq", M_NOWAIT, 399694c6518SBenno Rice taskqueue_thread_enqueue, &sc->smc_tq); 400694c6518SBenno Rice taskqueue_start_threads(&sc->smc_tq, 1, PI_NET, "%s taskq", 401694c6518SBenno Rice device_get_nameunit(sc->smc_dev)); 402694c6518SBenno Rice 403694c6518SBenno Rice /* Mask all interrupts. */ 404694c6518SBenno Rice sc->smc_mask = 0; 405694c6518SBenno Rice smc_write_1(sc, MSK, 0); 406694c6518SBenno Rice 407694c6518SBenno Rice /* Wire up interrupt */ 408694c6518SBenno Rice error = bus_setup_intr(dev, sc->smc_irq, 4093c463a49SBenno Rice INTR_TYPE_NET|INTR_MPSAFE, smc_intr, NULL, sc, &sc->smc_ih); 410694c6518SBenno Rice if (error != 0) 411694c6518SBenno Rice goto done; 412694c6518SBenno Rice 413694c6518SBenno Rice done: 414694c6518SBenno Rice if (error != 0) 415694c6518SBenno Rice smc_detach(dev); 416694c6518SBenno Rice return (error); 417694c6518SBenno Rice } 418694c6518SBenno Rice 419694c6518SBenno Rice int 420694c6518SBenno Rice smc_detach(device_t dev) 421694c6518SBenno Rice { 422694c6518SBenno Rice int type; 423694c6518SBenno Rice struct smc_softc *sc; 424694c6518SBenno Rice 425694c6518SBenno Rice sc = device_get_softc(dev); 426764e058aSBenno Rice SMC_LOCK(sc); 427764e058aSBenno Rice smc_stop(sc); 428764e058aSBenno Rice SMC_UNLOCK(sc); 429694c6518SBenno Rice 430aec9f8e9SBenno Rice if (sc->smc_ifp != NULL) { 431aec9f8e9SBenno Rice ether_ifdetach(sc->smc_ifp); 432aec9f8e9SBenno Rice } 433aec9f8e9SBenno Rice 434aec9f8e9SBenno Rice callout_drain(&sc->smc_watchdog); 435aec9f8e9SBenno Rice callout_drain(&sc->smc_mii_tick_ch); 436aec9f8e9SBenno Rice 437694c6518SBenno Rice #ifdef DEVICE_POLLING 438694c6518SBenno Rice if (sc->smc_ifp->if_capenable & IFCAP_POLLING) 439694c6518SBenno Rice ether_poll_deregister(sc->smc_ifp); 440694c6518SBenno Rice #endif 441694c6518SBenno Rice 442694c6518SBenno Rice if (sc->smc_ih != NULL) 443694c6518SBenno Rice bus_teardown_intr(sc->smc_dev, sc->smc_irq, sc->smc_ih); 444694c6518SBenno Rice 4456e482159SBenno Rice if (sc->smc_tq != NULL) { 4466e482159SBenno Rice taskqueue_drain(sc->smc_tq, &sc->smc_intr); 4476e482159SBenno Rice taskqueue_drain(sc->smc_tq, &sc->smc_rx); 4486e482159SBenno Rice taskqueue_drain(sc->smc_tq, &sc->smc_tx); 4496e482159SBenno Rice taskqueue_free(sc->smc_tq); 4506e482159SBenno Rice sc->smc_tq = NULL; 4516e482159SBenno Rice } 4526e482159SBenno Rice 453694c6518SBenno Rice if (sc->smc_ifp != NULL) { 454694c6518SBenno Rice if_free(sc->smc_ifp); 455694c6518SBenno Rice } 456694c6518SBenno Rice 457694c6518SBenno Rice if (sc->smc_miibus != NULL) { 458694c6518SBenno Rice device_delete_child(sc->smc_dev, sc->smc_miibus); 459694c6518SBenno Rice bus_generic_detach(sc->smc_dev); 460694c6518SBenno Rice } 461694c6518SBenno Rice 462694c6518SBenno Rice if (sc->smc_reg != NULL) { 463694c6518SBenno Rice type = SYS_RES_IOPORT; 464694c6518SBenno Rice if (sc->smc_usemem) 465694c6518SBenno Rice type = SYS_RES_MEMORY; 466694c6518SBenno Rice 467694c6518SBenno Rice bus_release_resource(sc->smc_dev, type, sc->smc_reg_rid, 468694c6518SBenno Rice sc->smc_reg); 469694c6518SBenno Rice } 470694c6518SBenno Rice 471694c6518SBenno Rice if (sc->smc_irq != NULL) 472694c6518SBenno Rice bus_release_resource(sc->smc_dev, SYS_RES_IRQ, sc->smc_irq_rid, 473694c6518SBenno Rice sc->smc_irq); 474694c6518SBenno Rice 475694c6518SBenno Rice if (mtx_initialized(&sc->smc_mtx)) 476694c6518SBenno Rice mtx_destroy(&sc->smc_mtx); 477694c6518SBenno Rice 478694c6518SBenno Rice return (0); 479694c6518SBenno Rice } 480694c6518SBenno Rice 481694c6518SBenno Rice static void 482694c6518SBenno Rice smc_start(struct ifnet *ifp) 483694c6518SBenno Rice { 484694c6518SBenno Rice struct smc_softc *sc; 485694c6518SBenno Rice 486694c6518SBenno Rice sc = ifp->if_softc; 487694c6518SBenno Rice SMC_LOCK(sc); 488694c6518SBenno Rice smc_start_locked(ifp); 489694c6518SBenno Rice SMC_UNLOCK(sc); 490694c6518SBenno Rice } 491694c6518SBenno Rice 492694c6518SBenno Rice static void 493694c6518SBenno Rice smc_start_locked(struct ifnet *ifp) 494694c6518SBenno Rice { 495694c6518SBenno Rice struct smc_softc *sc; 496694c6518SBenno Rice struct mbuf *m; 497694c6518SBenno Rice u_int len, npages, spin_count; 498694c6518SBenno Rice 499694c6518SBenno Rice sc = ifp->if_softc; 500694c6518SBenno Rice SMC_ASSERT_LOCKED(sc); 501694c6518SBenno Rice 502694c6518SBenno Rice if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 503694c6518SBenno Rice return; 504694c6518SBenno Rice if (IFQ_IS_EMPTY(&ifp->if_snd)) 505694c6518SBenno Rice return; 506694c6518SBenno Rice 507694c6518SBenno Rice /* 508694c6518SBenno Rice * Grab the next packet. If it's too big, drop it. 509694c6518SBenno Rice */ 510694c6518SBenno Rice IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 511694c6518SBenno Rice len = m_length(m, NULL); 512694c6518SBenno Rice len += (len & 1); 513694c6518SBenno Rice if (len > ETHER_MAX_LEN - ETHER_CRC_LEN) { 514694c6518SBenno Rice if_printf(ifp, "large packet discarded\n"); 515c0973d1fSGleb Smirnoff if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 516694c6518SBenno Rice m_freem(m); 517694c6518SBenno Rice return; /* XXX readcheck? */ 518694c6518SBenno Rice } 519694c6518SBenno Rice 520694c6518SBenno Rice /* 521694c6518SBenno Rice * Flag that we're busy. 522694c6518SBenno Rice */ 523694c6518SBenno Rice ifp->if_drv_flags |= IFF_DRV_OACTIVE; 524694c6518SBenno Rice sc->smc_pending = m; 525694c6518SBenno Rice 526694c6518SBenno Rice /* 527694c6518SBenno Rice * Work out how many 256 byte "pages" we need. We have to include the 528694c6518SBenno Rice * control data for the packet in this calculation. 529694c6518SBenno Rice */ 53094909337SRuslan Bukin npages = (len + PKT_CTRL_DATA_LEN) >> 8; 531694c6518SBenno Rice if (npages == 0) 532694c6518SBenno Rice npages = 1; 533694c6518SBenno Rice 534694c6518SBenno Rice /* 535694c6518SBenno Rice * Request memory. 536694c6518SBenno Rice */ 537694c6518SBenno Rice smc_select_bank(sc, 2); 538694c6518SBenno Rice smc_mmu_wait(sc); 539694c6518SBenno Rice smc_write_2(sc, MMUCR, MMUCR_CMD_TX_ALLOC | npages); 540694c6518SBenno Rice 541694c6518SBenno Rice /* 542694c6518SBenno Rice * Spin briefly to see if the allocation succeeds. 543694c6518SBenno Rice */ 544694c6518SBenno Rice spin_count = TX_ALLOC_WAIT_TIME; 545694c6518SBenno Rice do { 546694c6518SBenno Rice if (smc_read_1(sc, IST) & ALLOC_INT) { 547694c6518SBenno Rice smc_write_1(sc, ACK, ALLOC_INT); 548694c6518SBenno Rice break; 549694c6518SBenno Rice } 550694c6518SBenno Rice } while (--spin_count); 551694c6518SBenno Rice 552694c6518SBenno Rice /* 553694c6518SBenno Rice * If the allocation is taking too long, unmask the alloc interrupt 554694c6518SBenno Rice * and wait. 555694c6518SBenno Rice */ 556694c6518SBenno Rice if (spin_count == 0) { 557694c6518SBenno Rice sc->smc_mask |= ALLOC_INT; 558694c6518SBenno Rice if ((ifp->if_capenable & IFCAP_POLLING) == 0) 559694c6518SBenno Rice smc_write_1(sc, MSK, sc->smc_mask); 560694c6518SBenno Rice return; 561694c6518SBenno Rice } 562694c6518SBenno Rice 563694c6518SBenno Rice taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx); 564694c6518SBenno Rice } 565694c6518SBenno Rice 566694c6518SBenno Rice static void 567694c6518SBenno Rice smc_task_tx(void *context, int pending) 568694c6518SBenno Rice { 569694c6518SBenno Rice struct ifnet *ifp; 570694c6518SBenno Rice struct smc_softc *sc; 571694c6518SBenno Rice struct mbuf *m, *m0; 572694c6518SBenno Rice u_int packet, len; 573bd2369f6SStanislav Sedov int last_len; 574694c6518SBenno Rice uint8_t *data; 575694c6518SBenno Rice 576694c6518SBenno Rice (void)pending; 577694c6518SBenno Rice ifp = (struct ifnet *)context; 578694c6518SBenno Rice sc = ifp->if_softc; 579694c6518SBenno Rice 580694c6518SBenno Rice SMC_LOCK(sc); 581694c6518SBenno Rice 582694c6518SBenno Rice if (sc->smc_pending == NULL) { 583694c6518SBenno Rice SMC_UNLOCK(sc); 584694c6518SBenno Rice goto next_packet; 585694c6518SBenno Rice } 586694c6518SBenno Rice 587694c6518SBenno Rice m = m0 = sc->smc_pending; 588694c6518SBenno Rice sc->smc_pending = NULL; 589694c6518SBenno Rice smc_select_bank(sc, 2); 590694c6518SBenno Rice 591694c6518SBenno Rice /* 592694c6518SBenno Rice * Check the allocation result. 593694c6518SBenno Rice */ 594694c6518SBenno Rice packet = smc_read_1(sc, ARR); 595694c6518SBenno Rice 596694c6518SBenno Rice /* 597694c6518SBenno Rice * If the allocation failed, requeue the packet and retry. 598694c6518SBenno Rice */ 599694c6518SBenno Rice if (packet & ARR_FAILED) { 600694c6518SBenno Rice IFQ_DRV_PREPEND(&ifp->if_snd, m); 601c0973d1fSGleb Smirnoff if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 602694c6518SBenno Rice ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 603694c6518SBenno Rice smc_start_locked(ifp); 604694c6518SBenno Rice SMC_UNLOCK(sc); 605694c6518SBenno Rice return; 606694c6518SBenno Rice } 607694c6518SBenno Rice 608694c6518SBenno Rice /* 609694c6518SBenno Rice * Tell the device to write to our packet number. 610694c6518SBenno Rice */ 611694c6518SBenno Rice smc_write_1(sc, PNR, packet); 612694c6518SBenno Rice smc_write_2(sc, PTR, 0 | PTR_AUTO_INCR); 613694c6518SBenno Rice 614694c6518SBenno Rice /* 615694c6518SBenno Rice * Tell the device how long the packet is (including control data). 616694c6518SBenno Rice */ 617694c6518SBenno Rice len = m_length(m, 0); 618694c6518SBenno Rice len += PKT_CTRL_DATA_LEN; 619694c6518SBenno Rice smc_write_2(sc, DATA0, 0); 620694c6518SBenno Rice smc_write_2(sc, DATA0, len); 621694c6518SBenno Rice 622694c6518SBenno Rice /* 623694c6518SBenno Rice * Push the data out to the device. 624694c6518SBenno Rice */ 625694c6518SBenno Rice data = NULL; 626bd2369f6SStanislav Sedov last_len = 0; 627694c6518SBenno Rice for (; m != NULL; m = m->m_next) { 628694c6518SBenno Rice data = mtod(m, uint8_t *); 629694c6518SBenno Rice smc_write_multi_2(sc, DATA0, (uint16_t *)data, m->m_len / 2); 630bd2369f6SStanislav Sedov last_len = m->m_len; 631694c6518SBenno Rice } 632694c6518SBenno Rice 633694c6518SBenno Rice /* 634694c6518SBenno Rice * Push out the control byte and and the odd byte if needed. 635694c6518SBenno Rice */ 636694c6518SBenno Rice if ((len & 1) != 0 && data != NULL) 637bd2369f6SStanislav Sedov smc_write_2(sc, DATA0, (CTRL_ODD << 8) | data[last_len - 1]); 638694c6518SBenno Rice else 639694c6518SBenno Rice smc_write_2(sc, DATA0, 0); 640694c6518SBenno Rice 641694c6518SBenno Rice /* 642694c6518SBenno Rice * Unmask the TX empty interrupt. 643694c6518SBenno Rice */ 644694c6518SBenno Rice sc->smc_mask |= TX_EMPTY_INT; 645694c6518SBenno Rice if ((ifp->if_capenable & IFCAP_POLLING) == 0) 646694c6518SBenno Rice smc_write_1(sc, MSK, sc->smc_mask); 647694c6518SBenno Rice 648694c6518SBenno Rice /* 649694c6518SBenno Rice * Enqueue the packet. 650694c6518SBenno Rice */ 651694c6518SBenno Rice smc_mmu_wait(sc); 652694c6518SBenno Rice smc_write_2(sc, MMUCR, MMUCR_CMD_ENQUEUE); 6533c463a49SBenno Rice callout_reset(&sc->smc_watchdog, hz * 2, smc_watchdog, sc); 654694c6518SBenno Rice 655694c6518SBenno Rice /* 656694c6518SBenno Rice * Finish up. 657694c6518SBenno Rice */ 658c0973d1fSGleb Smirnoff if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 659694c6518SBenno Rice ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 660694c6518SBenno Rice SMC_UNLOCK(sc); 661694c6518SBenno Rice BPF_MTAP(ifp, m0); 662694c6518SBenno Rice m_freem(m0); 663694c6518SBenno Rice 664694c6518SBenno Rice next_packet: 665694c6518SBenno Rice /* 666694c6518SBenno Rice * See if there's anything else to do. 667694c6518SBenno Rice */ 668694c6518SBenno Rice smc_start(ifp); 669694c6518SBenno Rice } 670694c6518SBenno Rice 671694c6518SBenno Rice static void 672694c6518SBenno Rice smc_task_rx(void *context, int pending) 673694c6518SBenno Rice { 674694c6518SBenno Rice u_int packet, status, len; 675694c6518SBenno Rice uint8_t *data; 676694c6518SBenno Rice struct ifnet *ifp; 677694c6518SBenno Rice struct smc_softc *sc; 678694c6518SBenno Rice struct mbuf *m, *mhead, *mtail; 679694c6518SBenno Rice 680694c6518SBenno Rice (void)pending; 681694c6518SBenno Rice ifp = (struct ifnet *)context; 682694c6518SBenno Rice sc = ifp->if_softc; 683694c6518SBenno Rice mhead = mtail = NULL; 684694c6518SBenno Rice 685694c6518SBenno Rice SMC_LOCK(sc); 686694c6518SBenno Rice 687694c6518SBenno Rice packet = smc_read_1(sc, FIFO_RX); 688694c6518SBenno Rice while ((packet & FIFO_EMPTY) == 0) { 689694c6518SBenno Rice /* 690694c6518SBenno Rice * Grab an mbuf and attach a cluster. 691694c6518SBenno Rice */ 692c6499eccSGleb Smirnoff MGETHDR(m, M_NOWAIT, MT_DATA); 693694c6518SBenno Rice if (m == NULL) { 694694c6518SBenno Rice break; 695694c6518SBenno Rice } 6962a8c860fSRobert Watson if (!(MCLGET(m, M_NOWAIT))) { 697694c6518SBenno Rice m_freem(m); 698694c6518SBenno Rice break; 699694c6518SBenno Rice } 700694c6518SBenno Rice 701694c6518SBenno Rice /* 702694c6518SBenno Rice * Point to the start of the packet. 703694c6518SBenno Rice */ 704694c6518SBenno Rice smc_select_bank(sc, 2); 705694c6518SBenno Rice smc_write_1(sc, PNR, packet); 706694c6518SBenno Rice smc_write_2(sc, PTR, 0 | PTR_READ | PTR_RCV | PTR_AUTO_INCR); 707694c6518SBenno Rice 708694c6518SBenno Rice /* 709694c6518SBenno Rice * Grab status and packet length. 710694c6518SBenno Rice */ 711694c6518SBenno Rice status = smc_read_2(sc, DATA0); 712694c6518SBenno Rice len = smc_read_2(sc, DATA0) & RX_LEN_MASK; 713694c6518SBenno Rice len -= 6; 714694c6518SBenno Rice if (status & RX_ODDFRM) 715694c6518SBenno Rice len += 1; 716694c6518SBenno Rice 717694c6518SBenno Rice /* 718694c6518SBenno Rice * Check for errors. 719694c6518SBenno Rice */ 720694c6518SBenno Rice if (status & (RX_TOOSHORT | RX_TOOLNG | RX_BADCRC | RX_ALGNERR)) { 721694c6518SBenno Rice smc_mmu_wait(sc); 722694c6518SBenno Rice smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE); 723c0973d1fSGleb Smirnoff if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 724694c6518SBenno Rice m_freem(m); 725694c6518SBenno Rice break; 726694c6518SBenno Rice } 727694c6518SBenno Rice 728694c6518SBenno Rice /* 729694c6518SBenno Rice * Set the mbuf up the way we want it. 730694c6518SBenno Rice */ 731694c6518SBenno Rice m->m_pkthdr.rcvif = ifp; 732694c6518SBenno Rice m->m_pkthdr.len = m->m_len = len + 2; /* XXX: Is this right? */ 733694c6518SBenno Rice m_adj(m, ETHER_ALIGN); 734694c6518SBenno Rice 735694c6518SBenno Rice /* 736694c6518SBenno Rice * Pull the packet out of the device. Make sure we're in the 737694c6518SBenno Rice * right bank first as things may have changed while we were 738694c6518SBenno Rice * allocating our mbuf. 739694c6518SBenno Rice */ 740694c6518SBenno Rice smc_select_bank(sc, 2); 741694c6518SBenno Rice smc_write_1(sc, PNR, packet); 742694c6518SBenno Rice smc_write_2(sc, PTR, 4 | PTR_READ | PTR_RCV | PTR_AUTO_INCR); 743694c6518SBenno Rice data = mtod(m, uint8_t *); 744694c6518SBenno Rice smc_read_multi_2(sc, DATA0, (uint16_t *)data, len >> 1); 745694c6518SBenno Rice if (len & 1) { 746694c6518SBenno Rice data += len & ~1; 747694c6518SBenno Rice *data = smc_read_1(sc, DATA0); 748694c6518SBenno Rice } 749694c6518SBenno Rice 750694c6518SBenno Rice /* 751694c6518SBenno Rice * Tell the device we're done. 752694c6518SBenno Rice */ 753694c6518SBenno Rice smc_mmu_wait(sc); 754694c6518SBenno Rice smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE); 755694c6518SBenno Rice if (m == NULL) { 756694c6518SBenno Rice break; 757694c6518SBenno Rice } 758694c6518SBenno Rice 759694c6518SBenno Rice if (mhead == NULL) { 760694c6518SBenno Rice mhead = mtail = m; 761694c6518SBenno Rice m->m_next = NULL; 762694c6518SBenno Rice } else { 763694c6518SBenno Rice mtail->m_next = m; 764694c6518SBenno Rice mtail = m; 765694c6518SBenno Rice } 766694c6518SBenno Rice packet = smc_read_1(sc, FIFO_RX); 767694c6518SBenno Rice } 768694c6518SBenno Rice 769694c6518SBenno Rice sc->smc_mask |= RCV_INT; 770694c6518SBenno Rice if ((ifp->if_capenable & IFCAP_POLLING) == 0) 771694c6518SBenno Rice smc_write_1(sc, MSK, sc->smc_mask); 772694c6518SBenno Rice 773694c6518SBenno Rice SMC_UNLOCK(sc); 774694c6518SBenno Rice 775694c6518SBenno Rice while (mhead != NULL) { 776694c6518SBenno Rice m = mhead; 777694c6518SBenno Rice mhead = mhead->m_next; 778694c6518SBenno Rice m->m_next = NULL; 779c0973d1fSGleb Smirnoff if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 780694c6518SBenno Rice (*ifp->if_input)(ifp, m); 781694c6518SBenno Rice } 782694c6518SBenno Rice } 783694c6518SBenno Rice 784694c6518SBenno Rice #ifdef DEVICE_POLLING 785694c6518SBenno Rice static void 786694c6518SBenno Rice smc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 787694c6518SBenno Rice { 788694c6518SBenno Rice struct smc_softc *sc; 789694c6518SBenno Rice 790694c6518SBenno Rice sc = ifp->if_softc; 791694c6518SBenno Rice 792694c6518SBenno Rice SMC_LOCK(sc); 793694c6518SBenno Rice if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 794694c6518SBenno Rice SMC_UNLOCK(sc); 795694c6518SBenno Rice return; 796694c6518SBenno Rice } 797694c6518SBenno Rice SMC_UNLOCK(sc); 798694c6518SBenno Rice 799694c6518SBenno Rice if (cmd == POLL_AND_CHECK_STATUS) 8003c463a49SBenno Rice taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_intr); 801694c6518SBenno Rice } 802694c6518SBenno Rice #endif 803694c6518SBenno Rice 804694c6518SBenno Rice static int 805694c6518SBenno Rice smc_intr(void *context) 806694c6518SBenno Rice { 807694c6518SBenno Rice struct smc_softc *sc; 80894909337SRuslan Bukin uint32_t curbank; 8093c463a49SBenno Rice 8103c463a49SBenno Rice sc = (struct smc_softc *)context; 81194909337SRuslan Bukin 81294909337SRuslan Bukin /* 81394909337SRuslan Bukin * Save current bank and restore later in this function 81494909337SRuslan Bukin */ 81594909337SRuslan Bukin curbank = (smc_read_2(sc, BSR) & BSR_BANK_MASK); 81694909337SRuslan Bukin 81760aa1fe6SOleksandr Tymoshenko /* 81860aa1fe6SOleksandr Tymoshenko * Block interrupts in order to let smc_task_intr to kick in 81960aa1fe6SOleksandr Tymoshenko */ 82094909337SRuslan Bukin smc_select_bank(sc, 2); 82160aa1fe6SOleksandr Tymoshenko smc_write_1(sc, MSK, 0); 82294909337SRuslan Bukin 82394909337SRuslan Bukin /* Restore bank */ 82494909337SRuslan Bukin smc_select_bank(sc, curbank); 82594909337SRuslan Bukin 8263c463a49SBenno Rice taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_intr); 8273c463a49SBenno Rice return (FILTER_HANDLED); 8283c463a49SBenno Rice } 8293c463a49SBenno Rice 8303c463a49SBenno Rice static void 8313c463a49SBenno Rice smc_task_intr(void *context, int pending) 8323c463a49SBenno Rice { 8333c463a49SBenno Rice struct smc_softc *sc; 834694c6518SBenno Rice struct ifnet *ifp; 835694c6518SBenno Rice u_int status, packet, counter, tcr; 836694c6518SBenno Rice 8373c463a49SBenno Rice (void)pending; 838694c6518SBenno Rice ifp = (struct ifnet *)context; 839694c6518SBenno Rice sc = ifp->if_softc; 840694c6518SBenno Rice 841694c6518SBenno Rice SMC_LOCK(sc); 842764e058aSBenno Rice 843694c6518SBenno Rice smc_select_bank(sc, 2); 844694c6518SBenno Rice 845694c6518SBenno Rice /* 846694c6518SBenno Rice * Find out what interrupts are flagged. 847694c6518SBenno Rice */ 848694c6518SBenno Rice status = smc_read_1(sc, IST) & sc->smc_mask; 849694c6518SBenno Rice 850694c6518SBenno Rice /* 851694c6518SBenno Rice * Transmit error 852694c6518SBenno Rice */ 853694c6518SBenno Rice if (status & TX_INT) { 854694c6518SBenno Rice /* 855694c6518SBenno Rice * Kill off the packet if there is one and re-enable transmit. 856694c6518SBenno Rice */ 857694c6518SBenno Rice packet = smc_read_1(sc, FIFO_TX); 858694c6518SBenno Rice if ((packet & FIFO_EMPTY) == 0) { 85994909337SRuslan Bukin callout_stop(&sc->smc_watchdog); 86094909337SRuslan Bukin smc_select_bank(sc, 2); 861694c6518SBenno Rice smc_write_1(sc, PNR, packet); 862694c6518SBenno Rice smc_write_2(sc, PTR, 0 | PTR_READ | 863694c6518SBenno Rice PTR_AUTO_INCR); 86494909337SRuslan Bukin smc_select_bank(sc, 0); 86594909337SRuslan Bukin tcr = smc_read_2(sc, EPHSR); 86694909337SRuslan Bukin #if 0 867694c6518SBenno Rice if ((tcr & EPHSR_TX_SUC) == 0) 868694c6518SBenno Rice device_printf(sc->smc_dev, 869694c6518SBenno Rice "bad packet\n"); 87094909337SRuslan Bukin #endif 87194909337SRuslan Bukin smc_select_bank(sc, 2); 872694c6518SBenno Rice smc_mmu_wait(sc); 873694c6518SBenno Rice smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE_PKT); 874694c6518SBenno Rice 875694c6518SBenno Rice smc_select_bank(sc, 0); 876694c6518SBenno Rice tcr = smc_read_2(sc, TCR); 877694c6518SBenno Rice tcr |= TCR_TXENA | TCR_PAD_EN; 878694c6518SBenno Rice smc_write_2(sc, TCR, tcr); 879694c6518SBenno Rice smc_select_bank(sc, 2); 880694c6518SBenno Rice taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx); 881694c6518SBenno Rice } 882694c6518SBenno Rice 883694c6518SBenno Rice /* 884694c6518SBenno Rice * Ack the interrupt. 885694c6518SBenno Rice */ 886694c6518SBenno Rice smc_write_1(sc, ACK, TX_INT); 887694c6518SBenno Rice } 888694c6518SBenno Rice 889694c6518SBenno Rice /* 890694c6518SBenno Rice * Receive 891694c6518SBenno Rice */ 892694c6518SBenno Rice if (status & RCV_INT) { 893694c6518SBenno Rice smc_write_1(sc, ACK, RCV_INT); 894694c6518SBenno Rice sc->smc_mask &= ~RCV_INT; 895694c6518SBenno Rice taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_rx); 896694c6518SBenno Rice } 897694c6518SBenno Rice 898694c6518SBenno Rice /* 899694c6518SBenno Rice * Allocation 900694c6518SBenno Rice */ 901694c6518SBenno Rice if (status & ALLOC_INT) { 902694c6518SBenno Rice smc_write_1(sc, ACK, ALLOC_INT); 903694c6518SBenno Rice sc->smc_mask &= ~ALLOC_INT; 904694c6518SBenno Rice taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx); 905694c6518SBenno Rice } 906694c6518SBenno Rice 907694c6518SBenno Rice /* 908694c6518SBenno Rice * Receive overrun 909694c6518SBenno Rice */ 910694c6518SBenno Rice if (status & RX_OVRN_INT) { 911694c6518SBenno Rice smc_write_1(sc, ACK, RX_OVRN_INT); 912c0973d1fSGleb Smirnoff if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 913694c6518SBenno Rice } 914694c6518SBenno Rice 915694c6518SBenno Rice /* 916694c6518SBenno Rice * Transmit empty 917694c6518SBenno Rice */ 918694c6518SBenno Rice if (status & TX_EMPTY_INT) { 919694c6518SBenno Rice smc_write_1(sc, ACK, TX_EMPTY_INT); 920694c6518SBenno Rice sc->smc_mask &= ~TX_EMPTY_INT; 921694c6518SBenno Rice callout_stop(&sc->smc_watchdog); 922694c6518SBenno Rice 923694c6518SBenno Rice /* 924694c6518SBenno Rice * Update collision stats. 925694c6518SBenno Rice */ 926694c6518SBenno Rice smc_select_bank(sc, 0); 927694c6518SBenno Rice counter = smc_read_2(sc, ECR); 928694c6518SBenno Rice smc_select_bank(sc, 2); 92994b0d1aeSBjoern A. Zeeb if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 930c0973d1fSGleb Smirnoff ((counter & ECR_SNGLCOL_MASK) >> ECR_SNGLCOL_SHIFT) + 931c0973d1fSGleb Smirnoff ((counter & ECR_MULCOL_MASK) >> ECR_MULCOL_SHIFT)); 932694c6518SBenno Rice 933694c6518SBenno Rice /* 934694c6518SBenno Rice * See if there are any packets to transmit. 935694c6518SBenno Rice */ 936694c6518SBenno Rice taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx); 937694c6518SBenno Rice } 938694c6518SBenno Rice 939694c6518SBenno Rice /* 940694c6518SBenno Rice * Update the interrupt mask. 941694c6518SBenno Rice */ 94294909337SRuslan Bukin smc_select_bank(sc, 2); 943694c6518SBenno Rice if ((ifp->if_capenable & IFCAP_POLLING) == 0) 944694c6518SBenno Rice smc_write_1(sc, MSK, sc->smc_mask); 945694c6518SBenno Rice 946694c6518SBenno Rice SMC_UNLOCK(sc); 947694c6518SBenno Rice } 948694c6518SBenno Rice 9498c1093fcSMarius Strobl static uint32_t 9508c1093fcSMarius Strobl smc_mii_bitbang_read(device_t dev) 951694c6518SBenno Rice { 9528c1093fcSMarius Strobl struct smc_softc *sc; 9538c1093fcSMarius Strobl uint32_t val; 9548c1093fcSMarius Strobl 9558c1093fcSMarius Strobl sc = device_get_softc(dev); 956694c6518SBenno Rice 957694c6518SBenno Rice SMC_ASSERT_LOCKED(sc); 958694c6518SBenno Rice KASSERT((smc_read_2(sc, BSR) & BSR_BANK_MASK) == 3, 9598c1093fcSMarius Strobl ("%s: smc_mii_bitbang_read called with bank %d (!= 3)", 960694c6518SBenno Rice device_get_nameunit(sc->smc_dev), 961694c6518SBenno Rice smc_read_2(sc, BSR) & BSR_BANK_MASK)); 962694c6518SBenno Rice 9638c1093fcSMarius Strobl val = smc_read_2(sc, MGMT); 9648c1093fcSMarius Strobl smc_barrier(sc, MGMT, 2, 9658c1093fcSMarius Strobl BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 966694c6518SBenno Rice 967694c6518SBenno Rice return (val); 968694c6518SBenno Rice } 969694c6518SBenno Rice 970694c6518SBenno Rice static void 9718c1093fcSMarius Strobl smc_mii_bitbang_write(device_t dev, uint32_t val) 972694c6518SBenno Rice { 9738c1093fcSMarius Strobl struct smc_softc *sc; 9748c1093fcSMarius Strobl 9758c1093fcSMarius Strobl sc = device_get_softc(dev); 976694c6518SBenno Rice 977694c6518SBenno Rice SMC_ASSERT_LOCKED(sc); 978694c6518SBenno Rice KASSERT((smc_read_2(sc, BSR) & BSR_BANK_MASK) == 3, 9798c1093fcSMarius Strobl ("%s: smc_mii_bitbang_write called with bank %d (!= 3)", 980694c6518SBenno Rice device_get_nameunit(sc->smc_dev), 981694c6518SBenno Rice smc_read_2(sc, BSR) & BSR_BANK_MASK)); 982694c6518SBenno Rice 9838c1093fcSMarius Strobl smc_write_2(sc, MGMT, val); 9848c1093fcSMarius Strobl smc_barrier(sc, MGMT, 2, 9858c1093fcSMarius Strobl BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 986694c6518SBenno Rice } 987694c6518SBenno Rice 988694c6518SBenno Rice int 989694c6518SBenno Rice smc_miibus_readreg(device_t dev, int phy, int reg) 990694c6518SBenno Rice { 991694c6518SBenno Rice struct smc_softc *sc; 992694c6518SBenno Rice int val; 993694c6518SBenno Rice 994694c6518SBenno Rice sc = device_get_softc(dev); 995694c6518SBenno Rice 996694c6518SBenno Rice SMC_LOCK(sc); 997694c6518SBenno Rice 998694c6518SBenno Rice smc_select_bank(sc, 3); 999694c6518SBenno Rice 10008c1093fcSMarius Strobl val = mii_bitbang_readreg(dev, &smc_mii_bitbang_ops, phy, reg); 1001694c6518SBenno Rice 1002694c6518SBenno Rice SMC_UNLOCK(sc); 1003694c6518SBenno Rice return (val); 1004694c6518SBenno Rice } 1005694c6518SBenno Rice 10068e45f0b7SAndriy Gapon int 1007694c6518SBenno Rice smc_miibus_writereg(device_t dev, int phy, int reg, int data) 1008694c6518SBenno Rice { 1009694c6518SBenno Rice struct smc_softc *sc; 1010694c6518SBenno Rice 1011694c6518SBenno Rice sc = device_get_softc(dev); 1012694c6518SBenno Rice 1013694c6518SBenno Rice SMC_LOCK(sc); 1014694c6518SBenno Rice 1015694c6518SBenno Rice smc_select_bank(sc, 3); 1016694c6518SBenno Rice 10178c1093fcSMarius Strobl mii_bitbang_writereg(dev, &smc_mii_bitbang_ops, phy, reg, data); 1018694c6518SBenno Rice 1019694c6518SBenno Rice SMC_UNLOCK(sc); 10208e45f0b7SAndriy Gapon return (0); 1021694c6518SBenno Rice } 1022694c6518SBenno Rice 1023694c6518SBenno Rice void 1024694c6518SBenno Rice smc_miibus_statchg(device_t dev) 1025694c6518SBenno Rice { 1026694c6518SBenno Rice struct smc_softc *sc; 1027694c6518SBenno Rice struct mii_data *mii; 1028694c6518SBenno Rice uint16_t tcr; 1029694c6518SBenno Rice 1030694c6518SBenno Rice sc = device_get_softc(dev); 1031694c6518SBenno Rice mii = device_get_softc(sc->smc_miibus); 1032694c6518SBenno Rice 1033694c6518SBenno Rice SMC_LOCK(sc); 1034694c6518SBenno Rice 1035694c6518SBenno Rice smc_select_bank(sc, 0); 1036694c6518SBenno Rice tcr = smc_read_2(sc, TCR); 1037694c6518SBenno Rice 1038694c6518SBenno Rice if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 1039694c6518SBenno Rice tcr |= TCR_SWFDUP; 1040694c6518SBenno Rice else 1041694c6518SBenno Rice tcr &= ~TCR_SWFDUP; 1042694c6518SBenno Rice 1043694c6518SBenno Rice smc_write_2(sc, TCR, tcr); 1044694c6518SBenno Rice 1045694c6518SBenno Rice SMC_UNLOCK(sc); 1046694c6518SBenno Rice } 1047694c6518SBenno Rice 1048694c6518SBenno Rice static int 1049694c6518SBenno Rice smc_mii_ifmedia_upd(struct ifnet *ifp) 1050694c6518SBenno Rice { 1051694c6518SBenno Rice struct smc_softc *sc; 1052694c6518SBenno Rice struct mii_data *mii; 1053694c6518SBenno Rice 1054694c6518SBenno Rice sc = ifp->if_softc; 1055694c6518SBenno Rice if (sc->smc_miibus == NULL) 1056694c6518SBenno Rice return (ENXIO); 1057694c6518SBenno Rice 1058694c6518SBenno Rice mii = device_get_softc(sc->smc_miibus); 1059694c6518SBenno Rice return (mii_mediachg(mii)); 1060694c6518SBenno Rice } 1061694c6518SBenno Rice 1062694c6518SBenno Rice static void 1063694c6518SBenno Rice smc_mii_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1064694c6518SBenno Rice { 1065694c6518SBenno Rice struct smc_softc *sc; 1066694c6518SBenno Rice struct mii_data *mii; 1067694c6518SBenno Rice 1068694c6518SBenno Rice sc = ifp->if_softc; 1069694c6518SBenno Rice if (sc->smc_miibus == NULL) 1070694c6518SBenno Rice return; 1071694c6518SBenno Rice 1072694c6518SBenno Rice mii = device_get_softc(sc->smc_miibus); 1073694c6518SBenno Rice mii_pollstat(mii); 1074694c6518SBenno Rice ifmr->ifm_active = mii->mii_media_active; 1075694c6518SBenno Rice ifmr->ifm_status = mii->mii_media_status; 1076694c6518SBenno Rice } 1077694c6518SBenno Rice 1078694c6518SBenno Rice static void 1079694c6518SBenno Rice smc_mii_tick(void *context) 1080694c6518SBenno Rice { 1081694c6518SBenno Rice struct smc_softc *sc; 1082694c6518SBenno Rice 1083694c6518SBenno Rice sc = (struct smc_softc *)context; 1084694c6518SBenno Rice 1085694c6518SBenno Rice if (sc->smc_miibus == NULL) 1086694c6518SBenno Rice return; 1087694c6518SBenno Rice 10886e482159SBenno Rice SMC_UNLOCK(sc); 10896e482159SBenno Rice 1090694c6518SBenno Rice mii_tick(device_get_softc(sc->smc_miibus)); 1091694c6518SBenno Rice callout_reset(&sc->smc_mii_tick_ch, hz, smc_mii_tick, sc); 1092694c6518SBenno Rice } 1093694c6518SBenno Rice 1094694c6518SBenno Rice static void 1095694c6518SBenno Rice smc_mii_mediachg(struct smc_softc *sc) 1096694c6518SBenno Rice { 1097694c6518SBenno Rice 1098694c6518SBenno Rice if (sc->smc_miibus == NULL) 1099694c6518SBenno Rice return; 1100694c6518SBenno Rice mii_mediachg(device_get_softc(sc->smc_miibus)); 1101694c6518SBenno Rice } 1102694c6518SBenno Rice 1103694c6518SBenno Rice static int 1104694c6518SBenno Rice smc_mii_mediaioctl(struct smc_softc *sc, struct ifreq *ifr, u_long command) 1105694c6518SBenno Rice { 1106694c6518SBenno Rice struct mii_data *mii; 1107694c6518SBenno Rice 1108694c6518SBenno Rice if (sc->smc_miibus == NULL) 1109694c6518SBenno Rice return (EINVAL); 1110694c6518SBenno Rice 1111694c6518SBenno Rice mii = device_get_softc(sc->smc_miibus); 1112694c6518SBenno Rice return (ifmedia_ioctl(sc->smc_ifp, ifr, &mii->mii_media, command)); 1113694c6518SBenno Rice } 1114694c6518SBenno Rice 1115694c6518SBenno Rice static void 1116694c6518SBenno Rice smc_reset(struct smc_softc *sc) 1117694c6518SBenno Rice { 1118694c6518SBenno Rice u_int ctr; 1119694c6518SBenno Rice 1120694c6518SBenno Rice SMC_ASSERT_LOCKED(sc); 1121694c6518SBenno Rice 1122694c6518SBenno Rice smc_select_bank(sc, 2); 1123694c6518SBenno Rice 1124694c6518SBenno Rice /* 1125694c6518SBenno Rice * Mask all interrupts. 1126694c6518SBenno Rice */ 1127694c6518SBenno Rice smc_write_1(sc, MSK, 0); 1128694c6518SBenno Rice 1129694c6518SBenno Rice /* 1130694c6518SBenno Rice * Tell the device to reset. 1131694c6518SBenno Rice */ 1132694c6518SBenno Rice smc_select_bank(sc, 0); 1133694c6518SBenno Rice smc_write_2(sc, RCR, RCR_SOFT_RST); 1134694c6518SBenno Rice 1135694c6518SBenno Rice /* 1136694c6518SBenno Rice * Set up the configuration register. 1137694c6518SBenno Rice */ 1138694c6518SBenno Rice smc_select_bank(sc, 1); 1139694c6518SBenno Rice smc_write_2(sc, CR, CR_EPH_POWER_EN); 1140694c6518SBenno Rice DELAY(1); 1141694c6518SBenno Rice 1142694c6518SBenno Rice /* 1143694c6518SBenno Rice * Turn off transmit and receive. 1144694c6518SBenno Rice */ 1145694c6518SBenno Rice smc_select_bank(sc, 0); 1146694c6518SBenno Rice smc_write_2(sc, TCR, 0); 1147694c6518SBenno Rice smc_write_2(sc, RCR, 0); 1148694c6518SBenno Rice 1149694c6518SBenno Rice /* 1150694c6518SBenno Rice * Set up the control register. 1151694c6518SBenno Rice */ 1152694c6518SBenno Rice smc_select_bank(sc, 1); 1153694c6518SBenno Rice ctr = smc_read_2(sc, CTR); 1154694c6518SBenno Rice ctr |= CTR_LE_ENABLE | CTR_AUTO_RELEASE; 1155694c6518SBenno Rice smc_write_2(sc, CTR, ctr); 1156694c6518SBenno Rice 1157694c6518SBenno Rice /* 1158694c6518SBenno Rice * Reset the MMU. 1159694c6518SBenno Rice */ 1160694c6518SBenno Rice smc_select_bank(sc, 2); 1161694c6518SBenno Rice smc_mmu_wait(sc); 1162694c6518SBenno Rice smc_write_2(sc, MMUCR, MMUCR_CMD_MMU_RESET); 1163694c6518SBenno Rice } 1164694c6518SBenno Rice 1165694c6518SBenno Rice static void 1166694c6518SBenno Rice smc_enable(struct smc_softc *sc) 1167694c6518SBenno Rice { 1168694c6518SBenno Rice struct ifnet *ifp; 1169694c6518SBenno Rice 1170694c6518SBenno Rice SMC_ASSERT_LOCKED(sc); 1171694c6518SBenno Rice ifp = sc->smc_ifp; 1172694c6518SBenno Rice 1173694c6518SBenno Rice /* 1174694c6518SBenno Rice * Set up the receive/PHY control register. 1175694c6518SBenno Rice */ 1176694c6518SBenno Rice smc_select_bank(sc, 0); 1177694c6518SBenno Rice smc_write_2(sc, RPCR, RPCR_ANEG | (RPCR_LED_LINK_ANY << RPCR_LSA_SHIFT) 1178694c6518SBenno Rice | (RPCR_LED_ACT_ANY << RPCR_LSB_SHIFT)); 1179694c6518SBenno Rice 1180694c6518SBenno Rice /* 1181694c6518SBenno Rice * Set up the transmit and receive control registers. 1182694c6518SBenno Rice */ 1183694c6518SBenno Rice smc_write_2(sc, TCR, TCR_TXENA | TCR_PAD_EN); 1184694c6518SBenno Rice smc_write_2(sc, RCR, RCR_RXEN | RCR_STRIP_CRC); 1185694c6518SBenno Rice 1186694c6518SBenno Rice /* 1187694c6518SBenno Rice * Set up the interrupt mask. 1188694c6518SBenno Rice */ 1189694c6518SBenno Rice smc_select_bank(sc, 2); 1190694c6518SBenno Rice sc->smc_mask = EPH_INT | RX_OVRN_INT | RCV_INT | TX_INT; 1191694c6518SBenno Rice if ((ifp->if_capenable & IFCAP_POLLING) != 0) 1192694c6518SBenno Rice smc_write_1(sc, MSK, sc->smc_mask); 1193694c6518SBenno Rice } 1194694c6518SBenno Rice 1195694c6518SBenno Rice static void 1196694c6518SBenno Rice smc_stop(struct smc_softc *sc) 1197694c6518SBenno Rice { 1198694c6518SBenno Rice 1199694c6518SBenno Rice SMC_ASSERT_LOCKED(sc); 1200694c6518SBenno Rice 1201694c6518SBenno Rice /* 12026e482159SBenno Rice * Turn off callouts. 1203694c6518SBenno Rice */ 1204694c6518SBenno Rice callout_stop(&sc->smc_watchdog); 12056e482159SBenno Rice callout_stop(&sc->smc_mii_tick_ch); 1206694c6518SBenno Rice 1207694c6518SBenno Rice /* 1208694c6518SBenno Rice * Mask all interrupts. 1209694c6518SBenno Rice */ 1210694c6518SBenno Rice smc_select_bank(sc, 2); 1211694c6518SBenno Rice sc->smc_mask = 0; 1212694c6518SBenno Rice smc_write_1(sc, MSK, 0); 1213694c6518SBenno Rice #ifdef DEVICE_POLLING 1214694c6518SBenno Rice ether_poll_deregister(sc->smc_ifp); 1215694c6518SBenno Rice sc->smc_ifp->if_capenable &= ~IFCAP_POLLING; 12161abcdbd1SAttilio Rao sc->smc_ifp->if_capenable &= ~IFCAP_POLLING_NOCOUNT; 1217694c6518SBenno Rice #endif 1218694c6518SBenno Rice 1219694c6518SBenno Rice /* 1220694c6518SBenno Rice * Disable transmit and receive. 1221694c6518SBenno Rice */ 1222694c6518SBenno Rice smc_select_bank(sc, 0); 1223694c6518SBenno Rice smc_write_2(sc, TCR, 0); 1224694c6518SBenno Rice smc_write_2(sc, RCR, 0); 1225694c6518SBenno Rice 1226694c6518SBenno Rice sc->smc_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1227694c6518SBenno Rice } 1228694c6518SBenno Rice 1229694c6518SBenno Rice static void 1230694c6518SBenno Rice smc_watchdog(void *arg) 1231694c6518SBenno Rice { 12323c463a49SBenno Rice struct smc_softc *sc; 1233694c6518SBenno Rice 12343c463a49SBenno Rice sc = (struct smc_softc *)arg; 12353c463a49SBenno Rice device_printf(sc->smc_dev, "watchdog timeout\n"); 12363c463a49SBenno Rice taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_intr); 1237694c6518SBenno Rice } 1238694c6518SBenno Rice 1239694c6518SBenno Rice static void 1240694c6518SBenno Rice smc_init(void *context) 1241694c6518SBenno Rice { 1242694c6518SBenno Rice struct smc_softc *sc; 1243694c6518SBenno Rice 1244694c6518SBenno Rice sc = (struct smc_softc *)context; 1245694c6518SBenno Rice SMC_LOCK(sc); 1246694c6518SBenno Rice smc_init_locked(sc); 1247694c6518SBenno Rice SMC_UNLOCK(sc); 1248694c6518SBenno Rice } 1249694c6518SBenno Rice 1250694c6518SBenno Rice static void 1251694c6518SBenno Rice smc_init_locked(struct smc_softc *sc) 1252694c6518SBenno Rice { 1253694c6518SBenno Rice struct ifnet *ifp; 1254694c6518SBenno Rice 1255694c6518SBenno Rice SMC_ASSERT_LOCKED(sc); 12568a318315SStanislav Sedov ifp = sc->smc_ifp; 12578a318315SStanislav Sedov if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 12588a318315SStanislav Sedov return; 1259694c6518SBenno Rice 1260694c6518SBenno Rice smc_reset(sc); 1261694c6518SBenno Rice smc_enable(sc); 1262694c6518SBenno Rice 1263694c6518SBenno Rice ifp->if_drv_flags |= IFF_DRV_RUNNING; 1264694c6518SBenno Rice ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1265694c6518SBenno Rice 1266694c6518SBenno Rice smc_start_locked(ifp); 1267694c6518SBenno Rice 1268694c6518SBenno Rice if (sc->smc_mii_tick != NULL) 1269694c6518SBenno Rice callout_reset(&sc->smc_mii_tick_ch, hz, sc->smc_mii_tick, sc); 1270694c6518SBenno Rice 1271694c6518SBenno Rice #ifdef DEVICE_POLLING 1272694c6518SBenno Rice SMC_UNLOCK(sc); 1273694c6518SBenno Rice ether_poll_register(smc_poll, ifp); 1274694c6518SBenno Rice SMC_LOCK(sc); 1275694c6518SBenno Rice ifp->if_capenable |= IFCAP_POLLING; 12761abcdbd1SAttilio Rao ifp->if_capenable |= IFCAP_POLLING_NOCOUNT; 1277694c6518SBenno Rice #endif 1278694c6518SBenno Rice } 1279694c6518SBenno Rice 1280694c6518SBenno Rice static int 1281694c6518SBenno Rice smc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1282694c6518SBenno Rice { 1283694c6518SBenno Rice struct smc_softc *sc; 1284694c6518SBenno Rice int error; 1285694c6518SBenno Rice 1286694c6518SBenno Rice sc = ifp->if_softc; 1287694c6518SBenno Rice error = 0; 1288694c6518SBenno Rice 1289694c6518SBenno Rice switch (cmd) { 1290694c6518SBenno Rice case SIOCSIFFLAGS: 1291694c6518SBenno Rice if ((ifp->if_flags & IFF_UP) == 0 && 1292694c6518SBenno Rice (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1293694c6518SBenno Rice SMC_LOCK(sc); 1294694c6518SBenno Rice smc_stop(sc); 1295694c6518SBenno Rice SMC_UNLOCK(sc); 1296694c6518SBenno Rice } else { 1297694c6518SBenno Rice smc_init(sc); 1298694c6518SBenno Rice if (sc->smc_mii_mediachg != NULL) 1299694c6518SBenno Rice sc->smc_mii_mediachg(sc); 1300694c6518SBenno Rice } 1301694c6518SBenno Rice break; 1302694c6518SBenno Rice 1303694c6518SBenno Rice case SIOCADDMULTI: 1304694c6518SBenno Rice case SIOCDELMULTI: 1305694c6518SBenno Rice /* XXX 1306694c6518SBenno Rice SMC_LOCK(sc); 1307694c6518SBenno Rice smc_setmcast(sc); 1308694c6518SBenno Rice SMC_UNLOCK(sc); 1309694c6518SBenno Rice */ 1310694c6518SBenno Rice error = EINVAL; 1311694c6518SBenno Rice break; 1312694c6518SBenno Rice 1313694c6518SBenno Rice case SIOCGIFMEDIA: 1314694c6518SBenno Rice case SIOCSIFMEDIA: 1315694c6518SBenno Rice if (sc->smc_mii_mediaioctl == NULL) { 1316694c6518SBenno Rice error = EINVAL; 1317694c6518SBenno Rice break; 1318694c6518SBenno Rice } 1319694c6518SBenno Rice sc->smc_mii_mediaioctl(sc, (struct ifreq *)data, cmd); 1320694c6518SBenno Rice break; 1321694c6518SBenno Rice 1322694c6518SBenno Rice default: 1323694c6518SBenno Rice error = ether_ioctl(ifp, cmd, data); 1324694c6518SBenno Rice break; 1325694c6518SBenno Rice } 1326694c6518SBenno Rice 1327694c6518SBenno Rice return (error); 1328694c6518SBenno Rice } 1329