xref: /freebsd/sys/dev/smc/if_smc.c (revision 22b33ca4b22e960dab4724b61ca137b078cf3069)
1694c6518SBenno Rice /*-
2718cf2ccSPedro F. Giffuni  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3718cf2ccSPedro F. Giffuni  *
4269a0696SBenno Rice  * Copyright (c) 2008 Benno Rice.  All rights reserved.
5694c6518SBenno Rice  *
6694c6518SBenno Rice  * Redistribution and use in source and binary forms, with or without
7694c6518SBenno Rice  * modification, are permitted provided that the following conditions
8694c6518SBenno Rice  * are met:
9694c6518SBenno Rice  * 1. Redistributions of source code must retain the above copyright
10694c6518SBenno Rice  *    notice, this list of conditions and the following disclaimer.
11694c6518SBenno Rice  * 2. Redistributions in binary form must reproduce the above copyright
12694c6518SBenno Rice  *    notice, this list of conditions and the following disclaimer in the
13694c6518SBenno Rice  *    documentation and/or other materials provided with the distribution.
14694c6518SBenno Rice  *
15694c6518SBenno Rice  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16694c6518SBenno Rice  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17694c6518SBenno Rice  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18694c6518SBenno Rice  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19694c6518SBenno Rice  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20694c6518SBenno Rice  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21694c6518SBenno Rice  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22694c6518SBenno Rice  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23694c6518SBenno Rice  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24694c6518SBenno Rice  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25694c6518SBenno Rice  */
26694c6518SBenno Rice 
27694c6518SBenno Rice #include <sys/cdefs.h>
28694c6518SBenno Rice __FBSDID("$FreeBSD$");
29694c6518SBenno Rice 
30694c6518SBenno Rice /*
31694c6518SBenno Rice  * Driver for SMSC LAN91C111, may work for older variants.
32694c6518SBenno Rice  */
33694c6518SBenno Rice 
34694c6518SBenno Rice #ifdef HAVE_KERNEL_OPTION_HEADERS
35694c6518SBenno Rice #include "opt_device_polling.h"
36694c6518SBenno Rice #endif
37694c6518SBenno Rice 
38694c6518SBenno Rice #include <sys/param.h>
39694c6518SBenno Rice #include <sys/systm.h>
40694c6518SBenno Rice #include <sys/errno.h>
41694c6518SBenno Rice #include <sys/kernel.h>
42694c6518SBenno Rice #include <sys/sockio.h>
43694c6518SBenno Rice #include <sys/malloc.h>
44694c6518SBenno Rice #include <sys/mbuf.h>
45694c6518SBenno Rice #include <sys/queue.h>
46694c6518SBenno Rice #include <sys/socket.h>
47694c6518SBenno Rice #include <sys/syslog.h>
48694c6518SBenno Rice #include <sys/taskqueue.h>
49694c6518SBenno Rice 
50694c6518SBenno Rice #include <sys/module.h>
51694c6518SBenno Rice #include <sys/bus.h>
52694c6518SBenno Rice 
53694c6518SBenno Rice #include <machine/bus.h>
54694c6518SBenno Rice #include <machine/resource.h>
55694c6518SBenno Rice #include <sys/rman.h>
56694c6518SBenno Rice 
57694c6518SBenno Rice #include <net/ethernet.h>
58694c6518SBenno Rice #include <net/if.h>
5976039bc8SGleb Smirnoff #include <net/if_var.h>
60694c6518SBenno Rice #include <net/if_arp.h>
61694c6518SBenno Rice #include <net/if_dl.h>
62694c6518SBenno Rice #include <net/if_types.h>
63694c6518SBenno Rice #include <net/if_mib.h>
64694c6518SBenno Rice #include <net/if_media.h>
65694c6518SBenno Rice 
66694c6518SBenno Rice #ifdef INET
67694c6518SBenno Rice #include <netinet/in.h>
68694c6518SBenno Rice #include <netinet/in_systm.h>
69694c6518SBenno Rice #include <netinet/in_var.h>
70694c6518SBenno Rice #include <netinet/ip.h>
71694c6518SBenno Rice #endif
72694c6518SBenno Rice 
73694c6518SBenno Rice #include <net/bpf.h>
74694c6518SBenno Rice #include <net/bpfdesc.h>
75694c6518SBenno Rice 
76694c6518SBenno Rice #include <dev/smc/if_smcreg.h>
77694c6518SBenno Rice #include <dev/smc/if_smcvar.h>
78694c6518SBenno Rice 
79694c6518SBenno Rice #include <dev/mii/mii.h>
808c1093fcSMarius Strobl #include <dev/mii/mii_bitbang.h>
81694c6518SBenno Rice #include <dev/mii/miivar.h>
82694c6518SBenno Rice 
83*22b33ca4SAndrew Turner #include "miibus_if.h"
84*22b33ca4SAndrew Turner 
853c463a49SBenno Rice #define	SMC_LOCK(sc)		mtx_lock(&(sc)->smc_mtx)
863c463a49SBenno Rice #define	SMC_UNLOCK(sc)		mtx_unlock(&(sc)->smc_mtx)
873c463a49SBenno Rice #define	SMC_ASSERT_LOCKED(sc)	mtx_assert(&(sc)->smc_mtx, MA_OWNED)
883c463a49SBenno Rice 
893c463a49SBenno Rice #define	SMC_INTR_PRIORITY	0
903c463a49SBenno Rice #define	SMC_RX_PRIORITY		5
913c463a49SBenno Rice #define	SMC_TX_PRIORITY		10
923c463a49SBenno Rice 
93694c6518SBenno Rice devclass_t	smc_devclass;
94694c6518SBenno Rice 
95694c6518SBenno Rice static const char *smc_chip_ids[16] = {
96694c6518SBenno Rice 	NULL, NULL, NULL,
97694c6518SBenno Rice 	/* 3 */ "SMSC LAN91C90 or LAN91C92",
98694c6518SBenno Rice 	/* 4 */ "SMSC LAN91C94",
99694c6518SBenno Rice 	/* 5 */ "SMSC LAN91C95",
100694c6518SBenno Rice 	/* 6 */ "SMSC LAN91C96",
101694c6518SBenno Rice 	/* 7 */ "SMSC LAN91C100",
102694c6518SBenno Rice 	/* 8 */	"SMSC LAN91C100FD",
103694c6518SBenno Rice 	/* 9 */ "SMSC LAN91C110FD or LAN91C111FD",
104694c6518SBenno Rice 	NULL, NULL, NULL,
105694c6518SBenno Rice 	NULL, NULL, NULL
106694c6518SBenno Rice };
107694c6518SBenno Rice 
108694c6518SBenno Rice static void	smc_init(void *);
109694c6518SBenno Rice static void	smc_start(struct ifnet *);
110764e058aSBenno Rice static void	smc_stop(struct smc_softc *);
111694c6518SBenno Rice static int	smc_ioctl(struct ifnet *, u_long, caddr_t);
112694c6518SBenno Rice 
113694c6518SBenno Rice static void	smc_init_locked(struct smc_softc *);
114694c6518SBenno Rice static void	smc_start_locked(struct ifnet *);
115694c6518SBenno Rice static void	smc_reset(struct smc_softc *);
116694c6518SBenno Rice static int	smc_mii_ifmedia_upd(struct ifnet *);
117694c6518SBenno Rice static void	smc_mii_ifmedia_sts(struct ifnet *, struct ifmediareq *);
118694c6518SBenno Rice static void	smc_mii_tick(void *);
119694c6518SBenno Rice static void	smc_mii_mediachg(struct smc_softc *);
120694c6518SBenno Rice static int	smc_mii_mediaioctl(struct smc_softc *, struct ifreq *, u_long);
121694c6518SBenno Rice 
1223c463a49SBenno Rice static void	smc_task_intr(void *, int);
123694c6518SBenno Rice static void	smc_task_rx(void *, int);
124694c6518SBenno Rice static void	smc_task_tx(void *, int);
125694c6518SBenno Rice 
126694c6518SBenno Rice static driver_filter_t	smc_intr;
1275773ac11SJohn Baldwin static callout_func_t	smc_watchdog;
128694c6518SBenno Rice #ifdef DEVICE_POLLING
129694c6518SBenno Rice static poll_handler_t	smc_poll;
130694c6518SBenno Rice #endif
131694c6518SBenno Rice 
1328c1093fcSMarius Strobl /*
1338c1093fcSMarius Strobl  * MII bit-bang glue
1348c1093fcSMarius Strobl  */
1358c1093fcSMarius Strobl static uint32_t smc_mii_bitbang_read(device_t);
1368c1093fcSMarius Strobl static void smc_mii_bitbang_write(device_t, uint32_t);
1378c1093fcSMarius Strobl 
1388c1093fcSMarius Strobl static const struct mii_bitbang_ops smc_mii_bitbang_ops = {
1398c1093fcSMarius Strobl 	smc_mii_bitbang_read,
1408c1093fcSMarius Strobl 	smc_mii_bitbang_write,
1418c1093fcSMarius Strobl 	{
1428c1093fcSMarius Strobl 		MGMT_MDO,	/* MII_BIT_MDO */
1438c1093fcSMarius Strobl 		MGMT_MDI,	/* MII_BIT_MDI */
1448c1093fcSMarius Strobl 		MGMT_MCLK,	/* MII_BIT_MDC */
1458c1093fcSMarius Strobl 		MGMT_MDOE,	/* MII_BIT_DIR_HOST_PHY */
1468c1093fcSMarius Strobl 		0,		/* MII_BIT_DIR_PHY_HOST */
1478c1093fcSMarius Strobl 	}
1488c1093fcSMarius Strobl };
1498c1093fcSMarius Strobl 
150694c6518SBenno Rice static __inline void
151694c6518SBenno Rice smc_select_bank(struct smc_softc *sc, uint16_t bank)
152694c6518SBenno Rice {
153694c6518SBenno Rice 
1548c1093fcSMarius Strobl 	bus_barrier(sc->smc_reg, BSR, 2,
1558c1093fcSMarius Strobl 	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
156269a0696SBenno Rice 	bus_write_2(sc->smc_reg, BSR, bank & BSR_BANK_MASK);
1578c1093fcSMarius Strobl 	bus_barrier(sc->smc_reg, BSR, 2,
1588c1093fcSMarius Strobl 	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
159694c6518SBenno Rice }
160694c6518SBenno Rice 
161694c6518SBenno Rice /* Never call this when not in bank 2. */
162694c6518SBenno Rice static __inline void
163694c6518SBenno Rice smc_mmu_wait(struct smc_softc *sc)
164694c6518SBenno Rice {
165694c6518SBenno Rice 
166269a0696SBenno Rice 	KASSERT((bus_read_2(sc->smc_reg, BSR) &
167694c6518SBenno Rice 	    BSR_BANK_MASK) == 2, ("%s: smc_mmu_wait called when not in bank 2",
168694c6518SBenno Rice 	    device_get_nameunit(sc->smc_dev)));
169269a0696SBenno Rice 	while (bus_read_2(sc->smc_reg, MMUCR) & MMUCR_BUSY)
170694c6518SBenno Rice 		;
171694c6518SBenno Rice }
172694c6518SBenno Rice 
173694c6518SBenno Rice static __inline uint8_t
1748c1093fcSMarius Strobl smc_read_1(struct smc_softc *sc, bus_size_t offset)
175694c6518SBenno Rice {
176694c6518SBenno Rice 
177269a0696SBenno Rice 	return (bus_read_1(sc->smc_reg, offset));
178694c6518SBenno Rice }
179694c6518SBenno Rice 
180694c6518SBenno Rice static __inline void
1818c1093fcSMarius Strobl smc_write_1(struct smc_softc *sc, bus_size_t offset, uint8_t val)
182694c6518SBenno Rice {
183694c6518SBenno Rice 
184269a0696SBenno Rice 	bus_write_1(sc->smc_reg, offset, val);
185694c6518SBenno Rice }
186694c6518SBenno Rice 
187694c6518SBenno Rice static __inline uint16_t
1888c1093fcSMarius Strobl smc_read_2(struct smc_softc *sc, bus_size_t offset)
189694c6518SBenno Rice {
190694c6518SBenno Rice 
191269a0696SBenno Rice 	return (bus_read_2(sc->smc_reg, offset));
192694c6518SBenno Rice }
193694c6518SBenno Rice 
194694c6518SBenno Rice static __inline void
1958c1093fcSMarius Strobl smc_write_2(struct smc_softc *sc, bus_size_t offset, uint16_t val)
196694c6518SBenno Rice {
197694c6518SBenno Rice 
198269a0696SBenno Rice 	bus_write_2(sc->smc_reg, offset, val);
199694c6518SBenno Rice }
200694c6518SBenno Rice 
201694c6518SBenno Rice static __inline void
2028c1093fcSMarius Strobl smc_read_multi_2(struct smc_softc *sc, bus_size_t offset, uint16_t *datap,
203694c6518SBenno Rice     bus_size_t count)
204694c6518SBenno Rice {
205694c6518SBenno Rice 
206269a0696SBenno Rice 	bus_read_multi_2(sc->smc_reg, offset, datap, count);
207694c6518SBenno Rice }
208694c6518SBenno Rice 
209694c6518SBenno Rice static __inline void
2108c1093fcSMarius Strobl smc_write_multi_2(struct smc_softc *sc, bus_size_t offset, uint16_t *datap,
211694c6518SBenno Rice     bus_size_t count)
212694c6518SBenno Rice {
213694c6518SBenno Rice 
214269a0696SBenno Rice 	bus_write_multi_2(sc->smc_reg, offset, datap, count);
215694c6518SBenno Rice }
216694c6518SBenno Rice 
2178c1093fcSMarius Strobl static __inline void
2188c1093fcSMarius Strobl smc_barrier(struct smc_softc *sc, bus_size_t offset, bus_size_t length,
2198c1093fcSMarius Strobl     int flags)
2208c1093fcSMarius Strobl {
2218c1093fcSMarius Strobl 
2228c1093fcSMarius Strobl 	bus_barrier(sc->smc_reg, offset, length, flags);
2238c1093fcSMarius Strobl }
2248c1093fcSMarius Strobl 
225694c6518SBenno Rice int
226694c6518SBenno Rice smc_probe(device_t dev)
227694c6518SBenno Rice {
228694c6518SBenno Rice 	int			rid, type, error;
229694c6518SBenno Rice 	uint16_t		val;
230694c6518SBenno Rice 	struct smc_softc	*sc;
231694c6518SBenno Rice 	struct resource		*reg;
232694c6518SBenno Rice 
233694c6518SBenno Rice 	sc = device_get_softc(dev);
234694c6518SBenno Rice 	rid = 0;
235694c6518SBenno Rice 	type = SYS_RES_IOPORT;
236694c6518SBenno Rice 	error = 0;
237694c6518SBenno Rice 
238694c6518SBenno Rice 	if (sc->smc_usemem)
239694c6518SBenno Rice 		type = SYS_RES_MEMORY;
240694c6518SBenno Rice 
241c47476d7SJustin Hibbits 	reg = bus_alloc_resource_anywhere(dev, type, &rid, 16, RF_ACTIVE);
242694c6518SBenno Rice 	if (reg == NULL) {
243694c6518SBenno Rice 		if (bootverbose)
244694c6518SBenno Rice 			device_printf(dev,
245694c6518SBenno Rice 			    "could not allocate I/O resource for probe\n");
246694c6518SBenno Rice 		return (ENXIO);
247694c6518SBenno Rice 	}
248694c6518SBenno Rice 
249694c6518SBenno Rice 	/* Check for the identification value in the BSR. */
250269a0696SBenno Rice 	val = bus_read_2(reg, BSR);
251694c6518SBenno Rice 	if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) {
252694c6518SBenno Rice 		if (bootverbose)
253694c6518SBenno Rice 			device_printf(dev, "identification value not in BSR\n");
254694c6518SBenno Rice 		error = ENXIO;
255694c6518SBenno Rice 		goto done;
256694c6518SBenno Rice 	}
257694c6518SBenno Rice 
258694c6518SBenno Rice 	/*
259694c6518SBenno Rice 	 * Try switching banks and make sure we still get the identification
260694c6518SBenno Rice 	 * value.
261694c6518SBenno Rice 	 */
262269a0696SBenno Rice 	bus_write_2(reg, BSR, 0);
263269a0696SBenno Rice 	val = bus_read_2(reg, BSR);
264694c6518SBenno Rice 	if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) {
265694c6518SBenno Rice 		if (bootverbose)
266694c6518SBenno Rice 			device_printf(dev,
267694c6518SBenno Rice 			    "identification value not in BSR after write\n");
268694c6518SBenno Rice 		error = ENXIO;
269694c6518SBenno Rice 		goto done;
270694c6518SBenno Rice 	}
271694c6518SBenno Rice 
272694c6518SBenno Rice #if 0
273694c6518SBenno Rice 	/* Check the BAR. */
274269a0696SBenno Rice 	bus_write_2(reg, BSR, 1);
275269a0696SBenno Rice 	val = bus_read_2(reg, BAR);
276694c6518SBenno Rice 	val = BAR_ADDRESS(val);
277694c6518SBenno Rice 	if (rman_get_start(reg) != val) {
278694c6518SBenno Rice 		if (bootverbose)
279694c6518SBenno Rice 			device_printf(dev, "BAR address %x does not match "
280694c6518SBenno Rice 			    "I/O resource address %lx\n", val,
281694c6518SBenno Rice 			    rman_get_start(reg));
282694c6518SBenno Rice 		error = ENXIO;
283694c6518SBenno Rice 		goto done;
284694c6518SBenno Rice 	}
285694c6518SBenno Rice #endif
286694c6518SBenno Rice 
287694c6518SBenno Rice 	/* Compare REV against known chip revisions. */
288269a0696SBenno Rice 	bus_write_2(reg, BSR, 3);
289269a0696SBenno Rice 	val = bus_read_2(reg, REV);
290694c6518SBenno Rice 	val = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT;
291694c6518SBenno Rice 	if (smc_chip_ids[val] == NULL) {
292694c6518SBenno Rice 		if (bootverbose)
293694c6518SBenno Rice 			device_printf(dev, "Unknown chip revision: %d\n", val);
294694c6518SBenno Rice 		error = ENXIO;
295694c6518SBenno Rice 		goto done;
296694c6518SBenno Rice 	}
297694c6518SBenno Rice 
298694c6518SBenno Rice 	device_set_desc(dev, smc_chip_ids[val]);
299694c6518SBenno Rice 
300694c6518SBenno Rice done:
301694c6518SBenno Rice 	bus_release_resource(dev, type, rid, reg);
302694c6518SBenno Rice 	return (error);
303694c6518SBenno Rice }
304694c6518SBenno Rice 
305694c6518SBenno Rice int
306694c6518SBenno Rice smc_attach(device_t dev)
307694c6518SBenno Rice {
308694c6518SBenno Rice 	int			type, error;
309694c6518SBenno Rice 	uint16_t		val;
310694c6518SBenno Rice 	u_char			eaddr[ETHER_ADDR_LEN];
311694c6518SBenno Rice 	struct smc_softc	*sc;
312694c6518SBenno Rice 	struct ifnet		*ifp;
313694c6518SBenno Rice 
314694c6518SBenno Rice 	sc = device_get_softc(dev);
315694c6518SBenno Rice 	error = 0;
316694c6518SBenno Rice 
317694c6518SBenno Rice 	sc->smc_dev = dev;
318694c6518SBenno Rice 
319694c6518SBenno Rice 	ifp = sc->smc_ifp = if_alloc(IFT_ETHER);
320694c6518SBenno Rice 	if (ifp == NULL) {
321694c6518SBenno Rice 		error = ENOSPC;
322694c6518SBenno Rice 		goto done;
323694c6518SBenno Rice 	}
324694c6518SBenno Rice 
3253c463a49SBenno Rice 	mtx_init(&sc->smc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
326694c6518SBenno Rice 
3276e482159SBenno Rice 	/* Set up watchdog callout. */
3286e482159SBenno Rice 	callout_init_mtx(&sc->smc_watchdog, &sc->smc_mtx, 0);
3296e482159SBenno Rice 
330694c6518SBenno Rice 	type = SYS_RES_IOPORT;
331694c6518SBenno Rice 	if (sc->smc_usemem)
332694c6518SBenno Rice 		type = SYS_RES_MEMORY;
333694c6518SBenno Rice 
334694c6518SBenno Rice 	sc->smc_reg_rid = 0;
335c47476d7SJustin Hibbits 	sc->smc_reg = bus_alloc_resource_anywhere(dev, type, &sc->smc_reg_rid,
336694c6518SBenno Rice 	    16, RF_ACTIVE);
337694c6518SBenno Rice 	if (sc->smc_reg == NULL) {
338694c6518SBenno Rice 		error = ENXIO;
339694c6518SBenno Rice 		goto done;
340694c6518SBenno Rice 	}
341694c6518SBenno Rice 
342c47476d7SJustin Hibbits 	sc->smc_irq = bus_alloc_resource_anywhere(dev, SYS_RES_IRQ,
343c47476d7SJustin Hibbits 	    &sc->smc_irq_rid, 1, RF_ACTIVE | RF_SHAREABLE);
344694c6518SBenno Rice 	if (sc->smc_irq == NULL) {
345694c6518SBenno Rice 		error = ENXIO;
346694c6518SBenno Rice 		goto done;
347694c6518SBenno Rice 	}
348694c6518SBenno Rice 
349694c6518SBenno Rice 	SMC_LOCK(sc);
350694c6518SBenno Rice 	smc_reset(sc);
351694c6518SBenno Rice 	SMC_UNLOCK(sc);
352694c6518SBenno Rice 
353694c6518SBenno Rice 	smc_select_bank(sc, 3);
354694c6518SBenno Rice 	val = smc_read_2(sc, REV);
355694c6518SBenno Rice 	sc->smc_chip = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT;
356694c6518SBenno Rice 	sc->smc_rev = (val * REV_REV_MASK) >> REV_REV_SHIFT;
357694c6518SBenno Rice 	if (bootverbose)
358694c6518SBenno Rice 		device_printf(dev, "revision %x\n", sc->smc_rev);
359694c6518SBenno Rice 
3606e482159SBenno Rice 	callout_init_mtx(&sc->smc_mii_tick_ch, &sc->smc_mtx,
3616e482159SBenno Rice 	    CALLOUT_RETURNUNLOCKED);
362694c6518SBenno Rice 	if (sc->smc_chip >= REV_CHIP_91110FD) {
363d6c65d27SMarius Strobl 		(void)mii_attach(dev, &sc->smc_miibus, ifp,
364d6c65d27SMarius Strobl 		    smc_mii_ifmedia_upd, smc_mii_ifmedia_sts, BMSR_DEFCAPMASK,
365d6c65d27SMarius Strobl 		    MII_PHY_ANY, MII_OFFSET_ANY, 0);
366694c6518SBenno Rice 		if (sc->smc_miibus != NULL) {
367694c6518SBenno Rice 			sc->smc_mii_tick = smc_mii_tick;
368694c6518SBenno Rice 			sc->smc_mii_mediachg = smc_mii_mediachg;
369694c6518SBenno Rice 			sc->smc_mii_mediaioctl = smc_mii_mediaioctl;
370694c6518SBenno Rice 		}
371694c6518SBenno Rice 	}
372694c6518SBenno Rice 
373694c6518SBenno Rice 	smc_select_bank(sc, 1);
374694c6518SBenno Rice 	eaddr[0] = smc_read_1(sc, IAR0);
375694c6518SBenno Rice 	eaddr[1] = smc_read_1(sc, IAR1);
376694c6518SBenno Rice 	eaddr[2] = smc_read_1(sc, IAR2);
377694c6518SBenno Rice 	eaddr[3] = smc_read_1(sc, IAR3);
378694c6518SBenno Rice 	eaddr[4] = smc_read_1(sc, IAR4);
379694c6518SBenno Rice 	eaddr[5] = smc_read_1(sc, IAR5);
380694c6518SBenno Rice 
381694c6518SBenno Rice 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
382694c6518SBenno Rice 	ifp->if_softc = sc;
383694c6518SBenno Rice 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
384694c6518SBenno Rice 	ifp->if_init = smc_init;
385694c6518SBenno Rice 	ifp->if_ioctl = smc_ioctl;
386694c6518SBenno Rice 	ifp->if_start = smc_start;
387e50d35e6SMaxim Sobolev 	IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
388694c6518SBenno Rice 	IFQ_SET_READY(&ifp->if_snd);
389694c6518SBenno Rice 
390694c6518SBenno Rice 	ifp->if_capabilities = ifp->if_capenable = 0;
391694c6518SBenno Rice 
392694c6518SBenno Rice #ifdef DEVICE_POLLING
393694c6518SBenno Rice 	ifp->if_capabilities |= IFCAP_POLLING;
394694c6518SBenno Rice #endif
395694c6518SBenno Rice 
396694c6518SBenno Rice 	ether_ifattach(ifp, eaddr);
397694c6518SBenno Rice 
398694c6518SBenno Rice 	/* Set up taskqueue */
3993c463a49SBenno Rice 	TASK_INIT(&sc->smc_intr, SMC_INTR_PRIORITY, smc_task_intr, ifp);
4006c3e93cbSGleb Smirnoff 	NET_TASK_INIT(&sc->smc_rx, SMC_RX_PRIORITY, smc_task_rx, ifp);
401694c6518SBenno Rice 	TASK_INIT(&sc->smc_tx, SMC_TX_PRIORITY, smc_task_tx, ifp);
402694c6518SBenno Rice 	sc->smc_tq = taskqueue_create_fast("smc_taskq", M_NOWAIT,
403694c6518SBenno Rice 	    taskqueue_thread_enqueue, &sc->smc_tq);
404694c6518SBenno Rice 	taskqueue_start_threads(&sc->smc_tq, 1, PI_NET, "%s taskq",
405694c6518SBenno Rice 	    device_get_nameunit(sc->smc_dev));
406694c6518SBenno Rice 
407694c6518SBenno Rice 	/* Mask all interrupts. */
408694c6518SBenno Rice 	sc->smc_mask = 0;
409694c6518SBenno Rice 	smc_write_1(sc, MSK, 0);
410694c6518SBenno Rice 
411694c6518SBenno Rice 	/* Wire up interrupt */
412694c6518SBenno Rice 	error = bus_setup_intr(dev, sc->smc_irq,
4133c463a49SBenno Rice 	    INTR_TYPE_NET|INTR_MPSAFE, smc_intr, NULL, sc, &sc->smc_ih);
414694c6518SBenno Rice 	if (error != 0)
415694c6518SBenno Rice 		goto done;
416694c6518SBenno Rice 
417694c6518SBenno Rice done:
418694c6518SBenno Rice 	if (error != 0)
419694c6518SBenno Rice 		smc_detach(dev);
420694c6518SBenno Rice 	return (error);
421694c6518SBenno Rice }
422694c6518SBenno Rice 
423694c6518SBenno Rice int
424694c6518SBenno Rice smc_detach(device_t dev)
425694c6518SBenno Rice {
426694c6518SBenno Rice 	int			type;
427694c6518SBenno Rice 	struct smc_softc	*sc;
428694c6518SBenno Rice 
429694c6518SBenno Rice 	sc = device_get_softc(dev);
430764e058aSBenno Rice 	SMC_LOCK(sc);
431764e058aSBenno Rice 	smc_stop(sc);
432764e058aSBenno Rice 	SMC_UNLOCK(sc);
433694c6518SBenno Rice 
434aec9f8e9SBenno Rice 	if (sc->smc_ifp != NULL) {
435aec9f8e9SBenno Rice 		ether_ifdetach(sc->smc_ifp);
436aec9f8e9SBenno Rice 	}
437aec9f8e9SBenno Rice 
438aec9f8e9SBenno Rice 	callout_drain(&sc->smc_watchdog);
439aec9f8e9SBenno Rice 	callout_drain(&sc->smc_mii_tick_ch);
440aec9f8e9SBenno Rice 
441694c6518SBenno Rice #ifdef DEVICE_POLLING
442694c6518SBenno Rice 	if (sc->smc_ifp->if_capenable & IFCAP_POLLING)
443694c6518SBenno Rice 		ether_poll_deregister(sc->smc_ifp);
444694c6518SBenno Rice #endif
445694c6518SBenno Rice 
446694c6518SBenno Rice 	if (sc->smc_ih != NULL)
447694c6518SBenno Rice 		bus_teardown_intr(sc->smc_dev, sc->smc_irq, sc->smc_ih);
448694c6518SBenno Rice 
4496e482159SBenno Rice 	if (sc->smc_tq != NULL) {
4506e482159SBenno Rice 		taskqueue_drain(sc->smc_tq, &sc->smc_intr);
4516e482159SBenno Rice 		taskqueue_drain(sc->smc_tq, &sc->smc_rx);
4526e482159SBenno Rice 		taskqueue_drain(sc->smc_tq, &sc->smc_tx);
4536e482159SBenno Rice 		taskqueue_free(sc->smc_tq);
4546e482159SBenno Rice 		sc->smc_tq = NULL;
4556e482159SBenno Rice 	}
4566e482159SBenno Rice 
457694c6518SBenno Rice 	if (sc->smc_ifp != NULL) {
458694c6518SBenno Rice 		if_free(sc->smc_ifp);
459694c6518SBenno Rice 	}
460694c6518SBenno Rice 
461694c6518SBenno Rice 	if (sc->smc_miibus != NULL) {
462694c6518SBenno Rice 		device_delete_child(sc->smc_dev, sc->smc_miibus);
463694c6518SBenno Rice 		bus_generic_detach(sc->smc_dev);
464694c6518SBenno Rice 	}
465694c6518SBenno Rice 
466694c6518SBenno Rice 	if (sc->smc_reg != NULL) {
467694c6518SBenno Rice 		type = SYS_RES_IOPORT;
468694c6518SBenno Rice 		if (sc->smc_usemem)
469694c6518SBenno Rice 			type = SYS_RES_MEMORY;
470694c6518SBenno Rice 
471694c6518SBenno Rice 		bus_release_resource(sc->smc_dev, type, sc->smc_reg_rid,
472694c6518SBenno Rice 		    sc->smc_reg);
473694c6518SBenno Rice 	}
474694c6518SBenno Rice 
475694c6518SBenno Rice 	if (sc->smc_irq != NULL)
476694c6518SBenno Rice 		bus_release_resource(sc->smc_dev, SYS_RES_IRQ, sc->smc_irq_rid,
477694c6518SBenno Rice 		   sc->smc_irq);
478694c6518SBenno Rice 
479694c6518SBenno Rice 	if (mtx_initialized(&sc->smc_mtx))
480694c6518SBenno Rice 		mtx_destroy(&sc->smc_mtx);
481694c6518SBenno Rice 
482694c6518SBenno Rice 	return (0);
483694c6518SBenno Rice }
484694c6518SBenno Rice 
485*22b33ca4SAndrew Turner static device_method_t smc_methods[] = {
486*22b33ca4SAndrew Turner 	/* Device interface */
487*22b33ca4SAndrew Turner 	DEVMETHOD(device_attach,	smc_attach),
488*22b33ca4SAndrew Turner 	DEVMETHOD(device_detach,	smc_detach),
489*22b33ca4SAndrew Turner 
490*22b33ca4SAndrew Turner 	/* MII interface */
491*22b33ca4SAndrew Turner 	DEVMETHOD(miibus_readreg,	smc_miibus_readreg),
492*22b33ca4SAndrew Turner 	DEVMETHOD(miibus_writereg,	smc_miibus_writereg),
493*22b33ca4SAndrew Turner 	DEVMETHOD(miibus_statchg,	smc_miibus_statchg),
494*22b33ca4SAndrew Turner 
495*22b33ca4SAndrew Turner 	{ 0, 0 }
496*22b33ca4SAndrew Turner };
497*22b33ca4SAndrew Turner 
498*22b33ca4SAndrew Turner driver_t smc_driver = {
499*22b33ca4SAndrew Turner 	"smc",
500*22b33ca4SAndrew Turner 	smc_methods,
501*22b33ca4SAndrew Turner 	sizeof(struct smc_softc),
502*22b33ca4SAndrew Turner };
503*22b33ca4SAndrew Turner 
504*22b33ca4SAndrew Turner DRIVER_MODULE(miibus, smc, miibus_driver, miibus_devclass, 0, 0);
505*22b33ca4SAndrew Turner 
506694c6518SBenno Rice static void
507694c6518SBenno Rice smc_start(struct ifnet *ifp)
508694c6518SBenno Rice {
509694c6518SBenno Rice 	struct smc_softc	*sc;
510694c6518SBenno Rice 
511694c6518SBenno Rice 	sc = ifp->if_softc;
512694c6518SBenno Rice 	SMC_LOCK(sc);
513694c6518SBenno Rice 	smc_start_locked(ifp);
514694c6518SBenno Rice 	SMC_UNLOCK(sc);
515694c6518SBenno Rice }
516694c6518SBenno Rice 
517694c6518SBenno Rice static void
518694c6518SBenno Rice smc_start_locked(struct ifnet *ifp)
519694c6518SBenno Rice {
520694c6518SBenno Rice 	struct smc_softc	*sc;
521694c6518SBenno Rice 	struct mbuf		*m;
522694c6518SBenno Rice 	u_int			len, npages, spin_count;
523694c6518SBenno Rice 
524694c6518SBenno Rice 	sc = ifp->if_softc;
525694c6518SBenno Rice 	SMC_ASSERT_LOCKED(sc);
526694c6518SBenno Rice 
527694c6518SBenno Rice 	if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
528694c6518SBenno Rice 		return;
529694c6518SBenno Rice 	if (IFQ_IS_EMPTY(&ifp->if_snd))
530694c6518SBenno Rice 		return;
531694c6518SBenno Rice 
532694c6518SBenno Rice 	/*
533694c6518SBenno Rice 	 * Grab the next packet.  If it's too big, drop it.
534694c6518SBenno Rice 	 */
535694c6518SBenno Rice 	IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
536694c6518SBenno Rice 	len = m_length(m, NULL);
537694c6518SBenno Rice 	len += (len & 1);
538694c6518SBenno Rice 	if (len > ETHER_MAX_LEN - ETHER_CRC_LEN) {
539694c6518SBenno Rice 		if_printf(ifp, "large packet discarded\n");
540c0973d1fSGleb Smirnoff 		if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
541694c6518SBenno Rice 		m_freem(m);
542694c6518SBenno Rice 		return; /* XXX readcheck? */
543694c6518SBenno Rice 	}
544694c6518SBenno Rice 
545694c6518SBenno Rice 	/*
546694c6518SBenno Rice 	 * Flag that we're busy.
547694c6518SBenno Rice 	 */
548694c6518SBenno Rice 	ifp->if_drv_flags |= IFF_DRV_OACTIVE;
549694c6518SBenno Rice 	sc->smc_pending = m;
550694c6518SBenno Rice 
551694c6518SBenno Rice 	/*
552694c6518SBenno Rice 	 * Work out how many 256 byte "pages" we need.  We have to include the
553694c6518SBenno Rice 	 * control data for the packet in this calculation.
554694c6518SBenno Rice 	 */
55594909337SRuslan Bukin 	npages = (len + PKT_CTRL_DATA_LEN) >> 8;
556694c6518SBenno Rice 	if (npages == 0)
557694c6518SBenno Rice 		npages = 1;
558694c6518SBenno Rice 
559694c6518SBenno Rice 	/*
560694c6518SBenno Rice 	 * Request memory.
561694c6518SBenno Rice 	 */
562694c6518SBenno Rice 	smc_select_bank(sc, 2);
563694c6518SBenno Rice 	smc_mmu_wait(sc);
564694c6518SBenno Rice 	smc_write_2(sc, MMUCR, MMUCR_CMD_TX_ALLOC | npages);
565694c6518SBenno Rice 
566694c6518SBenno Rice 	/*
567694c6518SBenno Rice 	 * Spin briefly to see if the allocation succeeds.
568694c6518SBenno Rice 	 */
569694c6518SBenno Rice 	spin_count = TX_ALLOC_WAIT_TIME;
570694c6518SBenno Rice 	do {
571694c6518SBenno Rice 		if (smc_read_1(sc, IST) & ALLOC_INT) {
572694c6518SBenno Rice 			smc_write_1(sc, ACK, ALLOC_INT);
573694c6518SBenno Rice 			break;
574694c6518SBenno Rice 		}
575694c6518SBenno Rice 	} while (--spin_count);
576694c6518SBenno Rice 
577694c6518SBenno Rice 	/*
578694c6518SBenno Rice 	 * If the allocation is taking too long, unmask the alloc interrupt
579694c6518SBenno Rice 	 * and wait.
580694c6518SBenno Rice 	 */
581694c6518SBenno Rice 	if (spin_count == 0) {
582694c6518SBenno Rice 		sc->smc_mask |= ALLOC_INT;
583694c6518SBenno Rice 		if ((ifp->if_capenable & IFCAP_POLLING) == 0)
584694c6518SBenno Rice 			smc_write_1(sc, MSK, sc->smc_mask);
585694c6518SBenno Rice 		return;
586694c6518SBenno Rice 	}
587694c6518SBenno Rice 
588cbc4d2dbSJohn Baldwin 	taskqueue_enqueue(sc->smc_tq, &sc->smc_tx);
589694c6518SBenno Rice }
590694c6518SBenno Rice 
591694c6518SBenno Rice static void
592694c6518SBenno Rice smc_task_tx(void *context, int pending)
593694c6518SBenno Rice {
594694c6518SBenno Rice 	struct ifnet		*ifp;
595694c6518SBenno Rice 	struct smc_softc	*sc;
596694c6518SBenno Rice 	struct mbuf		*m, *m0;
597694c6518SBenno Rice 	u_int			packet, len;
598bd2369f6SStanislav Sedov 	int			last_len;
599694c6518SBenno Rice 	uint8_t			*data;
600694c6518SBenno Rice 
601694c6518SBenno Rice 	(void)pending;
602694c6518SBenno Rice 	ifp = (struct ifnet *)context;
603694c6518SBenno Rice 	sc = ifp->if_softc;
604694c6518SBenno Rice 
605694c6518SBenno Rice 	SMC_LOCK(sc);
606694c6518SBenno Rice 
607694c6518SBenno Rice 	if (sc->smc_pending == NULL) {
608694c6518SBenno Rice 		SMC_UNLOCK(sc);
609694c6518SBenno Rice 		goto next_packet;
610694c6518SBenno Rice 	}
611694c6518SBenno Rice 
612694c6518SBenno Rice 	m = m0 = sc->smc_pending;
613694c6518SBenno Rice 	sc->smc_pending = NULL;
614694c6518SBenno Rice 	smc_select_bank(sc, 2);
615694c6518SBenno Rice 
616694c6518SBenno Rice 	/*
617694c6518SBenno Rice 	 * Check the allocation result.
618694c6518SBenno Rice 	 */
619694c6518SBenno Rice 	packet = smc_read_1(sc, ARR);
620694c6518SBenno Rice 
621694c6518SBenno Rice 	/*
622694c6518SBenno Rice 	 * If the allocation failed, requeue the packet and retry.
623694c6518SBenno Rice 	 */
624694c6518SBenno Rice 	if (packet & ARR_FAILED) {
625694c6518SBenno Rice 		IFQ_DRV_PREPEND(&ifp->if_snd, m);
626c0973d1fSGleb Smirnoff 		if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
627694c6518SBenno Rice 		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
628694c6518SBenno Rice 		smc_start_locked(ifp);
629694c6518SBenno Rice 		SMC_UNLOCK(sc);
630694c6518SBenno Rice 		return;
631694c6518SBenno Rice 	}
632694c6518SBenno Rice 
633694c6518SBenno Rice 	/*
634694c6518SBenno Rice 	 * Tell the device to write to our packet number.
635694c6518SBenno Rice 	 */
636694c6518SBenno Rice 	smc_write_1(sc, PNR, packet);
637694c6518SBenno Rice 	smc_write_2(sc, PTR, 0 | PTR_AUTO_INCR);
638694c6518SBenno Rice 
639694c6518SBenno Rice 	/*
640694c6518SBenno Rice 	 * Tell the device how long the packet is (including control data).
641694c6518SBenno Rice 	 */
642694c6518SBenno Rice 	len = m_length(m, 0);
643694c6518SBenno Rice 	len += PKT_CTRL_DATA_LEN;
644694c6518SBenno Rice 	smc_write_2(sc, DATA0, 0);
645694c6518SBenno Rice 	smc_write_2(sc, DATA0, len);
646694c6518SBenno Rice 
647694c6518SBenno Rice 	/*
648694c6518SBenno Rice 	 * Push the data out to the device.
649694c6518SBenno Rice 	 */
650694c6518SBenno Rice 	data = NULL;
651bd2369f6SStanislav Sedov 	last_len = 0;
652694c6518SBenno Rice 	for (; m != NULL; m = m->m_next) {
653694c6518SBenno Rice 		data = mtod(m, uint8_t *);
654694c6518SBenno Rice 		smc_write_multi_2(sc, DATA0, (uint16_t *)data, m->m_len / 2);
655bd2369f6SStanislav Sedov 		last_len = m->m_len;
656694c6518SBenno Rice 	}
657694c6518SBenno Rice 
658694c6518SBenno Rice 	/*
659694c6518SBenno Rice 	 * Push out the control byte and and the odd byte if needed.
660694c6518SBenno Rice 	 */
661694c6518SBenno Rice 	if ((len & 1) != 0 && data != NULL)
662bd2369f6SStanislav Sedov 		smc_write_2(sc, DATA0, (CTRL_ODD << 8) | data[last_len - 1]);
663694c6518SBenno Rice 	else
664694c6518SBenno Rice 		smc_write_2(sc, DATA0, 0);
665694c6518SBenno Rice 
666694c6518SBenno Rice 	/*
667694c6518SBenno Rice 	 * Unmask the TX empty interrupt.
668694c6518SBenno Rice 	 */
669694c6518SBenno Rice 	sc->smc_mask |= TX_EMPTY_INT;
670694c6518SBenno Rice 	if ((ifp->if_capenable & IFCAP_POLLING) == 0)
671694c6518SBenno Rice 		smc_write_1(sc, MSK, sc->smc_mask);
672694c6518SBenno Rice 
673694c6518SBenno Rice 	/*
674694c6518SBenno Rice 	 * Enqueue the packet.
675694c6518SBenno Rice 	 */
676694c6518SBenno Rice 	smc_mmu_wait(sc);
677694c6518SBenno Rice 	smc_write_2(sc, MMUCR, MMUCR_CMD_ENQUEUE);
6783c463a49SBenno Rice 	callout_reset(&sc->smc_watchdog, hz * 2, smc_watchdog, sc);
679694c6518SBenno Rice 
680694c6518SBenno Rice 	/*
681694c6518SBenno Rice 	 * Finish up.
682694c6518SBenno Rice 	 */
683c0973d1fSGleb Smirnoff 	if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
684694c6518SBenno Rice 	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
685694c6518SBenno Rice 	SMC_UNLOCK(sc);
686694c6518SBenno Rice 	BPF_MTAP(ifp, m0);
687694c6518SBenno Rice 	m_freem(m0);
688694c6518SBenno Rice 
689694c6518SBenno Rice next_packet:
690694c6518SBenno Rice 	/*
691694c6518SBenno Rice 	 * See if there's anything else to do.
692694c6518SBenno Rice 	 */
693694c6518SBenno Rice 	smc_start(ifp);
694694c6518SBenno Rice }
695694c6518SBenno Rice 
696694c6518SBenno Rice static void
697694c6518SBenno Rice smc_task_rx(void *context, int pending)
698694c6518SBenno Rice {
699694c6518SBenno Rice 	u_int			packet, status, len;
700694c6518SBenno Rice 	uint8_t			*data;
701694c6518SBenno Rice 	struct ifnet		*ifp;
702694c6518SBenno Rice 	struct smc_softc	*sc;
703694c6518SBenno Rice 	struct mbuf		*m, *mhead, *mtail;
704694c6518SBenno Rice 
705694c6518SBenno Rice 	(void)pending;
706694c6518SBenno Rice 	ifp = (struct ifnet *)context;
707694c6518SBenno Rice 	sc = ifp->if_softc;
708694c6518SBenno Rice 	mhead = mtail = NULL;
709694c6518SBenno Rice 
710694c6518SBenno Rice 	SMC_LOCK(sc);
711694c6518SBenno Rice 
712694c6518SBenno Rice 	packet = smc_read_1(sc, FIFO_RX);
713694c6518SBenno Rice 	while ((packet & FIFO_EMPTY) == 0) {
714694c6518SBenno Rice 		/*
715694c6518SBenno Rice 		 * Grab an mbuf and attach a cluster.
716694c6518SBenno Rice 		 */
717c6499eccSGleb Smirnoff 		MGETHDR(m, M_NOWAIT, MT_DATA);
718694c6518SBenno Rice 		if (m == NULL) {
719694c6518SBenno Rice 			break;
720694c6518SBenno Rice 		}
7212a8c860fSRobert Watson 		if (!(MCLGET(m, M_NOWAIT))) {
722694c6518SBenno Rice 			m_freem(m);
723694c6518SBenno Rice 			break;
724694c6518SBenno Rice 		}
725694c6518SBenno Rice 
726694c6518SBenno Rice 		/*
727694c6518SBenno Rice 		 * Point to the start of the packet.
728694c6518SBenno Rice 		 */
729694c6518SBenno Rice 		smc_select_bank(sc, 2);
730694c6518SBenno Rice 		smc_write_1(sc, PNR, packet);
731694c6518SBenno Rice 		smc_write_2(sc, PTR, 0 | PTR_READ | PTR_RCV | PTR_AUTO_INCR);
732694c6518SBenno Rice 
733694c6518SBenno Rice 		/*
734694c6518SBenno Rice 		 * Grab status and packet length.
735694c6518SBenno Rice 		 */
736694c6518SBenno Rice 		status = smc_read_2(sc, DATA0);
737694c6518SBenno Rice 		len = smc_read_2(sc, DATA0) & RX_LEN_MASK;
738694c6518SBenno Rice 		len -= 6;
739694c6518SBenno Rice 		if (status & RX_ODDFRM)
740694c6518SBenno Rice 			len += 1;
741694c6518SBenno Rice 
742694c6518SBenno Rice 		/*
743694c6518SBenno Rice 		 * Check for errors.
744694c6518SBenno Rice 		 */
745694c6518SBenno Rice 		if (status & (RX_TOOSHORT | RX_TOOLNG | RX_BADCRC | RX_ALGNERR)) {
746694c6518SBenno Rice 			smc_mmu_wait(sc);
747694c6518SBenno Rice 			smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE);
748c0973d1fSGleb Smirnoff 			if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
749694c6518SBenno Rice 			m_freem(m);
750694c6518SBenno Rice 			break;
751694c6518SBenno Rice 		}
752694c6518SBenno Rice 
753694c6518SBenno Rice 		/*
754694c6518SBenno Rice 		 * Set the mbuf up the way we want it.
755694c6518SBenno Rice 		 */
756694c6518SBenno Rice 		m->m_pkthdr.rcvif = ifp;
757694c6518SBenno Rice 		m->m_pkthdr.len = m->m_len = len + 2; /* XXX: Is this right? */
758694c6518SBenno Rice 		m_adj(m, ETHER_ALIGN);
759694c6518SBenno Rice 
760694c6518SBenno Rice 		/*
761694c6518SBenno Rice 		 * Pull the packet out of the device.  Make sure we're in the
762694c6518SBenno Rice 		 * right bank first as things may have changed while we were
763694c6518SBenno Rice 		 * allocating our mbuf.
764694c6518SBenno Rice 		 */
765694c6518SBenno Rice 		smc_select_bank(sc, 2);
766694c6518SBenno Rice 		smc_write_1(sc, PNR, packet);
767694c6518SBenno Rice 		smc_write_2(sc, PTR, 4 | PTR_READ | PTR_RCV | PTR_AUTO_INCR);
768694c6518SBenno Rice 		data = mtod(m, uint8_t *);
769694c6518SBenno Rice 		smc_read_multi_2(sc, DATA0, (uint16_t *)data, len >> 1);
770694c6518SBenno Rice 		if (len & 1) {
771694c6518SBenno Rice 			data += len & ~1;
772694c6518SBenno Rice 			*data = smc_read_1(sc, DATA0);
773694c6518SBenno Rice 		}
774694c6518SBenno Rice 
775694c6518SBenno Rice 		/*
776694c6518SBenno Rice 		 * Tell the device we're done.
777694c6518SBenno Rice 		 */
778694c6518SBenno Rice 		smc_mmu_wait(sc);
779694c6518SBenno Rice 		smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE);
780694c6518SBenno Rice 		if (m == NULL) {
781694c6518SBenno Rice 			break;
782694c6518SBenno Rice 		}
783694c6518SBenno Rice 
784694c6518SBenno Rice 		if (mhead == NULL) {
785694c6518SBenno Rice 			mhead = mtail = m;
786694c6518SBenno Rice 			m->m_next = NULL;
787694c6518SBenno Rice 		} else {
788694c6518SBenno Rice 			mtail->m_next = m;
789694c6518SBenno Rice 			mtail = m;
790694c6518SBenno Rice 		}
791694c6518SBenno Rice 		packet = smc_read_1(sc, FIFO_RX);
792694c6518SBenno Rice 	}
793694c6518SBenno Rice 
794694c6518SBenno Rice 	sc->smc_mask |= RCV_INT;
795694c6518SBenno Rice 	if ((ifp->if_capenable & IFCAP_POLLING) == 0)
796694c6518SBenno Rice 		smc_write_1(sc, MSK, sc->smc_mask);
797694c6518SBenno Rice 
798694c6518SBenno Rice 	SMC_UNLOCK(sc);
799694c6518SBenno Rice 
800694c6518SBenno Rice 	while (mhead != NULL) {
801694c6518SBenno Rice 		m = mhead;
802694c6518SBenno Rice 		mhead = mhead->m_next;
803694c6518SBenno Rice 		m->m_next = NULL;
804c0973d1fSGleb Smirnoff 		if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
805694c6518SBenno Rice 		(*ifp->if_input)(ifp, m);
806694c6518SBenno Rice 	}
807694c6518SBenno Rice }
808694c6518SBenno Rice 
809694c6518SBenno Rice #ifdef DEVICE_POLLING
810eb847626SNick Hibma static int
811694c6518SBenno Rice smc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
812694c6518SBenno Rice {
813694c6518SBenno Rice 	struct smc_softc	*sc;
814694c6518SBenno Rice 
815694c6518SBenno Rice 	sc = ifp->if_softc;
816694c6518SBenno Rice 
817694c6518SBenno Rice 	SMC_LOCK(sc);
818694c6518SBenno Rice 	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
819694c6518SBenno Rice 		SMC_UNLOCK(sc);
820eb847626SNick Hibma 		return (0);
821694c6518SBenno Rice 	}
822694c6518SBenno Rice 	SMC_UNLOCK(sc);
823694c6518SBenno Rice 
824694c6518SBenno Rice 	if (cmd == POLL_AND_CHECK_STATUS)
825cbc4d2dbSJohn Baldwin 		taskqueue_enqueue(sc->smc_tq, &sc->smc_intr);
826eb847626SNick Hibma         return (0);
827694c6518SBenno Rice }
828694c6518SBenno Rice #endif
829694c6518SBenno Rice 
830694c6518SBenno Rice static int
831694c6518SBenno Rice smc_intr(void *context)
832694c6518SBenno Rice {
833694c6518SBenno Rice 	struct smc_softc	*sc;
83494909337SRuslan Bukin 	uint32_t curbank;
8353c463a49SBenno Rice 
8363c463a49SBenno Rice 	sc = (struct smc_softc *)context;
83794909337SRuslan Bukin 
83894909337SRuslan Bukin 	/*
83994909337SRuslan Bukin 	 * Save current bank and restore later in this function
84094909337SRuslan Bukin 	 */
84194909337SRuslan Bukin 	curbank = (smc_read_2(sc, BSR) & BSR_BANK_MASK);
84294909337SRuslan Bukin 
84360aa1fe6SOleksandr Tymoshenko 	/*
84460aa1fe6SOleksandr Tymoshenko 	 * Block interrupts in order to let smc_task_intr to kick in
84560aa1fe6SOleksandr Tymoshenko 	 */
84694909337SRuslan Bukin 	smc_select_bank(sc, 2);
84760aa1fe6SOleksandr Tymoshenko 	smc_write_1(sc, MSK, 0);
84894909337SRuslan Bukin 
84994909337SRuslan Bukin 	/* Restore bank */
85094909337SRuslan Bukin 	smc_select_bank(sc, curbank);
85194909337SRuslan Bukin 
852cbc4d2dbSJohn Baldwin 	taskqueue_enqueue(sc->smc_tq, &sc->smc_intr);
8533c463a49SBenno Rice 	return (FILTER_HANDLED);
8543c463a49SBenno Rice }
8553c463a49SBenno Rice 
8563c463a49SBenno Rice static void
8573c463a49SBenno Rice smc_task_intr(void *context, int pending)
8583c463a49SBenno Rice {
8593c463a49SBenno Rice 	struct smc_softc	*sc;
860694c6518SBenno Rice 	struct ifnet		*ifp;
861694c6518SBenno Rice 	u_int			status, packet, counter, tcr;
862694c6518SBenno Rice 
8633c463a49SBenno Rice 	(void)pending;
864694c6518SBenno Rice 	ifp = (struct ifnet *)context;
865694c6518SBenno Rice 	sc = ifp->if_softc;
866694c6518SBenno Rice 
867694c6518SBenno Rice 	SMC_LOCK(sc);
868764e058aSBenno Rice 
869694c6518SBenno Rice 	smc_select_bank(sc, 2);
870694c6518SBenno Rice 
871694c6518SBenno Rice 	/*
872694c6518SBenno Rice 	 * Find out what interrupts are flagged.
873694c6518SBenno Rice 	 */
874694c6518SBenno Rice 	status = smc_read_1(sc, IST) & sc->smc_mask;
875694c6518SBenno Rice 
876694c6518SBenno Rice 	/*
877694c6518SBenno Rice 	 * Transmit error
878694c6518SBenno Rice 	 */
879694c6518SBenno Rice 	if (status & TX_INT) {
880694c6518SBenno Rice 		/*
881694c6518SBenno Rice 		 * Kill off the packet if there is one and re-enable transmit.
882694c6518SBenno Rice 		 */
883694c6518SBenno Rice 		packet = smc_read_1(sc, FIFO_TX);
884694c6518SBenno Rice 		if ((packet & FIFO_EMPTY) == 0) {
88594909337SRuslan Bukin 			callout_stop(&sc->smc_watchdog);
88694909337SRuslan Bukin 			smc_select_bank(sc, 2);
887694c6518SBenno Rice 			smc_write_1(sc, PNR, packet);
888694c6518SBenno Rice 			smc_write_2(sc, PTR, 0 | PTR_READ |
889694c6518SBenno Rice 			    PTR_AUTO_INCR);
89094909337SRuslan Bukin 			smc_select_bank(sc, 0);
89194909337SRuslan Bukin 			tcr = smc_read_2(sc, EPHSR);
89294909337SRuslan Bukin #if 0
893694c6518SBenno Rice 			if ((tcr & EPHSR_TX_SUC) == 0)
894694c6518SBenno Rice 				device_printf(sc->smc_dev,
895694c6518SBenno Rice 				    "bad packet\n");
89694909337SRuslan Bukin #endif
89794909337SRuslan Bukin 			smc_select_bank(sc, 2);
898694c6518SBenno Rice 			smc_mmu_wait(sc);
899694c6518SBenno Rice 			smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE_PKT);
900694c6518SBenno Rice 
901694c6518SBenno Rice 			smc_select_bank(sc, 0);
902694c6518SBenno Rice 			tcr = smc_read_2(sc, TCR);
903694c6518SBenno Rice 			tcr |= TCR_TXENA | TCR_PAD_EN;
904694c6518SBenno Rice 			smc_write_2(sc, TCR, tcr);
905694c6518SBenno Rice 			smc_select_bank(sc, 2);
906cbc4d2dbSJohn Baldwin 			taskqueue_enqueue(sc->smc_tq, &sc->smc_tx);
907694c6518SBenno Rice 		}
908694c6518SBenno Rice 
909694c6518SBenno Rice 		/*
910694c6518SBenno Rice 		 * Ack the interrupt.
911694c6518SBenno Rice 		 */
912694c6518SBenno Rice 		smc_write_1(sc, ACK, TX_INT);
913694c6518SBenno Rice 	}
914694c6518SBenno Rice 
915694c6518SBenno Rice 	/*
916694c6518SBenno Rice 	 * Receive
917694c6518SBenno Rice 	 */
918694c6518SBenno Rice 	if (status & RCV_INT) {
919694c6518SBenno Rice 		smc_write_1(sc, ACK, RCV_INT);
920694c6518SBenno Rice 		sc->smc_mask &= ~RCV_INT;
921cbc4d2dbSJohn Baldwin 		taskqueue_enqueue(sc->smc_tq, &sc->smc_rx);
922694c6518SBenno Rice 	}
923694c6518SBenno Rice 
924694c6518SBenno Rice 	/*
925694c6518SBenno Rice 	 * Allocation
926694c6518SBenno Rice 	 */
927694c6518SBenno Rice 	if (status & ALLOC_INT) {
928694c6518SBenno Rice 		smc_write_1(sc, ACK, ALLOC_INT);
929694c6518SBenno Rice 		sc->smc_mask &= ~ALLOC_INT;
930cbc4d2dbSJohn Baldwin 		taskqueue_enqueue(sc->smc_tq, &sc->smc_tx);
931694c6518SBenno Rice 	}
932694c6518SBenno Rice 
933694c6518SBenno Rice 	/*
934694c6518SBenno Rice 	 * Receive overrun
935694c6518SBenno Rice 	 */
936694c6518SBenno Rice 	if (status & RX_OVRN_INT) {
937694c6518SBenno Rice 		smc_write_1(sc, ACK, RX_OVRN_INT);
938c0973d1fSGleb Smirnoff 		if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
939694c6518SBenno Rice 	}
940694c6518SBenno Rice 
941694c6518SBenno Rice 	/*
942694c6518SBenno Rice 	 * Transmit empty
943694c6518SBenno Rice 	 */
944694c6518SBenno Rice 	if (status & TX_EMPTY_INT) {
945694c6518SBenno Rice 		smc_write_1(sc, ACK, TX_EMPTY_INT);
946694c6518SBenno Rice 		sc->smc_mask &= ~TX_EMPTY_INT;
947694c6518SBenno Rice 		callout_stop(&sc->smc_watchdog);
948694c6518SBenno Rice 
949694c6518SBenno Rice 		/*
950694c6518SBenno Rice 		 * Update collision stats.
951694c6518SBenno Rice 		 */
952694c6518SBenno Rice 		smc_select_bank(sc, 0);
953694c6518SBenno Rice 		counter = smc_read_2(sc, ECR);
954694c6518SBenno Rice 		smc_select_bank(sc, 2);
95594b0d1aeSBjoern A. Zeeb 		if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
956c0973d1fSGleb Smirnoff 		    ((counter & ECR_SNGLCOL_MASK) >> ECR_SNGLCOL_SHIFT) +
957c0973d1fSGleb Smirnoff 		    ((counter & ECR_MULCOL_MASK) >> ECR_MULCOL_SHIFT));
958694c6518SBenno Rice 
959694c6518SBenno Rice 		/*
960694c6518SBenno Rice 		 * See if there are any packets to transmit.
961694c6518SBenno Rice 		 */
962cbc4d2dbSJohn Baldwin 		taskqueue_enqueue(sc->smc_tq, &sc->smc_tx);
963694c6518SBenno Rice 	}
964694c6518SBenno Rice 
965694c6518SBenno Rice 	/*
966694c6518SBenno Rice 	 * Update the interrupt mask.
967694c6518SBenno Rice 	 */
96894909337SRuslan Bukin 	smc_select_bank(sc, 2);
969694c6518SBenno Rice 	if ((ifp->if_capenable & IFCAP_POLLING) == 0)
970694c6518SBenno Rice 		smc_write_1(sc, MSK, sc->smc_mask);
971694c6518SBenno Rice 
972694c6518SBenno Rice 	SMC_UNLOCK(sc);
973694c6518SBenno Rice }
974694c6518SBenno Rice 
9758c1093fcSMarius Strobl static uint32_t
9768c1093fcSMarius Strobl smc_mii_bitbang_read(device_t dev)
977694c6518SBenno Rice {
9788c1093fcSMarius Strobl 	struct smc_softc	*sc;
9798c1093fcSMarius Strobl 	uint32_t		val;
9808c1093fcSMarius Strobl 
9818c1093fcSMarius Strobl 	sc = device_get_softc(dev);
982694c6518SBenno Rice 
983694c6518SBenno Rice 	SMC_ASSERT_LOCKED(sc);
984694c6518SBenno Rice 	KASSERT((smc_read_2(sc, BSR) & BSR_BANK_MASK) == 3,
9858c1093fcSMarius Strobl 	    ("%s: smc_mii_bitbang_read called with bank %d (!= 3)",
986694c6518SBenno Rice 	    device_get_nameunit(sc->smc_dev),
987694c6518SBenno Rice 	    smc_read_2(sc, BSR) & BSR_BANK_MASK));
988694c6518SBenno Rice 
9898c1093fcSMarius Strobl 	val = smc_read_2(sc, MGMT);
9908c1093fcSMarius Strobl 	smc_barrier(sc, MGMT, 2,
9918c1093fcSMarius Strobl 	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
992694c6518SBenno Rice 
993694c6518SBenno Rice 	return (val);
994694c6518SBenno Rice }
995694c6518SBenno Rice 
996694c6518SBenno Rice static void
9978c1093fcSMarius Strobl smc_mii_bitbang_write(device_t dev, uint32_t val)
998694c6518SBenno Rice {
9998c1093fcSMarius Strobl 	struct smc_softc	*sc;
10008c1093fcSMarius Strobl 
10018c1093fcSMarius Strobl 	sc = device_get_softc(dev);
1002694c6518SBenno Rice 
1003694c6518SBenno Rice 	SMC_ASSERT_LOCKED(sc);
1004694c6518SBenno Rice 	KASSERT((smc_read_2(sc, BSR) & BSR_BANK_MASK) == 3,
10058c1093fcSMarius Strobl 	    ("%s: smc_mii_bitbang_write called with bank %d (!= 3)",
1006694c6518SBenno Rice 	    device_get_nameunit(sc->smc_dev),
1007694c6518SBenno Rice 	    smc_read_2(sc, BSR) & BSR_BANK_MASK));
1008694c6518SBenno Rice 
10098c1093fcSMarius Strobl 	smc_write_2(sc, MGMT, val);
10108c1093fcSMarius Strobl 	smc_barrier(sc, MGMT, 2,
10118c1093fcSMarius Strobl 	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1012694c6518SBenno Rice }
1013694c6518SBenno Rice 
1014694c6518SBenno Rice int
1015694c6518SBenno Rice smc_miibus_readreg(device_t dev, int phy, int reg)
1016694c6518SBenno Rice {
1017694c6518SBenno Rice 	struct smc_softc	*sc;
1018694c6518SBenno Rice 	int			val;
1019694c6518SBenno Rice 
1020694c6518SBenno Rice 	sc = device_get_softc(dev);
1021694c6518SBenno Rice 
1022694c6518SBenno Rice 	SMC_LOCK(sc);
1023694c6518SBenno Rice 
1024694c6518SBenno Rice 	smc_select_bank(sc, 3);
1025694c6518SBenno Rice 
10268c1093fcSMarius Strobl 	val = mii_bitbang_readreg(dev, &smc_mii_bitbang_ops, phy, reg);
1027694c6518SBenno Rice 
1028694c6518SBenno Rice 	SMC_UNLOCK(sc);
1029694c6518SBenno Rice 	return (val);
1030694c6518SBenno Rice }
1031694c6518SBenno Rice 
10328e45f0b7SAndriy Gapon int
1033694c6518SBenno Rice smc_miibus_writereg(device_t dev, int phy, int reg, int data)
1034694c6518SBenno Rice {
1035694c6518SBenno Rice 	struct smc_softc	*sc;
1036694c6518SBenno Rice 
1037694c6518SBenno Rice 	sc = device_get_softc(dev);
1038694c6518SBenno Rice 
1039694c6518SBenno Rice 	SMC_LOCK(sc);
1040694c6518SBenno Rice 
1041694c6518SBenno Rice 	smc_select_bank(sc, 3);
1042694c6518SBenno Rice 
10438c1093fcSMarius Strobl 	mii_bitbang_writereg(dev, &smc_mii_bitbang_ops, phy, reg, data);
1044694c6518SBenno Rice 
1045694c6518SBenno Rice 	SMC_UNLOCK(sc);
10468e45f0b7SAndriy Gapon 	return (0);
1047694c6518SBenno Rice }
1048694c6518SBenno Rice 
1049694c6518SBenno Rice void
1050694c6518SBenno Rice smc_miibus_statchg(device_t dev)
1051694c6518SBenno Rice {
1052694c6518SBenno Rice 	struct smc_softc	*sc;
1053694c6518SBenno Rice 	struct mii_data		*mii;
1054694c6518SBenno Rice 	uint16_t		tcr;
1055694c6518SBenno Rice 
1056694c6518SBenno Rice 	sc = device_get_softc(dev);
1057694c6518SBenno Rice 	mii = device_get_softc(sc->smc_miibus);
1058694c6518SBenno Rice 
1059694c6518SBenno Rice 	SMC_LOCK(sc);
1060694c6518SBenno Rice 
1061694c6518SBenno Rice 	smc_select_bank(sc, 0);
1062694c6518SBenno Rice 	tcr = smc_read_2(sc, TCR);
1063694c6518SBenno Rice 
1064694c6518SBenno Rice 	if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
1065694c6518SBenno Rice 		tcr |= TCR_SWFDUP;
1066694c6518SBenno Rice 	else
1067694c6518SBenno Rice 		tcr &= ~TCR_SWFDUP;
1068694c6518SBenno Rice 
1069694c6518SBenno Rice 	smc_write_2(sc, TCR, tcr);
1070694c6518SBenno Rice 
1071694c6518SBenno Rice 	SMC_UNLOCK(sc);
1072694c6518SBenno Rice }
1073694c6518SBenno Rice 
1074694c6518SBenno Rice static int
1075694c6518SBenno Rice smc_mii_ifmedia_upd(struct ifnet *ifp)
1076694c6518SBenno Rice {
1077694c6518SBenno Rice 	struct smc_softc	*sc;
1078694c6518SBenno Rice 	struct mii_data		*mii;
1079694c6518SBenno Rice 
1080694c6518SBenno Rice 	sc = ifp->if_softc;
1081694c6518SBenno Rice 	if (sc->smc_miibus == NULL)
1082694c6518SBenno Rice 		return (ENXIO);
1083694c6518SBenno Rice 
1084694c6518SBenno Rice 	mii = device_get_softc(sc->smc_miibus);
1085694c6518SBenno Rice 	return (mii_mediachg(mii));
1086694c6518SBenno Rice }
1087694c6518SBenno Rice 
1088694c6518SBenno Rice static void
1089694c6518SBenno Rice smc_mii_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1090694c6518SBenno Rice {
1091694c6518SBenno Rice 	struct smc_softc	*sc;
1092694c6518SBenno Rice 	struct mii_data		*mii;
1093694c6518SBenno Rice 
1094694c6518SBenno Rice 	sc = ifp->if_softc;
1095694c6518SBenno Rice 	if (sc->smc_miibus == NULL)
1096694c6518SBenno Rice 		return;
1097694c6518SBenno Rice 
1098694c6518SBenno Rice 	mii = device_get_softc(sc->smc_miibus);
1099694c6518SBenno Rice 	mii_pollstat(mii);
1100694c6518SBenno Rice 	ifmr->ifm_active = mii->mii_media_active;
1101694c6518SBenno Rice 	ifmr->ifm_status = mii->mii_media_status;
1102694c6518SBenno Rice }
1103694c6518SBenno Rice 
1104694c6518SBenno Rice static void
1105694c6518SBenno Rice smc_mii_tick(void *context)
1106694c6518SBenno Rice {
1107694c6518SBenno Rice 	struct smc_softc	*sc;
1108694c6518SBenno Rice 
1109694c6518SBenno Rice 	sc = (struct smc_softc *)context;
1110694c6518SBenno Rice 
1111694c6518SBenno Rice 	if (sc->smc_miibus == NULL)
1112694c6518SBenno Rice 		return;
1113694c6518SBenno Rice 
11146e482159SBenno Rice 	SMC_UNLOCK(sc);
11156e482159SBenno Rice 
1116694c6518SBenno Rice 	mii_tick(device_get_softc(sc->smc_miibus));
1117694c6518SBenno Rice 	callout_reset(&sc->smc_mii_tick_ch, hz, smc_mii_tick, sc);
1118694c6518SBenno Rice }
1119694c6518SBenno Rice 
1120694c6518SBenno Rice static void
1121694c6518SBenno Rice smc_mii_mediachg(struct smc_softc *sc)
1122694c6518SBenno Rice {
1123694c6518SBenno Rice 
1124694c6518SBenno Rice 	if (sc->smc_miibus == NULL)
1125694c6518SBenno Rice 		return;
1126694c6518SBenno Rice 	mii_mediachg(device_get_softc(sc->smc_miibus));
1127694c6518SBenno Rice }
1128694c6518SBenno Rice 
1129694c6518SBenno Rice static int
1130694c6518SBenno Rice smc_mii_mediaioctl(struct smc_softc *sc, struct ifreq *ifr, u_long command)
1131694c6518SBenno Rice {
1132694c6518SBenno Rice 	struct mii_data	*mii;
1133694c6518SBenno Rice 
1134694c6518SBenno Rice 	if (sc->smc_miibus == NULL)
1135694c6518SBenno Rice 		return (EINVAL);
1136694c6518SBenno Rice 
1137694c6518SBenno Rice 	mii = device_get_softc(sc->smc_miibus);
1138694c6518SBenno Rice 	return (ifmedia_ioctl(sc->smc_ifp, ifr, &mii->mii_media, command));
1139694c6518SBenno Rice }
1140694c6518SBenno Rice 
1141694c6518SBenno Rice static void
1142694c6518SBenno Rice smc_reset(struct smc_softc *sc)
1143694c6518SBenno Rice {
1144694c6518SBenno Rice 	u_int	ctr;
1145694c6518SBenno Rice 
1146694c6518SBenno Rice 	SMC_ASSERT_LOCKED(sc);
1147694c6518SBenno Rice 
1148694c6518SBenno Rice 	smc_select_bank(sc, 2);
1149694c6518SBenno Rice 
1150694c6518SBenno Rice 	/*
1151694c6518SBenno Rice 	 * Mask all interrupts.
1152694c6518SBenno Rice 	 */
1153694c6518SBenno Rice 	smc_write_1(sc, MSK, 0);
1154694c6518SBenno Rice 
1155694c6518SBenno Rice 	/*
1156694c6518SBenno Rice 	 * Tell the device to reset.
1157694c6518SBenno Rice 	 */
1158694c6518SBenno Rice 	smc_select_bank(sc, 0);
1159694c6518SBenno Rice 	smc_write_2(sc, RCR, RCR_SOFT_RST);
1160694c6518SBenno Rice 
1161694c6518SBenno Rice 	/*
1162694c6518SBenno Rice 	 * Set up the configuration register.
1163694c6518SBenno Rice 	 */
1164694c6518SBenno Rice 	smc_select_bank(sc, 1);
1165694c6518SBenno Rice 	smc_write_2(sc, CR, CR_EPH_POWER_EN);
1166694c6518SBenno Rice 	DELAY(1);
1167694c6518SBenno Rice 
1168694c6518SBenno Rice 	/*
1169694c6518SBenno Rice 	 * Turn off transmit and receive.
1170694c6518SBenno Rice 	 */
1171694c6518SBenno Rice 	smc_select_bank(sc, 0);
1172694c6518SBenno Rice 	smc_write_2(sc, TCR, 0);
1173694c6518SBenno Rice 	smc_write_2(sc, RCR, 0);
1174694c6518SBenno Rice 
1175694c6518SBenno Rice 	/*
1176694c6518SBenno Rice 	 * Set up the control register.
1177694c6518SBenno Rice 	 */
1178694c6518SBenno Rice 	smc_select_bank(sc, 1);
1179694c6518SBenno Rice 	ctr = smc_read_2(sc, CTR);
1180694c6518SBenno Rice 	ctr |= CTR_LE_ENABLE | CTR_AUTO_RELEASE;
1181694c6518SBenno Rice 	smc_write_2(sc, CTR, ctr);
1182694c6518SBenno Rice 
1183694c6518SBenno Rice 	/*
1184694c6518SBenno Rice 	 * Reset the MMU.
1185694c6518SBenno Rice 	 */
1186694c6518SBenno Rice 	smc_select_bank(sc, 2);
1187694c6518SBenno Rice 	smc_mmu_wait(sc);
1188694c6518SBenno Rice 	smc_write_2(sc, MMUCR, MMUCR_CMD_MMU_RESET);
1189694c6518SBenno Rice }
1190694c6518SBenno Rice 
1191694c6518SBenno Rice static void
1192694c6518SBenno Rice smc_enable(struct smc_softc *sc)
1193694c6518SBenno Rice {
1194694c6518SBenno Rice 	struct ifnet		*ifp;
1195694c6518SBenno Rice 
1196694c6518SBenno Rice 	SMC_ASSERT_LOCKED(sc);
1197694c6518SBenno Rice 	ifp = sc->smc_ifp;
1198694c6518SBenno Rice 
1199694c6518SBenno Rice 	/*
1200694c6518SBenno Rice 	 * Set up the receive/PHY control register.
1201694c6518SBenno Rice 	 */
1202694c6518SBenno Rice 	smc_select_bank(sc, 0);
1203694c6518SBenno Rice 	smc_write_2(sc, RPCR, RPCR_ANEG | (RPCR_LED_LINK_ANY << RPCR_LSA_SHIFT)
1204694c6518SBenno Rice 	    | (RPCR_LED_ACT_ANY << RPCR_LSB_SHIFT));
1205694c6518SBenno Rice 
1206694c6518SBenno Rice 	/*
1207694c6518SBenno Rice 	 * Set up the transmit and receive control registers.
1208694c6518SBenno Rice 	 */
1209694c6518SBenno Rice 	smc_write_2(sc, TCR, TCR_TXENA | TCR_PAD_EN);
1210694c6518SBenno Rice 	smc_write_2(sc, RCR, RCR_RXEN | RCR_STRIP_CRC);
1211694c6518SBenno Rice 
1212694c6518SBenno Rice 	/*
1213694c6518SBenno Rice 	 * Set up the interrupt mask.
1214694c6518SBenno Rice 	 */
1215694c6518SBenno Rice 	smc_select_bank(sc, 2);
1216694c6518SBenno Rice 	sc->smc_mask = EPH_INT | RX_OVRN_INT | RCV_INT | TX_INT;
1217694c6518SBenno Rice 	if ((ifp->if_capenable & IFCAP_POLLING) != 0)
1218694c6518SBenno Rice 		smc_write_1(sc, MSK, sc->smc_mask);
1219694c6518SBenno Rice }
1220694c6518SBenno Rice 
1221694c6518SBenno Rice static void
1222694c6518SBenno Rice smc_stop(struct smc_softc *sc)
1223694c6518SBenno Rice {
1224694c6518SBenno Rice 
1225694c6518SBenno Rice 	SMC_ASSERT_LOCKED(sc);
1226694c6518SBenno Rice 
1227694c6518SBenno Rice 	/*
12286e482159SBenno Rice 	 * Turn off callouts.
1229694c6518SBenno Rice 	 */
1230694c6518SBenno Rice 	callout_stop(&sc->smc_watchdog);
12316e482159SBenno Rice 	callout_stop(&sc->smc_mii_tick_ch);
1232694c6518SBenno Rice 
1233694c6518SBenno Rice 	/*
1234694c6518SBenno Rice 	 * Mask all interrupts.
1235694c6518SBenno Rice 	 */
1236694c6518SBenno Rice 	smc_select_bank(sc, 2);
1237694c6518SBenno Rice 	sc->smc_mask = 0;
1238694c6518SBenno Rice 	smc_write_1(sc, MSK, 0);
1239694c6518SBenno Rice #ifdef DEVICE_POLLING
1240694c6518SBenno Rice 	ether_poll_deregister(sc->smc_ifp);
1241694c6518SBenno Rice 	sc->smc_ifp->if_capenable &= ~IFCAP_POLLING;
1242694c6518SBenno Rice #endif
1243694c6518SBenno Rice 
1244694c6518SBenno Rice 	/*
1245694c6518SBenno Rice 	 * Disable transmit and receive.
1246694c6518SBenno Rice 	 */
1247694c6518SBenno Rice 	smc_select_bank(sc, 0);
1248694c6518SBenno Rice 	smc_write_2(sc, TCR, 0);
1249694c6518SBenno Rice 	smc_write_2(sc, RCR, 0);
1250694c6518SBenno Rice 
1251694c6518SBenno Rice 	sc->smc_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1252694c6518SBenno Rice }
1253694c6518SBenno Rice 
1254694c6518SBenno Rice static void
1255694c6518SBenno Rice smc_watchdog(void *arg)
1256694c6518SBenno Rice {
12573c463a49SBenno Rice 	struct smc_softc	*sc;
1258694c6518SBenno Rice 
12593c463a49SBenno Rice 	sc = (struct smc_softc *)arg;
12603c463a49SBenno Rice 	device_printf(sc->smc_dev, "watchdog timeout\n");
1261cbc4d2dbSJohn Baldwin 	taskqueue_enqueue(sc->smc_tq, &sc->smc_intr);
1262694c6518SBenno Rice }
1263694c6518SBenno Rice 
1264694c6518SBenno Rice static void
1265694c6518SBenno Rice smc_init(void *context)
1266694c6518SBenno Rice {
1267694c6518SBenno Rice 	struct smc_softc	*sc;
1268694c6518SBenno Rice 
1269694c6518SBenno Rice 	sc = (struct smc_softc *)context;
1270694c6518SBenno Rice 	SMC_LOCK(sc);
1271694c6518SBenno Rice 	smc_init_locked(sc);
1272694c6518SBenno Rice 	SMC_UNLOCK(sc);
1273694c6518SBenno Rice }
1274694c6518SBenno Rice 
1275694c6518SBenno Rice static void
1276694c6518SBenno Rice smc_init_locked(struct smc_softc *sc)
1277694c6518SBenno Rice {
1278694c6518SBenno Rice 	struct ifnet	*ifp;
1279694c6518SBenno Rice 
1280694c6518SBenno Rice 	SMC_ASSERT_LOCKED(sc);
12818a318315SStanislav Sedov 	ifp = sc->smc_ifp;
12828a318315SStanislav Sedov 	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
12838a318315SStanislav Sedov 		return;
1284694c6518SBenno Rice 
1285694c6518SBenno Rice 	smc_reset(sc);
1286694c6518SBenno Rice 	smc_enable(sc);
1287694c6518SBenno Rice 
1288694c6518SBenno Rice 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
1289694c6518SBenno Rice 	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1290694c6518SBenno Rice 
1291694c6518SBenno Rice 	smc_start_locked(ifp);
1292694c6518SBenno Rice 
1293694c6518SBenno Rice 	if (sc->smc_mii_tick != NULL)
1294694c6518SBenno Rice 		callout_reset(&sc->smc_mii_tick_ch, hz, sc->smc_mii_tick, sc);
1295694c6518SBenno Rice 
1296694c6518SBenno Rice #ifdef DEVICE_POLLING
1297694c6518SBenno Rice 	SMC_UNLOCK(sc);
1298694c6518SBenno Rice 	ether_poll_register(smc_poll, ifp);
1299694c6518SBenno Rice 	SMC_LOCK(sc);
1300694c6518SBenno Rice 	ifp->if_capenable |= IFCAP_POLLING;
1301694c6518SBenno Rice #endif
1302694c6518SBenno Rice }
1303694c6518SBenno Rice 
1304694c6518SBenno Rice static int
1305694c6518SBenno Rice smc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1306694c6518SBenno Rice {
1307694c6518SBenno Rice 	struct smc_softc	*sc;
1308694c6518SBenno Rice 	int			error;
1309694c6518SBenno Rice 
1310694c6518SBenno Rice 	sc = ifp->if_softc;
1311694c6518SBenno Rice 	error = 0;
1312694c6518SBenno Rice 
1313694c6518SBenno Rice 	switch (cmd) {
1314694c6518SBenno Rice 	case SIOCSIFFLAGS:
1315694c6518SBenno Rice 		if ((ifp->if_flags & IFF_UP) == 0 &&
1316694c6518SBenno Rice 		    (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1317694c6518SBenno Rice 			SMC_LOCK(sc);
1318694c6518SBenno Rice 			smc_stop(sc);
1319694c6518SBenno Rice 			SMC_UNLOCK(sc);
1320694c6518SBenno Rice 		} else {
1321694c6518SBenno Rice 			smc_init(sc);
1322694c6518SBenno Rice 			if (sc->smc_mii_mediachg != NULL)
1323694c6518SBenno Rice 				sc->smc_mii_mediachg(sc);
1324694c6518SBenno Rice 		}
1325694c6518SBenno Rice 		break;
1326694c6518SBenno Rice 
1327694c6518SBenno Rice 	case SIOCADDMULTI:
1328694c6518SBenno Rice 	case SIOCDELMULTI:
1329694c6518SBenno Rice 		/* XXX
1330694c6518SBenno Rice 		SMC_LOCK(sc);
1331694c6518SBenno Rice 		smc_setmcast(sc);
1332694c6518SBenno Rice 		SMC_UNLOCK(sc);
1333694c6518SBenno Rice 		*/
1334694c6518SBenno Rice 		error = EINVAL;
1335694c6518SBenno Rice 		break;
1336694c6518SBenno Rice 
1337694c6518SBenno Rice 	case SIOCGIFMEDIA:
1338694c6518SBenno Rice 	case SIOCSIFMEDIA:
1339694c6518SBenno Rice 		if (sc->smc_mii_mediaioctl == NULL) {
1340694c6518SBenno Rice 			error = EINVAL;
1341694c6518SBenno Rice 			break;
1342694c6518SBenno Rice 		}
1343694c6518SBenno Rice 		sc->smc_mii_mediaioctl(sc, (struct ifreq *)data, cmd);
1344694c6518SBenno Rice 		break;
1345694c6518SBenno Rice 
1346694c6518SBenno Rice 	default:
1347694c6518SBenno Rice 		error = ether_ioctl(ifp, cmd, data);
1348694c6518SBenno Rice 		break;
1349694c6518SBenno Rice 	}
1350694c6518SBenno Rice 
1351694c6518SBenno Rice 	return (error);
1352694c6518SBenno Rice }
1353