1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2019, 2020, 2025 Kevin Lo <kevlo@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* $OpenBSD: if_rgereg.h,v 1.15 2025/09/19 00:41:14 kevlo Exp $ */ 20 21 #ifndef __IF_RGEREG_H__ 22 #define __IF_RGEREG_H__ 23 24 #define RGE_PCI_BAR0 PCI_MAPREG_START 25 #define RGE_PCI_BAR1 (PCI_MAPREG_START + 4) 26 #define RGE_PCI_BAR2 (PCI_MAPREG_START + 8) 27 28 /* For now, a single MSI message, no multi-RX/TX ring support */ 29 #define RGE_MSI_MESSAGES 1 30 31 #define RGE_MAC0 0x0000 32 #define RGE_MAC4 0x0004 33 #define RGE_MAR0 0x0008 34 #define RGE_MAR4 0x000c 35 #define RGE_DTCCR_LO 0x0010 36 #define RGE_DTCCR_CMD (1U << 3) 37 #define RGE_DTCCR_HI 0x0014 38 #define RGE_TXDESC_ADDR_LO 0x0020 39 #define RGE_TXDESC_ADDR_HI 0x0024 40 #define RGE_INT_CFG0 0x0034 41 #define RGE_CMD 0x0037 42 #define RGE_IMR 0x0038 43 #define RGE_ISR 0x003c 44 #define RGE_TXCFG 0x0040 45 #define RGE_RXCFG 0x0044 46 #define RGE_TIMERCNT 0x0048 47 #define RGE_EECMD 0x0050 48 #define RGE_CFG0 0x0051 49 #define RGE_CFG1 0x0052 50 #define RGE_CFG2 0x0053 51 #define RGE_CFG3 0x0054 52 #define RGE_CFG4 0x0055 53 #define RGE_CFG5 0x0056 54 #define RGE_TDFNR 0x0057 55 #define RGE_TIMERINT0 0x0058 56 #define RGE_TIMERINT1 0x005c 57 #define RGE_CSIDR 0x0064 58 #define RGE_CSIAR 0x0068 59 #define RGE_PHYSTAT 0x006c 60 #define RGE_PMCH 0x006f 61 #define RGE_INT_CFG1 0x007a 62 #define RGE_EPHYAR 0x0080 63 #define RGE_TIMERINT2 0x008c 64 #define RGE_TXSTART 0x0090 65 #define RGE_MACOCP 0x00b0 66 #define RGE_PHYOCP 0x00b8 67 #define RGE_DLLPR 0x00d0 68 #define RGE_TWICMD 0x00d2 69 #define RGE_MCUCMD 0x00d3 70 #define RGE_RXMAXSIZE 0x00da 71 #define RGE_CPLUSCMD 0x00e0 72 #define RGE_IM 0x00e2 73 #define RGE_RXDESC_ADDR_LO 0x00e4 74 #define RGE_RXDESC_ADDR_HI 0x00e8 75 #define RGE_PPSW 0x00f2 76 #define RGE_TIMERINT3 0x00f4 77 #define RGE_RADMFIFO_PROTECT 0x0402 78 #define RGE_INTMITI(i) (0x0a00 + (i) * 4) 79 #define RGE_PHYBASE 0x0a40 80 #define RGE_EPHYAR_EXT_ADDR 0x0ffe 81 #define RGE_ADDR0 0x19e0 82 #define RGE_ADDR1 0x19e4 83 #define RGE_RSS_CTRL 0x4500 84 #define RGE_RXQUEUE_CTRL 0x4800 85 #define RGE_EEE_TXIDLE_TIMER 0x6048 86 87 /* Flags for register RGE_INT_CFG0 */ 88 #define RGE_INT_CFG0_EN 0x01 89 #define RGE_INT_CFG0_TIMEOUT_BYPASS 0x02 90 #define RGE_INT_CFG0_MITIGATION_BYPASS 0x04 91 #define RGE_INT_CFG0_RDU_BYPASS_8126 0x10 92 #define RGE_INT_CFG0_AVOID_MISS_INTR 0x40 93 94 /* Flags for register RGE_CMD */ 95 #define RGE_CMD_RXBUF_EMPTY 0x01 96 #define RGE_CMD_TXENB 0x04 97 #define RGE_CMD_RXENB 0x08 98 #define RGE_CMD_RESET 0x10 99 #define RGE_CMD_STOPREQ 0x80 100 101 /* Flags for register RGE_ISR */ 102 #define RGE_ISR_RX_OK 0x00000001 103 #define RGE_ISR_RX_ERR 0x00000002 104 #define RGE_ISR_TX_OK 0x00000004 105 #define RGE_ISR_TX_ERR 0x00000008 106 #define RGE_ISR_RX_DESC_UNAVAIL 0x00000010 107 #define RGE_ISR_LINKCHG 0x00000020 108 #define RGE_ISR_RX_FIFO_OFLOW 0x00000040 109 #define RGE_ISR_TX_DESC_UNAVAIL 0x00000080 110 #define RGE_ISR_SWI 0x00000100 111 #define RGE_ISR_PCS_TIMEOUT 0x00004000 112 #define RGE_ISR_SYSTEM_ERR 0x00008000 113 114 #define RGE_INTRS \ 115 (RGE_ISR_RX_OK | RGE_ISR_RX_ERR | RGE_ISR_TX_OK | \ 116 RGE_ISR_TX_ERR | RGE_ISR_LINKCHG | RGE_ISR_TX_DESC_UNAVAIL | \ 117 RGE_ISR_PCS_TIMEOUT | RGE_ISR_SYSTEM_ERR) 118 119 #define RGE_INTRS_TIMER \ 120 (RGE_ISR_RX_ERR | RGE_ISR_TX_ERR | RGE_ISR_PCS_TIMEOUT | \ 121 RGE_ISR_SYSTEM_ERR) 122 123 /* Flags for register RGE_TXCFG */ 124 #define RGE_TXCFG_HWREV 0x7cf00000 125 126 /* Flags for register RGE_RXCFG */ 127 #define RGE_RXCFG_ALLPHYS 0x00000001 128 #define RGE_RXCFG_INDIV 0x00000002 129 #define RGE_RXCFG_MULTI 0x00000004 130 #define RGE_RXCFG_BROAD 0x00000008 131 #define RGE_RXCFG_RUNT 0x00000010 132 #define RGE_RXCFG_ERRPKT 0x00000020 133 #define RGE_RXCFG_VLANSTRIP 0x00c00000 134 135 /* Flags for register RGE_EECMD */ 136 #define RGE_EECMD_WRITECFG 0xc0 137 138 /* Flags for register RGE_CFG1 */ 139 #define RGE_CFG1_PM_EN 0x01 140 #define RGE_CFG1_SPEED_DOWN 0x10 141 142 /* Flags for register RGE_CFG2 */ 143 #define RGE_CFG2_PMSTS_EN 0x20 144 #define RGE_CFG2_CLKREQ_EN 0x80 145 146 /* Flags for register RGE_CFG3 */ 147 #define RGE_CFG3_RDY_TO_L23 0x02 148 #define RGE_CFG3_WOL_LINK 0x10 149 #define RGE_CFG3_WOL_MAGIC 0x20 150 151 /* Flags for register RGE_CFG5 */ 152 #define RGE_CFG5_PME_STS 0x01 153 #define RGE_CFG5_WOL_LANWAKE 0x02 154 #define RGE_CFG5_WOL_UCAST 0x10 155 #define RGE_CFG5_WOL_MCAST 0x20 156 #define RGE_CFG5_WOL_BCAST 0x40 157 158 /* Flags for register RGE_CSIAR */ 159 #define RGE_CSIAR_BYTE_EN 0x0000000f 160 #define RGE_CSIAR_BYTE_EN_SHIFT 12 161 #define RGE_CSIAR_ADDR_MASK 0x00000fff 162 #define RGE_CSIAR_BUSY 0x80000000 163 164 /* Flags for register RGE_PHYSTAT */ 165 #define RGE_PHYSTAT_FDX 0x0001 166 #define RGE_PHYSTAT_LINK 0x0002 167 #define RGE_PHYSTAT_10MBPS 0x0004 168 #define RGE_PHYSTAT_100MBPS 0x0008 169 #define RGE_PHYSTAT_1000MBPS 0x0010 170 #define RGE_PHYSTAT_RXFLOW 0x0020 171 #define RGE_PHYSTAT_TXFLOW 0x0040 172 #define RGE_PHYSTAT_2500MBPS 0x0400 173 #define RGE_PHYSTAT_5000MBPS 0x1000 174 #define RGE_PHYSTAT_10000MBPS 0x4000 175 176 /* Flags for register RGE_EPHYAR */ 177 #define RGE_EPHYAR_DATA_MASK 0x0000ffff 178 #define RGE_EPHYAR_BUSY 0x80000000 179 #define RGE_EPHYAR_ADDR_MASK 0x0000007f 180 #define RGE_EPHYAR_ADDR_SHIFT 16 181 182 /* Flags for register RGE_TXSTART */ 183 #define RGE_TXSTART_START 0x0001 184 185 /* Flags for register RGE_MACOCP */ 186 #define RGE_MACOCP_DATA_MASK 0x0000ffff 187 #define RGE_MACOCP_BUSY 0x80000000 188 #define RGE_MACOCP_ADDR_SHIFT 16 189 190 /* Flags for register RGE_PHYOCP */ 191 #define RGE_PHYOCP_DATA_MASK 0x0000ffff 192 #define RGE_PHYOCP_BUSY 0x80000000 193 #define RGE_PHYOCP_ADDR_SHIFT 16 194 195 /* Flags for register RGE_DLLPR. */ 196 #define RGE_DLLPR_PFM_EN 0x40 197 #define RGE_DLLPR_TX_10M_PS_EN 0x80 198 199 /* Flags for register RGE_MCUCMD */ 200 #define RGE_MCUCMD_RXFIFO_EMPTY 0x10 201 #define RGE_MCUCMD_TXFIFO_EMPTY 0x20 202 #define RGE_MCUCMD_IS_OOB 0x80 203 204 /* Flags for register RGE_CPLUSCMD */ 205 #define RGE_CPLUSCMD_RXCSUM 0x0020 206 207 #define RGE_TX_NSEGS 32 208 209 #define RGE_TX_LIST_CNT 1024 210 #define RGE_RX_LIST_CNT 1024 211 212 #define RGE_ALIGN 256 213 #define RGE_TX_LIST_SZ (sizeof(struct rge_tx_desc) * RGE_TX_LIST_CNT) 214 #define RGE_RX_LIST_SZ (sizeof(struct rge_rx_desc) * RGE_RX_LIST_CNT) 215 #define RGE_NEXT_TX_DESC(x) (((x) + 1) % RGE_TX_LIST_CNT) 216 #define RGE_NEXT_RX_DESC(x) (((x) + 1) % RGE_RX_LIST_CNT) 217 #define RGE_ADDR_LO(y) ((uint64_t) (y) & 0xffffffff) 218 #define RGE_ADDR_HI(y) ((uint64_t) (y) >> 32) 219 220 #define RGE_ADV_2500TFDX 0x0080 221 #define RGE_ADV_5000TFDX 0x0100 222 #define RGE_ADV_10000TFDX 0x1000 223 224 /* Tx descriptor */ 225 struct rge_tx_desc { 226 uint32_t rge_cmdsts; 227 uint32_t rge_extsts; 228 uint64_t rge_addr; 229 uint32_t reserved[4]; 230 } __packed __aligned(16); 231 232 #define RGE_TDCMDSTS_COLL 0x000f0000 233 #define RGE_TDCMDSTS_EXCESSCOLL 0x00100000 234 #define RGE_TDCMDSTS_TXERR 0x00800000 235 #define RGE_TDCMDSTS_EOF 0x10000000 236 #define RGE_TDCMDSTS_SOF 0x20000000 237 #define RGE_TDCMDSTS_EOR 0x40000000 238 #define RGE_TDCMDSTS_OWN 0x80000000 239 240 #define RGE_TDEXTSTS_VTAG 0x00020000 241 #define RGE_TDEXTSTS_IPCSUM 0x20000000 242 #define RGE_TDEXTSTS_TCPCSUM 0x40000000 243 #define RGE_TDEXTSTS_UDPCSUM 0x80000000 244 245 /* Rx descriptor */ 246 struct rge_rx_desc { 247 union { 248 struct { 249 uint32_t rsvd0; 250 uint32_t rsvd1; 251 } rx_qword0; 252 } lo_qword0; 253 254 union { 255 struct { 256 uint32_t rss; 257 uint16_t length; 258 uint16_t hdr_info; 259 } rx_qword1; 260 261 struct { 262 uint32_t rsvd2; 263 uint32_t rsvd3; 264 } rx_qword2; 265 } lo_qword1; 266 267 union { 268 uint64_t rge_addr; 269 270 struct { 271 uint64_t timestamp; 272 } rx_timestamp; 273 274 struct { 275 uint32_t rsvd4; 276 uint32_t rsvd5; 277 } rx_qword3; 278 } hi_qword0; 279 280 union { 281 struct { 282 uint32_t rge_extsts; 283 uint32_t rge_cmdsts; 284 } rx_qword4; 285 286 struct { 287 uint16_t rsvd6; 288 uint16_t rsvd7; 289 uint32_t rsvd8; 290 } rx_ptp; 291 } hi_qword1; 292 } __packed __aligned(16); 293 294 #define RGE_RDCMDSTS_RXERRSUM 0x00100000 295 #define RGE_RDCMDSTS_EOF 0x01000000 296 #define RGE_RDCMDSTS_SOF 0x02000000 297 #define RGE_RDCMDSTS_EOR 0x40000000 298 #define RGE_RDCMDSTS_OWN 0x80000000 299 #define RGE_RDCMDSTS_FRAGLEN 0x00003fff 300 301 #define RGE_RDEXTSTS_VTAG 0x00010000 302 #define RGE_RDEXTSTS_VLAN_MASK 0x0000ffff 303 #define RGE_RDEXTSTS_TCPCSUMERR 0x01000000 304 #define RGE_RDEXTSTS_UDPCSUMERR 0x02000000 305 #define RGE_RDEXTSTS_IPCSUMERR 0x04000000 306 #define RGE_RDEXTSTS_TCPPKT 0x10000000 307 #define RGE_RDEXTSTS_UDPPKT 0x20000000 308 #define RGE_RDEXTSTS_IPV4 0x40000000 309 #define RGE_RDEXTSTS_IPV6 0x80000000 310 311 /* 312 * @brief Statistics counter structure 313 * 314 * This is the layout of the hardware structure that 315 * is populated by the hardware when RGE_DTCCR_* is 316 * appropriately poked. 317 */ 318 struct rge_hw_mac_stats { 319 uint64_t rge_tx_ok; 320 uint64_t rge_rx_ok; 321 uint64_t rge_tx_er; 322 uint32_t rge_rx_er; 323 uint16_t rge_miss_pkt; 324 uint16_t rge_fae; /* frame align errors */ 325 uint32_t rge_tx_1col; /* one collision */ 326 uint32_t rge_tx_mcol; /* multple collisions */ 327 uint64_t rge_rx_ok_phy; /* unicast */ 328 uint64_t rge_rx_ok_brd; /* broadcasts */ 329 uint32_t rge_rx_ok_mul; /* multicasts */ 330 uint16_t rge_tx_abt; 331 uint16_t rge_tx_undrn; 332 333 /* extended */ 334 uint64_t re_tx_octets; 335 uint64_t re_rx_octets; 336 uint64_t re_rx_multicast64; 337 uint64_t re_tx_unicast64; 338 uint64_t re_tx_broadcast64; 339 uint64_t re_tx_multicast64; 340 uint32_t re_tx_pause_on; 341 uint32_t re_tx_pause_off; 342 uint32_t re_tx_pause_all; 343 uint32_t re_tx_deferred; 344 uint32_t re_tx_late_collision; 345 uint32_t re_tx_all_collision; 346 uint32_t re_tx_aborted32; 347 uint32_t re_align_errors32; 348 uint32_t re_rx_frame_too_long; 349 uint32_t re_rx_runt; 350 uint32_t re_rx_pause_on; 351 uint32_t re_rx_pause_off; 352 uint32_t re_rx_pause_all; 353 uint32_t re_rx_unknown_opcode; 354 uint32_t re_rx_mac_error; 355 uint32_t re_tx_underrun32; 356 uint32_t re_rx_mac_missed; 357 uint32_t re_rx_tcam_dropped; 358 uint32_t re_tdu; 359 uint32_t re_rdu; 360 361 } __packed __aligned(sizeof(uint64_t)); 362 363 #define RGE_STATS_BUF_SIZE sizeof(struct rge_hw_mac_stats) 364 365 #define RGE_STATS_ALIGNMENT 64 366 367 /* Ram version */ 368 #define RGE_MAC_R25D_RCODE_VER 0x0027 369 #define RGE_MAC_R26_RCODE_VER 0x0033 370 #define RGE_MAC_R27_RCODE_VER 0x0036 371 #define RGE_MAC_R25_RCODE_VER 0x0b33 372 #define RGE_MAC_R25B_RCODE_VER 0x0b99 373 374 #define RGE_TIMEOUT 100 375 376 #define RGE_JUMBO_FRAMELEN 9216 377 #define RGE_JUMBO_MTU \ 378 (RGE_JUMBO_FRAMELEN - ETHER_HDR_LEN - ETHER_CRC_LEN - \ 379 ETHER_VLAN_ENCAP_LEN) 380 381 #define RGE_TXCFG_CONFIG 0x03000700 382 #define RGE_RXCFG_CONFIG 0x41000700 383 #define RGE_RXCFG_CONFIG_8125B 0x41000c00 384 #define RGE_RXCFG_CONFIG_8125D 0x41200c00 385 #define RGE_RXCFG_CONFIG_8126 0x41200d00 386 387 #endif /* __IF_RGEREG_H__ */ 388