1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2025 Adrian Chadd <adrian@FreeBSD.org>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
11 * disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 /*
30 * This is a pinmux/gpio controller for the Qualcomm IPQ/MSM/Snapdragon SoCs.
31 */
32
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/bus.h>
36
37 #include <sys/kernel.h>
38 #include <sys/module.h>
39 #include <sys/rman.h>
40 #include <sys/lock.h>
41 #include <sys/malloc.h>
42 #include <sys/mutex.h>
43 #include <sys/gpio.h>
44
45 #include <machine/bus.h>
46 #include <machine/resource.h>
47 #include <dev/gpio/gpiobusvar.h>
48
49 #include <dev/fdt/fdt_common.h>
50 #include <dev/ofw/ofw_bus.h>
51 #include <dev/ofw/ofw_bus_subr.h>
52
53 #include <dev/fdt/fdt_pinctrl.h>
54
55 #include "qcom_tlmm_var.h"
56 #include "qcom_tlmm_pin.h"
57 #include "qcom_tlmm_debug.h"
58
59 #include "gpio_if.h"
60
61 #define DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \
62 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN)
63
64 /* TODO: put in a header file */
65 extern void qcom_tlmm_ipq4018_attach(struct qcom_tlmm_softc *sc);
66
67 struct qcom_tlmm_chipset_list {
68 qcom_tlmm_chipset_t id;
69 const char *ofw_str;
70 const char *desc_str;
71 void (*attach_func)(struct qcom_tlmm_softc *);
72 };
73
74 static struct qcom_tlmm_chipset_list qcom_tlmm_chipsets[] = {
75 { QCOM_TLMM_CHIPSET_IPQ4018, "qcom,ipq4019-pinctrl",
76 "Qualcomm Atheros TLMM IPQ4018/IPQ4019 GPIO/Pinmux driver",
77 qcom_tlmm_ipq4018_attach },
78 { 0, NULL, NULL, NULL },
79 };
80
81 static int
qcom_tlmm_probe(device_t dev)82 qcom_tlmm_probe(device_t dev)
83 {
84 struct qcom_tlmm_softc *sc = device_get_softc(dev);
85 struct qcom_tlmm_chipset_list *ql;
86 int i;
87
88 if (! ofw_bus_status_okay(dev))
89 return (ENXIO);
90
91 for (i = 0; qcom_tlmm_chipsets[i].id != 0; i++) {
92 ql = &qcom_tlmm_chipsets[i];
93 device_printf(dev, "%s: checking %s\n", __func__, ql->ofw_str);
94 if (ofw_bus_is_compatible(dev, ql->ofw_str) == 1) {
95 sc->sc_chipset = ql->id;
96 sc->sc_attach_func = ql->attach_func;
97 device_set_desc(dev, ql->desc_str);
98 return (0);
99 }
100 }
101
102 return (ENXIO);
103 }
104
105 static int
qcom_tlmm_detach(device_t dev)106 qcom_tlmm_detach(device_t dev)
107 {
108 struct qcom_tlmm_softc *sc = device_get_softc(dev);
109
110 KASSERT(mtx_initialized(&sc->gpio_mtx), ("gpio mutex not initialized"));
111
112 gpiobus_detach_bus(dev);
113 if (sc->gpio_ih)
114 bus_teardown_intr(dev, sc->gpio_irq_res, sc->gpio_ih);
115 if (sc->gpio_irq_res)
116 bus_release_resource(dev, SYS_RES_IRQ, sc->gpio_irq_rid,
117 sc->gpio_irq_res);
118 if (sc->gpio_mem_res)
119 bus_release_resource(dev, SYS_RES_MEMORY, sc->gpio_mem_rid,
120 sc->gpio_mem_res);
121 if (sc->gpio_pins)
122 free(sc->gpio_pins, M_DEVBUF);
123 mtx_destroy(&sc->gpio_mtx);
124
125 return(0);
126 }
127
128 static int
qcom_tlmm_attach(device_t dev)129 qcom_tlmm_attach(device_t dev)
130 {
131 struct qcom_tlmm_softc *sc = device_get_softc(dev);
132 int i;
133
134 KASSERT((device_get_unit(dev) == 0),
135 ("qcom_tlmm: Only one gpio module supported"));
136
137 mtx_init(&sc->gpio_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
138
139 /* Map control/status registers. */
140 sc->gpio_mem_rid = 0;
141 sc->gpio_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
142 &sc->gpio_mem_rid, RF_ACTIVE);
143
144 if (sc->gpio_mem_res == NULL) {
145 device_printf(dev, "couldn't map memory\n");
146 qcom_tlmm_detach(dev);
147 return (ENXIO);
148 }
149
150 if ((sc->gpio_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
151 &sc->gpio_irq_rid, RF_SHAREABLE | RF_ACTIVE)) == NULL) {
152 device_printf(dev, "unable to allocate IRQ resource\n");
153 qcom_tlmm_detach(dev);
154 return (ENXIO);
155 }
156
157 if ((bus_setup_intr(dev, sc->gpio_irq_res, INTR_TYPE_MISC,
158 qcom_tlmm_filter, qcom_tlmm_intr, sc, &sc->gpio_ih))) {
159 device_printf(dev,
160 "WARNING: unable to register interrupt handler\n");
161 qcom_tlmm_detach(dev);
162 return (ENXIO);
163 }
164
165 sc->dev = dev;
166 sc->sc_debug = 0;
167
168 /* Call platform specific attach function */
169 sc->sc_attach_func(sc);
170
171 qcom_tlmm_debug_sysctl_attach(sc);
172
173 /* Allocate local pin state for all of our pins */
174 sc->gpio_pins = malloc(sizeof(*sc->gpio_pins) * sc->gpio_npins,
175 M_DEVBUF, M_WAITOK | M_ZERO);
176
177 /* Note: direct map between gpio pin and gpio_pin[] entry */
178 for (i = 0; i < sc->gpio_npins; i++) {
179 snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME,
180 "gpio%d", i);
181 sc->gpio_pins[i].gp_pin = i;
182 sc->gpio_pins[i].gp_caps = DEFAULT_CAPS;
183 (void) qcom_tlmm_pin_getflags(dev, i,
184 &sc->gpio_pins[i].gp_flags);
185 }
186
187 fdt_pinctrl_register(dev, NULL);
188 fdt_pinctrl_configure_by_name(dev, "default");
189
190 sc->busdev = gpiobus_add_bus(dev);
191 if (sc->busdev == NULL) {
192 device_printf(dev, "%s: failed to attach bus\n", __func__);
193 qcom_tlmm_detach(dev);
194 return (ENXIO);
195 }
196 bus_attach_children(dev);
197
198 return (0);
199 }
200
201 static device_method_t qcom_tlmm_methods[] = {
202 /* Driver */
203 DEVMETHOD(device_probe, qcom_tlmm_probe),
204 DEVMETHOD(device_attach, qcom_tlmm_attach),
205 DEVMETHOD(device_detach, qcom_tlmm_detach),
206
207 /* GPIO protocol */
208 DEVMETHOD(gpio_get_bus, qcom_tlmm_get_bus),
209 DEVMETHOD(gpio_pin_max, qcom_tlmm_pin_max),
210 DEVMETHOD(gpio_pin_getname, qcom_tlmm_pin_getname),
211 DEVMETHOD(gpio_pin_getflags, qcom_tlmm_pin_getflags),
212 DEVMETHOD(gpio_pin_getcaps, qcom_tlmm_pin_getcaps),
213 DEVMETHOD(gpio_pin_setflags, qcom_tlmm_pin_setflags),
214 DEVMETHOD(gpio_pin_get, qcom_tlmm_pin_get),
215 DEVMETHOD(gpio_pin_set, qcom_tlmm_pin_set),
216 DEVMETHOD(gpio_pin_toggle, qcom_tlmm_pin_toggle),
217
218 /* OFW */
219 DEVMETHOD(ofw_bus_get_node, qcom_tlmm_pin_get_node),
220
221 /* fdt_pinctrl interface */
222 DEVMETHOD(fdt_pinctrl_configure, qcom_tlmm_pinctrl_configure),
223
224 {0, 0},
225 };
226
227 static driver_t qcom_tlmm_driver = {
228 "gpio",
229 qcom_tlmm_methods,
230 sizeof(struct qcom_tlmm_softc),
231 };
232
233 EARLY_DRIVER_MODULE(qcom_tlmm, simplebus, qcom_tlmm_driver,
234 NULL, NULL, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);
235 EARLY_DRIVER_MODULE(qcom_tlmm, ofwbus, qcom_tlmm_driver,
236 NULL, NULL, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);
237 MODULE_VERSION(qcom_tlmm, 1);
238