1 /* SPDX-License-Identifier: BSD-2-Clause-NetBSD AND BSD-3-Clause */ 2 /* $NetBSD: qat_c2xxx.c,v 1.1 2019/11/20 09:37:46 hikaru Exp $ */ 3 4 /* 5 * Copyright (c) 2019 Internet Initiative Japan, Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Copyright(c) 2007-2013 Intel Corporation. All rights reserved. 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 37 * * Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * * Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in 41 * the documentation and/or other materials provided with the 42 * distribution. 43 * * Neither the name of Intel Corporation nor the names of its 44 * contributors may be used to endorse or promote products derived 45 * from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 48 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 49 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 50 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 51 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 52 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 53 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 54 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 55 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 56 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 57 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 58 */ 59 60 #include <sys/cdefs.h> 61 __FBSDID("$FreeBSD$"); 62 #if 0 63 __KERNEL_RCSID(0, "$NetBSD: qat_c2xxx.c,v 1.1 2019/11/20 09:37:46 hikaru Exp $"); 64 #endif 65 66 #include <sys/param.h> 67 #include <sys/bus.h> 68 #include <sys/systm.h> 69 70 #include <machine/bus.h> 71 72 #include <dev/pci/pcireg.h> 73 #include <dev/pci/pcivar.h> 74 75 #include "qatreg.h" 76 #include "qat_hw15reg.h" 77 #include "qat_c2xxxreg.h" 78 #include "qatvar.h" 79 #include "qat_hw15var.h" 80 81 static uint32_t 82 qat_c2xxx_get_accel_mask(struct qat_softc *sc) 83 { 84 uint32_t fusectl; 85 86 fusectl = pci_read_config(sc->sc_dev, FUSECTL_REG, 4); 87 88 return ((~fusectl) & ACCEL_MASK_C2XXX); 89 } 90 91 static uint32_t 92 qat_c2xxx_get_ae_mask(struct qat_softc *sc) 93 { 94 uint32_t fusectl; 95 96 fusectl = pci_read_config(sc->sc_dev, FUSECTL_REG, 4); 97 if (fusectl & ( 98 FUSECTL_C2XXX_PKE_DISABLE | 99 FUSECTL_C2XXX_ATH_DISABLE | 100 FUSECTL_C2XXX_CPH_DISABLE)) { 101 return 0; 102 } else { 103 if ((~fusectl & AE_MASK_C2XXX) == 0x3) { 104 /* 105 * With both AEs enabled we get spurious completions on 106 * ETR rings. Work around that for now by simply 107 * disabling the second AE. 108 */ 109 device_printf(sc->sc_dev, "disabling second AE\n"); 110 fusectl |= 0x2; 111 } 112 return ((~fusectl) & AE_MASK_C2XXX); 113 } 114 } 115 116 static enum qat_sku 117 qat_c2xxx_get_sku(struct qat_softc *sc) 118 { 119 uint32_t fusectl; 120 121 fusectl = pci_read_config(sc->sc_dev, FUSECTL_REG, 4); 122 123 switch (sc->sc_ae_num) { 124 case 1: 125 if (fusectl & FUSECTL_C2XXX_LOW_SKU) 126 return QAT_SKU_3; 127 else if (fusectl & FUSECTL_C2XXX_MID_SKU) 128 return QAT_SKU_2; 129 break; 130 case MAX_AE_C2XXX: 131 return QAT_SKU_1; 132 } 133 134 return QAT_SKU_UNKNOWN; 135 } 136 137 static uint32_t 138 qat_c2xxx_get_accel_cap(struct qat_softc *sc) 139 { 140 return QAT_ACCEL_CAP_CRYPTO_SYMMETRIC | 141 QAT_ACCEL_CAP_CRYPTO_ASYMMETRIC | 142 QAT_ACCEL_CAP_CIPHER | 143 QAT_ACCEL_CAP_AUTHENTICATION; 144 } 145 146 static const char * 147 qat_c2xxx_get_fw_uof_name(struct qat_softc *sc) 148 { 149 if (sc->sc_rev < QAT_REVID_C2XXX_B0) 150 return AE_FW_UOF_NAME_C2XXX_A0; 151 152 /* QAT_REVID_C2XXX_B0 and QAT_REVID_C2XXX_C0 */ 153 return AE_FW_UOF_NAME_C2XXX_B0; 154 } 155 156 static void 157 qat_c2xxx_enable_intr(struct qat_softc *sc) 158 { 159 160 qat_misc_write_4(sc, EP_SMIA_C2XXX, EP_SMIA_MASK_C2XXX); 161 } 162 163 static void 164 qat_c2xxx_init_etr_intr(struct qat_softc *sc, int bank) 165 { 166 /* 167 * For now, all rings within the bank are setup such that the generation 168 * of flag interrupts will be triggered when ring leaves the empty 169 * state. Note that in order for the ring interrupt to generate an IRQ 170 * the interrupt must also be enabled for the ring. 171 */ 172 qat_etr_bank_write_4(sc, bank, ETR_INT_SRCSEL, 173 ETR_INT_SRCSEL_MASK_0_C2XXX); 174 qat_etr_bank_write_4(sc, bank, ETR_INT_SRCSEL_2, 175 ETR_INT_SRCSEL_MASK_X_C2XXX); 176 } 177 178 const struct qat_hw qat_hw_c2xxx = { 179 .qhw_sram_bar_id = BAR_SRAM_ID_C2XXX, 180 .qhw_misc_bar_id = BAR_PMISC_ID_C2XXX, 181 .qhw_etr_bar_id = BAR_ETR_ID_C2XXX, 182 .qhw_cap_global_offset = CAP_GLOBAL_OFFSET_C2XXX, 183 .qhw_ae_offset = AE_OFFSET_C2XXX, 184 .qhw_ae_local_offset = AE_LOCAL_OFFSET_C2XXX, 185 .qhw_etr_bundle_size = ETR_BUNDLE_SIZE_C2XXX, 186 .qhw_num_banks = ETR_MAX_BANKS_C2XXX, 187 .qhw_num_ap_banks = ETR_MAX_AP_BANKS_C2XXX, 188 .qhw_num_rings_per_bank = ETR_MAX_RINGS_PER_BANK, 189 .qhw_num_accel = MAX_ACCEL_C2XXX, 190 .qhw_num_engines = MAX_AE_C2XXX, 191 .qhw_tx_rx_gap = ETR_TX_RX_GAP_C2XXX, 192 .qhw_tx_rings_mask = ETR_TX_RINGS_MASK_C2XXX, 193 .qhw_msix_ae_vec_gap = MSIX_AE_VEC_GAP_C2XXX, 194 .qhw_fw_auth = false, 195 .qhw_fw_req_size = FW_REQ_DEFAULT_SZ_HW15, 196 .qhw_fw_resp_size = FW_REQ_DEFAULT_SZ_HW15, 197 .qhw_ring_asym_tx = 2, 198 .qhw_ring_asym_rx = 3, 199 .qhw_ring_sym_tx = 4, 200 .qhw_ring_sym_rx = 5, 201 .qhw_mof_fwname = AE_FW_MOF_NAME_C2XXX, 202 .qhw_mmp_fwname = AE_FW_MMP_NAME_C2XXX, 203 .qhw_prod_type = AE_FW_PROD_TYPE_C2XXX, 204 .qhw_get_accel_mask = qat_c2xxx_get_accel_mask, 205 .qhw_get_ae_mask = qat_c2xxx_get_ae_mask, 206 .qhw_get_sku = qat_c2xxx_get_sku, 207 .qhw_get_accel_cap = qat_c2xxx_get_accel_cap, 208 .qhw_get_fw_uof_name = qat_c2xxx_get_fw_uof_name, 209 .qhw_enable_intr = qat_c2xxx_enable_intr, 210 .qhw_init_etr_intr = qat_c2xxx_init_etr_intr, 211 .qhw_init_admin_comms = qat_adm_ring_init, 212 .qhw_send_admin_init = qat_adm_ring_send_init, 213 .qhw_crypto_setup_desc = qat_hw15_crypto_setup_desc, 214 .qhw_crypto_setup_req_params = qat_hw15_crypto_setup_req_params, 215 .qhw_crypto_opaque_offset = 216 offsetof(struct fw_la_resp, comn_resp.opaque_data), 217 }; 218