1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2007-2025 Intel Corporation */ 3 /** 4 ***************************************************************************** 5 * @file icp_qat_fw_comp.h 6 * @defgroup icp_qat_fw_comp ICP QAT FW Compression Service 7 * Interface Definitions 8 * @ingroup icp_qat_fw 9 * @description 10 * This file documents structs used to provide the interface to the 11 * Compression QAT FW service 12 * 13 *****************************************************************************/ 14 15 #ifndef _ICP_QAT_FW_COMP_H_ 16 #define _ICP_QAT_FW_COMP_H_ 17 18 /* 19 ****************************************************************************** 20 * Include local header files 21 ****************************************************************************** 22 */ 23 #include "icp_qat_fw.h" 24 25 /** 26 ***************************************************************************** 27 * @ingroup icp_qat_fw_comp 28 * Definition of the Compression command types 29 * @description 30 * Enumeration which is used to indicate the ids of functions 31 * that are exposed by the Compression QAT FW service 32 * 33 *****************************************************************************/ 34 35 typedef enum { 36 ICP_QAT_FW_COMP_CMD_STATIC = 0, 37 /*!< Static Compress Request */ 38 39 ICP_QAT_FW_COMP_CMD_DYNAMIC = 1, 40 /*!< Dynamic Compress Request */ 41 42 ICP_QAT_FW_COMP_CMD_DECOMPRESS = 2, 43 /*!< Decompress Request */ 44 45 ICP_QAT_FW_COMP_CMD_DELIMITER 46 /**< Delimiter type */ 47 48 } icp_qat_fw_comp_cmd_id_t; 49 50 /* 51 * REQUEST FLAGS IN COMMON COMPRESSION 52 * In common message it is named as SERVICE SPECIFIC FLAGS. 53 * 54 * + ===== + ------ + ------ + --- + ----- + ----- + ----- + -- + ---- + --- + 55 * | Bit | 15 - 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 56 * + ===== + ------ + ----- + --- + ----- + ----- + ----- + -- + ---- + --- + 57 * | Flags | Rsvd | Dis. |Resvd| Dis. | Enh. |Auto |Sess| Rsvd | Rsvd| 58 * | | Bits | secure | =0 | Type0 | ASB |Select |Type| = 0 | = 0 | 59 * | | = 0 |RAM use | | Header | |Best | | | | 60 * | | |as intmd| | | | | | | | 61 * | | | buf | | | | | | | | 62 * + ===== + ------ + ----- + --- + ------ + ----- + ----- + -- + ---- + --- + 63 * Note: For QAT 2.0 Disable Secure Ram, DisType0 Header and Enhanced ASB bits 64 * are don't care. i.e., these features are removed from QAT 2.0. 65 */ 66 67 /**< Flag usage */ 68 69 #define ICP_QAT_FW_COMP_STATELESS_SESSION 0 70 /**< @ingroup icp_qat_fw_comp 71 * Flag representing that session is stateless */ 72 73 #define ICP_QAT_FW_COMP_STATEFUL_SESSION 1 74 /**< @ingroup icp_qat_fw_comp 75 * Flag representing that session is stateful */ 76 77 #define ICP_QAT_FW_COMP_NOT_AUTO_SELECT_BEST 0 78 /**< @ingroup icp_qat_fw_comp 79 * Flag representing that autoselectbest is NOT used */ 80 81 #define ICP_QAT_FW_COMP_AUTO_SELECT_BEST 1 82 /**< @ingroup icp_qat_fw_comp 83 * Flag representing that autoselectbest is used */ 84 85 #define ICP_QAT_FW_COMP_NOT_ENH_AUTO_SELECT_BEST 0 86 /**< @ingroup icp_qat_fw_comp 87 * Flag representing that enhanced autoselectbest is NOT used */ 88 89 #define ICP_QAT_FW_COMP_ENH_AUTO_SELECT_BEST 1 90 /**< @ingroup icp_qat_fw_comp 91 * Flag representing that enhanced autoselectbest is used */ 92 93 #define ICP_QAT_FW_COMP_NOT_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST 0 94 /**< @ingroup icp_qat_fw_comp 95 * Flag representing that enhanced autoselectbest is NOT used */ 96 97 #define ICP_QAT_FW_COMP_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST 1 98 /**< @ingroup icp_qat_fw_comp 99 * Flag representing that enhanced autoselectbest is used */ 100 101 #define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_USED_AS_INTMD_BUF 1 102 /**< @ingroup icp_qat_fw_comp 103 * Flag representing secure RAM from being used as 104 * an intermediate buffer is DISABLED. */ 105 106 #define ICP_QAT_FW_COMP_ENABLE_SECURE_RAM_USED_AS_INTMD_BUF 0 107 /**< @ingroup icp_qat_fw_comp 108 * Flag representing secure RAM from being used as 109 * an intermediate buffer is ENABLED. */ 110 111 /**< Flag mask & bit position */ 112 113 #define ICP_QAT_FW_COMP_SESSION_TYPE_BITPOS 2 114 /**< @ingroup icp_qat_fw_comp 115 * Starting bit position for the session type */ 116 117 #define ICP_QAT_FW_COMP_SESSION_TYPE_MASK 0x1 118 /**< @ingroup icp_qat_fw_comp 119 * One bit mask used to determine the session type */ 120 121 #define ICP_QAT_FW_COMP_AUTO_SELECT_BEST_BITPOS 3 122 /**< @ingroup icp_qat_fw_comp 123 * Starting bit position for auto select best */ 124 125 #define ICP_QAT_FW_COMP_AUTO_SELECT_BEST_MASK 0x1 126 /**< @ingroup icp_qat_fw_comp 127 * One bit mask for auto select best */ 128 129 #define ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_BITPOS 4 130 /**< @ingroup icp_qat_fw_comp 131 * Starting bit position for enhanced auto select best */ 132 133 #define ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_MASK 0x1 134 /**< @ingroup icp_qat_fw_comp 135 * One bit mask for enhanced auto select best */ 136 137 #define ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_BITPOS 5 138 /**< @ingroup icp_qat_fw_comp 139 * Starting bit position for disabling type zero header write back 140 when Enhanced autoselect best is enabled. If set firmware does 141 not return type0 store block header, only copies src to dest. 142 (if best output is Type0) */ 143 144 #define ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_MASK 0x1 145 /**< @ingroup icp_qat_fw_comp 146 * One bit mask for auto select best */ 147 148 #define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_BITPOS 7 149 /**< @ingroup icp_qat_fw_comp 150 * Starting bit position for flag used to disable secure ram from 151 being used as an intermediate buffer. */ 152 153 #define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_MASK 0x1 154 /**< @ingroup icp_qat_fw_comp 155 * One bit mask for disable secure ram for use as an intermediate 156 buffer. */ 157 158 /** 159 ****************************************************************************** 160 * @ingroup icp_qat_fw_comp 161 * 162 * @description 163 * Macro used for the generation of the command flags for Compression Request. 164 * This should always be used for the generation of the flags. No direct sets or 165 * masks should be performed on the flags data 166 * 167 * @param sesstype Session Type 168 * @param autoselect AutoSelectBest 169 * @enhanced_asb Enhanced AutoSelectBest 170 * @ret_uncomp RetUnCompressed 171 * @secure_ram Secure Ram usage 172 * 173 ******************************************************************************/ 174 #define ICP_QAT_FW_COMP_FLAGS_BUILD( \ 175 sesstype, autoselect, enhanced_asb, ret_uncomp, secure_ram) \ 176 (((sesstype & ICP_QAT_FW_COMP_SESSION_TYPE_MASK) \ 177 << ICP_QAT_FW_COMP_SESSION_TYPE_BITPOS) | \ 178 ((autoselect & ICP_QAT_FW_COMP_AUTO_SELECT_BEST_MASK) \ 179 << ICP_QAT_FW_COMP_AUTO_SELECT_BEST_BITPOS) | \ 180 ((enhanced_asb & ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_MASK) \ 181 << ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_BITPOS) | \ 182 ((ret_uncomp & ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_MASK) \ 183 << ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_BITPOS) | \ 184 ((secure_ram & ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_MASK) \ 185 << ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_BITPOS)) 186 187 /** 188 ****************************************************************************** 189 * @ingroup icp_qat_fw_comp 190 * 191 * @description 192 * Macro used for the generation of the command flags for Compression Request. 193 * This should always be used for the generation of the flags. No direct sets or 194 * masks should be performed on the flags data 195 * 196 * @param sesstype Session Type 197 * @param autoselect AutoSelectBest 198 * Selects between compressed and uncompressed output. 199 * No distinction made between static and dynamic 200 * compressed data. 201 * 202 *********************************************************************************/ 203 #define ICP_QAT_FW_COMP_20_FLAGS_BUILD(sesstype, autoselect) \ 204 (((sesstype & ICP_QAT_FW_COMP_SESSION_TYPE_MASK) \ 205 << ICP_QAT_FW_COMP_SESSION_TYPE_BITPOS) | \ 206 ((autoselect & ICP_QAT_FW_COMP_AUTO_SELECT_BEST_MASK) \ 207 << ICP_QAT_FW_COMP_AUTO_SELECT_BEST_BITPOS)) 208 209 /** 210 ****************************************************************************** 211 * @ingroup icp_qat_fw_comp 212 * 213 * @description 214 * Macro for extraction of the session type bit 215 * 216 * @param flags Flags to extract the session type bit from 217 * 218 *****************************************************************************/ 219 #define ICP_QAT_FW_COMP_SESSION_TYPE_GET(flags) \ 220 QAT_FIELD_GET(flags, \ 221 ICP_QAT_FW_COMP_SESSION_TYPE_BITPOS, \ 222 ICP_QAT_FW_COMP_SESSION_TYPE_MASK) 223 224 /** 225 ****************************************************************************** 226 * @ingroup icp_qat_fw_comp 227 * 228 * @description 229 * Macro for extraction of the autoSelectBest bit 230 * 231 * @param flags Flags to extract the autoSelectBest bit from 232 * 233 *****************************************************************************/ 234 #define ICP_QAT_FW_COMP_AUTO_SELECT_BEST_GET(flags) \ 235 QAT_FIELD_GET(flags, \ 236 ICP_QAT_FW_COMP_AUTO_SELECT_BEST_BITPOS, \ 237 ICP_QAT_FW_COMP_AUTO_SELECT_BEST_MASK) 238 239 /** 240 ****************************************************************************** 241 * @ingroup icp_qat_fw_comp 242 * 243 * @description 244 * Macro for extraction of the enhanced asb bit 245 * 246 * @param flags Flags to extract the enhanced asb bit from 247 * 248 *****************************************************************************/ 249 #define ICP_QAT_FW_COMP_EN_ASB_GET(flags) \ 250 QAT_FIELD_GET(flags, \ 251 ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_BITPOS, \ 252 ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_MASK) 253 254 /** 255 ****************************************************************************** 256 * @ingroup icp_qat_fw_comp 257 * 258 * @description 259 * Macro for extraction of the RetUncomp bit 260 * 261 * @param flags Flags to extract the Ret Uncomp bit from 262 * 263 *****************************************************************************/ 264 #define ICP_QAT_FW_COMP_RET_UNCOMP_GET(flags) \ 265 QAT_FIELD_GET(flags, \ 266 ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_BITPOS, \ 267 ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_MASK) 268 269 /** 270 ****************************************************************************** 271 * @ingroup icp_qat_fw_comp 272 * 273 * @description 274 * Macro for extraction of the Secure Ram usage bit 275 * 276 * @param flags Flags to extract the Secure Ram usage from 277 * 278 *****************************************************************************/ 279 #define ICP_QAT_FW_COMP_SECURE_RAM_USE_GET(flags) \ 280 QAT_FIELD_GET(flags, \ 281 ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_BITPOS, \ 282 ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_MASK) 283 284 /** 285 ***************************************************************************** 286 * @ingroup icp_qat_fw_comp 287 * Definition of the compression header cd pars block 288 * @description 289 * Definition of the compression processing cd pars block. 290 * The structure is a service-specific implementation of the common 291 * structure. 292 *****************************************************************************/ 293 typedef union icp_qat_fw_comp_req_hdr_cd_pars_s { 294 /**< LWs 2-5 */ 295 struct { 296 uint64_t content_desc_addr; 297 /**< Address of the content descriptor */ 298 299 uint16_t content_desc_resrvd1; 300 /**< Content descriptor reserved field */ 301 302 uint8_t content_desc_params_sz; 303 /**< Size of the content descriptor parameters in quad words. 304 * These parameters describe the session setup configuration 305 * info for the slices that this request relies upon i.e. the 306 * configuration word and cipher key needed by the cipher slice 307 * if there is a request for cipher processing. */ 308 309 uint8_t content_desc_hdr_resrvd2; 310 /**< Content descriptor reserved field */ 311 312 uint32_t content_desc_resrvd3; 313 /**< Content descriptor reserved field */ 314 } s; 315 316 struct { 317 uint32_t comp_slice_cfg_word[ICP_QAT_FW_NUM_LONGWORDS_2]; 318 /* Compression Slice Config Word */ 319 320 uint32_t content_desc_resrvd4; 321 /**< Content descriptor reserved field */ 322 323 } sl; 324 325 } icp_qat_fw_comp_req_hdr_cd_pars_t; 326 327 /** 328 ***************************************************************************** 329 * @ingroup icp_qat_fw_comp 330 * Definition of the compression request parameters block 331 * @description 332 * Definition of the compression processing request parameters block. 333 * The structure below forms part of the Compression + Translation 334 * Parameters block spanning LWs 14-23, thus differing from the common 335 * base Parameters block structure. Unused fields must be set to 0. 336 * 337 *****************************************************************************/ 338 typedef struct icp_qat_fw_comp_req_params_s { 339 /**< LW 14 */ 340 uint32_t comp_len; 341 /**< Size of input to process in bytes Note: Only EOP requests can be 342 * odd for decompression. IA must set LSB to zero for odd sized 343 * intermediate inputs */ 344 345 /**< LW 15 */ 346 uint32_t out_buffer_sz; 347 /**< Size of output buffer in bytes */ 348 349 /**< LW 16 */ 350 union { 351 struct { 352 /** LW 16 */ 353 uint32_t initial_crc32; 354 /**< CRC for processed bytes (input byte count) */ 355 356 /** LW 17 */ 357 uint32_t initial_adler; 358 /**< Adler for processed bytes (input byte count) */ 359 } legacy; 360 361 /** LW 16-17 */ 362 uint64_t crc_data_addr; 363 /**< CRC data structure pointer */ 364 } crc; 365 366 /**< LW 18 */ 367 uint32_t req_par_flags; 368 369 /**< LW 19 */ 370 uint32_t rsrvd; 371 372 } icp_qat_fw_comp_req_params_t; 373 374 /** 375 ****************************************************************************** 376 * @ingroup icp_qat_fw_comp 377 * 378 * @description 379 * Macro used for the generation of the request parameter flags. 380 * This should always be used for the generation of the flags. No direct sets or 381 * masks should be performed on the flags data 382 * 383 * @param sop SOP Flag, 0 restore, 1 don't restore 384 * @param eop EOP Flag, 0 restore, 1 don't restore 385 * @param bfinal Set bfinal in this block or not 386 * @param cnv Whether internal CNV check is to be performed 387 * * ICP_QAT_FW_COMP_NO_CNV 388 * * ICP_QAT_FW_COMP_CNV 389 * @param cnvnr Whether internal CNV recovery is to be performed 390 * * ICP_QAT_FW_COMP_NO_CNV_RECOVERY 391 * * ICP_QAT_FW_COMP_CNV_RECOVERY 392 * @param cnvdfx Whether CNV error injection is to be performed 393 * * ICP_QAT_FW_COMP_NO_CNV_DFX 394 * * ICP_QAT_FW_COMP_CNV_DFX 395 * @param crc CRC Mode Flag - 0 legacy, 1 crc data struct 396 *****************************************************************************/ 397 #define ICP_QAT_FW_COMP_REQ_PARAM_FLAGS_BUILD( \ 398 sop, eop, bfinal, cnv, cnvnr, cnvdfx, crc) \ 399 (((sop & ICP_QAT_FW_COMP_SOP_MASK) << ICP_QAT_FW_COMP_SOP_BITPOS) | \ 400 ((eop & ICP_QAT_FW_COMP_EOP_MASK) << ICP_QAT_FW_COMP_EOP_BITPOS) | \ 401 ((bfinal & ICP_QAT_FW_COMP_BFINAL_MASK) \ 402 << ICP_QAT_FW_COMP_BFINAL_BITPOS) | \ 403 ((cnv & ICP_QAT_FW_COMP_CNV_MASK) << ICP_QAT_FW_COMP_CNV_BITPOS) | \ 404 ((cnvnr & ICP_QAT_FW_COMP_CNVNR_MASK) \ 405 << ICP_QAT_FW_COMP_CNVNR_BITPOS) | \ 406 ((cnvdfx & ICP_QAT_FW_COMP_CNV_DFX_MASK) \ 407 << ICP_QAT_FW_COMP_CNV_DFX_BITPOS) | \ 408 ((crc & ICP_QAT_FW_COMP_CRC_MODE_MASK) \ 409 << ICP_QAT_FW_COMP_CRC_MODE_BITPOS)) 410 411 /* 412 * REQUEST FLAGS IN REQUEST PARAMETERS COMPRESSION 413 * 414 * +=====+-----+----- + --- + --- +-----+ --- + ----- + --- + ---- + -- + -- + 415 * | Bit |31-24| 20 | 19 | 18 | 17 | 16 | 15-7 | 6 | 5-2 | 1 | 0 | 416 * +=====+-----+----- + --- + ----+-----+ --- + ----- + --- + ---- + -- + -- + 417 * |Flags|Resvd|xxHash| CRC | CNV |CNVNR| CNV | Resvd |BFin | Resvd|EOP |SOP | 418 * | |=0 |acc | MODE| DFX | | | =0 | | =0 | | | 419 * | | | | | | | | | | | | | 420 * +=====+-----+----- + --- + ----+-----+ --- + ----- + --- + ---- + -- + -- + 421 */ 422 423 /** 424 ***************************************************************************** 425 * @ingroup icp_qat_fw_comp 426 * Definition of the additional QAT2.0 Compression command types 427 * @description 428 * Enumeration which is used to indicate the ids of functions 429 * that are exposed by the Compression QAT FW service 430 * 431 *****************************************************************************/ 432 typedef enum { 433 ICP_QAT_FW_COMP_20_CMD_LZ4_COMPRESS = 3, 434 /*!< LZ4 Compress Request */ 435 436 ICP_QAT_FW_COMP_20_CMD_LZ4_DECOMPRESS = 4, 437 /*!< LZ4 Decompress Request */ 438 439 ICP_QAT_FW_COMP_20_CMD_LZ4S_COMPRESS = 5, 440 /*!< LZ4S Compress Request */ 441 442 ICP_QAT_FW_COMP_20_CMD_LZ4S_DECOMPRESS = 6, 443 /*!< LZ4S Decompress Request */ 444 445 ICP_QAT_FW_COMP_20_CMD_RESERVED_1 = 7, 446 /*!< Placeholder */ 447 448 ICP_QAT_FW_COMP_20_CMD_RESERVED_2 = 8, 449 /*!< Placeholder */ 450 451 ICP_QAT_FW_COMP_20_CMD_DELIMITER 452 /**< Delimiter type */ 453 454 } icp_qat_fw_comp_20_cmd_id_t; 455 456 /* 457 * REQUEST FLAGS IN REQUEST PARAMETERS COMPRESSION 458 * 459 * + ===== + ----- + --- +-----+-------+ --- + ---------+ --- + ---- + --- + --- + 460 * | Bit | 31-20 | 19 | 18 | 17 | 16 | 15 - 7 | 6 | 5-2 | 1 | 0 | 461 * + ===== + ----- + --- +-----+-------+ --- + ---------+ --- | ---- + --- + --- + 462 * | Flags | Resvd | CRC | CNV | CNVNR | CNV |Resvd Bits|BFin |Resvd | EOP | SOP | 463 * | | =0 | Mode| DFX | | | =0 | | =0 | | | 464 * | | | | | | | | | | | | 465 * + ===== + ----- + --- +-----+-------+ --- + ---------+ --- | ---- + --- + --- + 466 */ 467 468 #define ICP_QAT_FW_COMP_NOT_SOP 0 469 /**< @ingroup icp_qat_fw_comp 470 * Flag representing that a request is NOT Start of Packet */ 471 472 #define ICP_QAT_FW_COMP_SOP 1 473 /**< @ingroup icp_qat_fw_comp 474 * * Flag representing that a request IS Start of Packet */ 475 476 #define ICP_QAT_FW_COMP_NOT_EOP 0 477 /**< @ingroup icp_qat_fw_comp 478 * Flag representing that a request is NOT Start of Packet */ 479 480 #define ICP_QAT_FW_COMP_EOP 1 481 /**< @ingroup icp_qat_fw_comp 482 * Flag representing that a request IS End of Packet */ 483 484 #define ICP_QAT_FW_COMP_NOT_BFINAL 0 485 /**< @ingroup icp_qat_fw_comp 486 * Flag representing to indicate firmware this is not the last block */ 487 488 #define ICP_QAT_FW_COMP_BFINAL 1 489 /**< @ingroup icp_qat_fw_comp 490 * Flag representing to indicate firmware this is the last block */ 491 492 #define ICP_QAT_FW_COMP_NO_CNV 0 493 /**< @ingroup icp_qat_fw_comp 494 * Flag indicating that NO cnv check is to be performed on the request */ 495 496 #define ICP_QAT_FW_COMP_CNV 1 497 /**< @ingroup icp_qat_fw_comp 498 * Flag indicating that a cnv check IS to be performed on the request */ 499 500 #define ICP_QAT_FW_COMP_NO_CNV_RECOVERY 0 501 /**< @ingroup icp_qat_fw_comp 502 * Flag indicating that NO cnv recovery is to be performed on the request */ 503 504 #define ICP_QAT_FW_COMP_CNV_RECOVERY 1 505 /**< @ingroup icp_qat_fw_comp 506 * Flag indicating that a cnv recovery is to be performed on the request */ 507 508 #define ICP_QAT_FW_COMP_NO_CNV_DFX 0 509 /**< @ingroup icp_qat_fw_comp 510 * Flag indicating that NO CNV inject error is to be performed on the request */ 511 512 #define ICP_QAT_FW_COMP_CNV_DFX 1 513 /**< @ingroup icp_qat_fw_comp 514 * Flag indicating that CNV inject error is to be performed on the request */ 515 516 #define ICP_QAT_FW_COMP_CRC_MODE_LEGACY 0 517 /**< @ingroup icp_qat_fw_comp 518 * Flag representing to use the legacy CRC mode */ 519 520 #define ICP_QAT_FW_COMP_CRC_MODE_E2E 1 521 /**< @ingroup icp_qat_fw_comp 522 * Flag representing to use the external CRC data struct */ 523 524 #define ICP_QAT_FW_COMP_NO_XXHASH_ACC 0 525 /**< @ingroup icp_qat_fw_comp 526 * * Flag indicating that xxHash will NOT be accumulated across requests */ 527 528 #define ICP_QAT_FW_COMP_XXHASH_ACC 1 529 /**< @ingroup icp_qat_fw_comp 530 * * Flag indicating that xxHash WILL be accumulated across requests */ 531 532 #define ICP_QAT_FW_COMP_PART_DECOMP 1 533 /**< @ingroup icp_qat_fw_comp 534 * * Flag indicating to perform partial de-compressing */ 535 536 #define ICP_QAT_FW_COMP_NO_PART_DECOMP 1 537 /**< @ingroup icp_qat_fw_comp 538 * * Flag indicating to not perform partial de-compressing */ 539 540 #define ICP_QAT_FW_COMP_ZEROPAD 1 541 /**< @ingroup icp_qat_fw_comp 542 * * Flag indicating to perform zero-padding in compression request */ 543 544 #define ICP_QAT_FW_COMP_NO_ZEROPAD 0 545 /**< @ingroup icp_qat_fw_comp 546 * * Flag indicating to not perform zero-padding in compression request */ 547 548 #define ICP_QAT_FW_COMP_SOP_BITPOS 0 549 /**< @ingroup icp_qat_fw_comp 550 * Starting bit position for SOP */ 551 552 #define ICP_QAT_FW_COMP_SOP_MASK 0x1 553 /**< @ingroup icp_qat_fw_comp 554 * One bit mask used to determine SOP */ 555 556 #define ICP_QAT_FW_COMP_EOP_BITPOS 1 557 /**< @ingroup icp_qat_fw_comp 558 * Starting bit position for EOP */ 559 560 #define ICP_QAT_FW_COMP_EOP_MASK 0x1 561 /**< @ingroup icp_qat_fw_comp 562 * One bit mask used to determine EOP */ 563 564 #define ICP_QAT_FW_COMP_BFINAL_MASK 0x1 565 /**< @ingroup icp_qat_fw_comp 566 * One bit mask for the bfinal bit */ 567 568 #define ICP_QAT_FW_COMP_BFINAL_BITPOS 6 569 /**< @ingroup icp_qat_fw_comp 570 * Starting bit position for the bfinal bit */ 571 572 #define ICP_QAT_FW_COMP_CNV_MASK 0x1 573 /**< @ingroup icp_qat_fw_comp 574 * One bit mask for the CNV bit */ 575 576 #define ICP_QAT_FW_COMP_CNV_BITPOS 16 577 /**< @ingroup icp_qat_fw_comp 578 * Starting bit position for the CNV bit */ 579 580 #define ICP_QAT_FW_COMP_CNVNR_MASK 0x1 581 /**< @ingroup icp_qat_fw_comp 582 * One bit mask for the CNV Recovery bit */ 583 584 #define ICP_QAT_FW_COMP_CNVNR_BITPOS 17 585 /**< @ingroup icp_qat_fw_comp 586 * Starting bit position for the CNV Recovery bit */ 587 588 #define ICP_QAT_FW_COMP_CNV_DFX_BITPOS 18 589 /**< @ingroup icp_qat_fw_comp 590 * Starting bit position for the CNV DFX bit */ 591 592 #define ICP_QAT_FW_COMP_CNV_DFX_MASK 0x1 593 /**< @ingroup icp_qat_fw_comp 594 * One bit mask for the CNV DFX bit */ 595 596 #define ICP_QAT_FW_COMP_CRC_MODE_BITPOS 19 597 /**< @ingroup icp_qat_fw_comp 598 * Starting bit position for CRC mode */ 599 600 #define ICP_QAT_FW_COMP_CRC_MODE_MASK 0x1 601 /**< @ingroup icp_qat_fw_comp 602 * One bit mask used to determine CRC mode */ 603 604 #define ICP_QAT_FW_COMP_XXHASH_ACC_MODE_BITPOS 20 605 /**< @ingroup icp_qat_fw_comp 606 * Starting bit position for xxHash accumulate mode */ 607 608 #define ICP_QAT_FW_COMP_XXHASH_ACC_MODE_MASK 0x1 609 /**< @ingroup icp_qat_fw_comp 610 * One bit mask used to determine xxHash accumulate mode */ 611 612 #define ICP_QAT_FW_COMP_PART_DECOMP_BITPOS 27 613 /**< @ingroup icp_qat_fw_comp 614 * Starting bit position for the partial de-compress bit */ 615 616 #define ICP_QAT_FW_COMP_PART_DECOMP_MASK 0x1 617 /**< @ingroup icp_qat_fw_comp 618 * Starting bit position for the partial de-compress mask */ 619 620 #define ICP_QAT_FW_COMP_ZEROPAD_BITPOS 26 621 /**< @ingroup icp_qat_fw_comp 622 * Starting bit position for the partial zero-pad bit */ 623 624 #define ICP_QAT_FW_COMP_ZEROPAD_MASK 0x1 625 /**< @ingroup icp_qat_fw_comp 626 * Starting bit position for the partial zero-pad mask */ 627 628 /** 629 ****************************************************************************** 630 * @ingroup icp_qat_fw_comp 631 * 632 * @description 633 * Macro for extraction of the SOP bit 634 * 635 * @param flags Flags to extract the SOP bit from 636 * 637 *****************************************************************************/ 638 #define ICP_QAT_FW_COMP_SOP_GET(flags) \ 639 QAT_FIELD_GET(flags, \ 640 ICP_QAT_FW_COMP_SOP_BITPOS, \ 641 ICP_QAT_FW_COMP_SOP_MASK) 642 643 /** 644 ****************************************************************************** 645 * @ingroup icp_qat_fw_comp 646 * 647 * @description 648 * Macro for extraction of the EOP bit 649 * 650 * @param flags Flags to extract the EOP bit from 651 * 652 *****************************************************************************/ 653 #define ICP_QAT_FW_COMP_EOP_GET(flags) \ 654 QAT_FIELD_GET(flags, \ 655 ICP_QAT_FW_COMP_EOP_BITPOS, \ 656 ICP_QAT_FW_COMP_EOP_MASK) 657 /** 658 659 660 ****************************************************************************** 661 * @ingroup icp_qat_fw_comp 662 * 663 * @description 664 * Macro for extraction of the bfinal bit 665 * 666 * @param flags Flags to extract the bfinal bit from 667 * 668 *****************************************************************************/ 669 #define ICP_QAT_FW_COMP_BFINAL_GET(flags) \ 670 QAT_FIELD_GET(flags, \ 671 ICP_QAT_FW_COMP_BFINAL_BITPOS, \ 672 ICP_QAT_FW_COMP_BFINAL_MASK) 673 674 /** 675 ****************************************************************************** 676 * @ingroup icp_qat_fw_comp 677 * 678 * @description 679 * Macro for extraction of the CNV bit 680 * 681 * @param flags Flag set containing the CNV flag 682 * 683 *****************************************************************************/ 684 #define ICP_QAT_FW_COMP_CNV_GET(flags) \ 685 QAT_FIELD_GET(flags, \ 686 ICP_QAT_FW_COMP_CNV_BITPOS, \ 687 ICP_QAT_FW_COMP_CNV_MASK) 688 689 /** 690 ****************************************************************************** 691 * @ingroup icp_qat_fw_comp 692 * 693 * @description 694 * Macro for extraction of the crc mode bit 695 * 696 * @param flags Flags to extract the crc mode bit from 697 * 698 ******************************************************************************/ 699 #define ICP_QAT_FW_COMP_CRC_MODE_GET(flags) \ 700 QAT_FIELD_GET(flags, \ 701 ICP_QAT_FW_COMP_CRC_MODE_BITPOS, \ 702 ICP_QAT_FW_COMP_CRC_MODE_MASK) 703 704 /** 705 ****************************************************************************** 706 * @ingroup icp_qat_fw_comp 707 * 708 * @description 709 * Macro for extraction of the xxHash accumulate mode bit 710 * 711 * @param flags Flags to extract the xxHash accumulate mode bit from 712 * 713 *****************************************************************************/ 714 #define ICP_QAT_FW_COMP_XXHASH_ACC_MODE_GET(flags) \ 715 QAT_FIELD_GET(flags, \ 716 ICP_QAT_FW_COMP_XXHASH_ACC_MODE_BITPOS, \ 717 ICP_QAT_FW_COMP_XXHASH_ACC_MODE_MASK) 718 719 /** 720 ****************************************************************************** 721 * @ingroup icp_qat_fw_comp 722 * 723 * @description 724 * Macro for setting of the xxHash accumulate mode bit 725 * 726 * @param flags Flags to set the xxHash accumulate mode bit to 727 * @param val xxHash accumulate mode to set 728 * 729 *****************************************************************************/ 730 #define ICP_QAT_FW_COMP_XXHASH_ACC_MODE_SET(flags, val) \ 731 QAT_FIELD_SET(flags, \ 732 val, \ 733 ICP_QAT_FW_COMP_XXHASH_ACC_MODE_BITPOS, \ 734 ICP_QAT_FW_COMP_XXHASH_ACC_MODE_MASK) 735 736 /** 737 ****************************************************************************** 738 * @ingroup icp_qat_fw_comp 739 * 740 * @description 741 * Macro for extraction of the partial de-compress on/off bit 742 * 743 * @param flags Flags to extract the partial de-compress on/off bit from 744 * 745 ******************************************************************************/ 746 #define ICP_QAT_FW_COMP_PART_DECOMP_GET(flags) \ 747 QAT_FIELD_GET(flags, \ 748 ICP_QAT_FW_COMP_PART_DECOMP_BITPOS, \ 749 ICP_QAT_FW_COMP_PART_DECOMP_MASK) 750 751 /** 752 ****************************************************************************** 753 * @ingroup icp_qat_fw_comp 754 * 755 * @description 756 * Macro for setting of the partial de-compress on/off bit 757 * 758 * @param flags Flags to set the partial de-compress on/off bit to 759 * @param val partial de-compress on/off bit 760 * 761 *****************************************************************************/ 762 #define ICP_QAT_FW_COMP_PART_DECOMP_SET(flags, val) \ 763 QAT_FIELD_SET(flags, \ 764 val, \ 765 ICP_QAT_FW_COMP_PART_DECOMP_BITPOS, \ 766 ICP_QAT_FW_COMP_PART_DECOMP_MASK) 767 768 /** 769 ****************************************************************************** 770 * @ingroup icp_qat_fw_comp 771 * 772 * @description 773 * Macro for extraction of the zero padding on/off bit 774 * 775 * @param flags Flags to extract the zero padding on/off bit from 776 * 777 ******************************************************************************/ 778 #define ICP_QAT_FW_COMP_ZEROPAD_GET(flags) \ 779 QAT_FIELD_GET(flags, \ 780 ICP_QAT_FW_COMP_ZEROPAD_BITPOS, \ 781 ICP_QAT_FW_COMP_ZEROPAD_MASK) 782 783 /** 784 ****************************************************************************** 785 * @ingroup icp_qat_fw_comp 786 * 787 * @description 788 * Macro for setting of the zero-padding on/off bit 789 * 790 * @param flags Flags to set the zero-padding on/off bit to 791 * @param val zero-padding on/off bit 792 * 793 *****************************************************************************/ 794 #define ICP_QAT_FW_COMP_ZEROPAD_SET(flags, val) \ 795 QAT_FIELD_SET(flags, \ 796 val, \ 797 ICP_QAT_FW_COMP_ZEROPAD_BITPOS, \ 798 ICP_QAT_FW_COMP_ZEROPAD_MASK) 799 800 /** 801 ****************************************************************************** 802 * @ingroup icp_qat_fw_comp 803 * Definition of the translator request parameters block 804 * @description 805 * Definition of the translator processing request parameters block 806 * The structure below forms part of the Compression + Translation 807 * Parameters block spanning LWs 14-23, thus differing from the common 808 * base Parameters block structure. Unused fields must be set to 0. 809 * 810 *****************************************************************************/ 811 typedef struct icp_qat_fw_xlt_req_params_s { 812 /**< LWs 20-21 */ 813 uint64_t inter_buff_ptr; 814 /**< This field specifies the physical address of an intermediate 815 * buffer SGL array. The array contains a pair of 64-bit 816 * intermediate buffer pointers to SGL buffer descriptors, one pair 817 * per CPM. Please refer to the CPM1.6 Firmware Interface HLD 818 * specification for more details. */ 819 820 } icp_qat_fw_xlt_req_params_t; 821 822 /** 823 ***************************************************************************** 824 * @ingroup icp_qat_fw_comp 825 * Compression header of the content descriptor block 826 * @description 827 * Definition of the service-specific compression control block header 828 * structure. The compression parameters are defined per algorithm 829 * and are located in the icp_qat_hw.h file. This compression 830 * cd block spans LWs 24-29, forming part of the compression + translation 831 * cd block, thus differing from the common base content descriptor 832 * structure. 833 * 834 *****************************************************************************/ 835 typedef struct icp_qat_fw_comp_cd_hdr_s { 836 /**< LW 24 */ 837 uint16_t ram_bank_flags; 838 /**< Flags to show which ram banks to access */ 839 840 uint8_t comp_cfg_offset; 841 /**< Quad word offset from the content descriptor parameters address to 842 * the parameters for the compression processing */ 843 844 uint8_t next_curr_id; 845 /**< This field combines the next and current id (each four bits) - 846 * the next id is the most significant nibble. 847 * Next Id: Set to the next slice to pass the compressed data through. 848 * Set to ICP_QAT_FW_SLICE_DRAM_WR if the data is not to go through 849 * anymore slices after compression 850 * Current Id: Initialised with the compression slice type */ 851 852 /**< LW 25 */ 853 uint32_t resrvd; 854 855 /**< LWs 26-27 */ 856 uint64_t comp_state_addr; 857 /**< Pointer to compression state */ 858 859 /**< LWs 28-29 */ 860 uint64_t ram_banks_addr; 861 /**< Pointer to banks */ 862 863 } icp_qat_fw_comp_cd_hdr_t; 864 865 #define COMP_CPR_INITIAL_CRC 0 866 #define COMP_CPR_INITIAL_ADLER 1 867 868 /** 869 ***************************************************************************** 870 * @ingroup icp_qat_fw_comp 871 * Translator content descriptor header block 872 * @description 873 * Definition of the structure used to describe the translation processing 874 * to perform on data. The translator parameters are defined per algorithm 875 * and are located in the icp_qat_hw.h file. This translation cd block 876 * spans LWs 30-31, forming part of the compression + translation cd block, 877 * thus differing from the common base content descriptor structure. 878 * 879 *****************************************************************************/ 880 typedef struct icp_qat_fw_xlt_cd_hdr_s { 881 /**< LW 30 */ 882 uint16_t resrvd1; 883 /**< Reserved field and assumed set to 0 */ 884 885 uint8_t resrvd2; 886 /**< Reserved field and assumed set to 0 */ 887 888 uint8_t next_curr_id; 889 /**< This field combines the next and current id (each four bits) - 890 * the next id is the most significant nibble. 891 * Next Id: Set to the next slice to pass the translated data through. 892 * Set to ICP_QAT_FW_SLICE_DRAM_WR if the data is not to go through 893 * any more slices after compression 894 * Current Id: Initialised with the translation slice type */ 895 896 /**< LW 31 */ 897 uint32_t resrvd3; 898 /**< Reserved and should be set to zero, needed for quadword alignment 899 */ 900 901 } icp_qat_fw_xlt_cd_hdr_t; 902 903 /** 904 ***************************************************************************** 905 * @ingroup icp_qat_fw_comp 906 * Definition of the common Compression QAT FW request 907 * @description 908 * This is a definition of the full request structure for 909 * compression and translation. 910 * 911 *****************************************************************************/ 912 typedef struct icp_qat_fw_comp_req_s { 913 /**< LWs 0-1 */ 914 icp_qat_fw_comn_req_hdr_t comn_hdr; 915 /**< Common request header - for Service Command Id, 916 * use service-specific Compression Command Id. 917 * Service Specific Flags - use Compression Command Flags */ 918 919 /**< LWs 2-5 */ 920 icp_qat_fw_comp_req_hdr_cd_pars_t cd_pars; 921 /**< Compression service-specific content descriptor field which points 922 * either to a content descriptor parameter block or contains the 923 * compression slice config word. */ 924 925 /**< LWs 6-13 */ 926 icp_qat_fw_comn_req_mid_t comn_mid; 927 /**< Common request middle section */ 928 929 /**< LWs 14-19 */ 930 icp_qat_fw_comp_req_params_t comp_pars; 931 /**< Compression request Parameters block */ 932 933 /**< LWs 20-21 */ 934 union { 935 icp_qat_fw_xlt_req_params_t xlt_pars; 936 /**< Translation request Parameters block */ 937 938 uint32_t resrvd1[ICP_QAT_FW_NUM_LONGWORDS_2]; 939 /**< Reserved if not used for translation */ 940 941 struct { 942 uint32_t partial_decompress_length; 943 /**< LW 20 \n Length of the decompressed data to return 944 */ 945 946 uint32_t partial_decompress_offset; 947 /**< LW 21 \n Offset of the decompressed data at which 948 * to return */ 949 950 } partial_decompress; 951 952 } u1; 953 954 /**< LWs 22-23 */ 955 union { 956 uint32_t resrvd2[ICP_QAT_FW_NUM_LONGWORDS_2]; 957 /**< Reserved - not used if Batch and Pack is disabled.*/ 958 959 uint64_t resrvd3; 960 /**< Reserved - not used if Batch and Pack is disabled.*/ 961 } u3; 962 963 /**< LWs 24-29 */ 964 icp_qat_fw_comp_cd_hdr_t comp_cd_ctrl; 965 /**< Compression request content descriptor control 966 * block header */ 967 968 /**< LWs 30-31 */ 969 union { 970 icp_qat_fw_xlt_cd_hdr_t xlt_cd_ctrl; 971 /**< Translation request content descriptor 972 * control block header */ 973 974 uint32_t resrvd3[ICP_QAT_FW_NUM_LONGWORDS_2]; 975 /**< Reserved if not used for translation */ 976 977 } u2; 978 979 } icp_qat_fw_comp_req_t; 980 981 /** 982 ***************************************************************************** 983 * @ingroup icp_qat_fw_comp 984 * Definition of the compression QAT FW response descriptor parameters 985 * @description 986 * This part of the response is specific to the compression response. 987 * 988 *****************************************************************************/ 989 typedef struct icp_qat_fw_resp_comp_pars_s { 990 /**< LW 4 */ 991 uint32_t input_byte_counter; 992 /**< Input byte counter */ 993 994 /**< LW 5 */ 995 uint32_t output_byte_counter; 996 /**< Output byte counter */ 997 998 /** LW 6-7 */ 999 union { 1000 struct { 1001 /** LW 6 */ 1002 uint32_t curr_crc32; 1003 /**< Current CRC32 */ 1004 1005 /** LW 7 */ 1006 uint32_t curr_adler_32; 1007 /**< Current Adler32 */ 1008 } legacy; 1009 1010 uint32_t resrvd[ICP_QAT_FW_NUM_LONGWORDS_2]; 1011 /**< Reserved if not in legacy mode */ 1012 } crc; 1013 1014 } icp_qat_fw_resp_comp_pars_t; 1015 1016 /** 1017 ***************************************************************************** 1018 * @ingroup icp_qat_fw_comp 1019 * Definition of the Compression Eagle Tail Response 1020 * @description 1021 * This is the response delivered to the ET rings by the Compression 1022 * QAT FW service for all commands 1023 * 1024 *****************************************************************************/ 1025 typedef struct icp_qat_fw_comp_resp_s { 1026 /**< LWs 0-1 */ 1027 icp_qat_fw_comn_resp_hdr_t comn_resp; 1028 /**< Common interface response format see icp_qat_fw.h */ 1029 1030 /**< LWs 2-3 */ 1031 uint64_t opaque_data; 1032 /**< Opaque data passed from the request to the response message */ 1033 1034 /**< LWs 4-7 */ 1035 icp_qat_fw_resp_comp_pars_t comp_resp_pars; 1036 /**< Common response params (checksums and byte counts) */ 1037 1038 } icp_qat_fw_comp_resp_t; 1039 1040 /* RAM Bank defines */ 1041 #define QAT_FW_COMP_BANK_FLAG_MASK 0x1 1042 1043 #define QAT_FW_COMP_BANK_I_BITPOS 8 1044 #define QAT_FW_COMP_BANK_H_BITPOS 7 1045 #define QAT_FW_COMP_BANK_G_BITPOS 6 1046 #define QAT_FW_COMP_BANK_F_BITPOS 5 1047 #define QAT_FW_COMP_BANK_E_BITPOS 4 1048 #define QAT_FW_COMP_BANK_D_BITPOS 3 1049 #define QAT_FW_COMP_BANK_C_BITPOS 2 1050 #define QAT_FW_COMP_BANK_B_BITPOS 1 1051 #define QAT_FW_COMP_BANK_A_BITPOS 0 1052 1053 /** 1054 ***************************************************************************** 1055 * @ingroup icp_qat_fw_comp 1056 * Definition of the ram bank enabled values 1057 * @description 1058 * Enumeration used to define whether a ram bank is enabled or not 1059 * 1060 *****************************************************************************/ 1061 typedef enum { 1062 ICP_QAT_FW_COMP_BANK_DISABLED = 0, /*!< BANK DISABLED */ 1063 ICP_QAT_FW_COMP_BANK_ENABLED = 1, /*!< BANK ENABLED */ 1064 ICP_QAT_FW_COMP_BANK_DELIMITER = 2 /**< Delimiter type */ 1065 1066 } icp_qat_fw_comp_bank_enabled_t; 1067 1068 /** 1069 ****************************************************************************** 1070 * @ingroup icp_qat_fw_comp 1071 * 1072 * @description 1073 * Build the ram bank flags in the compression content descriptor 1074 * which specify which banks are used to save history 1075 * 1076 * @param bank_i_enable 1077 * @param bank_h_enable 1078 * @param bank_g_enable 1079 * @param bank_f_enable 1080 * @param bank_e_enable 1081 * @param bank_d_enable 1082 * @param bank_c_enable 1083 * @param bank_b_enable 1084 * @param bank_a_enable 1085 *****************************************************************************/ 1086 #define ICP_QAT_FW_COMP_RAM_FLAGS_BUILD(bank_i_enable, \ 1087 bank_h_enable, \ 1088 bank_g_enable, \ 1089 bank_f_enable, \ 1090 bank_e_enable, \ 1091 bank_d_enable, \ 1092 bank_c_enable, \ 1093 bank_b_enable, \ 1094 bank_a_enable) \ 1095 ((((bank_i_enable)&QAT_FW_COMP_BANK_FLAG_MASK) \ 1096 << QAT_FW_COMP_BANK_I_BITPOS) | \ 1097 (((bank_h_enable)&QAT_FW_COMP_BANK_FLAG_MASK) \ 1098 << QAT_FW_COMP_BANK_H_BITPOS) | \ 1099 (((bank_g_enable)&QAT_FW_COMP_BANK_FLAG_MASK) \ 1100 << QAT_FW_COMP_BANK_G_BITPOS) | \ 1101 (((bank_f_enable)&QAT_FW_COMP_BANK_FLAG_MASK) \ 1102 << QAT_FW_COMP_BANK_F_BITPOS) | \ 1103 (((bank_e_enable)&QAT_FW_COMP_BANK_FLAG_MASK) \ 1104 << QAT_FW_COMP_BANK_E_BITPOS) | \ 1105 (((bank_d_enable)&QAT_FW_COMP_BANK_FLAG_MASK) \ 1106 << QAT_FW_COMP_BANK_D_BITPOS) | \ 1107 (((bank_c_enable)&QAT_FW_COMP_BANK_FLAG_MASK) \ 1108 << QAT_FW_COMP_BANK_C_BITPOS) | \ 1109 (((bank_b_enable)&QAT_FW_COMP_BANK_FLAG_MASK) \ 1110 << QAT_FW_COMP_BANK_B_BITPOS) | \ 1111 (((bank_a_enable)&QAT_FW_COMP_BANK_FLAG_MASK) \ 1112 << QAT_FW_COMP_BANK_A_BITPOS)) 1113 1114 /** 1115 ***************************************************************************** 1116 * @ingroup icp_qat_fw_comp 1117 * Definition of the xxhash32 acc state buffer 1118 * @description 1119 * This is data structure used in stateful lite for xxhash32 1120 * 1121 *****************************************************************************/ 1122 typedef struct xxhash_acc_state_buff_s { 1123 /**< LW 0 */ 1124 uint32_t in_counter; 1125 /**< Accumulated (total) consumed bytes. As oppose to the per request 1126 * IBC in the response.*/ 1127 1128 /**< LW 1 */ 1129 uint32_t out_counter; 1130 /**< OBC as in the response.*/ 1131 1132 /**< LW 2-5 */ 1133 uint32_t xxhash_state[4]; 1134 /**< Initial value is set by IA to the values stated in HAS.*/ 1135 1136 /**< LW 6-9 */ 1137 uint32_t clear_txt[4]; 1138 /**< Set to 0 for the first request.*/ 1139 } xxhash_acc_state_buff_t; 1140 1141 #endif /* _ICP_QAT_FW_COMP_H_ */ 1142