1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2007-2022 Intel Corporation */ 3 /* $FreeBSD$ */ 4 #ifndef ADF_GEN4VF_HW_CSR_DATA_H_ 5 #define ADF_GEN4VF_HW_CSR_DATA_H_ 6 7 #define ADF_RING_CSR_ADDR_OFFSET_GEN4VF 0x0 8 #define ADF_RING_BUNDLE_SIZE_GEN4 0x2000 9 #define ADF_RING_CSR_RING_HEAD 0x0C0 10 #define ADF_RING_CSR_RING_TAIL 0x100 11 #define ADF_RING_CSR_E_STAT 0x14C 12 #define ADF_RING_CSR_RING_CONFIG_GEN4 0x1000 13 #define ADF_RING_CSR_RING_LBASE_GEN4 0x1040 14 #define ADF_RING_CSR_RING_UBASE_GEN4 0x1080 15 #define ADF_RING_CSR_INT_FLAG 0x170 16 #define ADF_RING_CSR_INT_FLAG_AND_COL 0x184 17 #define ADF_RING_CSR_NEXT_INT_SRCSEL 0x4 18 #define ADF_RING_CSR_INT_SRCSEL 0x174 19 #define ADF_RING_CSR_INT_COL_EN 0x17C 20 #define ADF_RING_CSR_INT_COL_CTL 0x180 21 #define ADF_RING_CSR_RING_SRV_ARB_EN 0x19C 22 #define ADF_BANK_INT_SRC_SEL_MASK_GEN4 0x44UL 23 #define ADF_RING_CSR_INT_COL_CTL_ENABLE 0x80000000 24 #define ADF_BANK_INT_FLAG_CLEAR_MASK_GEN4 0x3 25 #define ADF_RINGS_PER_INT_SRCSEL_GEN4 2 26 27 #define BUILD_RING_BASE_ADDR_GEN4(addr, size) \ 28 ((((addr) >> 6) & (0xFFFFFFFFFFFFFFFFULL << (size))) << 6) 29 #define READ_CSR_RING_HEAD_GEN4VF(csr_base_addr, bank, ring) \ 30 ADF_CSR_RD((csr_base_addr), \ 31 (ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \ 32 ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \ 33 ADF_RING_CSR_RING_HEAD + ((ring) << 2)) 34 #define READ_CSR_RING_TAIL_GEN4VF(csr_base_addr, bank, ring) \ 35 ADF_CSR_RD((csr_base_addr), \ 36 (ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \ 37 ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \ 38 ADF_RING_CSR_RING_TAIL + ((ring) << 2)) 39 #define READ_CSR_E_STAT_GEN4VF(csr_base_addr, bank) \ 40 ADF_CSR_RD((csr_base_addr), \ 41 (ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \ 42 ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \ 43 ADF_RING_CSR_E_STAT) 44 #define WRITE_CSR_RING_CONFIG_GEN4VF(csr_base_addr, bank, ring, value) \ 45 ADF_CSR_WR((csr_base_addr), \ 46 (ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \ 47 ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \ 48 ADF_RING_CSR_RING_CONFIG_GEN4 + ((ring) << 2), \ 49 (value)) 50 #define WRITE_CSR_RING_BASE_GEN4VF(csr_base_addr, bank, ring, value) \ 51 do { \ 52 struct resource *_csr_base_addr = csr_base_addr; \ 53 u32 _bank = bank; \ 54 u32 _ring = ring; \ 55 dma_addr_t _value = value; \ 56 u32 l_base = 0, u_base = 0; \ 57 l_base = (u32)((_value)&0xFFFFFFFF); \ 58 u_base = (u32)(((_value)&0xFFFFFFFF00000000ULL) >> 32); \ 59 ADF_CSR_WR((_csr_base_addr), \ 60 (ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \ 61 ADF_RING_BUNDLE_SIZE_GEN4 * (_bank)) + \ 62 ADF_RING_CSR_RING_LBASE_GEN4 + ((_ring) << 2), \ 63 l_base); \ 64 ADF_CSR_WR((_csr_base_addr), \ 65 (ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \ 66 ADF_RING_BUNDLE_SIZE_GEN4 * (_bank)) + \ 67 ADF_RING_CSR_RING_UBASE_GEN4 + ((_ring) << 2), \ 68 u_base); \ 69 } while (0) 70 71 static inline u64 72 read_base_gen4vf(struct resource *csr_base_addr, u32 bank, u32 ring) 73 { 74 u32 l_base, u_base; 75 u64 addr; 76 77 l_base = ADF_CSR_RD(csr_base_addr, 78 (ADF_RING_BUNDLE_SIZE_GEN4 * bank) + 79 ADF_RING_CSR_RING_LBASE_GEN4 + (ring << 2)); 80 u_base = ADF_CSR_RD(csr_base_addr, 81 (ADF_RING_BUNDLE_SIZE_GEN4 * bank) + 82 ADF_RING_CSR_RING_UBASE_GEN4 + (ring << 2)); 83 84 addr = (u64)l_base & 0x00000000FFFFFFFFULL; 85 addr |= (u64)u_base << 32 & 0xFFFFFFFF00000000ULL; 86 87 return addr; 88 } 89 90 #define WRITE_CSR_INT_SRCSEL_GEN4VF(csr_base_addr, bank) \ 91 ADF_CSR_WR((csr_base_addr), \ 92 ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \ 93 ADF_RING_BUNDLE_SIZE_GEN4 * (bank) + \ 94 ADF_RING_CSR_INT_SRCSEL, \ 95 ADF_BANK_INT_SRC_SEL_MASK_GEN4) 96 97 #define READ_CSR_RING_BASE_GEN4VF(csr_base_addr, bank, ring) \ 98 read_base_gen4vf((csr_base_addr), (bank), (ring)) 99 100 #define WRITE_CSR_RING_HEAD_GEN4VF(csr_base_addr, bank, ring, value) \ 101 ADF_CSR_WR((csr_base_addr), \ 102 (ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \ 103 ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \ 104 ADF_RING_CSR_RING_HEAD + ((ring) << 2), \ 105 (value)) 106 #define WRITE_CSR_RING_TAIL_GEN4VF(csr_base_addr, bank, ring, value) \ 107 ADF_CSR_WR((csr_base_addr), \ 108 (ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \ 109 ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \ 110 ADF_RING_CSR_RING_TAIL + ((ring) << 2), \ 111 (value)) 112 #define WRITE_CSR_INT_FLAG_GEN4VF(csr_base_addr, bank, value) \ 113 ADF_CSR_WR((csr_base_addr), \ 114 (ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \ 115 ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \ 116 ADF_RING_CSR_INT_FLAG, \ 117 (value)) 118 #define WRITE_CSR_INT_COL_EN_GEN4VF(csr_base_addr, bank, value) \ 119 ADF_CSR_WR((csr_base_addr), \ 120 (ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \ 121 ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \ 122 ADF_RING_CSR_INT_COL_EN, \ 123 (value)) 124 #define WRITE_CSR_INT_COL_CTL_GEN4VF(csr_base_addr, bank, value) \ 125 ADF_CSR_WR((csr_base_addr), \ 126 (ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \ 127 ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \ 128 ADF_RING_CSR_INT_COL_CTL, \ 129 (value)) 130 #define WRITE_CSR_INT_FLAG_AND_COL_GEN4VF(csr_base_addr, bank, value) \ 131 ADF_CSR_WR((csr_base_addr), \ 132 (ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \ 133 ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \ 134 ADF_RING_CSR_INT_FLAG_AND_COL, \ 135 (value)) 136 #define READ_CSR_RING_SRV_ARB_EN_GEN4VF(csr_base_addr, bank) \ 137 ADF_CSR_RD((csr_base_addr), \ 138 (ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \ 139 ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \ 140 ADF_RING_CSR_RING_SRV_ARB_EN) 141 #define WRITE_CSR_RING_SRV_ARB_EN_GEN4VF(csr_base_addr, bank, value) \ 142 ADF_CSR_WR((csr_base_addr), \ 143 (ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \ 144 ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \ 145 ADF_RING_CSR_RING_SRV_ARB_EN, \ 146 (value)) 147 148 struct adf_hw_csr_info; 149 void gen4vf_init_hw_csr_info(struct adf_hw_csr_info *csr_info); 150 151 #endif /* ADF_GEN4VF_HW_CSR_DATA_H_ */ 152