1 /* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $Id: pci.c,v 1.86 1998/09/06 22:41:41 tegge Exp $ 27 * 28 */ 29 30 #include "pci.h" 31 #if NPCI > 0 32 33 #include "opt_devfs.h" 34 #include "opt_simos.h" 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/malloc.h> 39 #include <sys/fcntl.h> 40 #include <sys/conf.h> 41 #include <sys/kernel.h> 42 #include <sys/queue.h> 43 #include <sys/types.h> 44 #include <sys/buf.h> 45 #ifdef DEVFS 46 #include <sys/devfsext.h> 47 #endif /* DEVFS */ 48 49 #include <vm/vm.h> 50 #include <vm/pmap.h> 51 #include <vm/vm_extern.h> 52 53 #include <pci/pcireg.h> 54 #include <pci/pcivar.h> 55 #include <pci/pci_ioctl.h> 56 57 #ifdef APIC_IO 58 #include <machine/smp.h> 59 #endif /* APIC_IO */ 60 61 STAILQ_HEAD(devlist, pci_devinfo) pci_devq; 62 u_int32_t pci_numdevs = 0; 63 u_int32_t pci_generation = 0; 64 65 /* return highest PCI bus number known to be used, or -1 if none */ 66 67 static int 68 pci_bushigh(void) 69 { 70 if (pci_cfgopen() == 0) 71 return (-1); 72 return (0); 73 } 74 75 /* return base address of memory or port map */ 76 77 static int 78 pci_mapbase(unsigned mapreg) 79 { 80 int mask = 0x03; 81 if ((mapreg & 0x01) == 0) 82 mask = 0x0f; 83 return (mapreg & ~mask); 84 } 85 86 /* return map type of memory or port map */ 87 88 static int 89 pci_maptype(unsigned mapreg) 90 { 91 static u_int8_t maptype[0x10] = { 92 PCI_MAPMEM, PCI_MAPPORT, 93 PCI_MAPMEM, 0, 94 PCI_MAPMEM, PCI_MAPPORT, 95 0, 0, 96 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 97 PCI_MAPMEM|PCI_MAPMEMP, 0, 98 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 99 0, 0, 100 }; 101 102 return maptype[mapreg & 0x0f]; 103 } 104 105 /* return log2 of map size decoded for memory or port map */ 106 107 static int 108 pci_mapsize(unsigned testval) 109 { 110 int ln2size; 111 112 testval = pci_mapbase(testval); 113 ln2size = 0; 114 if (testval != 0) { 115 while ((testval & 1) == 0) 116 { 117 ln2size++; 118 testval >>= 1; 119 } 120 } 121 return (ln2size); 122 } 123 124 /* return log2 of address range supported by map register */ 125 126 static int 127 pci_maprange(unsigned mapreg) 128 { 129 int ln2range = 0; 130 switch (mapreg & 0x07) { 131 case 0x00: 132 case 0x01: 133 case 0x05: 134 ln2range = 32; 135 break; 136 case 0x02: 137 ln2range = 20; 138 break; 139 case 0x04: 140 ln2range = 64; 141 break; 142 } 143 return (ln2range); 144 } 145 146 /* extract map parameters into newly allocated array of pcimap structures */ 147 148 static pcimap * 149 pci_readmaps(pcicfgregs *cfg, int maxmaps) 150 { 151 int i; 152 pcimap *map; 153 int map64 = 0; 154 155 for (i = 0; i < maxmaps; i++) { 156 int reg = PCIR_MAPS + i*4; 157 u_int32_t base; 158 u_int32_t ln2range; 159 160 base = pci_cfgread(cfg, reg, 4); 161 ln2range = pci_maprange(base); 162 163 if (base == 0 || ln2range == 0) 164 maxmaps = i; 165 else if (ln2range > 32) 166 i++; 167 } 168 169 map = malloc(maxmaps * sizeof (pcimap), M_DEVBUF, M_WAITOK); 170 if (map != NULL) { 171 bzero(map, sizeof(pcimap) * maxmaps); 172 173 for (i = 0; i < maxmaps; i++) { 174 int reg = PCIR_MAPS + i*4; 175 u_int32_t base; 176 u_int32_t testval; 177 178 base = pci_cfgread(cfg, reg, 4); 179 180 if (map64 == 0) { 181 pci_cfgwrite(cfg, reg, 0xffffffff, 4); 182 testval = pci_cfgread(cfg, reg, 4); 183 pci_cfgwrite(cfg, reg, base, 4); 184 185 map[i].base = pci_mapbase(base); 186 map[i].type = pci_maptype(base); 187 map[i].ln2size = pci_mapsize(testval); 188 map[i].ln2range = pci_maprange(testval); 189 map64 = map[i].ln2range == 64; 190 } else { 191 /* only fill in base, other fields are 0 */ 192 map[i].base = base; 193 map64 = 0; 194 } 195 } 196 cfg->nummaps = maxmaps; 197 } 198 return (map); 199 } 200 201 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 202 203 static void 204 pci_fixancient(pcicfgregs *cfg) 205 { 206 if (cfg->hdrtype != 0) 207 return; 208 209 /* PCI to PCI bridges use header type 1 */ 210 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 211 cfg->hdrtype = 1; 212 } 213 214 /* read config data specific to header type 1 device (PCI to PCI bridge) */ 215 216 static void * 217 pci_readppb(pcicfgregs *cfg) 218 { 219 pcih1cfgregs *p; 220 221 p = malloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK); 222 if (p == NULL) 223 return (NULL); 224 225 bzero(p, sizeof *p); 226 227 p->secstat = pci_cfgread(cfg, PCIR_SECSTAT_1, 2); 228 p->bridgectl = pci_cfgread(cfg, PCIR_BRIDGECTL_1, 2); 229 230 p->seclat = pci_cfgread(cfg, PCIR_SECLAT_1, 1); 231 232 p->iobase = PCI_PPBIOBASE (pci_cfgread(cfg, PCIR_IOBASEH_1, 2), 233 pci_cfgread(cfg, PCIR_IOBASEL_1, 1)); 234 p->iolimit = PCI_PPBIOLIMIT (pci_cfgread(cfg, PCIR_IOLIMITH_1, 2), 235 pci_cfgread(cfg, PCIR_IOLIMITL_1, 1)); 236 237 p->membase = PCI_PPBMEMBASE (0, 238 pci_cfgread(cfg, PCIR_MEMBASE_1, 2)); 239 p->memlimit = PCI_PPBMEMLIMIT (0, 240 pci_cfgread(cfg, PCIR_MEMLIMIT_1, 2)); 241 242 p->pmembase = PCI_PPBMEMBASE ( 243 (pci_addr_t)pci_cfgread(cfg, PCIR_PMBASEH_1, 4), 244 pci_cfgread(cfg, PCIR_PMBASEL_1, 2)); 245 246 p->pmemlimit = PCI_PPBMEMLIMIT ( 247 (pci_addr_t)pci_cfgread(cfg, PCIR_PMLIMITH_1, 4), 248 pci_cfgread(cfg, PCIR_PMLIMITL_1, 2)); 249 return (p); 250 } 251 252 /* read config data specific to header type 2 device (PCI to CardBus bridge) */ 253 254 static void * 255 pci_readpcb(pcicfgregs *cfg) 256 { 257 pcih2cfgregs *p; 258 259 p = malloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK); 260 if (p == NULL) 261 return (NULL); 262 263 bzero(p, sizeof *p); 264 265 p->secstat = pci_cfgread(cfg, PCIR_SECSTAT_2, 2); 266 p->bridgectl = pci_cfgread(cfg, PCIR_BRIDGECTL_2, 2); 267 268 p->seclat = pci_cfgread(cfg, PCIR_SECLAT_2, 1); 269 270 p->membase0 = pci_cfgread(cfg, PCIR_MEMBASE0_2, 4); 271 p->memlimit0 = pci_cfgread(cfg, PCIR_MEMLIMIT0_2, 4); 272 p->membase1 = pci_cfgread(cfg, PCIR_MEMBASE1_2, 4); 273 p->memlimit1 = pci_cfgread(cfg, PCIR_MEMLIMIT1_2, 4); 274 275 p->iobase0 = pci_cfgread(cfg, PCIR_IOBASE0_2, 4); 276 p->iolimit0 = pci_cfgread(cfg, PCIR_IOLIMIT0_2, 4); 277 p->iobase1 = pci_cfgread(cfg, PCIR_IOBASE1_2, 4); 278 p->iolimit1 = pci_cfgread(cfg, PCIR_IOLIMIT1_2, 4); 279 280 p->pccardif = pci_cfgread(cfg, PCIR_PCCARDIF_2, 4); 281 return p; 282 } 283 284 /* extract header type specific config data */ 285 286 static void 287 pci_hdrtypedata(pcicfgregs *cfg) 288 { 289 switch (cfg->hdrtype) { 290 case 0: 291 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_0, 2); 292 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_0, 2); 293 cfg->map = pci_readmaps(cfg, PCI_MAXMAPS_0); 294 break; 295 case 1: 296 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_1, 2); 297 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_1, 2); 298 cfg->secondarybus = pci_cfgread(cfg, PCIR_SECBUS_1, 1); 299 cfg->subordinatebus = pci_cfgread(cfg, PCIR_SUBBUS_1, 1); 300 cfg->map = pci_readmaps(cfg, PCI_MAXMAPS_1); 301 cfg->hdrspec = pci_readppb(cfg); 302 break; 303 case 2: 304 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_2, 2); 305 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_2, 2); 306 cfg->secondarybus = pci_cfgread(cfg, PCIR_SECBUS_2, 1); 307 cfg->subordinatebus = pci_cfgread(cfg, PCIR_SUBBUS_2, 1); 308 cfg->map = pci_readmaps(cfg, PCI_MAXMAPS_2); 309 cfg->hdrspec = pci_readpcb(cfg); 310 break; 311 } 312 } 313 314 /* read configuration header into pcicfgrect structure */ 315 316 static struct pci_devinfo * 317 pci_readcfg(pcicfgregs *probe) 318 { 319 pcicfgregs *cfg = NULL; 320 struct pci_devinfo *devlist_entry; 321 struct devlist *devlist_head; 322 323 devlist_head = &pci_devq; 324 325 devlist_entry = NULL; 326 327 if (pci_cfgread(probe, PCIR_DEVVENDOR, 4) != -1) { 328 devlist_entry = malloc(sizeof(struct pci_devinfo), 329 M_DEVBUF, M_WAITOK); 330 if (devlist_entry == NULL) 331 return (NULL); 332 333 cfg = &devlist_entry->cfg; 334 335 bzero(cfg, sizeof *cfg); 336 337 cfg->bus = probe->bus; 338 cfg->slot = probe->slot; 339 cfg->func = probe->func; 340 cfg->vendor = pci_cfgread(cfg, PCIR_VENDOR, 2); 341 cfg->device = pci_cfgread(cfg, PCIR_DEVICE, 2); 342 cfg->cmdreg = pci_cfgread(cfg, PCIR_COMMAND, 2); 343 cfg->statreg = pci_cfgread(cfg, PCIR_STATUS, 2); 344 cfg->baseclass = pci_cfgread(cfg, PCIR_CLASS, 1); 345 cfg->subclass = pci_cfgread(cfg, PCIR_SUBCLASS, 1); 346 cfg->progif = pci_cfgread(cfg, PCIR_PROGIF, 1); 347 cfg->revid = pci_cfgread(cfg, PCIR_REVID, 1); 348 cfg->hdrtype = pci_cfgread(cfg, PCIR_HEADERTYPE, 1); 349 cfg->cachelnsz = pci_cfgread(cfg, PCIR_CACHELNSZ, 1); 350 cfg->lattimer = pci_cfgread(cfg, PCIR_LATTIMER, 1); 351 cfg->intpin = pci_cfgread(cfg, PCIR_INTPIN, 1); 352 cfg->intline = pci_cfgread(cfg, PCIR_INTLINE, 1); 353 #ifdef __alpha__ 354 alpha_platform_assign_pciintr(cfg); 355 #endif 356 357 #ifdef APIC_IO 358 if (cfg->intpin != 0) { 359 int airq; 360 361 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin); 362 if (airq >= 0) { 363 /* PCI specific entry found in MP table */ 364 if (airq != cfg->intline) { 365 undirect_pci_irq(cfg->intline); 366 cfg->intline = airq; 367 } 368 } else { 369 /* 370 * PCI interrupts might be redirected to the 371 * ISA bus according to some MP tables. Use the 372 * same methods as used by the ISA devices 373 * devices to find the proper IOAPIC int pin. 374 */ 375 airq = isa_apic_irq(cfg->intline); 376 if ((airq >= 0) && (airq != cfg->intline)) { 377 /* XXX: undirect_pci_irq() ? */ 378 undirect_isa_irq(cfg->intline); 379 cfg->intline = airq; 380 } 381 } 382 } 383 #endif /* APIC_IO */ 384 385 cfg->mingnt = pci_cfgread(cfg, PCIR_MINGNT, 1); 386 cfg->maxlat = pci_cfgread(cfg, PCIR_MAXLAT, 1); 387 388 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 389 cfg->hdrtype &= ~PCIM_MFDEV; 390 391 pci_fixancient(cfg); 392 pci_hdrtypedata(cfg); 393 394 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 395 396 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 397 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 398 devlist_entry->conf.pc_sel.pc_func = cfg->func; 399 devlist_entry->conf.pc_hdr = cfg->hdrtype; 400 401 devlist_entry->conf.pc_subvendor = cfg->subvendor; 402 devlist_entry->conf.pc_subdevice = cfg->subdevice; 403 devlist_entry->conf.pc_vendor = cfg->vendor; 404 devlist_entry->conf.pc_device = cfg->device; 405 406 devlist_entry->conf.pc_class = cfg->baseclass; 407 devlist_entry->conf.pc_subclass = cfg->subclass; 408 devlist_entry->conf.pc_progif = cfg->progif; 409 devlist_entry->conf.pc_revid = cfg->revid; 410 411 pci_numdevs++; 412 pci_generation++; 413 } 414 return (devlist_entry); 415 } 416 417 #if 0 418 /* free pcicfgregs structure and all depending data structures */ 419 420 static int 421 pci_freecfg(struct pci_devinfo *dinfo) 422 { 423 struct devlist *devlist_head; 424 425 devlist_head = &pci_devq; 426 427 if (dinfo->cfg.hdrspec != NULL) 428 free(dinfo->cfg.hdrspec, M_DEVBUF); 429 if (dinfo->cfg.map != NULL) 430 free(dinfo->cfg.map, M_DEVBUF); 431 /* XXX this hasn't been tested */ 432 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 433 free(dinfo, M_DEVBUF); 434 435 /* increment the generation count */ 436 pci_generation++; 437 438 /* we're losing one device */ 439 pci_numdevs--; 440 return (0); 441 } 442 #endif 443 444 static void 445 pci_addcfg(struct pci_devinfo *dinfo) 446 { 447 if (bootverbose) { 448 int i; 449 pcicfgregs *cfg = &dinfo->cfg; 450 451 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 452 cfg->vendor, cfg->device, cfg->revid); 453 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 454 cfg->baseclass, cfg->subclass, cfg->progif, 455 cfg->hdrtype, cfg->mfdev); 456 #ifdef PCI_DEBUG 457 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 458 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 459 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 460 cfg->lattimer, cfg->lattimer * 30, 461 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 462 #endif /* PCI_DEBUG */ 463 if (cfg->intpin > 0) 464 printf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline); 465 466 for (i = 0; i < cfg->nummaps; i++) { 467 pcimap *m = &cfg->map[i]; 468 printf("\tmap[%d]: type %x, range %2d, base %08x, size %2d\n", 469 i, m->type, m->ln2range, m->base, m->ln2size); 470 } 471 } 472 pci_drvattach(dinfo); /* XXX currently defined in pci_compat.c */ 473 } 474 475 /* return pointer to device that is a bridge to this bus */ 476 477 static pcicfgregs * 478 pci_bridgeto(int bus) 479 { 480 return (NULL); /* XXX not yet implemented */ 481 } 482 483 /* scan one PCI bus for devices */ 484 485 static int 486 pci_probebus(int bus) 487 { 488 pcicfgregs probe; 489 int bushigh = bus; 490 491 #ifdef SIMOS 492 #undef PCI_SLOTMAX 493 #define PCI_SLOTMAX 0 494 #endif 495 496 bzero(&probe, sizeof probe); 497 /* XXX KDM */ 498 /* probe.parent = pci_bridgeto(bus); */ 499 probe.bus = bus; 500 for (probe.slot = 0; probe.slot <= PCI_SLOTMAX; probe.slot++) { 501 int pcifunchigh = 0; 502 for (probe.func = 0; probe.func <= pcifunchigh; probe.func++) { 503 struct pci_devinfo *dinfo = pci_readcfg(&probe); 504 if (dinfo != NULL) { 505 if (dinfo->cfg.mfdev) 506 pcifunchigh = 7; 507 /* 508 * XXX: Temporarily move pci_addcfg() up before 509 * the use of cfg->subordinatebus. This is 510 * necessary, since pci_addcfg() calls the 511 * device's probe(), which may read the bus# 512 * from some device dependent register of 513 * some host to PCI bridges. The probe will 514 * eventually be moved to pci_readcfg(), and 515 * pci_addcfg() will then be moved back down 516 * below the conditional statement ... 517 */ 518 pci_addcfg(dinfo); 519 520 if (bushigh < dinfo->cfg.subordinatebus) 521 bushigh = dinfo->cfg.subordinatebus; 522 523 /* XXX KDM */ 524 /* cfg = NULL; we don't own this anymore ... */ 525 } 526 } 527 } 528 return (bushigh); 529 } 530 531 /* scan a PCI bus tree reached through one PCI attachment point */ 532 533 int 534 pci_probe(pciattach *parent) 535 { 536 int bushigh; 537 int bus = 0; 538 539 STAILQ_INIT(&pci_devq); 540 541 bushigh = pci_bushigh(); 542 while (bus <= bushigh) { 543 int newbushigh; 544 545 printf("Probing for devices on PCI bus %d:\n", bus); 546 newbushigh = pci_probebus(bus); 547 548 if (bushigh < newbushigh) 549 bushigh = newbushigh; 550 bus++; 551 } 552 return (bushigh); 553 } 554 555 /* 556 * This is the user interface to PCI configuration space. 557 */ 558 559 static int 560 pci_open(dev_t dev, int oflags, int devtype, struct proc *p) 561 { 562 if ((oflags & FWRITE) && securelevel > 0) { 563 return EPERM; 564 } 565 return 0; 566 } 567 568 static int 569 pci_close(dev_t dev, int flag, int devtype, struct proc *p) 570 { 571 return 0; 572 } 573 574 /* 575 * Match a single pci_conf structure against an array of pci_match_conf 576 * structures. The first argument, 'matches', is an array of num_matches 577 * pci_match_conf structures. match_buf is a pointer to the pci_conf 578 * structure that will be compared to every entry in the matches array. 579 * This function returns 1 on failure, 0 on success. 580 */ 581 static int 582 pci_conf_match(struct pci_match_conf *matches, int num_matches, 583 struct pci_conf *match_buf) 584 { 585 int i; 586 587 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0)) 588 return(1); 589 590 for (i = 0; i < num_matches; i++) { 591 /* 592 * I'm not sure why someone would do this...but... 593 */ 594 if (matches[i].flags == PCI_GETCONF_NO_MATCH) 595 continue; 596 597 /* 598 * Look at each of the match flags. If it's set, do the 599 * comparison. If the comparison fails, we don't have a 600 * match, go on to the next item if there is one. 601 */ 602 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0) 603 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus)) 604 continue; 605 606 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0) 607 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev)) 608 continue; 609 610 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0) 611 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func)) 612 continue; 613 614 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0) 615 && (match_buf->pc_vendor != matches[i].pc_vendor)) 616 continue; 617 618 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0) 619 && (match_buf->pc_device != matches[i].pc_device)) 620 continue; 621 622 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0) 623 && (match_buf->pc_class != matches[i].pc_class)) 624 continue; 625 626 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0) 627 && (match_buf->pd_unit != matches[i].pd_unit)) 628 continue; 629 630 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0) 631 && (strncmp(matches[i].pd_name, match_buf->pd_name, 632 sizeof(match_buf->pd_name)) != 0)) 633 continue; 634 635 return(0); 636 } 637 638 return(1); 639 } 640 641 static int 642 pci_ioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) 643 { 644 struct pci_io *io; 645 int error; 646 647 if (!(flag & FWRITE)) 648 return EPERM; 649 650 651 switch(cmd) { 652 case PCIOCGETCONF: 653 { 654 struct pci_devinfo *dinfo; 655 struct pci_conf_io *cio; 656 struct devlist *devlist_head; 657 struct pci_match_conf *pattern_buf; 658 int num_patterns; 659 size_t iolen; 660 int ionum, i; 661 662 cio = (struct pci_conf_io *)data; 663 664 num_patterns = 0; 665 dinfo = NULL; 666 667 /* 668 * Hopefully the user won't pass in a null pointer, but it 669 * can't hurt to check. 670 */ 671 if (cio == NULL) { 672 error = EINVAL; 673 break; 674 } 675 676 /* 677 * If the user specified an offset into the device list, 678 * but the list has changed since they last called this 679 * ioctl, tell them that the list has changed. They will 680 * have to get the list from the beginning. 681 */ 682 if ((cio->offset != 0) 683 && (cio->generation != pci_generation)){ 684 cio->num_matches = 0; 685 cio->status = PCI_GETCONF_LIST_CHANGED; 686 error = 0; 687 break; 688 } 689 690 /* 691 * Check to see whether the user has asked for an offset 692 * past the end of our list. 693 */ 694 if (cio->offset >= pci_numdevs) { 695 cio->num_matches = 0; 696 cio->status = PCI_GETCONF_LAST_DEVICE; 697 error = 0; 698 break; 699 } 700 701 /* get the head of the device queue */ 702 devlist_head = &pci_devq; 703 704 /* 705 * Determine how much room we have for pci_conf structures. 706 * Round the user's buffer size down to the nearest 707 * multiple of sizeof(struct pci_conf) in case the user 708 * didn't specify a multiple of that size. 709 */ 710 iolen = min(cio->match_buf_len - 711 (cio->match_buf_len % sizeof(struct pci_conf)), 712 pci_numdevs * sizeof(struct pci_conf)); 713 714 /* 715 * Since we know that iolen is a multiple of the size of 716 * the pciconf union, it's okay to do this. 717 */ 718 ionum = iolen / sizeof(struct pci_conf); 719 720 /* 721 * If this test is true, the user wants the pci_conf 722 * structures returned to match the supplied entries. 723 */ 724 if ((cio->num_patterns > 0) 725 && (cio->pat_buf_len > 0)) { 726 /* 727 * pat_buf_len needs to be: 728 * num_patterns * sizeof(struct pci_match_conf) 729 * While it is certainly possible the user just 730 * allocated a large buffer, but set the number of 731 * matches correctly, it is far more likely that 732 * their kernel doesn't match the userland utility 733 * they're using. It's also possible that the user 734 * forgot to initialize some variables. Yes, this 735 * may be overly picky, but I hazard to guess that 736 * it's far more likely to just catch folks that 737 * updated their kernel but not their userland. 738 */ 739 if ((cio->num_patterns * 740 sizeof(struct pci_match_conf)) != cio->pat_buf_len){ 741 /* The user made a mistake, return an error*/ 742 cio->status = PCI_GETCONF_ERROR; 743 printf("pci_ioctl: pat_buf_len %d != " 744 "num_patterns (%d) * sizeof(struct " 745 "pci_match_conf) (%d)\npci_ioctl: " 746 "pat_buf_len should be = %d\n", 747 cio->pat_buf_len, cio->num_patterns, 748 sizeof(struct pci_match_conf), 749 sizeof(struct pci_match_conf) * 750 cio->num_patterns); 751 printf("pci_ioctl: do your headers match your " 752 "kernel?\n"); 753 cio->num_matches = 0; 754 error = EINVAL; 755 break; 756 } 757 758 /* 759 * Check the user's buffer to make sure it's readable. 760 */ 761 if ((error = useracc((caddr_t)cio->patterns, 762 cio->pat_buf_len, B_READ)) != 1){ 763 printf("pci_ioctl: pattern buffer %#lx, " 764 "length %u isn't user accessible for" 765 " READ\n", cio->patterns, 766 cio->pat_buf_len); 767 error = EACCES; 768 break; 769 } 770 /* 771 * Allocate a buffer to hold the patterns. 772 */ 773 pattern_buf = malloc(cio->pat_buf_len, M_TEMP, 774 M_WAITOK); 775 error = copyin(cio->patterns, pattern_buf, 776 cio->pat_buf_len); 777 if (error != 0) 778 break; 779 num_patterns = cio->num_patterns; 780 781 } else if ((cio->num_patterns > 0) 782 || (cio->pat_buf_len > 0)) { 783 /* 784 * The user made a mistake, spit out an error. 785 */ 786 cio->status = PCI_GETCONF_ERROR; 787 cio->num_matches = 0; 788 printf("pci_ioctl: invalid GETCONF arguments\n"); 789 error = EINVAL; 790 break; 791 } else 792 pattern_buf = NULL; 793 794 /* 795 * Make sure we can write to the match buffer. 796 */ 797 if ((error = useracc((caddr_t)cio->matches, cio->match_buf_len, 798 B_WRITE)) != 1) { 799 printf("pci_ioctl: match buffer %#lx, length %u " 800 "isn't user accessible for WRITE\n", 801 cio->matches, cio->match_buf_len); 802 error = EACCES; 803 break; 804 } 805 806 /* 807 * Go through the list of devices and copy out the devices 808 * that match the user's criteria. 809 */ 810 for (cio->num_matches = 0, error = 0, i = 0, 811 dinfo = STAILQ_FIRST(devlist_head); 812 (dinfo != NULL) && (cio->num_matches < ionum) 813 && (error == 0) && (i < pci_numdevs); 814 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 815 816 if (i < cio->offset) 817 continue; 818 819 if ((pattern_buf == NULL) || 820 (pci_conf_match(pattern_buf, num_patterns, 821 &dinfo->conf) == 0)) { 822 823 /* 824 * If we've filled up the user's buffer, 825 * break out at this point. Since we've 826 * got a match here, we'll pick right back 827 * up at the matching entry. We can also 828 * tell the user that there are more matches 829 * left. 830 */ 831 if (cio->num_matches >= ionum) 832 break; 833 834 error = copyout(&dinfo->conf, 835 &cio->matches[cio->num_matches], 836 sizeof(struct pci_conf)); 837 cio->num_matches++; 838 } 839 } 840 841 /* 842 * Set the pointer into the list, so if the user is getting 843 * n records at a time, where n < pci_numdevs, 844 */ 845 cio->offset = i; 846 847 /* 848 * Set the generation, the user will need this if they make 849 * another ioctl call with offset != 0. 850 */ 851 cio->generation = pci_generation; 852 853 /* 854 * If this is the last device, inform the user so he won't 855 * bother asking for more devices. If dinfo isn't NULL, we 856 * know that there are more matches in the list because of 857 * the way the traversal is done. 858 */ 859 if (dinfo == NULL) 860 cio->status = PCI_GETCONF_LAST_DEVICE; 861 else 862 cio->status = PCI_GETCONF_MORE_DEVS; 863 864 if (pattern_buf != NULL) 865 free(pattern_buf, M_TEMP); 866 867 break; 868 } 869 case PCIOCREAD: 870 io = (struct pci_io *)data; 871 switch(io->pi_width) { 872 pcicfgregs probe; 873 case 4: 874 case 2: 875 case 1: 876 probe.bus = io->pi_sel.pc_bus; 877 probe.slot = io->pi_sel.pc_dev; 878 probe.func = io->pi_sel.pc_func; 879 io->pi_data = pci_cfgread(&probe, 880 io->pi_reg, io->pi_width); 881 error = 0; 882 break; 883 default: 884 error = ENODEV; 885 break; 886 } 887 break; 888 889 case PCIOCWRITE: 890 io = (struct pci_io *)data; 891 switch(io->pi_width) { 892 pcicfgregs probe; 893 case 4: 894 case 2: 895 case 1: 896 probe.bus = io->pi_sel.pc_bus; 897 probe.slot = io->pi_sel.pc_dev; 898 probe.func = io->pi_sel.pc_func; 899 pci_cfgwrite(&probe, 900 io->pi_reg, io->pi_data, io->pi_width); 901 error = 0; 902 break; 903 default: 904 error = ENODEV; 905 break; 906 } 907 break; 908 909 default: 910 error = ENOTTY; 911 break; 912 } 913 914 return (error); 915 } 916 917 #define PCI_CDEV 78 918 919 static struct cdevsw pcicdev = { 920 pci_open, pci_close, noread, nowrite, pci_ioctl, nostop, noreset, 921 nodevtotty, seltrue, nommap, nostrategy, "pci", 0, PCI_CDEV 922 }; 923 924 #ifdef DEVFS 925 static void *pci_devfs_token; 926 #endif 927 928 static void 929 pci_cdevinit(void *dummy) 930 { 931 dev_t dev; 932 933 dev = makedev(PCI_CDEV, 0); 934 cdevsw_add(&dev, &pcicdev, NULL); 935 #ifdef DEVFS 936 pci_devfs_token = devfs_add_devswf(&pcicdev, 0, DV_CHR, 937 UID_ROOT, GID_WHEEL, 0644, "pci"); 938 #endif 939 } 940 941 SYSINIT(pcidev, SI_SUB_DRIVERS, SI_ORDER_MIDDLE+PCI_CDEV, pci_cdevinit, NULL); 942 943 #endif /* NPCI > 0 */ 944