1 /*- 2 * Copyright (c) 2017 Broadcom. All rights reserved. 3 * The term "Broadcom" refers to Broadcom Limited and/or its subsidiaries. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the copyright holder nor the names of its contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 * 31 * $FreeBSD$ 32 */ 33 34 /** 35 * @file 36 * Define common SLI-4 structures and function prototypes. 37 */ 38 39 #ifndef _SLI4_H 40 #define _SLI4_H 41 42 #include "ocs_os.h" 43 44 #define SLI_PAGE_SIZE (4096) 45 #define SLI_SUB_PAGE_MASK (SLI_PAGE_SIZE - 1) 46 #define SLI_PAGE_SHIFT 12 47 #define SLI_ROUND_PAGE(b) (((b) + SLI_SUB_PAGE_MASK) & ~SLI_SUB_PAGE_MASK) 48 49 #define SLI4_BMBX_TIMEOUT_MSEC 30000 50 #define SLI4_FW_READY_TIMEOUT_MSEC 30000 51 52 static inline uint32_t 53 sli_page_count(size_t bytes, uint32_t page_size) 54 { 55 uint32_t mask = page_size - 1; 56 uint32_t shift = 0; 57 58 switch (page_size) { 59 case 4096: 60 shift = 12; 61 break; 62 case 8192: 63 shift = 13; 64 break; 65 case 16384: 66 shift = 14; 67 break; 68 case 32768: 69 shift = 15; 70 break; 71 case 65536: 72 shift = 16; 73 break; 74 default: 75 return 0; 76 } 77 78 return (bytes + mask) >> shift; 79 } 80 81 /************************************************************************* 82 * Common PCI configuration space register definitions 83 */ 84 85 #define SLI4_PCI_CLASS_REVISION 0x0008 /** register offset */ 86 #define SLI4_PCI_REV_ID_SHIFT 0 87 #define SLI4_PCI_REV_ID_MASK 0xff 88 #define SLI4_PCI_CLASS_SHIFT 8 89 #define SLI4_PCI_CLASS_MASK 0xfff 90 91 #define SLI4_PCI_SOFT_RESET_CSR 0x005c /** register offset */ 92 #define SLI4_PCI_SOFT_RESET_MASK 0x0080 93 94 /************************************************************************* 95 * Common SLI-4 register offsets and field definitions 96 */ 97 98 /** 99 * @brief SLI_INTF - SLI Interface Definition Register 100 */ 101 #define SLI4_INTF_REG 0x0058 /** register offset */ 102 #define SLI4_INTF_VALID_SHIFT 29 103 #define SLI4_INTF_VALID_MASK 0x7 104 #define SLI4_INTF_VALID 0x6 105 #define SLI4_INTF_IF_TYPE_SHIFT 12 106 #define SLI4_INTF_IF_TYPE_MASK 0xf 107 #define SLI4_INTF_SLI_FAMILY_SHIFT 8 108 #define SLI4_INTF_SLI_FAMILY_MASK 0xf 109 #define SLI4_INTF_SLI_REVISION_SHIFT 4 110 #define SLI4_INTF_SLI_REVISION_MASK 0xf 111 #define SLI4_FAMILY_CHECK_ASIC_TYPE 0xf 112 113 #define SLI4_IF_TYPE_BE3_SKH_PF 0 114 #define SLI4_IF_TYPE_BE3_SKH_VF 1 115 #define SLI4_IF_TYPE_LANCER_FC_ETH 2 116 #define SLI4_IF_TYPE_LANCER_RDMA 3 117 #define SLI4_IF_TYPE_LANCER_G7 6 118 #define SLI4_MAX_IF_TYPES 7 119 120 /** 121 * @brief ASIC_ID - SLI ASIC Type and Revision Register 122 */ 123 #define SLI4_ASIC_ID_REG 0x009c /* register offset */ 124 #define SLI4_ASIC_REV_SHIFT 0 125 #define SLI4_ASIC_REV_MASK 0xf 126 #define SLI4_ASIC_VER_SHIFT 4 127 #define SLI4_ASIC_VER_MASK 0xf 128 #define SLI4_ASIC_GEN_SHIFT 8 129 #define SLI4_ASIC_GEN_MASK 0xff 130 #define SLI4_ASIC_GEN_BE2 0x00 131 #define SLI4_ASIC_GEN_BE3 0x03 132 #define SLI4_ASIC_GEN_SKYHAWK 0x04 133 #define SLI4_ASIC_GEN_CORSAIR 0x05 134 #define SLI4_ASIC_GEN_LANCER 0x0b 135 136 /** 137 * @brief BMBX - Bootstrap Mailbox Register 138 */ 139 #define SLI4_BMBX_REG 0x0160 /* register offset */ 140 #define SLI4_BMBX_MASK_HI 0x3 141 #define SLI4_BMBX_MASK_LO 0xf 142 #define SLI4_BMBX_RDY BIT(0) 143 #define SLI4_BMBX_HI BIT(1) 144 #define SLI4_BMBX_WRITE_HI(r) ((ocs_addr32_hi(r) & ~SLI4_BMBX_MASK_HI) | \ 145 SLI4_BMBX_HI) 146 #define SLI4_BMBX_WRITE_LO(r) (((ocs_addr32_hi(r) & SLI4_BMBX_MASK_HI) << 30) | \ 147 (((r) & ~SLI4_BMBX_MASK_LO) >> 2)) 148 149 #define SLI4_BMBX_SIZE 256 150 151 /** 152 * @brief EQCQ_DOORBELL - EQ and CQ Doorbell Register 153 */ 154 #define SLI4_EQCQ_DOORBELL_REG 0x120 155 #define SLI4_EQCQ_DOORBELL_CI BIT(9) 156 #define SLI4_EQCQ_DOORBELL_QT BIT(10) 157 #define SLI4_EQCQ_DOORBELL_ARM BIT(29) 158 #define SLI4_EQCQ_DOORBELL_SE BIT(31) 159 #define SLI4_EQCQ_NUM_SHIFT 16 160 #define SLI4_EQCQ_NUM_MASK 0x01ff 161 #define SLI4_EQCQ_EQ_ID_MASK 0x3fff 162 #define SLI4_EQCQ_CQ_ID_MASK 0x7fff 163 #define SLI4_EQCQ_EQ_ID_MASK_LO 0x01ff 164 #define SLI4_EQCQ_CQ_ID_MASK_LO 0x03ff 165 #define SLI4_EQCQ_EQCQ_ID_MASK_HI 0xf800 166 #define SLI4_IF6_EQ_DOORBELL_REG 0x120 167 #define SLI4_IF6_CQ_DOORBELL_REG 0xC0 168 169 /** 170 * @brief SLIPORT_CONTROL - SLI Port Control Register 171 */ 172 #define SLI4_SLIPORT_CONTROL_REG 0x0408 173 #define SLI4_SLIPORT_CONTROL_END BIT(30) 174 #define SLI4_SLIPORT_CONTROL_LITTLE_ENDIAN (0) 175 #define SLI4_SLIPORT_CONTROL_BIG_ENDIAN BIT(30) 176 #define SLI4_SLIPORT_CONTROL_IP BIT(27) 177 #define SLI4_SLIPORT_CONTROL_IDIS BIT(22) 178 #define SLI4_SLIPORT_CONTROL_FDD BIT(31) 179 180 /** 181 * @brief SLI4_SLIPORT_ERROR1 - SLI Port Error Register 182 */ 183 #define SLI4_SLIPORT_ERROR1 0x040c 184 185 /** 186 * @brief SLI4_SLIPORT_ERROR2 - SLI Port Error Register 187 */ 188 #define SLI4_SLIPORT_ERROR2 0x0410 189 190 /** 191 * @brief User error registers 192 */ 193 #define SLI4_UERR_STATUS_LOW_REG 0xA0 194 #define SLI4_UERR_STATUS_HIGH_REG 0xA4 195 #define SLI4_UERR_MASK_LOW_REG 0xA8 196 #define SLI4_UERR_MASK_HIGH_REG 0xAC 197 198 /** 199 * @brief Registers for generating software UE (BE3) 200 */ 201 #define SLI4_SW_UE_CSR1 0x138 202 #define SLI4_SW_UE_CSR2 0x1FFFC 203 204 /** 205 * @brief Registers for generating software UE (Skyhawk) 206 */ 207 #define SLI4_SW_UE_REG 0x5C /* register offset */ 208 209 static inline uint32_t sli_eq_doorbell(uint16_t n_popped, uint16_t id, uint8_t arm) 210 { 211 uint32_t reg = 0; 212 #if BYTE_ORDER == LITTLE_ENDIAN 213 struct { 214 uint32_t eq_id_lo:9, 215 ci:1, /* clear interrupt */ 216 qt:1, /* queue type */ 217 eq_id_hi:5, 218 number_popped:13, 219 arm:1, 220 :1, 221 se:1; 222 } * eq_doorbell = (void *)® 223 #else 224 #error big endian version not defined 225 #endif 226 227 eq_doorbell->eq_id_lo = id & SLI4_EQCQ_EQ_ID_MASK_LO; 228 eq_doorbell->qt = 1; /* EQ is type 1 (section 2.2.3.3 SLI Arch) */ 229 eq_doorbell->eq_id_hi = (id >> 9) & 0x1f; 230 eq_doorbell->number_popped = n_popped; 231 eq_doorbell->arm = arm; 232 eq_doorbell->ci = TRUE; 233 234 return reg; 235 } 236 237 static inline uint32_t sli_cq_doorbell(uint16_t n_popped, uint16_t id, uint8_t arm) 238 { 239 uint32_t reg = 0; 240 #if BYTE_ORDER == LITTLE_ENDIAN 241 struct { 242 uint32_t cq_id_lo:10, 243 qt:1, /* queue type */ 244 cq_id_hi:5, 245 number_popped:13, 246 arm:1, 247 :1, 248 se:1; 249 } * cq_doorbell = (void *)® 250 #else 251 #error big endian version not defined 252 #endif 253 254 cq_doorbell->cq_id_lo = id & SLI4_EQCQ_CQ_ID_MASK_LO; 255 cq_doorbell->qt = 0; /* CQ is type 0 (section 2.2.3.3 SLI Arch) */ 256 cq_doorbell->cq_id_hi = (id >> 10) & 0x1f; 257 cq_doorbell->number_popped = n_popped; 258 cq_doorbell->arm = arm; 259 260 return reg; 261 } 262 263 static inline uint32_t sli_iftype6_eq_doorbell(uint16_t n_popped, uint16_t id, uint8_t arm) 264 { 265 uint32_t reg = 0; 266 #if BYTE_ORDER == LITTLE_ENDIAN 267 struct { 268 uint32_t eq_id:12, 269 :4, /* clear interrupt */ 270 number_popped:13, 271 arm:1, 272 :1, 273 io:1; 274 } * eq_doorbell = (void *)® 275 #else 276 #error big endian version not defined 277 #endif 278 279 eq_doorbell->eq_id = id; 280 eq_doorbell->number_popped = n_popped; 281 eq_doorbell->arm = arm; 282 283 return reg; 284 } 285 286 static inline uint32_t sli_iftype6_cq_doorbell(uint16_t n_popped, uint16_t id, uint8_t arm) 287 { 288 uint32_t reg = 0; 289 #if BYTE_ORDER == LITTLE_ENDIAN 290 struct { 291 uint32_t cq_id:16, 292 number_popped:13, 293 arm:1, 294 :1, 295 se:1; 296 } * cq_doorbell = (void *)® 297 #else 298 #error big endian version not defined 299 #endif 300 301 cq_doorbell->cq_id = id; 302 cq_doorbell->number_popped = n_popped; 303 cq_doorbell->arm = arm; 304 305 return reg; 306 } 307 308 /** 309 * @brief MQ_DOORBELL - MQ Doorbell Register 310 */ 311 #define SLI4_MQ_DOORBELL_REG 0x0140 /* register offset */ 312 #define SLI4_IF6_MQ_DOORBELL_REG 0x0160 /* register offset if_type = 6 */ 313 #define SLI4_MQ_DOORBELL_NUM_SHIFT 16 314 #define SLI4_MQ_DOORBELL_NUM_MASK 0x3fff 315 #define SLI4_MQ_DOORBELL_ID_MASK 0xffff 316 #define SLI4_MQ_DOORBELL(n, i) ((((n) & SLI4_MQ_DOORBELL_NUM_MASK) << SLI4_MQ_DOORBELL_NUM_SHIFT) | \ 317 ((i) & SLI4_MQ_DOORBELL_ID_MASK)) 318 319 /** 320 * @brief RQ_DOORBELL - RQ Doorbell Register 321 */ 322 #define SLI4_RQ_DOORBELL_REG 0x0a0 /* register offset */ 323 #define SLI4_IF6_RQ_DOORBELL_REG 0x0080 /* register offset of if_type = 6 */ 324 #define SLI4_RQ_DOORBELL_NUM_SHIFT 16 325 #define SLI4_RQ_DOORBELL_NUM_MASK 0x3fff 326 #define SLI4_RQ_DOORBELL_ID_MASK 0xffff 327 #define SLI4_RQ_DOORBELL(n, i) ((((n) & SLI4_RQ_DOORBELL_NUM_MASK) << SLI4_RQ_DOORBELL_NUM_SHIFT) | \ 328 ((i) & SLI4_RQ_DOORBELL_ID_MASK)) 329 330 /** 331 * @brief WQ_DOORBELL - WQ Doorbell Register 332 */ 333 #define SLI4_IO_WQ_DOORBELL_REG 0x040 /* register offset */ 334 #define SLI4_IF6_WQ_DOORBELL_REG 0x040 /* register offset for if_type = 6 */ 335 #define SLI4_WQ_DOORBELL_IDX_SHIFT 16 336 #define SLI4_WQ_DOORBELL_IDX_MASK 0x00ff 337 #define SLI4_WQ_DOORBELL_NUM_SHIFT 24 338 #define SLI4_WQ_DOORBELL_NUM_MASK 0x00ff 339 #define SLI4_WQ_DOORBELL_ID_MASK 0xffff 340 #define SLI4_WQ_DOORBELL(n, x, i) ((((n) & SLI4_WQ_DOORBELL_NUM_MASK) << SLI4_WQ_DOORBELL_NUM_SHIFT) | \ 341 (((x) & SLI4_WQ_DOORBELL_IDX_MASK) << SLI4_WQ_DOORBELL_IDX_SHIFT) | \ 342 ((i) & SLI4_WQ_DOORBELL_ID_MASK)) 343 344 /** 345 * @brief SLIPORT_SEMAPHORE - SLI Port Host and Port Status Register 346 */ 347 #define SLI4_PORT_SEMAPHORE_REG_0 0x00ac /** register offset Interface Type 0 + 1 */ 348 #define SLI4_PORT_SEMAPHORE_REG_1 0x0180 /** register offset Interface Type 0 + 1 */ 349 #define SLI4_PORT_SEMAPHORE_REG_236 0x0400 /** register offset Interface Type 2 + 3 + 6*/ 350 #define SLI4_PORT_SEMAPHORE_PORT_MASK 0x0000ffff 351 #define SLI4_PORT_SEMAPHORE_PORT(r) ((r) & SLI4_PORT_SEMAPHORE_PORT_MASK) 352 #define SLI4_PORT_SEMAPHORE_HOST_MASK 0x00ff0000 353 #define SLI4_PORT_SEMAPHORE_HOST_SHIFT 16 354 #define SLI4_PORT_SEMAPHORE_HOST(r) (((r) & SLI4_PORT_SEMAPHORE_HOST_MASK) >> \ 355 SLI4_PORT_SEMAPHORE_HOST_SHIFT) 356 #define SLI4_PORT_SEMAPHORE_SCR2 BIT(26) /** scratch area 2 */ 357 #define SLI4_PORT_SEMAPHORE_SCR1 BIT(27) /** scratch area 1 */ 358 #define SLI4_PORT_SEMAPHORE_IPC BIT(28) /** IP conflict */ 359 #define SLI4_PORT_SEMAPHORE_NIP BIT(29) /** no IP address */ 360 #define SLI4_PORT_SEMAPHORE_SFI BIT(30) /** secondary firmware image used */ 361 #define SLI4_PORT_SEMAPHORE_PERR BIT(31) /** POST fatal error */ 362 363 #define SLI4_PORT_SEMAPHORE_STATUS_POST_READY 0xc000 364 #define SLI4_PORT_SEMAPHORE_STATUS_UNRECOV_ERR 0xf000 365 #define SLI4_PORT_SEMAPHORE_STATUS_ERR_MASK 0xf000 366 #define SLI4_PORT_SEMAPHORE_IN_ERR(r) (SLI4_PORT_SEMAPHORE_STATUS_UNRECOV_ERR == ((r) & \ 367 SLI4_PORT_SEMAPHORE_STATUS_ERR_MASK)) 368 369 /** 370 * @brief SLIPORT_STATUS - SLI Port Status Register 371 */ 372 373 #define SLI4_PORT_STATUS_REG_236 0x0404 /** register offset Interface Type 2 + 3 + 6*/ 374 #define SLI4_PORT_STATUS_FDP BIT(21) /** function specific dump present */ 375 #define SLI4_PORT_STATUS_RDY BIT(23) /** ready */ 376 #define SLI4_PORT_STATUS_RN BIT(24) /** reset needed */ 377 #define SLI4_PORT_STATUS_DIP BIT(25) /** dump present */ 378 #define SLI4_PORT_STATUS_OTI BIT(29) /** over temp indicator */ 379 #define SLI4_PORT_STATUS_END BIT(30) /** endianness */ 380 #define SLI4_PORT_STATUS_ERR BIT(31) /** SLI port error */ 381 #define SLI4_PORT_STATUS_READY(r) ((r) & SLI4_PORT_STATUS_RDY) 382 #define SLI4_PORT_STATUS_ERROR(r) ((r) & SLI4_PORT_STATUS_ERR) 383 #define SLI4_PORT_STATUS_DUMP_PRESENT(r) ((r) & SLI4_PORT_STATUS_DIP) 384 #define SLI4_PORT_STATUS_FDP_PRESENT(r) ((r) & SLI4_PORT_STATUS_FDP) 385 386 #define SLI4_PHSDEV_CONTROL_REG_236 0x0414 /** register offset Interface Type 2 + 3 + 6*/ 387 #define SLI4_PHYDEV_CONTROL_DRST BIT(0) /** physical device reset */ 388 #define SLI4_PHYDEV_CONTROL_FRST BIT(1) /** firmware reset */ 389 #define SLI4_PHYDEV_CONTROL_DD BIT(2) /** diagnostic dump */ 390 #define SLI4_PHYDEV_CONTROL_FRL_MASK 0x000000f0 391 #define SLI4_PHYDEV_CONTROL_FRL_SHIFT 4 392 #define SLI4_PHYDEV_CONTROL_FRL(r) (((r) & SLI4_PHYDEV_CONTROL_FRL_MASK) >> \ 393 SLI4_PHYDEV_CONTROL_FRL_SHIFT_SHIFT) 394 395 /************************************************************************* 396 * SLI-4 mailbox command formats and definitions 397 */ 398 399 typedef struct sli4_mbox_command_header_s { 400 #if BYTE_ORDER == LITTLE_ENDIAN 401 uint32_t :8, 402 command:8, 403 status:16; /** Port writes to indicate success / fail */ 404 #else 405 #error big endian version not defined 406 #endif 407 } sli4_mbox_command_header_t; 408 409 #define SLI4_MBOX_COMMAND_CONFIG_LINK 0x07 410 #define SLI4_MBOX_COMMAND_DUMP 0x17 411 #define SLI4_MBOX_COMMAND_DOWN_LINK 0x06 412 #define SLI4_MBOX_COMMAND_INIT_LINK 0x05 413 #define SLI4_MBOX_COMMAND_INIT_VFI 0xa3 414 #define SLI4_MBOX_COMMAND_INIT_VPI 0xa4 415 #define SLI4_MBOX_COMMAND_POST_XRI 0xa7 416 #define SLI4_MBOX_COMMAND_RELEASE_XRI 0xac 417 #define SLI4_MBOX_COMMAND_READ_CONFIG 0x0b 418 #define SLI4_MBOX_COMMAND_READ_STATUS 0x0e 419 #define SLI4_MBOX_COMMAND_READ_NVPARMS 0x02 420 #define SLI4_MBOX_COMMAND_READ_REV 0x11 421 #define SLI4_MBOX_COMMAND_READ_LNK_STAT 0x12 422 #define SLI4_MBOX_COMMAND_READ_SPARM64 0x8d 423 #define SLI4_MBOX_COMMAND_READ_TOPOLOGY 0x95 424 #define SLI4_MBOX_COMMAND_REG_FCFI 0xa0 425 #define SLI4_MBOX_COMMAND_REG_FCFI_MRQ 0xaf 426 #define SLI4_MBOX_COMMAND_REG_RPI 0x93 427 #define SLI4_MBOX_COMMAND_REG_RX_RQ 0xa6 428 #define SLI4_MBOX_COMMAND_REG_VFI 0x9f 429 #define SLI4_MBOX_COMMAND_REG_VPI 0x96 430 #define SLI4_MBOX_COMMAND_REQUEST_FEATURES 0x9d 431 #define SLI4_MBOX_COMMAND_SLI_CONFIG 0x9b 432 #define SLI4_MBOX_COMMAND_UNREG_FCFI 0xa2 433 #define SLI4_MBOX_COMMAND_UNREG_RPI 0x14 434 #define SLI4_MBOX_COMMAND_UNREG_VFI 0xa1 435 #define SLI4_MBOX_COMMAND_UNREG_VPI 0x97 436 #define SLI4_MBOX_COMMAND_WRITE_NVPARMS 0x03 437 #define SLI4_MBOX_COMMAND_CONFIG_AUTO_XFER_RDY 0xAD 438 #define SLI4_MBOX_COMMAND_CONFIG_AUTO_XFER_RDY_HP 0xAE 439 440 #define SLI4_MBOX_STATUS_SUCCESS 0x0000 441 #define SLI4_MBOX_STATUS_FAILURE 0x0001 442 #define SLI4_MBOX_STATUS_RPI_NOT_REG 0x1400 443 444 /** 445 * @brief Buffer Descriptor Entry (BDE) 446 */ 447 typedef struct sli4_bde_s { 448 #if BYTE_ORDER == LITTLE_ENDIAN 449 uint32_t buffer_length:24, 450 bde_type:8; 451 union { 452 struct { 453 uint32_t buffer_address_low; 454 uint32_t buffer_address_high; 455 } data; 456 struct { 457 uint32_t offset; 458 uint32_t rsvd2; 459 } imm; 460 struct { 461 uint32_t sgl_segment_address_low; 462 uint32_t sgl_segment_address_high; 463 } blp; 464 } u; 465 #else 466 #error big endian version not defined 467 #endif 468 } sli4_bde_t; 469 470 #define SLI4_BDE_TYPE_BDE_64 0x00 /** Generic 64-bit data */ 471 #define SLI4_BDE_TYPE_BDE_IMM 0x01 /** Immediate data */ 472 #define SLI4_BDE_TYPE_BLP 0x40 /** Buffer List Pointer */ 473 474 /** 475 * @brief Scatter-Gather Entry (SGE) 476 */ 477 typedef struct sli4_sge_s { 478 #if BYTE_ORDER == LITTLE_ENDIAN 479 uint32_t buffer_address_high; 480 uint32_t buffer_address_low; 481 uint32_t data_offset:27, 482 sge_type:4, 483 last:1; 484 uint32_t buffer_length; 485 #else 486 #error big endian version not defined 487 #endif 488 } sli4_sge_t; 489 490 /** 491 * @brief T10 DIF Scatter-Gather Entry (SGE) 492 */ 493 typedef struct sli4_dif_sge_s { 494 #if BYTE_ORDER == LITTLE_ENDIAN 495 uint32_t buffer_address_high; 496 uint32_t buffer_address_low; 497 uint32_t :27, 498 sge_type:4, 499 last:1; 500 uint32_t :32; 501 #else 502 #error big endian version not defined 503 #endif 504 } sli4_dif_sge_t; 505 506 /** 507 * @brief T10 DIF Seed Scatter-Gather Entry (SGE) 508 */ 509 typedef struct sli4_diseed_sge_s { 510 #if BYTE_ORDER == LITTLE_ENDIAN 511 uint32_t ref_tag_cmp; 512 uint32_t ref_tag_repl; 513 uint32_t app_tag_repl:16, 514 :2, 515 hs:1, 516 ws:1, 517 ic:1, 518 ics:1, 519 atrt:1, 520 at:1, 521 fwd_app_tag:1, 522 repl_app_tag:1, 523 head_insert:1, 524 sge_type:4, 525 last:1; 526 uint32_t app_tag_cmp:16, 527 dif_blk_size:3, 528 auto_incr_ref_tag:1, 529 check_app_tag:1, 530 check_ref_tag:1, 531 check_crc:1, 532 new_ref_tag:1, 533 dif_op_rx:4, 534 dif_op_tx:4; 535 #else 536 #error big endian version not defined 537 #endif 538 } sli4_diseed_sge_t; 539 540 /** 541 * @brief List Segment Pointer Scatter-Gather Entry (SGE) 542 */ 543 typedef struct sli4_lsp_sge_s { 544 #if BYTE_ORDER == LITTLE_ENDIAN 545 uint32_t buffer_address_high; 546 uint32_t buffer_address_low; 547 uint32_t :27, 548 sge_type:4, 549 last:1; 550 uint32_t segment_length:24, 551 :8; 552 #else 553 #error big endian version not defined 554 #endif 555 } sli4_lsp_sge_t; 556 557 #define SLI4_SGE_MAX_RESERVED 3 558 559 #define SLI4_SGE_DIF_OP_IN_NODIF_OUT_CRC 0x00 560 #define SLI4_SGE_DIF_OP_IN_CRC_OUT_NODIF 0x01 561 #define SLI4_SGE_DIF_OP_IN_NODIF_OUT_CHKSUM 0x02 562 #define SLI4_SGE_DIF_OP_IN_CHKSUM_OUT_NODIF 0x03 563 #define SLI4_SGE_DIF_OP_IN_CRC_OUT_CRC 0x04 564 #define SLI4_SGE_DIF_OP_IN_CHKSUM_OUT_CHKSUM 0x05 565 #define SLI4_SGE_DIF_OP_IN_CRC_OUT_CHKSUM 0x06 566 #define SLI4_SGE_DIF_OP_IN_CHKSUM_OUT_CRC 0x07 567 #define SLI4_SGE_DIF_OP_IN_RAW_OUT_RAW 0x08 568 569 #define SLI4_SGE_TYPE_DATA 0x00 570 #define SLI4_SGE_TYPE_CHAIN 0x03 /** Skyhawk only */ 571 #define SLI4_SGE_TYPE_DIF 0x04 /** Data Integrity Field */ 572 #define SLI4_SGE_TYPE_LSP 0x05 /** List Segment Pointer */ 573 #define SLI4_SGE_TYPE_PEDIF 0x06 /** Post Encryption Engine DIF */ 574 #define SLI4_SGE_TYPE_PESEED 0x07 /** Post Encryption Engine DIF Seed */ 575 #define SLI4_SGE_TYPE_DISEED 0x08 /** DIF Seed */ 576 #define SLI4_SGE_TYPE_ENC 0x09 /** Encryption */ 577 #define SLI4_SGE_TYPE_ATM 0x0a /** DIF Application Tag Mask */ 578 #define SLI4_SGE_TYPE_SKIP 0x0c /** SKIP */ 579 580 #define OCS_MAX_SGE_SIZE 0x80000000 /* Maximum data allowed in a SGE */ 581 582 /** 583 * @brief CONFIG_LINK 584 */ 585 typedef struct sli4_cmd_config_link_s { 586 sli4_mbox_command_header_t hdr; 587 #if BYTE_ORDER == LITTLE_ENDIAN 588 uint32_t maxbbc:8, /** Max buffer-to-buffer credit */ 589 :24; 590 uint32_t alpa:8, 591 n_port_id:16, 592 :8; 593 uint32_t rsvd3; 594 uint32_t e_d_tov; 595 uint32_t lp_tov; 596 uint32_t r_a_tov; 597 uint32_t r_t_tov; 598 uint32_t al_tov; 599 uint32_t rsvd9; 600 uint32_t :8, 601 bbscn:4, /** buffer-to-buffer state change number */ 602 cscn:1, /** configure BBSCN */ 603 :19; 604 #else 605 #error big endian version not defined 606 #endif 607 } sli4_cmd_config_link_t; 608 609 /** 610 * @brief DUMP Type 4 611 */ 612 #define SLI4_WKI_TAG_SAT_TEM 0x1040 613 typedef struct sli4_cmd_dump4_s { 614 sli4_mbox_command_header_t hdr; 615 #if BYTE_ORDER == LITTLE_ENDIAN 616 uint32_t type:4, 617 :28; 618 uint32_t wki_selection:16, 619 :16; 620 uint32_t resv; 621 uint32_t returned_byte_cnt; 622 uint32_t resp_data[59]; 623 #else 624 #error big endian version not defined 625 #endif 626 } sli4_cmd_dump4_t; 627 628 /** 629 * @brief FW_INITIALIZE - initialize a SLI port 630 * 631 * @note This command uses a different format than all others. 632 */ 633 634 extern const uint8_t sli4_fw_initialize[8]; 635 636 /** 637 * @brief FW_DEINITIALIZE - deinitialize a SLI port 638 * 639 * @note This command uses a different format than all others. 640 */ 641 642 extern const uint8_t sli4_fw_deinitialize[8]; 643 644 /** 645 * @brief INIT_LINK - initialize the link for a FC/FCoE port 646 */ 647 typedef struct sli4_cmd_init_link_flags_s { 648 uint32_t loopback:1, 649 topology:2, 650 #define FC_TOPOLOGY_FCAL 0 651 #define FC_TOPOLOGY_P2P 1 652 :3, 653 unfair:1, 654 skip_lirp_lilp:1, 655 gen_loop_validity_check:1, 656 skip_lisa:1, 657 enable_topology_failover:1, 658 fixed_speed:1, 659 :3, 660 select_hightest_al_pa:1, 661 :16; /* pad to 32 bits */ 662 } sli4_cmd_init_link_flags_t; 663 664 #define SLI4_INIT_LINK_F_LOOP_BACK BIT(0) 665 #define SLI4_INIT_LINK_F_UNFAIR BIT(6) 666 #define SLI4_INIT_LINK_F_NO_LIRP BIT(7) 667 #define SLI4_INIT_LINK_F_LOOP_VALID_CHK BIT(8) 668 #define SLI4_INIT_LINK_F_NO_LISA BIT(9) 669 #define SLI4_INIT_LINK_F_FAIL_OVER BIT(10) 670 #define SLI4_INIT_LINK_F_NO_AUTOSPEED BIT(11) 671 #define SLI4_INIT_LINK_F_PICK_HI_ALPA BIT(15) 672 673 #define SLI4_INIT_LINK_F_P2P_ONLY 1 674 #define SLI4_INIT_LINK_F_FCAL_ONLY 2 675 676 #define SLI4_INIT_LINK_F_FCAL_FAIL_OVER 0 677 #define SLI4_INIT_LINK_F_P2P_FAIL_OVER 1 678 679 typedef struct sli4_cmd_init_link_s { 680 sli4_mbox_command_header_t hdr; 681 #if BYTE_ORDER == LITTLE_ENDIAN 682 uint32_t selective_reset_al_pa:8, 683 :24; 684 sli4_cmd_init_link_flags_t link_flags; 685 uint32_t link_speed_selection_code; 686 #define FC_LINK_SPEED_1G 1 687 #define FC_LINK_SPEED_2G 2 688 #define FC_LINK_SPEED_AUTO_1_2 3 689 #define FC_LINK_SPEED_4G 4 690 #define FC_LINK_SPEED_AUTO_4_1 5 691 #define FC_LINK_SPEED_AUTO_4_2 6 692 #define FC_LINK_SPEED_AUTO_4_2_1 7 693 #define FC_LINK_SPEED_8G 8 694 #define FC_LINK_SPEED_AUTO_8_1 9 695 #define FC_LINK_SPEED_AUTO_8_2 10 696 #define FC_LINK_SPEED_AUTO_8_2_1 11 697 #define FC_LINK_SPEED_AUTO_8_4 12 698 #define FC_LINK_SPEED_AUTO_8_4_1 13 699 #define FC_LINK_SPEED_AUTO_8_4_2 14 700 #define FC_LINK_SPEED_10G 16 701 #define FC_LINK_SPEED_16G 17 702 #define FC_LINK_SPEED_AUTO_16_8_4 18 703 #define FC_LINK_SPEED_AUTO_16_8 19 704 #define FC_LINK_SPEED_32G 20 705 #define FC_LINK_SPEED_AUTO_32_16_8 21 706 #define FC_LINK_SPEED_AUTO_32_16 22 707 #else 708 #error big endian version not defined 709 #endif 710 } sli4_cmd_init_link_t; 711 712 /** 713 * @brief INIT_VFI - initialize the VFI resource 714 */ 715 typedef struct sli4_cmd_init_vfi_s { 716 sli4_mbox_command_header_t hdr; 717 #if BYTE_ORDER == LITTLE_ENDIAN 718 uint32_t vfi:16, 719 :12, 720 vp:1, 721 vf:1, 722 vt:1, 723 vr:1; 724 uint32_t fcfi:16, 725 vpi:16; 726 uint32_t vf_id:13, 727 pri:3, 728 :16; 729 uint32_t :24, 730 hop_count:8; 731 #else 732 #error big endian version not defined 733 #endif 734 } sli4_cmd_init_vfi_t; 735 736 /** 737 * @brief INIT_VPI - initialize the VPI resource 738 */ 739 typedef struct sli4_cmd_init_vpi_s { 740 sli4_mbox_command_header_t hdr; 741 #if BYTE_ORDER == LITTLE_ENDIAN 742 uint32_t vpi:16, 743 vfi:16; 744 #else 745 #error big endian version not defined 746 #endif 747 } sli4_cmd_init_vpi_t; 748 749 /** 750 * @brief POST_XRI - post XRI resources to the SLI Port 751 */ 752 typedef struct sli4_cmd_post_xri_s { 753 sli4_mbox_command_header_t hdr; 754 #if BYTE_ORDER == LITTLE_ENDIAN 755 uint32_t xri_base:16, 756 xri_count:12, 757 enx:1, 758 dl:1, 759 di:1, 760 val:1; 761 #else 762 #error big endian version not defined 763 #endif 764 } sli4_cmd_post_xri_t; 765 766 /** 767 * @brief RELEASE_XRI - Release XRI resources from the SLI Port 768 */ 769 typedef struct sli4_cmd_release_xri_s { 770 sli4_mbox_command_header_t hdr; 771 #if BYTE_ORDER == LITTLE_ENDIAN 772 uint32_t released_xri_count:5, 773 :11, 774 xri_count:5, 775 :11; 776 struct { 777 uint32_t xri_tag0:16, 778 xri_tag1:16; 779 } xri_tbl[62]; 780 #else 781 #error big endian version not defined 782 #endif 783 } sli4_cmd_release_xri_t; 784 785 /** 786 * @brief READ_CONFIG - read SLI port configuration parameters 787 */ 788 typedef struct sli4_cmd_read_config_s { 789 sli4_mbox_command_header_t hdr; 790 } sli4_cmd_read_config_t; 791 792 typedef struct sli4_res_read_config_s { 793 sli4_mbox_command_header_t hdr; 794 #if BYTE_ORDER == LITTLE_ENDIAN 795 uint32_t :31, 796 ext:1; /** Resource Extents */ 797 uint32_t :24, 798 topology:8; 799 uint32_t rsvd3; 800 uint32_t e_d_tov:16, 801 :16; 802 uint32_t rsvd5; 803 uint32_t r_a_tov:16, 804 :16; 805 uint32_t rsvd7; 806 uint32_t rsvd8; 807 uint32_t lmt:16, /** Link Module Type */ 808 :16; 809 uint32_t rsvd10; 810 uint32_t rsvd11; 811 uint32_t xri_base:16, 812 xri_count:16; 813 uint32_t rpi_base:16, 814 rpi_count:16; 815 uint32_t vpi_base:16, 816 vpi_count:16; 817 uint32_t vfi_base:16, 818 vfi_count:16; 819 uint32_t :16, 820 fcfi_count:16; 821 uint32_t rq_count:16, 822 eq_count:16; 823 uint32_t wq_count:16, 824 cq_count:16; 825 uint32_t pad[45]; 826 #else 827 #error big endian version not defined 828 #endif 829 } sli4_res_read_config_t; 830 831 #define SLI4_READ_CFG_TOPO_FCOE 0x0 /** FCoE topology */ 832 #define SLI4_READ_CFG_TOPO_FC 0x1 /** FC topology unknown */ 833 #define SLI4_READ_CFG_TOPO_FC_DA 0x2 /** FC Direct Attach (non FC-AL) topology */ 834 #define SLI4_READ_CFG_TOPO_FC_AL 0x3 /** FC-AL topology */ 835 836 /** 837 * @brief READ_NVPARMS - read SLI port configuration parameters 838 */ 839 typedef struct sli4_cmd_read_nvparms_s { 840 sli4_mbox_command_header_t hdr; 841 #if BYTE_ORDER == LITTLE_ENDIAN 842 uint32_t rsvd1; 843 uint32_t rsvd2; 844 uint32_t rsvd3; 845 uint32_t rsvd4; 846 uint8_t wwpn[8]; 847 uint8_t wwnn[8]; 848 uint32_t hard_alpa:8, 849 preferred_d_id:24; 850 #else 851 #error big endian version not defined 852 #endif 853 } sli4_cmd_read_nvparms_t; 854 855 /** 856 * @brief WRITE_NVPARMS - write SLI port configuration parameters 857 */ 858 typedef struct sli4_cmd_write_nvparms_s { 859 sli4_mbox_command_header_t hdr; 860 #if BYTE_ORDER == LITTLE_ENDIAN 861 uint32_t rsvd1; 862 uint32_t rsvd2; 863 uint32_t rsvd3; 864 uint32_t rsvd4; 865 uint8_t wwpn[8]; 866 uint8_t wwnn[8]; 867 uint32_t hard_alpa:8, 868 preferred_d_id:24; 869 #else 870 #error big endian version not defined 871 #endif 872 } sli4_cmd_write_nvparms_t; 873 874 /** 875 * @brief READ_REV - read the Port revision levels 876 */ 877 typedef struct sli4_cmd_read_rev_s { 878 sli4_mbox_command_header_t hdr; 879 #if BYTE_ORDER == LITTLE_ENDIAN 880 uint32_t :16, 881 sli_level:4, 882 fcoem:1, 883 ceev:2, 884 :6, 885 vpd:1, 886 :2; 887 uint32_t first_hw_revision; 888 uint32_t second_hw_revision; 889 uint32_t rsvd4; 890 uint32_t third_hw_revision; 891 uint32_t fc_ph_low:8, 892 fc_ph_high:8, 893 feature_level_low:8, 894 feature_level_high:8; 895 uint32_t rsvd7; 896 uint32_t first_fw_id; 897 char first_fw_name[16]; 898 uint32_t second_fw_id; 899 char second_fw_name[16]; 900 uint32_t rsvd18[30]; 901 uint32_t available_length:24, 902 :8; 903 uint32_t physical_address_low; 904 uint32_t physical_address_high; 905 uint32_t returned_vpd_length; 906 uint32_t actual_vpd_length; 907 #else 908 #error big endian version not defined 909 #endif 910 } sli4_cmd_read_rev_t; 911 912 /** 913 * @brief READ_SPARM64 - read the Port service parameters 914 */ 915 typedef struct sli4_cmd_read_sparm64_s { 916 sli4_mbox_command_header_t hdr; 917 #if BYTE_ORDER == LITTLE_ENDIAN 918 uint32_t rsvd1; 919 uint32_t rsvd2; 920 sli4_bde_t bde_64; 921 uint32_t vpi:16, 922 :16; 923 uint32_t port_name_start:16, 924 port_name_length:16; 925 uint32_t node_name_start:16, 926 node_name_length:16; 927 #else 928 #error big endian version not defined 929 #endif 930 } sli4_cmd_read_sparm64_t; 931 932 #define SLI4_READ_SPARM64_VPI_DEFAULT 0 933 #define SLI4_READ_SPARM64_VPI_SPECIAL UINT16_MAX 934 935 #define SLI4_READ_SPARM64_WWPN_OFFSET (4 * sizeof(uint32_t)) 936 #define SLI4_READ_SPARM64_WWNN_OFFSET (SLI4_READ_SPARM64_WWPN_OFFSET + sizeof(uint64_t)) 937 938 typedef struct sli4_port_state_s { 939 #if BYTE_ORDER == LITTLE_ENDIAN 940 uint32_t nx_port_recv_state:2, 941 nx_port_trans_state:2, 942 nx_port_state_machine:4, 943 link_speed:8, 944 :14, 945 tf:1, 946 lu:1; 947 #else 948 #error big endian version not defined 949 #endif 950 } sli4_port_state_t; 951 952 /** 953 * @brief READ_TOPOLOGY - read the link event information 954 */ 955 typedef struct sli4_cmd_read_topology_s { 956 sli4_mbox_command_header_t hdr; 957 #if BYTE_ORDER == LITTLE_ENDIAN 958 uint32_t event_tag; 959 uint32_t attention_type:8, 960 il:1, 961 pb_recvd:1, 962 :22; 963 uint32_t topology:8, 964 lip_type:8, 965 lip_al_ps:8, 966 al_pa_granted:8; 967 sli4_bde_t bde_loop_map; 968 sli4_port_state_t link_down; 969 sli4_port_state_t link_current; 970 uint32_t max_bbc:8, 971 init_bbc:8, 972 bbscn:4, 973 cbbscn:4, 974 :8; 975 uint32_t r_t_tov:9, 976 :3, 977 al_tov:4, 978 lp_tov:16; 979 uint32_t acquired_al_pa:8, 980 :7, 981 pb:1, 982 specified_al_pa:16; 983 uint32_t initial_n_port_id:24, 984 :8; 985 #else 986 #error big endian version not defined 987 #endif 988 } sli4_cmd_read_topology_t; 989 990 #define SLI4_MIN_LOOP_MAP_BYTES 128 991 992 #define SLI4_READ_TOPOLOGY_LINK_UP 0x1 993 #define SLI4_READ_TOPOLOGY_LINK_DOWN 0x2 994 #define SLI4_READ_TOPOLOGY_LINK_NO_ALPA 0x3 995 996 #define SLI4_READ_TOPOLOGY_UNKNOWN 0x0 997 #define SLI4_READ_TOPOLOGY_NPORT 0x1 998 #define SLI4_READ_TOPOLOGY_FC_AL 0x2 999 1000 #define SLI4_READ_TOPOLOGY_SPEED_NONE 0x00 1001 #define SLI4_READ_TOPOLOGY_SPEED_1G 0x04 1002 #define SLI4_READ_TOPOLOGY_SPEED_2G 0x08 1003 #define SLI4_READ_TOPOLOGY_SPEED_4G 0x10 1004 #define SLI4_READ_TOPOLOGY_SPEED_8G 0x20 1005 #define SLI4_READ_TOPOLOGY_SPEED_10G 0x40 1006 #define SLI4_READ_TOPOLOGY_SPEED_16G 0x80 1007 #define SLI4_READ_TOPOLOGY_SPEED_32G 0x90 1008 1009 /** 1010 * @brief REG_FCFI - activate a FC Forwarder 1011 */ 1012 #define SLI4_CMD_REG_FCFI_NUM_RQ_CFG 4 1013 typedef struct sli4_cmd_reg_fcfi_s { 1014 sli4_mbox_command_header_t hdr; 1015 #if BYTE_ORDER == LITTLE_ENDIAN 1016 uint32_t fcf_index:16, 1017 fcfi:16; 1018 uint32_t rq_id_1:16, 1019 rq_id_0:16; 1020 uint32_t rq_id_3:16, 1021 rq_id_2:16; 1022 struct { 1023 uint32_t r_ctl_mask:8, 1024 r_ctl_match:8, 1025 type_mask:8, 1026 type_match:8; 1027 } rq_cfg[SLI4_CMD_REG_FCFI_NUM_RQ_CFG]; 1028 uint32_t vlan_tag:12, 1029 vv:1, 1030 :19; 1031 #else 1032 #error big endian version not defined 1033 #endif 1034 } sli4_cmd_reg_fcfi_t; 1035 1036 #define SLI4_CMD_REG_FCFI_MRQ_NUM_RQ_CFG 4 1037 #define SLI4_CMD_REG_FCFI_MRQ_MAX_NUM_RQ 32 1038 #define SLI4_CMD_REG_FCFI_SET_FCFI_MODE 0 1039 #define SLI4_CMD_REG_FCFI_SET_MRQ_MODE 1 1040 1041 typedef struct sli4_cmd_reg_fcfi_mrq_s { 1042 sli4_mbox_command_header_t hdr; 1043 #if BYTE_ORDER == LITTLE_ENDIAN 1044 uint32_t fcf_index:16, 1045 fcfi:16; 1046 1047 uint32_t rq_id_1:16, 1048 rq_id_0:16; 1049 1050 uint32_t rq_id_3:16, 1051 rq_id_2:16; 1052 1053 struct { 1054 uint32_t r_ctl_mask:8, 1055 r_ctl_match:8, 1056 type_mask:8, 1057 type_match:8; 1058 } rq_cfg[SLI4_CMD_REG_FCFI_MRQ_NUM_RQ_CFG]; 1059 1060 uint32_t vlan_tag:12, 1061 vv:1, 1062 mode:1, 1063 :18; 1064 1065 uint32_t num_mrq_pairs:8, 1066 mrq_filter_bitmask:4, 1067 rq_selection_policy:4, 1068 :16; 1069 #endif 1070 } sli4_cmd_reg_fcfi_mrq_t; 1071 1072 /** 1073 * @brief REG_RPI - register a Remote Port Indicator 1074 */ 1075 typedef struct sli4_cmd_reg_rpi_s { 1076 sli4_mbox_command_header_t hdr; 1077 #if BYTE_ORDER == LITTLE_ENDIAN 1078 uint32_t rpi:16, 1079 :16; 1080 uint32_t remote_n_port_id:24, 1081 upd:1, 1082 :2, 1083 etow:1, 1084 :1, 1085 terp:1, 1086 :1, 1087 ci:1; 1088 sli4_bde_t bde_64; 1089 uint32_t vpi:16, 1090 :16; 1091 #else 1092 #error big endian version not defined 1093 #endif 1094 } sli4_cmd_reg_rpi_t; 1095 #define SLI4_REG_RPI_BUF_LEN 0x70 1096 1097 /** 1098 * @brief REG_VFI - register a Virtual Fabric Indicator 1099 */ 1100 typedef struct sli4_cmd_reg_vfi_s { 1101 sli4_mbox_command_header_t hdr; 1102 #if BYTE_ORDER == LITTLE_ENDIAN 1103 uint32_t vfi:16, 1104 :12, 1105 vp:1, 1106 upd:1, 1107 :2; 1108 uint32_t fcfi:16, 1109 vpi:16; /* vp=TRUE */ 1110 uint8_t wwpn[8]; /* vp=TRUE */ 1111 sli4_bde_t sparm; /* either FLOGI or PLOGI */ 1112 uint32_t e_d_tov; 1113 uint32_t r_a_tov; 1114 uint32_t local_n_port_id:24, /* vp=TRUE */ 1115 :8; 1116 #else 1117 #error big endian version not defined 1118 #endif 1119 } sli4_cmd_reg_vfi_t; 1120 1121 /** 1122 * @brief REG_VPI - register a Virtual Port Indicator 1123 */ 1124 typedef struct sli4_cmd_reg_vpi_s { 1125 sli4_mbox_command_header_t hdr; 1126 #if BYTE_ORDER == LITTLE_ENDIAN 1127 uint32_t rsvd1; 1128 uint32_t local_n_port_id:24, 1129 upd:1, 1130 :7; 1131 uint8_t wwpn[8]; 1132 uint32_t rsvd5; 1133 uint32_t vpi:16, 1134 vfi:16; 1135 #else 1136 #error big endian version not defined 1137 #endif 1138 } sli4_cmd_reg_vpi_t; 1139 1140 /** 1141 * @brief REQUEST_FEATURES - request / query SLI features 1142 */ 1143 typedef union { 1144 #if BYTE_ORDER == LITTLE_ENDIAN 1145 struct { 1146 uint32_t iaab:1, /** inhibit auto-ABTS originator */ 1147 npiv:1, /** NPIV support */ 1148 dif:1, /** DIF/DIX support */ 1149 vf:1, /** virtual fabric support */ 1150 fcpi:1, /** FCP initiator support */ 1151 fcpt:1, /** FCP target support */ 1152 fcpc:1, /** combined FCP initiator/target */ 1153 :1, 1154 rqd:1, /** recovery qualified delay */ 1155 iaar:1, /** inhibit auto-ABTS responder */ 1156 hlm:1, /** High Login Mode */ 1157 perfh:1, /** performance hints */ 1158 rxseq:1, /** RX Sequence Coalescing */ 1159 rxri:1, /** Release XRI variant of Coalescing */ 1160 dcl2:1, /** Disable Class 2 */ 1161 rsco:1, /** Receive Sequence Coalescing Optimizations */ 1162 mrqp:1, /** Multi RQ Pair Mode Support */ 1163 :15; 1164 } flag; 1165 uint32_t dword; 1166 #else 1167 #error big endian version not defined 1168 #endif 1169 } sli4_features_t; 1170 1171 typedef struct sli4_cmd_request_features_s { 1172 sli4_mbox_command_header_t hdr; 1173 #if BYTE_ORDER == LITTLE_ENDIAN 1174 uint32_t qry:1, 1175 :31; 1176 #else 1177 #error big endian version not defined 1178 #endif 1179 sli4_features_t command; 1180 sli4_features_t response; 1181 } sli4_cmd_request_features_t; 1182 1183 /** 1184 * @brief SLI_CONFIG - submit a configuration command to Port 1185 * 1186 * Command is either embedded as part of the payload (embed) or located 1187 * in a separate memory buffer (mem) 1188 */ 1189 1190 typedef struct sli4_sli_config_pmd_s { 1191 uint32_t address_low; 1192 uint32_t address_high; 1193 uint32_t length:24, 1194 :8; 1195 } sli4_sli_config_pmd_t; 1196 1197 typedef struct sli4_cmd_sli_config_s { 1198 sli4_mbox_command_header_t hdr; 1199 #if BYTE_ORDER == LITTLE_ENDIAN 1200 uint32_t emb:1, 1201 :2, 1202 pmd_count:5, 1203 :24; 1204 uint32_t payload_length; 1205 uint32_t rsvd3; 1206 uint32_t rsvd4; 1207 uint32_t rsvd5; 1208 union { 1209 uint8_t embed[58 * sizeof(uint32_t)]; 1210 sli4_sli_config_pmd_t mem; 1211 } payload; 1212 #else 1213 #error big endian version not defined 1214 #endif 1215 } sli4_cmd_sli_config_t; 1216 1217 /** 1218 * @brief READ_STATUS - read tx/rx status of a particular port 1219 * 1220 */ 1221 1222 typedef struct sli4_cmd_read_status_s { 1223 sli4_mbox_command_header_t hdr; 1224 #if BYTE_ORDER == LITTLE_ENDIAN 1225 uint32_t cc:1, 1226 :31; 1227 uint32_t rsvd2; 1228 uint32_t transmit_kbyte_count; 1229 uint32_t receive_kbyte_count; 1230 uint32_t transmit_frame_count; 1231 uint32_t receive_frame_count; 1232 uint32_t transmit_sequence_count; 1233 uint32_t receive_sequence_count; 1234 uint32_t total_exchanges_originator; 1235 uint32_t total_exchanges_responder; 1236 uint32_t receive_p_bsy_count; 1237 uint32_t receive_f_bsy_count; 1238 uint32_t dropped_frames_due_to_no_rq_buffer_count; 1239 uint32_t empty_rq_timeout_count; 1240 uint32_t dropped_frames_due_to_no_xri_count; 1241 uint32_t empty_xri_pool_count; 1242 1243 #else 1244 #error big endian version not defined 1245 #endif 1246 } sli4_cmd_read_status_t; 1247 1248 /** 1249 * @brief READ_LNK_STAT - read link status of a particular port 1250 * 1251 */ 1252 1253 typedef struct sli4_cmd_read_link_stats_s { 1254 sli4_mbox_command_header_t hdr; 1255 #if BYTE_ORDER == LITTLE_ENDIAN 1256 uint32_t rec:1, 1257 gec:1, 1258 w02of:1, 1259 w03of:1, 1260 w04of:1, 1261 w05of:1, 1262 w06of:1, 1263 w07of:1, 1264 w08of:1, 1265 w09of:1, 1266 w10of:1, 1267 w11of:1, 1268 w12of:1, 1269 w13of:1, 1270 w14of:1, 1271 w15of:1, 1272 w16of:1, 1273 w17of:1, 1274 w18of:1, 1275 w19of:1, 1276 w20of:1, 1277 w21of:1, 1278 resv0:8, 1279 clrc:1, 1280 clof:1; 1281 uint32_t link_failure_error_count; 1282 uint32_t loss_of_sync_error_count; 1283 uint32_t loss_of_signal_error_count; 1284 uint32_t primitive_sequence_error_count; 1285 uint32_t invalid_transmission_word_error_count; 1286 uint32_t crc_error_count; 1287 uint32_t primitive_sequence_event_timeout_count; 1288 uint32_t elastic_buffer_overrun_error_count; 1289 uint32_t arbitration_fc_al_timout_count; 1290 uint32_t advertised_receive_bufftor_to_buffer_credit; 1291 uint32_t current_receive_buffer_to_buffer_credit; 1292 uint32_t advertised_transmit_buffer_to_buffer_credit; 1293 uint32_t current_transmit_buffer_to_buffer_credit; 1294 uint32_t received_eofa_count; 1295 uint32_t received_eofdti_count; 1296 uint32_t received_eofni_count; 1297 uint32_t received_soff_count; 1298 uint32_t received_dropped_no_aer_count; 1299 uint32_t received_dropped_no_available_rpi_resources_count; 1300 uint32_t received_dropped_no_available_xri_resources_count; 1301 1302 #else 1303 #error big endian version not defined 1304 #endif 1305 } sli4_cmd_read_link_stats_t; 1306 1307 /** 1308 * @brief Format a WQE with WQ_ID Association performance hint 1309 * 1310 * @par Description 1311 * PHWQ works by over-writing part of Word 10 in the WQE with the WQ ID. 1312 * 1313 * @param entry Pointer to the WQE. 1314 * @param q_id Queue ID. 1315 * 1316 * @return None. 1317 */ 1318 static inline void 1319 sli_set_wq_id_association(void *entry, uint16_t q_id) 1320 { 1321 uint32_t *wqe = entry; 1322 1323 /* 1324 * Set Word 10, bit 0 to zero 1325 * Set Word 10, bits 15:1 to the WQ ID 1326 */ 1327 #if BYTE_ORDER == LITTLE_ENDIAN 1328 wqe[10] &= ~0xffff; 1329 wqe[10] |= q_id << 1; 1330 #else 1331 #error big endian version not defined 1332 #endif 1333 } 1334 1335 /** 1336 * @brief UNREG_FCFI - unregister a FCFI 1337 */ 1338 typedef struct sli4_cmd_unreg_fcfi_s { 1339 sli4_mbox_command_header_t hdr; 1340 uint32_t rsvd1; 1341 #if BYTE_ORDER == LITTLE_ENDIAN 1342 uint32_t fcfi:16, 1343 :16; 1344 #else 1345 #error big endian version not defined 1346 #endif 1347 } sli4_cmd_unreg_fcfi_t; 1348 1349 /** 1350 * @brief UNREG_RPI - unregister one or more RPI 1351 */ 1352 typedef struct sli4_cmd_unreg_rpi_s { 1353 sli4_mbox_command_header_t hdr; 1354 #if BYTE_ORDER == LITTLE_ENDIAN 1355 uint32_t index:16, 1356 :13, 1357 dp:1, 1358 ii:2; 1359 uint32_t destination_n_port_id:24, 1360 :8; 1361 #else 1362 #error big endian version not defined 1363 #endif 1364 } sli4_cmd_unreg_rpi_t; 1365 1366 #define SLI4_UNREG_RPI_II_RPI 0x0 1367 #define SLI4_UNREG_RPI_II_VPI 0x1 1368 #define SLI4_UNREG_RPI_II_VFI 0x2 1369 #define SLI4_UNREG_RPI_II_FCFI 0x3 1370 1371 /** 1372 * @brief UNREG_VFI - unregister one or more VFI 1373 */ 1374 typedef struct sli4_cmd_unreg_vfi_s { 1375 sli4_mbox_command_header_t hdr; 1376 #if BYTE_ORDER == LITTLE_ENDIAN 1377 uint32_t rsvd1; 1378 uint32_t index:16, 1379 :14, 1380 ii:2; 1381 #else 1382 #error big endian version not defined 1383 #endif 1384 } sli4_cmd_unreg_vfi_t; 1385 1386 #define SLI4_UNREG_VFI_II_VFI 0x0 1387 #define SLI4_UNREG_VFI_II_FCFI 0x3 1388 1389 enum { 1390 SLI4_UNREG_TYPE_PORT, 1391 SLI4_UNREG_TYPE_DOMAIN, 1392 SLI4_UNREG_TYPE_FCF, 1393 SLI4_UNREG_TYPE_ALL 1394 }; 1395 1396 /** 1397 * @brief UNREG_VPI - unregister one or more VPI 1398 */ 1399 typedef struct sli4_cmd_unreg_vpi_s { 1400 sli4_mbox_command_header_t hdr; 1401 #if BYTE_ORDER == LITTLE_ENDIAN 1402 uint32_t rsvd1; 1403 uint32_t index:16, 1404 :14, 1405 ii:2; 1406 #else 1407 #error big endian version not defined 1408 #endif 1409 } sli4_cmd_unreg_vpi_t; 1410 1411 #define SLI4_UNREG_VPI_II_VPI 0x0 1412 #define SLI4_UNREG_VPI_II_VFI 0x2 1413 #define SLI4_UNREG_VPI_II_FCFI 0x3 1414 1415 /** 1416 * @brief AUTO_XFER_RDY - Configure the auto-generate XFER-RDY feature. 1417 */ 1418 typedef struct sli4_cmd_config_auto_xfer_rdy_s { 1419 sli4_mbox_command_header_t hdr; 1420 #if BYTE_ORDER == LITTLE_ENDIAN 1421 uint32_t resv; 1422 uint32_t max_burst_len; 1423 #else 1424 #error big endian version not defined 1425 #endif 1426 } sli4_cmd_config_auto_xfer_rdy_t; 1427 1428 typedef struct sli4_cmd_config_auto_xfer_rdy_hp_s { 1429 sli4_mbox_command_header_t hdr; 1430 #if BYTE_ORDER == LITTLE_ENDIAN 1431 uint32_t resv; 1432 uint32_t max_burst_len; 1433 uint32_t esoc:1, 1434 :31; 1435 uint32_t block_size:16, 1436 :16; 1437 #else 1438 #error big endian version not defined 1439 #endif 1440 } sli4_cmd_config_auto_xfer_rdy_hp_t; 1441 1442 /************************************************************************* 1443 * SLI-4 common configuration command formats and definitions 1444 */ 1445 1446 #define SLI4_CFG_STATUS_SUCCESS 0x00 1447 #define SLI4_CFG_STATUS_FAILED 0x01 1448 #define SLI4_CFG_STATUS_ILLEGAL_REQUEST 0x02 1449 #define SLI4_CFG_STATUS_ILLEGAL_FIELD 0x03 1450 1451 #define SLI4_MGMT_STATUS_FLASHROM_READ_FAILED 0xcb 1452 1453 #define SLI4_CFG_ADD_STATUS_NO_STATUS 0x00 1454 #define SLI4_CFG_ADD_STATUS_INVALID_OPCODE 0x1e 1455 1456 /** 1457 * Subsystem values. 1458 */ 1459 #define SLI4_SUBSYSTEM_COMMON 0x01 1460 #define SLI4_SUBSYSTEM_LOWLEVEL 0x0B 1461 #define SLI4_SUBSYSTEM_FCFCOE 0x0c 1462 #define SLI4_SUBSYSTEM_DMTF 0x11 1463 1464 #define SLI4_OPC_LOWLEVEL_SET_WATCHDOG 0X36 1465 1466 /** 1467 * Common opcode (OPC) values. 1468 */ 1469 #define SLI4_OPC_COMMON_FUNCTION_RESET 0x3d 1470 #define SLI4_OPC_COMMON_CREATE_CQ 0x0c 1471 #define SLI4_OPC_COMMON_CREATE_CQ_SET 0x1d 1472 #define SLI4_OPC_COMMON_DESTROY_CQ 0x36 1473 #define SLI4_OPC_COMMON_MODIFY_EQ_DELAY 0x29 1474 #define SLI4_OPC_COMMON_CREATE_EQ 0x0d 1475 #define SLI4_OPC_COMMON_DESTROY_EQ 0x37 1476 #define SLI4_OPC_COMMON_CREATE_MQ_EXT 0x5a 1477 #define SLI4_OPC_COMMON_DESTROY_MQ 0x35 1478 #define SLI4_OPC_COMMON_GET_CNTL_ATTRIBUTES 0x20 1479 #define SLI4_OPC_COMMON_NOP 0x21 1480 #define SLI4_OPC_COMMON_GET_RESOURCE_EXTENT_INFO 0x9a 1481 #define SLI4_OPC_COMMON_GET_SLI4_PARAMETERS 0xb5 1482 #define SLI4_OPC_COMMON_QUERY_FW_CONFIG 0x3a 1483 #define SLI4_OPC_COMMON_GET_PORT_NAME 0x4d 1484 1485 #define SLI4_OPC_COMMON_WRITE_FLASHROM 0x07 1486 #define SLI4_OPC_COMMON_MANAGE_FAT 0x44 1487 #define SLI4_OPC_COMMON_READ_TRANSCEIVER_DATA 0x49 1488 #define SLI4_OPC_COMMON_GET_CNTL_ADDL_ATTRIBUTES 0x79 1489 #define SLI4_OPC_COMMON_GET_EXT_FAT_CAPABILITIES 0x7d 1490 #define SLI4_OPC_COMMON_SET_EXT_FAT_CAPABILITIES 0x7e 1491 #define SLI4_OPC_COMMON_EXT_FAT_CONFIGURE_SNAPSHOT 0x7f 1492 #define SLI4_OPC_COMMON_EXT_FAT_RETRIEVE_SNAPSHOT 0x80 1493 #define SLI4_OPC_COMMON_EXT_FAT_READ_STRING_TABLE 0x82 1494 #define SLI4_OPC_COMMON_GET_FUNCTION_CONFIG 0xa0 1495 #define SLI4_OPC_COMMON_GET_PROFILE_CONFIG 0xa4 1496 #define SLI4_OPC_COMMON_SET_PROFILE_CONFIG 0xa5 1497 #define SLI4_OPC_COMMON_GET_PROFILE_LIST 0xa6 1498 #define SLI4_OPC_COMMON_GET_ACTIVE_PROFILE 0xa7 1499 #define SLI4_OPC_COMMON_SET_ACTIVE_PROFILE 0xa8 1500 #define SLI4_OPC_COMMON_READ_OBJECT 0xab 1501 #define SLI4_OPC_COMMON_WRITE_OBJECT 0xac 1502 #define SLI4_OPC_COMMON_DELETE_OBJECT 0xae 1503 #define SLI4_OPC_COMMON_READ_OBJECT_LIST 0xad 1504 #define SLI4_OPC_COMMON_SET_DUMP_LOCATION 0xb8 1505 #define SLI4_OPC_COMMON_SET_FEATURES 0xbf 1506 #define SLI4_OPC_COMMON_GET_RECONFIG_LINK_INFO 0xc9 1507 #define SLI4_OPC_COMMON_SET_RECONFIG_LINK_ID 0xca 1508 1509 /** 1510 * DMTF opcode (OPC) values. 1511 */ 1512 #define SLI4_OPC_DMTF_EXEC_CLP_CMD 0x01 1513 1514 /** 1515 * @brief Generic Command Request header 1516 */ 1517 typedef struct sli4_req_hdr_s { 1518 #if BYTE_ORDER == LITTLE_ENDIAN 1519 uint32_t opcode:8, 1520 subsystem:8, 1521 :16; 1522 uint32_t timeout; 1523 uint32_t request_length; 1524 uint32_t version:8, 1525 :24; 1526 #else 1527 #error big endian version not defined 1528 #endif 1529 } sli4_req_hdr_t; 1530 1531 /** 1532 * @brief Generic Command Response header 1533 */ 1534 typedef struct sli4_res_hdr_s { 1535 #if BYTE_ORDER == LITTLE_ENDIAN 1536 uint32_t opcode:8, 1537 subsystem:8, 1538 :16; 1539 uint32_t status:8, 1540 additional_status:8, 1541 :16; 1542 uint32_t response_length; 1543 uint32_t actual_response_length; 1544 #else 1545 #error big endian version not defined 1546 #endif 1547 } sli4_res_hdr_t; 1548 1549 /** 1550 * @brief COMMON_FUNCTION_RESET 1551 * 1552 * Resets the Port, returning it to a power-on state. This configuration 1553 * command does not have a payload and should set/expect the lengths to 1554 * be zero. 1555 */ 1556 typedef struct sli4_req_common_function_reset_s { 1557 sli4_req_hdr_t hdr; 1558 } sli4_req_common_function_reset_t; 1559 1560 typedef struct sli4_res_common_function_reset_s { 1561 sli4_res_hdr_t hdr; 1562 } sli4_res_common_function_reset_t; 1563 1564 /** 1565 * @brief COMMON_CREATE_CQ_V0 1566 * 1567 * Create a Completion Queue. 1568 */ 1569 typedef struct sli4_req_common_create_cq_v0_s { 1570 sli4_req_hdr_t hdr; 1571 #if BYTE_ORDER == LITTLE_ENDIAN 1572 uint32_t num_pages:16, 1573 :16; 1574 uint32_t :12, 1575 clswm:2, 1576 nodelay:1, 1577 :12, 1578 cqecnt:2, 1579 valid:1, 1580 :1, 1581 evt:1; 1582 uint32_t :22, 1583 eq_id:8, 1584 :1, 1585 arm:1; 1586 uint32_t rsvd[2]; 1587 struct { 1588 uint32_t low; 1589 uint32_t high; 1590 } page_physical_address[0]; 1591 #else 1592 #error big endian version not defined 1593 #endif 1594 } sli4_req_common_create_cq_v0_t; 1595 1596 /** 1597 * @brief COMMON_CREATE_CQ_V2 1598 * 1599 * Create a Completion Queue. 1600 */ 1601 typedef struct sli4_req_common_create_cq_v2_s { 1602 sli4_req_hdr_t hdr; 1603 #if BYTE_ORDER == LITTLE_ENDIAN 1604 uint32_t num_pages:16, 1605 page_size:8, 1606 :8, 1607 uint32_t :12, 1608 clswm:2, 1609 nodelay:1, 1610 autovalid:1, 1611 :9, 1612 cqe_size:2, 1613 cqecnt:2, 1614 valid:1, 1615 :1, 1616 evt:1; 1617 uint32_t eq_id:16, 1618 :15, 1619 arm:1; 1620 uint32_t cqe_count:16, 1621 :16; 1622 uint32_t rsvd[1]; 1623 struct { 1624 uint32_t low; 1625 uint32_t high; 1626 } page_physical_address[0]; 1627 #else 1628 #error big endian version not defined 1629 #endif 1630 } sli4_req_common_create_cq_v2_t; 1631 1632 /** 1633 * @brief COMMON_CREATE_CQ_SET_V0 1634 * 1635 * Create a set of Completion Queues. 1636 */ 1637 typedef struct sli4_req_common_create_cq_set_v0_s { 1638 sli4_req_hdr_t hdr; 1639 #if BYTE_ORDER == LITTLE_ENDIAN 1640 uint32_t num_pages:16, 1641 page_size:8, 1642 :8; 1643 uint32_t :12, 1644 clswm:2, 1645 nodelay:1, 1646 autovalid:1, 1647 rsvd:11, 1648 cqecnt:2, 1649 valid:1, 1650 :1, 1651 evt:1; 1652 uint32_t num_cq_req:16, 1653 cqe_count:15, 1654 arm:1; 1655 uint16_t eq_id[16]; 1656 struct { 1657 uint32_t low; 1658 uint32_t high; 1659 } page_physical_address[0]; 1660 #else 1661 #error big endian version not defined 1662 #endif 1663 } sli4_req_common_create_cq_set_v0_t; 1664 1665 /** 1666 * CQE count. 1667 */ 1668 #define SLI4_CQ_CNT_256 0 1669 #define SLI4_CQ_CNT_512 1 1670 #define SLI4_CQ_CNT_1024 2 1671 #define SLI4_CQ_CNT_LARGE 3 1672 1673 #define SLI4_CQE_BYTES (4 * sizeof(uint32_t)) 1674 1675 #define SLI4_COMMON_CREATE_CQ_V2_MAX_PAGES 8 1676 1677 /** 1678 * @brief Generic Common Create EQ/CQ/MQ/WQ/RQ Queue completion 1679 */ 1680 typedef struct sli4_res_common_create_queue_s { 1681 sli4_res_hdr_t hdr; 1682 #if BYTE_ORDER == LITTLE_ENDIAN 1683 uint32_t q_id:16, 1684 :8, 1685 ulp:8; 1686 uint32_t db_offset; 1687 uint32_t db_rs:16, 1688 db_fmt:16; 1689 #else 1690 #error big endian version not defined 1691 #endif 1692 } sli4_res_common_create_queue_t; 1693 1694 typedef struct sli4_res_common_create_queue_set_s { 1695 sli4_res_hdr_t hdr; 1696 #if BYTE_ORDER == LITTLE_ENDIAN 1697 uint32_t q_id:16, 1698 num_q_allocated:16; 1699 #else 1700 #error big endian version not defined 1701 #endif 1702 } sli4_res_common_create_queue_set_t; 1703 1704 /** 1705 * @brief Common Destroy CQ 1706 */ 1707 typedef struct sli4_req_common_destroy_cq_s { 1708 sli4_req_hdr_t hdr; 1709 #if BYTE_ORDER == LITTLE_ENDIAN 1710 uint32_t cq_id:16, 1711 :16; 1712 #else 1713 #error big endian version not defined 1714 #endif 1715 } sli4_req_common_destroy_cq_t; 1716 1717 /** 1718 * @brief COMMON_MODIFY_EQ_DELAY 1719 * 1720 * Modify the delay multiplier for EQs 1721 */ 1722 typedef struct sli4_req_common_modify_eq_delay_s { 1723 sli4_req_hdr_t hdr; 1724 #if BYTE_ORDER == LITTLE_ENDIAN 1725 uint32_t num_eq; 1726 struct { 1727 uint32_t eq_id; 1728 uint32_t phase; 1729 uint32_t delay_multiplier; 1730 } eq_delay_record[8]; 1731 #else 1732 #error big endian version not defined 1733 #endif 1734 } sli4_req_common_modify_eq_delay_t; 1735 1736 /** 1737 * @brief COMMON_CREATE_EQ 1738 * 1739 * Create an Event Queue. 1740 */ 1741 typedef struct sli4_req_common_create_eq_s { 1742 sli4_req_hdr_t hdr; 1743 #if BYTE_ORDER == LITTLE_ENDIAN 1744 uint32_t num_pages:16, 1745 :16; 1746 uint32_t :28, 1747 autovalid:1, 1748 valid:1, 1749 :1, 1750 eqesz:1; 1751 uint32_t :26, 1752 count:3, 1753 :2, 1754 arm:1; 1755 uint32_t :13, 1756 delay_multiplier:10, 1757 :9; 1758 uint32_t rsvd; 1759 struct { 1760 uint32_t low; 1761 uint32_t high; 1762 } page_address[8]; 1763 #else 1764 #error big endian version not defined 1765 #endif 1766 } sli4_req_common_create_eq_t; 1767 1768 #define SLI4_EQ_CNT_256 0 1769 #define SLI4_EQ_CNT_512 1 1770 #define SLI4_EQ_CNT_1024 2 1771 #define SLI4_EQ_CNT_2048 3 1772 #define SLI4_EQ_CNT_4096 4 1773 1774 #define SLI4_EQE_SIZE_4 0 1775 #define SLI4_EQE_SIZE_16 1 1776 1777 /** 1778 * @brief Common Destroy EQ 1779 */ 1780 typedef struct sli4_req_common_destroy_eq_s { 1781 sli4_req_hdr_t hdr; 1782 #if BYTE_ORDER == LITTLE_ENDIAN 1783 uint32_t eq_id:16, 1784 :16; 1785 #else 1786 #error big endian version not defined 1787 #endif 1788 } sli4_req_common_destroy_eq_t; 1789 1790 /** 1791 * @brief COMMON_CREATE_MQ_EXT 1792 * 1793 * Create a Mailbox Queue; accommodate v0 and v1 forms. 1794 */ 1795 typedef struct sli4_req_common_create_mq_ext_s { 1796 sli4_req_hdr_t hdr; 1797 #if BYTE_ORDER == LITTLE_ENDIAN 1798 uint32_t num_pages:16, 1799 cq_id_v1:16; 1800 uint32_t async_event_bitmap; 1801 uint32_t async_cq_id_v1:16, 1802 ring_size:4, 1803 :2, 1804 cq_id_v0:10; 1805 uint32_t :31, 1806 val:1; 1807 uint32_t acqv:1, 1808 async_cq_id_v0:10, 1809 :21; 1810 uint32_t rsvd9; 1811 struct { 1812 uint32_t low; 1813 uint32_t high; 1814 } page_physical_address[8]; 1815 #else 1816 #error big endian version not defined 1817 #endif 1818 } sli4_req_common_create_mq_ext_t; 1819 1820 #define SLI4_MQE_SIZE_16 0x05 1821 #define SLI4_MQE_SIZE_32 0x06 1822 #define SLI4_MQE_SIZE_64 0x07 1823 #define SLI4_MQE_SIZE_128 0x08 1824 1825 #define SLI4_ASYNC_EVT_LINK_STATE BIT(1) 1826 #define SLI4_ASYNC_EVT_FCOE_FIP BIT(2) 1827 #define SLI4_ASYNC_EVT_DCBX BIT(3) 1828 #define SLI4_ASYNC_EVT_ISCSI BIT(4) 1829 #define SLI4_ASYNC_EVT_GRP5 BIT(5) 1830 #define SLI4_ASYNC_EVT_FC BIT(16) 1831 #define SLI4_ASYNC_EVT_SLI_PORT BIT(17) 1832 #define SLI4_ASYNC_EVT_VF BIT(18) 1833 #define SLI4_ASYNC_EVT_MR BIT(19) 1834 1835 #define SLI4_ASYNC_EVT_ALL \ 1836 SLI4_ASYNC_EVT_LINK_STATE | \ 1837 SLI4_ASYNC_EVT_FCOE_FIP | \ 1838 SLI4_ASYNC_EVT_DCBX | \ 1839 SLI4_ASYNC_EVT_ISCSI | \ 1840 SLI4_ASYNC_EVT_GRP5 | \ 1841 SLI4_ASYNC_EVT_FC | \ 1842 SLI4_ASYNC_EVT_SLI_PORT | \ 1843 SLI4_ASYNC_EVT_VF |\ 1844 SLI4_ASYNC_EVT_MR 1845 1846 #define SLI4_ASYNC_EVT_FC_FCOE \ 1847 SLI4_ASYNC_EVT_LINK_STATE | \ 1848 SLI4_ASYNC_EVT_FCOE_FIP | \ 1849 SLI4_ASYNC_EVT_GRP5 | \ 1850 SLI4_ASYNC_EVT_FC | \ 1851 SLI4_ASYNC_EVT_SLI_PORT 1852 1853 /** 1854 * @brief Common Destroy MQ 1855 */ 1856 typedef struct sli4_req_common_destroy_mq_s { 1857 sli4_req_hdr_t hdr; 1858 #if BYTE_ORDER == LITTLE_ENDIAN 1859 uint32_t mq_id:16, 1860 :16; 1861 #else 1862 #error big endian version not defined 1863 #endif 1864 } sli4_req_common_destroy_mq_t; 1865 1866 /** 1867 * @brief COMMON_GET_CNTL_ATTRIBUTES 1868 * 1869 * Query for information about the SLI Port 1870 */ 1871 typedef struct sli4_res_common_get_cntl_attributes_s { 1872 sli4_res_hdr_t hdr; 1873 #if BYTE_ORDER == LITTLE_ENDIAN 1874 uint8_t version_string[32]; 1875 uint8_t manufacturer_name[32]; 1876 uint32_t supported_modes; 1877 uint32_t eprom_version_lo:8, 1878 eprom_version_hi:8, 1879 :16; 1880 uint32_t mbx_data_structure_version; 1881 uint32_t ep_firmware_data_structure_version; 1882 uint8_t ncsi_version_string[12]; 1883 uint32_t default_extended_timeout; 1884 uint8_t model_number[32]; 1885 uint8_t description[64]; 1886 uint8_t serial_number[32]; 1887 uint8_t ip_version_string[32]; 1888 uint8_t fw_version_string[32]; 1889 uint8_t bios_version_string[32]; 1890 uint8_t redboot_version_string[32]; 1891 uint8_t driver_version_string[32]; 1892 uint8_t fw_on_flash_version_string[32]; 1893 uint32_t functionalities_supported; 1894 uint32_t max_cdb_length:16, 1895 asic_revision:8, 1896 generational_guid0:8; 1897 uint32_t generational_guid1_12[3]; 1898 uint32_t generational_guid13:24, 1899 hba_port_count:8; 1900 uint32_t default_link_down_timeout:16, 1901 iscsi_version_min_max:8, 1902 multifunctional_device:8; 1903 uint32_t cache_valid:8, 1904 hba_status:8, 1905 max_domains_supported:8, 1906 port_number:6, 1907 port_type:2; 1908 uint32_t firmware_post_status; 1909 uint32_t hba_mtu; 1910 uint32_t iscsi_features:8, 1911 rsvd121:24; 1912 uint32_t pci_vendor_id:16, 1913 pci_device_id:16; 1914 uint32_t pci_sub_vendor_id:16, 1915 pci_sub_system_id:16; 1916 uint32_t pci_bus_number:8, 1917 pci_device_number:8, 1918 pci_function_number:8, 1919 interface_type:8; 1920 uint64_t unique_identifier; 1921 uint32_t number_of_netfilters:8, 1922 rsvd130:24; 1923 #else 1924 #error big endian version not defined 1925 #endif 1926 } sli4_res_common_get_cntl_attributes_t; 1927 1928 /** 1929 * @brief COMMON_GET_CNTL_ATTRIBUTES 1930 * 1931 * This command queries the controller information from the Flash ROM. 1932 */ 1933 typedef struct sli4_req_common_get_cntl_addl_attributes_s { 1934 sli4_req_hdr_t hdr; 1935 } sli4_req_common_get_cntl_addl_attributes_t; 1936 1937 typedef struct sli4_res_common_get_cntl_addl_attributes_s { 1938 sli4_res_hdr_t hdr; 1939 uint16_t ipl_file_number; 1940 uint8_t ipl_file_version; 1941 uint8_t rsvd0; 1942 uint8_t on_die_temperature; 1943 uint8_t rsvd1[3]; 1944 uint32_t driver_advanced_features_supported; 1945 uint32_t rsvd2[4]; 1946 char fcoe_universal_bios_version[32]; 1947 char fcoe_x86_bios_version[32]; 1948 char fcoe_efi_bios_version[32]; 1949 char fcoe_fcode_version[32]; 1950 char uefi_bios_version[32]; 1951 char uefi_nic_version[32]; 1952 char uefi_fcode_version[32]; 1953 char uefi_iscsi_version[32]; 1954 char iscsi_x86_bios_version[32]; 1955 char pxe_x86_bios_version[32]; 1956 uint8_t fcoe_default_wwpn[8]; 1957 uint8_t ext_phy_version[32]; 1958 uint8_t fc_universal_bios_version[32]; 1959 uint8_t fc_x86_bios_version[32]; 1960 uint8_t fc_efi_bios_version[32]; 1961 uint8_t fc_fcode_version[32]; 1962 uint8_t ext_phy_crc_label[8]; 1963 uint8_t ipl_file_name[16]; 1964 uint8_t rsvd3[72]; 1965 } sli4_res_common_get_cntl_addl_attributes_t; 1966 1967 /** 1968 * @brief COMMON_NOP 1969 * 1970 * This command does not do anything; it only returns the payload in the completion. 1971 */ 1972 typedef struct sli4_req_common_nop_s { 1973 sli4_req_hdr_t hdr; 1974 #if BYTE_ORDER == LITTLE_ENDIAN 1975 uint32_t context[2]; 1976 #else 1977 #error big endian version not defined 1978 #endif 1979 } sli4_req_common_nop_t; 1980 1981 typedef struct sli4_res_common_nop_s { 1982 sli4_res_hdr_t hdr; 1983 #if BYTE_ORDER == LITTLE_ENDIAN 1984 uint32_t context[2]; 1985 #else 1986 #error big endian version not defined 1987 #endif 1988 } sli4_res_common_nop_t; 1989 1990 /** 1991 * @brief COMMON_GET_RESOURCE_EXTENT_INFO 1992 */ 1993 typedef struct sli4_req_common_get_resource_extent_info_s { 1994 sli4_req_hdr_t hdr; 1995 #if BYTE_ORDER == LITTLE_ENDIAN 1996 uint32_t resource_type:16, 1997 :16; 1998 #else 1999 #error big endian version not defined 2000 #endif 2001 } sli4_req_common_get_resource_extent_info_t; 2002 2003 #define SLI4_RSC_TYPE_ISCSI_INI_XRI 0x0c 2004 #define SLI4_RSC_TYPE_FCOE_VFI 0x20 2005 #define SLI4_RSC_TYPE_FCOE_VPI 0x21 2006 #define SLI4_RSC_TYPE_FCOE_RPI 0x22 2007 #define SLI4_RSC_TYPE_FCOE_XRI 0x23 2008 2009 typedef struct sli4_res_common_get_resource_extent_info_s { 2010 sli4_res_hdr_t hdr; 2011 #if BYTE_ORDER == LITTLE_ENDIAN 2012 uint32_t resource_extent_count:16, 2013 resource_extent_size:16; 2014 #else 2015 #error big endian version not defined 2016 #endif 2017 } sli4_res_common_get_resource_extent_info_t; 2018 2019 #define SLI4_128BYTE_WQE_SUPPORT 0x02 2020 /** 2021 * @brief COMMON_GET_SLI4_PARAMETERS 2022 */ 2023 typedef struct sli4_res_common_get_sli4_parameters_s { 2024 sli4_res_hdr_t hdr; 2025 #if BYTE_ORDER == LITTLE_ENDIAN 2026 uint32_t protocol_type:8, 2027 :24; 2028 uint32_t ft:1, 2029 :3, 2030 sli_revision:4, 2031 sli_family:4, 2032 if_type:4, 2033 sli_hint_1:8, 2034 sli_hint_2:5, 2035 :3; 2036 uint32_t eq_page_cnt:4, 2037 :4, 2038 eqe_sizes:4, 2039 :4, 2040 eq_page_sizes:8, 2041 eqe_count_method:4, 2042 :4; 2043 uint32_t eqe_count_mask:16, 2044 :16; 2045 uint32_t cq_page_cnt:4, 2046 :4, 2047 cqe_sizes:4, 2048 :2, 2049 cqv:2, 2050 cq_page_sizes:8, 2051 cqe_count_method:4, 2052 :4; 2053 uint32_t cqe_count_mask:16, 2054 :16; 2055 uint32_t mq_page_cnt:4, 2056 :10, 2057 mqv:2, 2058 mq_page_sizes:8, 2059 mqe_count_method:4, 2060 :4; 2061 uint32_t mqe_count_mask:16, 2062 :16; 2063 uint32_t wq_page_cnt:4, 2064 :4, 2065 wqe_sizes:4, 2066 :2, 2067 wqv:2, 2068 wq_page_sizes:8, 2069 wqe_count_method:4, 2070 :4; 2071 uint32_t wqe_count_mask:16, 2072 :16; 2073 uint32_t rq_page_cnt:4, 2074 :4, 2075 rqe_sizes:4, 2076 :2, 2077 rqv:2, 2078 rq_page_sizes:8, 2079 rqe_count_method:4, 2080 :4; 2081 uint32_t rqe_count_mask:16, 2082 :12, 2083 rq_db_window:4; 2084 uint32_t fcoe:1, 2085 ext:1, 2086 hdrr:1, 2087 sglr:1, 2088 fbrr:1, 2089 areg:1, 2090 tgt:1, 2091 terp:1, 2092 assi:1, 2093 wchn:1, 2094 tcca:1, 2095 trty:1, 2096 trir:1, 2097 phoff:1, 2098 phon:1, 2099 phwq:1, /** Performance Hint WQ_ID Association */ 2100 boundary_4ga:1, 2101 rxc:1, 2102 hlm:1, 2103 ipr:1, 2104 rxri:1, 2105 sglc:1, 2106 timm:1, 2107 tsmm:1, 2108 :1, 2109 oas:1, 2110 lc:1, 2111 agxf:1, 2112 loopback_scope:4; 2113 uint32_t sge_supported_length; 2114 uint32_t sgl_page_cnt:4, 2115 :4, 2116 sgl_page_sizes:8, 2117 sgl_pp_align:8, 2118 :8; 2119 uint32_t min_rq_buffer_size:16, 2120 :16; 2121 uint32_t max_rq_buffer_size; 2122 uint32_t physical_xri_max:16, 2123 physical_rpi_max:16; 2124 uint32_t physical_vpi_max:16, 2125 physical_vfi_max:16; 2126 uint32_t rsvd19; 2127 uint32_t frag_num_field_offset:16, /* dword 20 */ 2128 frag_num_field_size:16; 2129 uint32_t sgl_index_field_offset:16, /* dword 21 */ 2130 sgl_index_field_size:16; 2131 uint32_t chain_sge_initial_value_lo; /* dword 22 */ 2132 uint32_t chain_sge_initial_value_hi; /* dword 23 */ 2133 #else 2134 #error big endian version not defined 2135 #endif 2136 } sli4_res_common_get_sli4_parameters_t; 2137 2138 /** 2139 * @brief COMMON_QUERY_FW_CONFIG 2140 * 2141 * This command retrieves firmware configuration parameters and adapter 2142 * resources available to the driver. 2143 */ 2144 typedef struct sli4_req_common_query_fw_config_s { 2145 sli4_req_hdr_t hdr; 2146 } sli4_req_common_query_fw_config_t; 2147 2148 #define SLI4_FUNCTION_MODE_FCOE_INI_MODE 0x40 2149 #define SLI4_FUNCTION_MODE_FCOE_TGT_MODE 0x80 2150 #define SLI4_FUNCTION_MODE_DUA_MODE 0x800 2151 2152 #define SLI4_ULP_MODE_FCOE_INI 0x40 2153 #define SLI4_ULP_MODE_FCOE_TGT 0x80 2154 2155 typedef struct sli4_res_common_query_fw_config_s { 2156 sli4_res_hdr_t hdr; 2157 uint32_t config_number; 2158 uint32_t asic_rev; 2159 uint32_t physical_port; 2160 uint32_t function_mode; 2161 uint32_t ulp0_mode; 2162 uint32_t ulp0_nic_wqid_base; 2163 uint32_t ulp0_nic_wq_total; /* Dword 10 */ 2164 uint32_t ulp0_toe_wqid_base; 2165 uint32_t ulp0_toe_wq_total; 2166 uint32_t ulp0_toe_rqid_base; 2167 uint32_t ulp0_toe_rq_total; 2168 uint32_t ulp0_toe_defrqid_base; 2169 uint32_t ulp0_toe_defrq_total; 2170 uint32_t ulp0_lro_rqid_base; 2171 uint32_t ulp0_lro_rq_total; 2172 uint32_t ulp0_iscsi_icd_base; 2173 uint32_t ulp0_iscsi_icd_total; /* Dword 20 */ 2174 uint32_t ulp1_mode; 2175 uint32_t ulp1_nic_wqid_base; 2176 uint32_t ulp1_nic_wq_total; 2177 uint32_t ulp1_toe_wqid_base; 2178 uint32_t ulp1_toe_wq_total; 2179 uint32_t ulp1_toe_rqid_base; 2180 uint32_t ulp1_toe_rq_total; 2181 uint32_t ulp1_toe_defrqid_base; 2182 uint32_t ulp1_toe_defrq_total; 2183 uint32_t ulp1_lro_rqid_base; /* Dword 30 */ 2184 uint32_t ulp1_lro_rq_total; 2185 uint32_t ulp1_iscsi_icd_base; 2186 uint32_t ulp1_iscsi_icd_total; 2187 uint32_t function_capabilities; 2188 uint32_t ulp0_cq_base; 2189 uint32_t ulp0_cq_total; 2190 uint32_t ulp0_eq_base; 2191 uint32_t ulp0_eq_total; 2192 uint32_t ulp0_iscsi_chain_icd_base; 2193 uint32_t ulp0_iscsi_chain_icd_total; /* Dword 40 */ 2194 uint32_t ulp1_iscsi_chain_icd_base; 2195 uint32_t ulp1_iscsi_chain_icd_total; 2196 } sli4_res_common_query_fw_config_t; 2197 2198 /** 2199 * @brief COMMON_GET_PORT_NAME 2200 */ 2201 typedef struct sli4_req_common_get_port_name_s { 2202 sli4_req_hdr_t hdr; 2203 #if BYTE_ORDER == LITTLE_ENDIAN 2204 uint32_t pt:2, /* only COMMON_GET_PORT_NAME_V1 */ 2205 :30; 2206 #else 2207 #error big endian version not defined 2208 #endif 2209 } sli4_req_common_get_port_name_t; 2210 2211 typedef struct sli4_res_common_get_port_name_s { 2212 sli4_res_hdr_t hdr; 2213 char port_name[4]; 2214 } sli4_res_common_get_port_name_t; 2215 2216 /** 2217 * @brief COMMON_WRITE_FLASHROM 2218 */ 2219 typedef struct sli4_req_common_write_flashrom_s { 2220 sli4_req_hdr_t hdr; 2221 #if BYTE_ORDER == LITTLE_ENDIAN 2222 uint32_t flash_rom_access_opcode; 2223 uint32_t flash_rom_access_operation_type; 2224 uint32_t data_buffer_size; 2225 uint32_t offset; 2226 uint8_t data_buffer[4]; 2227 #else 2228 #error big endian version not defined 2229 #endif 2230 } sli4_req_common_write_flashrom_t; 2231 2232 #define SLI4_MGMT_FLASHROM_OPCODE_FLASH 0x01 2233 #define SLI4_MGMT_FLASHROM_OPCODE_SAVE 0x02 2234 #define SLI4_MGMT_FLASHROM_OPCODE_CLEAR 0x03 2235 #define SLI4_MGMT_FLASHROM_OPCODE_REPORT 0x04 2236 #define SLI4_MGMT_FLASHROM_OPCODE_IMAGE_INFO 0x05 2237 #define SLI4_MGMT_FLASHROM_OPCODE_IMAGE_CRC 0x06 2238 #define SLI4_MGMT_FLASHROM_OPCODE_OFFSET_BASED_FLASH 0x07 2239 #define SLI4_MGMT_FLASHROM_OPCODE_OFFSET_BASED_SAVE 0x08 2240 #define SLI4_MGMT_PHY_FLASHROM_OPCODE_FLASH 0x09 2241 #define SLI4_MGMT_PHY_FLASHROM_OPCODE_SAVE 0x0a 2242 2243 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_ISCSI 0x00 2244 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_REDBOOT 0x01 2245 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_BIOS 0x02 2246 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_PXE_BIOS 0x03 2247 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_CODE_CONTROL 0x04 2248 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_IPSEC_CFG 0x05 2249 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_INIT_DATA 0x06 2250 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_ROM_OFFSET 0x07 2251 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_FCOE_BIOS 0x08 2252 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_ISCSI_BAK 0x09 2253 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_FCOE_ACT 0x0a 2254 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_FCOE_BAK 0x0b 2255 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_CODE_CTRL_P 0x0c 2256 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_NCSI 0x0d 2257 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_NIC 0x0e 2258 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_DCBX 0x0f 2259 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_PXE_BIOS_CFG 0x10 2260 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_ALL_CFG_DATA 0x11 2261 2262 /** 2263 * @brief COMMON_MANAGE_FAT 2264 */ 2265 typedef struct sli4_req_common_manage_fat_s { 2266 sli4_req_hdr_t hdr; 2267 #if BYTE_ORDER == LITTLE_ENDIAN 2268 uint32_t fat_operation; 2269 uint32_t read_log_offset; 2270 uint32_t read_log_length; 2271 uint32_t data_buffer_size; 2272 uint32_t data_buffer; /* response only */ 2273 #else 2274 #error big endian version not defined 2275 #endif 2276 } sli4_req_common_manage_fat_t; 2277 2278 /** 2279 * @brief COMMON_GET_EXT_FAT_CAPABILITIES 2280 */ 2281 typedef struct sli4_req_common_get_ext_fat_capabilities_s { 2282 sli4_req_hdr_t hdr; 2283 #if BYTE_ORDER == LITTLE_ENDIAN 2284 uint32_t parameter_type; 2285 #else 2286 #error big endian version not defined 2287 #endif 2288 } sli4_req_common_get_ext_fat_capabilities_t; 2289 2290 /** 2291 * @brief COMMON_SET_EXT_FAT_CAPABILITIES 2292 */ 2293 typedef struct sli4_req_common_set_ext_fat_capabilities_s { 2294 sli4_req_hdr_t hdr; 2295 #if BYTE_ORDER == LITTLE_ENDIAN 2296 uint32_t maximum_log_entries; 2297 uint32_t log_entry_size; 2298 uint32_t logging_type:8, 2299 maximum_logging_functions:8, 2300 maximum_logging_ports:8, 2301 :8; 2302 uint32_t supported_modes; 2303 uint32_t number_modules; 2304 uint32_t debug_module[14]; 2305 #else 2306 #error big endian version not defined 2307 #endif 2308 } sli4_req_common_set_ext_fat_capabilities_t; 2309 2310 /** 2311 * @brief COMMON_EXT_FAT_CONFIGURE_SNAPSHOT 2312 */ 2313 typedef struct sli4_req_common_ext_fat_configure_snapshot_s { 2314 sli4_req_hdr_t hdr; 2315 #if BYTE_ORDER == LITTLE_ENDIAN 2316 uint32_t total_log_entries; 2317 #else 2318 #error big endian version not defined 2319 #endif 2320 } sli4_req_common_ext_fat_configure_snapshot_t; 2321 2322 /** 2323 * @brief COMMON_EXT_FAT_RETRIEVE_SNAPSHOT 2324 */ 2325 typedef struct sli4_req_common_ext_fat_retrieve_snapshot_s { 2326 sli4_req_hdr_t hdr; 2327 #if BYTE_ORDER == LITTLE_ENDIAN 2328 uint32_t snapshot_mode; 2329 uint32_t start_index; 2330 uint32_t number_log_entries; 2331 #else 2332 #error big endian version not defined 2333 #endif 2334 } sli4_req_common_ext_fat_retrieve_snapshot_t; 2335 2336 typedef struct sli4_res_common_ext_fat_retrieve_snapshot_s { 2337 sli4_res_hdr_t hdr; 2338 #if BYTE_ORDER == LITTLE_ENDIAN 2339 uint32_t number_log_entries; 2340 uint32_t version:8, 2341 physical_port:8, 2342 function_id:16; 2343 uint32_t trace_level; 2344 uint32_t module_mask[2]; 2345 uint32_t trace_table_index; 2346 uint32_t timestamp; 2347 uint8_t string_data[16]; 2348 uint32_t data[6]; 2349 #else 2350 #error big endian version not defined 2351 #endif 2352 } sli4_res_common_ext_fat_retrieve_snapshot_t; 2353 2354 /** 2355 * @brief COMMON_EXT_FAT_READ_STRING_TABLE 2356 */ 2357 typedef struct sli4_req_common_ext_fat_read_string_table_s { 2358 sli4_req_hdr_t hdr; 2359 #if BYTE_ORDER == LITTLE_ENDIAN 2360 uint32_t byte_offset; 2361 uint32_t number_bytes; 2362 #else 2363 #error big endian version not defined 2364 #endif 2365 } sli4_req_common_ext_fat_read_string_table_t; 2366 2367 typedef struct sli4_res_common_ext_fat_read_string_table_s { 2368 sli4_res_hdr_t hdr; 2369 #if BYTE_ORDER == LITTLE_ENDIAN 2370 uint32_t number_returned_bytes; 2371 uint32_t number_remaining_bytes; 2372 uint32_t table_data0:8, 2373 :24; 2374 uint8_t table_data[0]; 2375 #else 2376 #error big endian version not defined 2377 #endif 2378 } sli4_res_common_ext_fat_read_string_table_t; 2379 2380 /** 2381 * @brief COMMON_READ_TRANSCEIVER_DATA 2382 * 2383 * This command reads SFF transceiver data(Format is defined 2384 * by the SFF-8472 specification). 2385 */ 2386 typedef struct sli4_req_common_read_transceiver_data_s { 2387 sli4_req_hdr_t hdr; 2388 #if BYTE_ORDER == LITTLE_ENDIAN 2389 uint32_t page_number; 2390 uint32_t port; 2391 #else 2392 #error big endian version not defined 2393 #endif 2394 } sli4_req_common_read_transceiver_data_t; 2395 2396 typedef struct sli4_res_common_read_transceiver_data_s { 2397 sli4_res_hdr_t hdr; 2398 #if BYTE_ORDER == LITTLE_ENDIAN 2399 uint32_t page_number; 2400 uint32_t port; 2401 uint32_t page_data[32]; 2402 uint32_t page_data_2[32]; 2403 #else 2404 #error big endian version not defined 2405 #endif 2406 } sli4_res_common_read_transceiver_data_t; 2407 2408 /** 2409 * @brief COMMON_READ_OBJECT 2410 */ 2411 typedef struct sli4_req_common_read_object_s { 2412 sli4_req_hdr_t hdr; 2413 #if BYTE_ORDER == LITTLE_ENDIAN 2414 uint32_t desired_read_length:24, 2415 :8; 2416 uint32_t read_offset; 2417 uint8_t object_name[104]; 2418 uint32_t host_buffer_descriptor_count; 2419 sli4_bde_t host_buffer_descriptor[0]; 2420 #else 2421 #error big endian version not defined 2422 #endif 2423 } sli4_req_common_read_object_t; 2424 2425 typedef struct sli4_res_common_read_object_s { 2426 sli4_res_hdr_t hdr; 2427 #if BYTE_ORDER == LITTLE_ENDIAN 2428 uint32_t actual_read_length; 2429 uint32_t resv:31, 2430 eof:1; 2431 #else 2432 #error big endian version not defined 2433 #endif 2434 } sli4_res_common_read_object_t; 2435 2436 /** 2437 * @brief COMMON_WRITE_OBJECT 2438 */ 2439 typedef struct sli4_req_common_write_object_s { 2440 sli4_req_hdr_t hdr; 2441 #if BYTE_ORDER == LITTLE_ENDIAN 2442 uint32_t desired_write_length:24, 2443 :6, 2444 noc:1, 2445 eof:1; 2446 uint32_t write_offset; 2447 uint8_t object_name[104]; 2448 uint32_t host_buffer_descriptor_count; 2449 sli4_bde_t host_buffer_descriptor[0]; 2450 #else 2451 #error big endian version not defined 2452 #endif 2453 } sli4_req_common_write_object_t; 2454 2455 typedef struct sli4_res_common_write_object_s { 2456 sli4_res_hdr_t hdr; 2457 #if BYTE_ORDER == LITTLE_ENDIAN 2458 uint32_t actual_write_length; 2459 uint32_t change_status:8, 2460 :24; 2461 #else 2462 #error big endian version not defined 2463 #endif 2464 } sli4_res_common_write_object_t; 2465 2466 /** 2467 * @brief COMMON_DELETE_OBJECT 2468 */ 2469 typedef struct sli4_req_common_delete_object_s { 2470 sli4_req_hdr_t hdr; 2471 #if BYTE_ORDER == LITTLE_ENDIAN 2472 uint32_t rsvd4; 2473 uint32_t rsvd5; 2474 uint8_t object_name[104]; 2475 #else 2476 #error big endian version not defined 2477 #endif 2478 } sli4_req_common_delete_object_t; 2479 2480 /** 2481 * @brief COMMON_READ_OBJECT_LIST 2482 */ 2483 typedef struct sli4_req_common_read_object_list_s { 2484 sli4_req_hdr_t hdr; 2485 #if BYTE_ORDER == LITTLE_ENDIAN 2486 uint32_t desired_read_length:24, 2487 :8; 2488 uint32_t read_offset; 2489 uint8_t object_name[104]; 2490 uint32_t host_buffer_descriptor_count; 2491 sli4_bde_t host_buffer_descriptor[0]; 2492 #else 2493 #error big endian version not defined 2494 #endif 2495 } sli4_req_common_read_object_list_t; 2496 2497 /** 2498 * @brief COMMON_SET_DUMP_LOCATION 2499 */ 2500 typedef struct sli4_req_common_set_dump_location_s { 2501 sli4_req_hdr_t hdr; 2502 #if BYTE_ORDER == LITTLE_ENDIAN 2503 uint32_t buffer_length:24, 2504 :5, 2505 fdb:1, 2506 blp:1, 2507 qry:1; 2508 uint32_t buf_addr_low; 2509 uint32_t buf_addr_high; 2510 #else 2511 #error big endian version not defined 2512 #endif 2513 } sli4_req_common_set_dump_location_t; 2514 2515 typedef struct sli4_res_common_set_dump_location_s { 2516 sli4_res_hdr_t hdr; 2517 #if BYTE_ORDER == LITTLE_ENDIAN 2518 uint32_t buffer_length:24, 2519 :8; 2520 #else 2521 #error big endian version not defined 2522 #endif 2523 }sli4_res_common_set_dump_location_t; 2524 2525 /** 2526 * @brief COMMON_SET_SET_FEATURES 2527 */ 2528 #define SLI4_SET_FEATURES_DIF_SEED 0x01 2529 #define SLI4_SET_FEATURES_XRI_TIMER 0x03 2530 #define SLI4_SET_FEATURES_MAX_PCIE_SPEED 0x04 2531 #define SLI4_SET_FEATURES_FCTL_CHECK 0x05 2532 #define SLI4_SET_FEATURES_FEC 0x06 2533 #define SLI4_SET_FEATURES_PCIE_RECV_DETECT 0x07 2534 #define SLI4_SET_FEATURES_DIF_MEMORY_MODE 0x08 2535 #define SLI4_SET_FEATURES_DISABLE_SLI_PORT_PAUSE_STATE 0x09 2536 #define SLI4_SET_FEATURES_ENABLE_PCIE_OPTIONS 0x0A 2537 #define SLI4_SET_FEATURES_SET_CONFIG_AUTO_XFER_RDY_T10PI 0x0C 2538 #define SLI4_SET_FEATURES_ENABLE_MULTI_RECEIVE_QUEUE 0x0D 2539 #define SLI4_SET_FEATURES_SET_FTD_XFER_HINT 0x0F 2540 #define SLI4_SET_FEATURES_SLI_PORT_HEALTH_CHECK 0x11 2541 2542 typedef struct sli4_req_common_set_features_s { 2543 sli4_req_hdr_t hdr; 2544 #if BYTE_ORDER == LITTLE_ENDIAN 2545 uint32_t feature; 2546 uint32_t param_len; 2547 uint32_t params[8]; 2548 #else 2549 #error big endian version not defined 2550 #endif 2551 } sli4_req_common_set_features_t; 2552 2553 typedef struct sli4_req_common_set_features_dif_seed_s { 2554 #if BYTE_ORDER == LITTLE_ENDIAN 2555 uint32_t seed:16, 2556 :16; 2557 #else 2558 #error big endian version not defined 2559 #endif 2560 } sli4_req_common_set_features_dif_seed_t; 2561 2562 typedef struct sli4_req_common_set_features_t10_pi_mem_model_s { 2563 #if BYTE_ORDER == LITTLE_ENDIAN 2564 uint32_t tmm:1, 2565 :31; 2566 #else 2567 #error big endian version not defined 2568 #endif 2569 } sli4_req_common_set_features_t10_pi_mem_model_t; 2570 2571 typedef struct sli4_req_common_set_features_multirq_s { 2572 #if BYTE_ORDER == LITTLE_ENDIAN 2573 uint32_t isr:1, /*<< Include Sequence Reporting */ 2574 agxfe:1, /*<< Auto Generate XFER-RDY Feature Enabled */ 2575 :30; 2576 uint32_t num_rqs:8, 2577 rq_select_policy:4, 2578 :20; 2579 #else 2580 #error big endian version not defined 2581 #endif 2582 } sli4_req_common_set_features_multirq_t; 2583 2584 typedef struct sli4_req_common_set_features_xfer_rdy_t10pi_s { 2585 #if BYTE_ORDER == LITTLE_ENDIAN 2586 uint32_t rtc:1, 2587 atv:1, 2588 tmm:1, 2589 :1, 2590 p_type:3, 2591 blk_size:3, 2592 :22; 2593 uint32_t app_tag:16, 2594 :16; 2595 #else 2596 #error big endian version not defined 2597 #endif 2598 } sli4_req_common_set_features_xfer_rdy_t10pi_t; 2599 2600 typedef struct sli4_req_common_set_features_health_check_s { 2601 #if BYTE_ORDER == LITTLE_ENDIAN 2602 uint32_t hck:1, 2603 qry:1, 2604 :30; 2605 #else 2606 #error big endian version not defined 2607 #endif 2608 } sli4_req_common_set_features_health_check_t; 2609 2610 typedef struct sli4_req_common_set_features_set_fdt_xfer_hint_s { 2611 #if BYTE_ORDER == LITTLE_ENDIAN 2612 uint32_t fdt_xfer_hint; 2613 #else 2614 #error big endian version not defined 2615 #endif 2616 } sli4_req_common_set_features_set_fdt_xfer_hint_t; 2617 2618 /** 2619 * @brief DMTF_EXEC_CLP_CMD 2620 */ 2621 typedef struct sli4_req_dmtf_exec_clp_cmd_s { 2622 sli4_req_hdr_t hdr; 2623 #if BYTE_ORDER == LITTLE_ENDIAN 2624 uint32_t cmd_buf_length; 2625 uint32_t resp_buf_length; 2626 uint32_t cmd_buf_addr_low; 2627 uint32_t cmd_buf_addr_high; 2628 uint32_t resp_buf_addr_low; 2629 uint32_t resp_buf_addr_high; 2630 #else 2631 #error big endian version not defined 2632 #endif 2633 } sli4_req_dmtf_exec_clp_cmd_t; 2634 2635 typedef struct sli4_res_dmtf_exec_clp_cmd_s { 2636 sli4_res_hdr_t hdr; 2637 #if BYTE_ORDER == LITTLE_ENDIAN 2638 uint32_t :32; 2639 uint32_t resp_length; 2640 uint32_t :32; 2641 uint32_t :32; 2642 uint32_t :32; 2643 uint32_t :32; 2644 uint32_t clp_status; 2645 uint32_t clp_detailed_status; 2646 #else 2647 #error big endian version not defined 2648 #endif 2649 } sli4_res_dmtf_exec_clp_cmd_t; 2650 2651 /** 2652 * @brief Resource descriptor 2653 */ 2654 2655 #define SLI4_RESOURCE_DESCRIPTOR_TYPE_PCIE 0x50 2656 #define SLI4_RESOURCE_DESCRIPTOR_TYPE_NIC 0x51 2657 #define SLI4_RESOURCE_DESCRIPTOR_TYPE_ISCSI 0x52 2658 #define SLI4_RESOURCE_DESCRIPTOR_TYPE_FCFCOE 0x53 2659 #define SLI4_RESOURCE_DESCRIPTOR_TYPE_RDMA 0x54 2660 #define SLI4_RESOURCE_DESCRIPTOR_TYPE_PORT 0x55 2661 #define SLI4_RESOURCE_DESCRIPTOR_TYPE_ISAP 0x56 2662 2663 #define SLI4_PROTOCOL_NIC_TOE 0x01 2664 #define SLI4_PROTOCOL_ISCSI 0x02 2665 #define SLI4_PROTOCOL_FCOE 0x04 2666 #define SLI4_PROTOCOL_NIC_TOE_RDMA 0x08 2667 #define SLI4_PROTOCOL_FC 0x10 2668 #define SLI4_PROTOCOL_DEFAULT 0xff 2669 2670 typedef struct sli4_resource_descriptor_v1_s { 2671 uint32_t descriptor_type:8, 2672 descriptor_length:8, 2673 :16; 2674 uint32_t type_specific[0]; 2675 } sli4_resource_descriptor_v1_t; 2676 2677 typedef struct sli4_pcie_resource_descriptor_v1_s { 2678 uint32_t descriptor_type:8, 2679 descriptor_length:8, 2680 :14, 2681 imm:1, 2682 nosv:1; 2683 uint32_t :16, 2684 pf_number:10, 2685 :6; 2686 uint32_t rsvd1; 2687 uint32_t sriov_state:8, 2688 pf_state:8, 2689 pf_type:8, 2690 :8; 2691 uint32_t number_of_vfs:16, 2692 :16; 2693 uint32_t mission_roles:8, 2694 :19, 2695 pchg:1, 2696 schg:1, 2697 xchg:1, 2698 xrom:2; 2699 uint32_t rsvd2[16]; 2700 } sli4_pcie_resource_descriptor_v1_t; 2701 2702 typedef struct sli4_isap_resource_descriptor_v1_s { 2703 uint32_t descriptor_type:8, 2704 descriptor_length:8, 2705 :16; 2706 uint32_t iscsi_tgt:1, 2707 iscsi_ini:1, 2708 iscsi_dif:1, 2709 :29; 2710 uint32_t rsvd1[3]; 2711 uint32_t fcoe_tgt:1, 2712 fcoe_ini:1, 2713 fcoe_dif:1, 2714 :29; 2715 uint32_t rsvd2[7]; 2716 uint32_t mc_type0:8, 2717 mc_type1:8, 2718 mc_type2:8, 2719 mc_type3:8; 2720 uint32_t rsvd3[3]; 2721 } sli4_isap_resouce_descriptor_v1_t; 2722 2723 /** 2724 * @brief COMMON_GET_FUNCTION_CONFIG 2725 */ 2726 typedef struct sli4_req_common_get_function_config_s { 2727 sli4_req_hdr_t hdr; 2728 } sli4_req_common_get_function_config_t; 2729 2730 typedef struct sli4_res_common_get_function_config_s { 2731 sli4_res_hdr_t hdr; 2732 #if BYTE_ORDER == LITTLE_ENDIAN 2733 uint32_t desc_count; 2734 uint32_t desc[54]; 2735 #else 2736 #error big endian version not defined 2737 #endif 2738 } sli4_res_common_get_function_config_t; 2739 2740 /** 2741 * @brief COMMON_GET_PROFILE_CONFIG 2742 */ 2743 typedef struct sli4_req_common_get_profile_config_s { 2744 sli4_req_hdr_t hdr; 2745 uint32_t profile_id:8, 2746 typ:2, 2747 :22; 2748 } sli4_req_common_get_profile_config_t; 2749 2750 typedef struct sli4_res_common_get_profile_config_s { 2751 sli4_res_hdr_t hdr; 2752 #if BYTE_ORDER == LITTLE_ENDIAN 2753 uint32_t desc_count; 2754 uint32_t desc[0]; 2755 #else 2756 #error big endian version not defined 2757 #endif 2758 } sli4_res_common_get_profile_config_t; 2759 2760 /** 2761 * @brief COMMON_SET_PROFILE_CONFIG 2762 */ 2763 typedef struct sli4_req_common_set_profile_config_s { 2764 sli4_req_hdr_t hdr; 2765 uint32_t profile_id:8, 2766 :23, 2767 isap:1; 2768 uint32_t desc_count; 2769 uint32_t desc[0]; 2770 } sli4_req_common_set_profile_config_t; 2771 2772 typedef struct sli4_res_common_set_profile_config_s { 2773 sli4_res_hdr_t hdr; 2774 #if BYTE_ORDER == LITTLE_ENDIAN 2775 #else 2776 #error big endian version not defined 2777 #endif 2778 } sli4_res_common_set_profile_config_t; 2779 2780 /** 2781 * @brief Profile Descriptor for profile functions 2782 */ 2783 typedef struct sli4_profile_descriptor_s { 2784 #if BYTE_ORDER == LITTLE_ENDIAN 2785 uint32_t profile_id:8, 2786 :8, 2787 profile_index:8, 2788 :8; 2789 uint32_t profile_description[128]; 2790 #else 2791 #error big endian version not defined 2792 #endif 2793 } sli4_profile_descriptor_t; 2794 2795 /* We don't know in advance how many descriptors there are. We have 2796 to pick a number that we think will be big enough and ask for that 2797 many. */ 2798 2799 #define MAX_PRODUCT_DESCRIPTORS 40 2800 2801 /** 2802 * @brief COMMON_GET_PROFILE_LIST 2803 */ 2804 typedef struct sli4_req_common_get_profile_list_s { 2805 sli4_req_hdr_t hdr; 2806 #if BYTE_ORDER == LITTLE_ENDIAN 2807 uint32_t start_profile_index:8, 2808 :24; 2809 #else 2810 #error big endian version not defined 2811 #endif 2812 } sli4_req_common_get_profile_list_t; 2813 2814 typedef struct sli4_res_common_get_profile_list_s { 2815 sli4_res_hdr_t hdr; 2816 #if BYTE_ORDER == LITTLE_ENDIAN 2817 uint32_t profile_descriptor_count; 2818 sli4_profile_descriptor_t profile_descriptor[MAX_PRODUCT_DESCRIPTORS]; 2819 #else 2820 #error big endian version not defined 2821 #endif 2822 } sli4_res_common_get_profile_list_t; 2823 2824 /** 2825 * @brief COMMON_GET_ACTIVE_PROFILE 2826 */ 2827 typedef struct sli4_req_common_get_active_profile_s { 2828 sli4_req_hdr_t hdr; 2829 } sli4_req_common_get_active_profile_t; 2830 2831 typedef struct sli4_res_common_get_active_profile_s { 2832 sli4_res_hdr_t hdr; 2833 #if BYTE_ORDER == LITTLE_ENDIAN 2834 uint32_t active_profile_id:8, 2835 :8, 2836 next_profile_id:8, 2837 :8; 2838 #else 2839 #error big endian version not defined 2840 #endif 2841 } sli4_res_common_get_active_profile_t; 2842 2843 /** 2844 * @brief COMMON_SET_ACTIVE_PROFILE 2845 */ 2846 typedef struct sli4_req_common_set_active_profile_s { 2847 sli4_req_hdr_t hdr; 2848 #if BYTE_ORDER == LITTLE_ENDIAN 2849 uint32_t active_profile_id:8, 2850 :23, 2851 fd:1; 2852 #else 2853 #error big endian version not defined 2854 #endif 2855 } sli4_req_common_set_active_profile_t; 2856 2857 typedef struct sli4_res_common_set_active_profile_s { 2858 sli4_res_hdr_t hdr; 2859 } sli4_res_common_set_active_profile_t; 2860 2861 /** 2862 * @brief Link Config Descriptor for link config functions 2863 */ 2864 typedef struct sli4_link_config_descriptor_s { 2865 #if BYTE_ORDER == LITTLE_ENDIAN 2866 uint32_t link_config_id:8, 2867 :24; 2868 uint32_t config_description[8]; 2869 #else 2870 #error big endian version not defined 2871 #endif 2872 } sli4_link_config_descriptor_t; 2873 2874 #define MAX_LINK_CONFIG_DESCRIPTORS 10 2875 2876 /** 2877 * @brief COMMON_GET_RECONFIG_LINK_INFO 2878 */ 2879 typedef struct sli4_req_common_get_reconfig_link_info_s { 2880 sli4_req_hdr_t hdr; 2881 #if BYTE_ORDER == LITTLE_ENDIAN 2882 #else 2883 #error big endian version not defined 2884 #endif 2885 } sli4_req_common_get_reconfig_link_info_t; 2886 2887 typedef struct sli4_res_common_get_reconfig_link_info_s { 2888 sli4_res_hdr_t hdr; 2889 #if BYTE_ORDER == LITTLE_ENDIAN 2890 uint32_t active_link_config_id:8, 2891 :8, 2892 next_link_config_id:8, 2893 :8; 2894 uint32_t link_configuration_descriptor_count; 2895 sli4_link_config_descriptor_t desc[MAX_LINK_CONFIG_DESCRIPTORS]; 2896 #else 2897 #error big endian version not defined 2898 #endif 2899 } sli4_res_common_get_reconfig_link_info_t; 2900 2901 /** 2902 * @brief COMMON_SET_RECONFIG_LINK_ID 2903 */ 2904 typedef struct sli4_req_common_set_reconfig_link_id_s { 2905 sli4_req_hdr_t hdr; 2906 #if BYTE_ORDER == LITTLE_ENDIAN 2907 uint32_t next_link_config_id:8, 2908 :23, 2909 fd:1; 2910 #else 2911 #error big endian version not defined 2912 #endif 2913 } sli4_req_common_set_reconfig_link_id_t; 2914 2915 typedef struct sli4_res_common_set_reconfig_link_id_s { 2916 sli4_res_hdr_t hdr; 2917 #if BYTE_ORDER == LITTLE_ENDIAN 2918 #else 2919 #error big endian version not defined 2920 #endif 2921 } sli4_res_common_set_reconfig_link_id_t; 2922 2923 typedef struct sli4_req_lowlevel_set_watchdog_s { 2924 sli4_req_hdr_t hdr; 2925 #if BYTE_ORDER == LITTLE_ENDIAN 2926 uint32_t watchdog_timeout:16, 2927 :16; 2928 #else 2929 #error big endian version not defined 2930 #endif 2931 2932 } sli4_req_lowlevel_set_watchdog_t; 2933 2934 typedef struct sli4_res_lowlevel_set_watchdog_s { 2935 sli4_res_hdr_t hdr; 2936 #if BYTE_ORDER == LITTLE_ENDIAN 2937 uint32_t rsvd; 2938 #else 2939 #error big endian version not defined 2940 #endif 2941 } sli4_res_lowlevel_set_watchdog_t; 2942 2943 /** 2944 * @brief Event Queue Entry 2945 */ 2946 typedef struct sli4_eqe_s { 2947 #if BYTE_ORDER == LITTLE_ENDIAN 2948 uint32_t vld:1, /** valid */ 2949 major_code:3, 2950 minor_code:12, 2951 resource_id:16; 2952 #else 2953 #error big endian version not defined 2954 #endif 2955 } sli4_eqe_t; 2956 2957 #define SLI4_MAJOR_CODE_STANDARD 0 2958 #define SLI4_MAJOR_CODE_SENTINEL 1 2959 2960 /** 2961 * @brief Mailbox Completion Queue Entry 2962 * 2963 * A CQE generated on the completion of a MQE from a MQ. 2964 */ 2965 typedef struct sli4_mcqe_s { 2966 #if BYTE_ORDER == LITTLE_ENDIAN 2967 uint32_t completion_status:16, /** values are protocol specific */ 2968 extended_status:16; 2969 uint32_t mqe_tag_low; 2970 uint32_t mqe_tag_high; 2971 uint32_t :27, 2972 con:1, /** consumed - command now being executed */ 2973 cmp:1, /** completed - command still executing if clear */ 2974 :1, 2975 ae:1, /** async event - this is an ACQE */ 2976 val:1; /** valid - contents of CQE are valid */ 2977 #else 2978 #error big endian version not defined 2979 #endif 2980 } sli4_mcqe_t; 2981 2982 /** 2983 * @brief Asynchronous Completion Queue Entry 2984 * 2985 * A CQE generated asynchronously in response to the link or other internal events. 2986 */ 2987 typedef struct sli4_acqe_s { 2988 #if BYTE_ORDER == LITTLE_ENDIAN 2989 uint32_t event_data[3]; 2990 uint32_t :8, 2991 event_code:8, 2992 event_type:8, /** values are protocol specific */ 2993 :6, 2994 ae:1, /** async event - this is an ACQE */ 2995 val:1; /** valid - contents of CQE are valid */ 2996 #else 2997 #error big endian version not defined 2998 #endif 2999 } sli4_acqe_t; 3000 3001 #define SLI4_ACQE_EVENT_CODE_LINK_STATE 0x01 3002 #define SLI4_ACQE_EVENT_CODE_FCOE_FIP 0x02 3003 #define SLI4_ACQE_EVENT_CODE_DCBX 0x03 3004 #define SLI4_ACQE_EVENT_CODE_ISCSI 0x04 3005 #define SLI4_ACQE_EVENT_CODE_GRP_5 0x05 3006 #define SLI4_ACQE_EVENT_CODE_FC_LINK_EVENT 0x10 3007 #define SLI4_ACQE_EVENT_CODE_SLI_PORT_EVENT 0x11 3008 #define SLI4_ACQE_EVENT_CODE_VF_EVENT 0x12 3009 #define SLI4_ACQE_EVENT_CODE_MR_EVENT 0x13 3010 3011 /** 3012 * @brief Register name enums 3013 */ 3014 typedef enum { 3015 SLI4_REG_BMBX, 3016 SLI4_REG_EQ_DOORBELL, 3017 SLI4_REG_CQ_DOORBELL, 3018 SLI4_REG_FCOE_RQ_DOORBELL, 3019 SLI4_REG_IO_WQ_DOORBELL, 3020 SLI4_REG_MQ_DOORBELL, 3021 SLI4_REG_PHYSDEV_CONTROL, 3022 SLI4_REG_SLIPORT_CONTROL, 3023 SLI4_REG_SLIPORT_ERROR1, 3024 SLI4_REG_SLIPORT_ERROR2, 3025 SLI4_REG_SLIPORT_SEMAPHORE, 3026 SLI4_REG_SLIPORT_STATUS, 3027 SLI4_REG_UERR_MASK_HI, 3028 SLI4_REG_UERR_MASK_LO, 3029 SLI4_REG_UERR_STATUS_HI, 3030 SLI4_REG_UERR_STATUS_LO, 3031 SLI4_REG_SW_UE_CSR1, 3032 SLI4_REG_SW_UE_CSR2, 3033 SLI4_REG_MAX /* must be last */ 3034 } sli4_regname_e; 3035 3036 typedef struct sli4_reg_s { 3037 uint32_t rset; 3038 uint32_t off; 3039 } sli4_reg_t; 3040 3041 typedef enum { 3042 SLI_QTYPE_EQ, 3043 SLI_QTYPE_CQ, 3044 SLI_QTYPE_MQ, 3045 SLI_QTYPE_WQ, 3046 SLI_QTYPE_RQ, 3047 SLI_QTYPE_MAX, /* must be last */ 3048 } sli4_qtype_e; 3049 3050 #define SLI_USER_MQ_COUNT 1 /** User specified max mail queues */ 3051 #define SLI_MAX_CQ_SET_COUNT 16 3052 #define SLI_MAX_RQ_SET_COUNT 16 3053 3054 typedef enum { 3055 SLI_QENTRY_ASYNC, 3056 SLI_QENTRY_MQ, 3057 SLI_QENTRY_RQ, 3058 SLI_QENTRY_WQ, 3059 SLI_QENTRY_WQ_RELEASE, 3060 SLI_QENTRY_OPT_WRITE_CMD, 3061 SLI_QENTRY_OPT_WRITE_DATA, 3062 SLI_QENTRY_XABT, 3063 SLI_QENTRY_MAX /* must be last */ 3064 } sli4_qentry_e; 3065 3066 typedef struct sli4_queue_s { 3067 /* Common to all queue types */ 3068 ocs_dma_t dma; 3069 ocs_lock_t lock; 3070 uint32_t index; /** current host entry index */ 3071 uint16_t size; /** entry size */ 3072 uint16_t length; /** number of entries */ 3073 uint16_t n_posted; /** number entries posted */ 3074 uint16_t id; /** Port assigned xQ_ID */ 3075 uint16_t ulp; /** ULP assigned to this queue */ 3076 uint32_t doorbell_offset;/** The offset for the doorbell */ 3077 uint16_t doorbell_rset; /** register set for the doorbell */ 3078 uint8_t type; /** queue type ie EQ, CQ, ... */ 3079 uint32_t proc_limit; /** limit number of CQE processed per iteration */ 3080 uint32_t posted_limit; /** number of CQE/EQE to process before ringing doorbell */ 3081 uint32_t max_num_processed; 3082 time_t max_process_time; 3083 3084 uint16_t phase; /** For if_type = 6, this value toggle for each iteration 3085 of the queue, a queue entry is valid when a cqe valid 3086 bit matches this value */ 3087 /* Type specific gunk */ 3088 union { 3089 uint32_t r_idx; /** "read" index (MQ only) */ 3090 struct { 3091 uint32_t is_mq:1,/** CQ contains MQ/Async completions */ 3092 is_hdr:1,/** is a RQ for packet headers */ 3093 rq_batch:1;/** RQ index incremented by 8 */ 3094 } flag; 3095 } u; 3096 } sli4_queue_t; 3097 3098 static inline void 3099 sli_queue_lock(sli4_queue_t *q) 3100 { 3101 ocs_lock(&q->lock); 3102 } 3103 3104 static inline void 3105 sli_queue_unlock(sli4_queue_t *q) 3106 { 3107 ocs_unlock(&q->lock); 3108 } 3109 3110 #define SLI4_QUEUE_DEFAULT_CQ UINT16_MAX /** Use the default CQ */ 3111 3112 #define SLI4_QUEUE_RQ_BATCH 8 3113 3114 typedef enum { 3115 SLI4_CB_LINK, 3116 SLI4_CB_FIP, 3117 SLI4_CB_MAX /* must be last */ 3118 } sli4_callback_e; 3119 3120 typedef enum { 3121 SLI_LINK_STATUS_UP, 3122 SLI_LINK_STATUS_DOWN, 3123 SLI_LINK_STATUS_NO_ALPA, 3124 SLI_LINK_STATUS_MAX, 3125 } sli4_link_status_e; 3126 3127 typedef enum { 3128 SLI_LINK_TOPO_NPORT = 1, /** fabric or point-to-point */ 3129 SLI_LINK_TOPO_LOOP, 3130 SLI_LINK_TOPO_LOOPBACK_INTERNAL, 3131 SLI_LINK_TOPO_LOOPBACK_EXTERNAL, 3132 SLI_LINK_TOPO_NONE, 3133 SLI_LINK_TOPO_MAX, 3134 } sli4_link_topology_e; 3135 3136 /* TODO do we need both sli4_port_type_e & sli4_link_medium_e */ 3137 typedef enum { 3138 SLI_LINK_MEDIUM_ETHERNET, 3139 SLI_LINK_MEDIUM_FC, 3140 SLI_LINK_MEDIUM_MAX, 3141 } sli4_link_medium_e; 3142 3143 typedef struct sli4_link_event_s { 3144 sli4_link_status_e status; /* link up/down */ 3145 sli4_link_topology_e topology; 3146 sli4_link_medium_e medium; /* Ethernet / FC */ 3147 uint32_t speed; /* Mbps */ 3148 uint8_t *loop_map; 3149 uint32_t fc_id; 3150 } sli4_link_event_t; 3151 3152 /** 3153 * @brief Fields retrieved from skyhawk that used used to build chained SGL 3154 */ 3155 typedef struct sli4_sgl_chaining_params_s { 3156 uint8_t chaining_capable; 3157 uint16_t frag_num_field_offset; 3158 uint16_t sgl_index_field_offset; 3159 uint64_t frag_num_field_mask; 3160 uint64_t sgl_index_field_mask; 3161 uint32_t chain_sge_initial_value_lo; 3162 uint32_t chain_sge_initial_value_hi; 3163 } sli4_sgl_chaining_params_t; 3164 3165 typedef struct sli4_fip_event_s { 3166 uint32_t type; 3167 uint32_t index; /* FCF index or UINT32_MAX if invalid */ 3168 } sli4_fip_event_t; 3169 3170 typedef enum { 3171 SLI_RSRC_FCOE_VFI, 3172 SLI_RSRC_FCOE_VPI, 3173 SLI_RSRC_FCOE_RPI, 3174 SLI_RSRC_FCOE_XRI, 3175 SLI_RSRC_FCOE_FCFI, 3176 SLI_RSRC_MAX /* must be last */ 3177 } sli4_resource_e; 3178 3179 typedef enum { 3180 SLI4_PORT_TYPE_FC, 3181 SLI4_PORT_TYPE_NIC, 3182 SLI4_PORT_TYPE_MAX /* must be last */ 3183 } sli4_port_type_e; 3184 3185 typedef enum { 3186 SLI4_ASIC_TYPE_BE3 = 1, 3187 SLI4_ASIC_TYPE_SKYHAWK, 3188 SLI4_ASIC_TYPE_LANCER, 3189 SLI4_ASIC_TYPE_CORSAIR, 3190 SLI4_ASIC_TYPE_LANCERG6, 3191 SLI4_ASIC_TYPE_LANCERG7 3192 } sli4_asic_type_e; 3193 3194 typedef enum { 3195 SLI4_ASIC_REV_FPGA = 1, 3196 SLI4_ASIC_REV_A0, 3197 SLI4_ASIC_REV_A1, 3198 SLI4_ASIC_REV_A2, 3199 SLI4_ASIC_REV_A3, 3200 SLI4_ASIC_REV_B0, 3201 SLI4_ASIC_REV_B1, 3202 SLI4_ASIC_REV_C0, 3203 SLI4_ASIC_REV_D0, 3204 } sli4_asic_rev_e; 3205 3206 typedef struct sli4_s { 3207 ocs_os_handle_t os; 3208 sli4_port_type_e port_type; 3209 3210 uint32_t sli_rev; /* SLI revision number */ 3211 uint32_t sli_family; 3212 uint32_t if_type; /* SLI Interface type */ 3213 3214 sli4_asic_type_e asic_type; /*<< ASIC type */ 3215 sli4_asic_rev_e asic_rev; /*<< ASIC revision */ 3216 uint32_t physical_port; 3217 3218 struct { 3219 uint16_t e_d_tov; 3220 uint16_t r_a_tov; 3221 uint16_t max_qcount[SLI_QTYPE_MAX]; 3222 uint32_t max_qentries[SLI_QTYPE_MAX]; 3223 uint16_t count_mask[SLI_QTYPE_MAX]; 3224 uint16_t count_method[SLI_QTYPE_MAX]; 3225 uint32_t qpage_count[SLI_QTYPE_MAX]; 3226 uint16_t link_module_type; 3227 uint8_t rq_batch; 3228 uint16_t rq_min_buf_size; 3229 uint32_t rq_max_buf_size; 3230 uint8_t topology; 3231 uint8_t wwpn[8]; 3232 uint8_t wwnn[8]; 3233 uint32_t fw_rev[2]; 3234 uint8_t fw_name[2][16]; 3235 char ipl_name[16]; 3236 uint32_t hw_rev[3]; 3237 uint8_t port_number; 3238 char port_name[2]; 3239 char bios_version_string[32]; 3240 uint8_t dual_ulp_capable; 3241 uint8_t is_ulp_fc[2]; 3242 /* 3243 * Tracks the port resources using extents metaphor. For 3244 * devices that don't implement extents (i.e. 3245 * has_extents == FALSE), the code models each resource as 3246 * a single large extent. 3247 */ 3248 struct { 3249 uint32_t number; /* number of extents */ 3250 uint32_t size; /* number of elements in each extent */ 3251 uint32_t n_alloc;/* number of elements allocated */ 3252 uint32_t *base; 3253 ocs_bitmap_t *use_map;/* bitmap showing resources in use */ 3254 uint32_t map_size;/* number of bits in bitmap */ 3255 } extent[SLI_RSRC_MAX]; 3256 sli4_features_t features; 3257 uint32_t has_extents:1, 3258 auto_reg:1, 3259 auto_xfer_rdy:1, 3260 hdr_template_req:1, 3261 perf_hint:1, 3262 perf_wq_id_association:1, 3263 cq_create_version:2, 3264 mq_create_version:2, 3265 high_login_mode:1, 3266 sgl_pre_registered:1, 3267 sgl_pre_registration_required:1, 3268 t10_dif_inline_capable:1, 3269 t10_dif_separate_capable:1; 3270 uint32_t sge_supported_length; 3271 uint32_t sgl_page_sizes; 3272 uint32_t max_sgl_pages; 3273 sli4_sgl_chaining_params_t sgl_chaining_params; 3274 size_t wqe_size; 3275 } config; 3276 3277 /* 3278 * Callback functions 3279 */ 3280 int32_t (*link)(void *, void *); 3281 void *link_arg; 3282 int32_t (*fip)(void *, void *); 3283 void *fip_arg; 3284 3285 ocs_dma_t bmbx; 3286 #if defined(OCS_INCLUDE_DEBUG) 3287 /* Save pointer to physical memory descriptor for non-embedded SLI_CONFIG 3288 * commands for BMBX dumping purposes */ 3289 ocs_dma_t *bmbx_non_emb_pmd; 3290 #endif 3291 3292 struct { 3293 ocs_dma_t data; 3294 uint32_t length; 3295 } vpd; 3296 } sli4_t; 3297 3298 /** 3299 * Get / set parameter functions 3300 */ 3301 static inline uint32_t 3302 sli_get_max_rsrc(sli4_t *sli4, sli4_resource_e rsrc) 3303 { 3304 if (rsrc >= SLI_RSRC_MAX) { 3305 return 0; 3306 } 3307 3308 return sli4->config.extent[rsrc].size; 3309 } 3310 3311 static inline uint32_t 3312 sli_get_max_queue(sli4_t *sli4, sli4_qtype_e qtype) 3313 { 3314 if (qtype >= SLI_QTYPE_MAX) { 3315 return 0; 3316 } 3317 return sli4->config.max_qcount[qtype]; 3318 } 3319 3320 static inline uint32_t 3321 sli_get_max_qentries(sli4_t *sli4, sli4_qtype_e qtype) 3322 { 3323 3324 return sli4->config.max_qentries[qtype]; 3325 } 3326 3327 static inline uint32_t 3328 sli_get_max_sge(sli4_t *sli4) 3329 { 3330 return sli4->config.sge_supported_length; 3331 } 3332 3333 static inline uint32_t 3334 sli_get_max_sgl(sli4_t *sli4) 3335 { 3336 3337 if (sli4->config.sgl_page_sizes != 1) { 3338 ocs_log_test(sli4->os, "unsupported SGL page sizes %#x\n", 3339 sli4->config.sgl_page_sizes); 3340 return 0; 3341 } 3342 3343 return ((sli4->config.max_sgl_pages * SLI_PAGE_SIZE) / sizeof(sli4_sge_t)); 3344 } 3345 3346 static inline sli4_link_medium_e 3347 sli_get_medium(sli4_t *sli4) 3348 { 3349 switch (sli4->config.topology) { 3350 case SLI4_READ_CFG_TOPO_FCOE: 3351 return SLI_LINK_MEDIUM_ETHERNET; 3352 case SLI4_READ_CFG_TOPO_FC: 3353 case SLI4_READ_CFG_TOPO_FC_DA: 3354 case SLI4_READ_CFG_TOPO_FC_AL: 3355 return SLI_LINK_MEDIUM_FC; 3356 default: 3357 return SLI_LINK_MEDIUM_MAX; 3358 } 3359 } 3360 3361 static inline void 3362 sli_skh_chain_sge_build(sli4_t *sli4, sli4_sge_t *sge, uint32_t xri_index, uint32_t frag_num, uint32_t offset) 3363 { 3364 sli4_sgl_chaining_params_t *cparms = &sli4->config.sgl_chaining_params; 3365 3366 ocs_memset(sge, 0, sizeof(*sge)); 3367 sge->sge_type = SLI4_SGE_TYPE_CHAIN; 3368 sge->buffer_address_high = (uint32_t)cparms->chain_sge_initial_value_hi; 3369 sge->buffer_address_low = 3370 (uint32_t)((cparms->chain_sge_initial_value_lo | 3371 (((uintptr_t)(xri_index & cparms->sgl_index_field_mask)) << 3372 cparms->sgl_index_field_offset) | 3373 (((uintptr_t)(frag_num & cparms->frag_num_field_mask)) << 3374 cparms->frag_num_field_offset) | 3375 offset) >> 3); 3376 } 3377 3378 static inline uint32_t 3379 sli_get_sli_rev(sli4_t *sli4) 3380 { 3381 return sli4->sli_rev; 3382 } 3383 3384 static inline uint32_t 3385 sli_get_sli_family(sli4_t *sli4) 3386 { 3387 return sli4->sli_family; 3388 } 3389 3390 static inline uint32_t 3391 sli_get_if_type(sli4_t *sli4) 3392 { 3393 return sli4->if_type; 3394 } 3395 3396 static inline void * 3397 sli_get_wwn_port(sli4_t *sli4) 3398 { 3399 return sli4->config.wwpn; 3400 } 3401 3402 static inline void * 3403 sli_get_wwn_node(sli4_t *sli4) 3404 { 3405 return sli4->config.wwnn; 3406 } 3407 3408 static inline void * 3409 sli_get_vpd(sli4_t *sli4) 3410 { 3411 return sli4->vpd.data.virt; 3412 } 3413 3414 static inline uint32_t 3415 sli_get_vpd_len(sli4_t *sli4) 3416 { 3417 return sli4->vpd.length; 3418 } 3419 3420 static inline uint32_t 3421 sli_get_fw_revision(sli4_t *sli4, uint32_t which) 3422 { 3423 return sli4->config.fw_rev[which]; 3424 } 3425 3426 static inline void * 3427 sli_get_fw_name(sli4_t *sli4, uint32_t which) 3428 { 3429 return sli4->config.fw_name[which]; 3430 } 3431 3432 static inline char * 3433 sli_get_ipl_name(sli4_t *sli4) 3434 { 3435 return sli4->config.ipl_name; 3436 } 3437 3438 static inline uint32_t 3439 sli_get_hw_revision(sli4_t *sli4, uint32_t which) 3440 { 3441 return sli4->config.hw_rev[which]; 3442 } 3443 3444 static inline uint32_t 3445 sli_get_auto_xfer_rdy_capable(sli4_t *sli4) 3446 { 3447 return sli4->config.auto_xfer_rdy; 3448 } 3449 3450 static inline uint32_t 3451 sli_get_dif_capable(sli4_t *sli4) 3452 { 3453 return sli4->config.features.flag.dif; 3454 } 3455 3456 static inline uint32_t 3457 sli_is_dif_inline_capable(sli4_t *sli4) 3458 { 3459 return sli_get_dif_capable(sli4) && sli4->config.t10_dif_inline_capable; 3460 } 3461 3462 static inline uint32_t 3463 sli_is_dif_separate_capable(sli4_t *sli4) 3464 { 3465 return sli_get_dif_capable(sli4) && sli4->config.t10_dif_separate_capable; 3466 } 3467 3468 static inline uint32_t 3469 sli_get_is_dual_ulp_capable(sli4_t *sli4) 3470 { 3471 return sli4->config.dual_ulp_capable; 3472 } 3473 3474 static inline uint32_t 3475 sli_get_is_sgl_chaining_capable(sli4_t *sli4) 3476 { 3477 return sli4->config.sgl_chaining_params.chaining_capable; 3478 } 3479 3480 static inline uint32_t 3481 sli_get_is_ulp_enabled(sli4_t *sli4, uint16_t ulp) 3482 { 3483 return sli4->config.is_ulp_fc[ulp]; 3484 } 3485 3486 static inline uint32_t 3487 sli_get_hlm_capable(sli4_t *sli4) 3488 { 3489 return sli4->config.features.flag.hlm; 3490 } 3491 3492 static inline int32_t 3493 sli_set_hlm(sli4_t *sli4, uint32_t value) 3494 { 3495 if (value && !sli4->config.features.flag.hlm) { 3496 ocs_log_test(sli4->os, "HLM not supported\n"); 3497 return -1; 3498 } 3499 3500 sli4->config.high_login_mode = value != 0 ? TRUE : FALSE; 3501 3502 return 0; 3503 } 3504 3505 static inline uint32_t 3506 sli_get_hlm(sli4_t *sli4) 3507 { 3508 return sli4->config.high_login_mode; 3509 } 3510 3511 static inline uint32_t 3512 sli_get_sgl_preregister_required(sli4_t *sli4) 3513 { 3514 return sli4->config.sgl_pre_registration_required; 3515 } 3516 3517 static inline uint32_t 3518 sli_get_sgl_preregister(sli4_t *sli4) 3519 { 3520 return sli4->config.sgl_pre_registered; 3521 } 3522 3523 static inline int32_t 3524 sli_set_sgl_preregister(sli4_t *sli4, uint32_t value) 3525 { 3526 if ((value == 0) && sli4->config.sgl_pre_registration_required) { 3527 ocs_log_test(sli4->os, "SGL pre-registration required\n"); 3528 return -1; 3529 } 3530 3531 sli4->config.sgl_pre_registered = value != 0 ? TRUE : FALSE; 3532 3533 return 0; 3534 } 3535 3536 static inline sli4_asic_type_e 3537 sli_get_asic_type(sli4_t *sli4) 3538 { 3539 return sli4->asic_type; 3540 } 3541 3542 static inline sli4_asic_rev_e 3543 sli_get_asic_rev(sli4_t *sli4) 3544 { 3545 return sli4->asic_rev; 3546 } 3547 3548 static inline int32_t 3549 sli_set_topology(sli4_t *sli4, uint32_t value) 3550 { 3551 int32_t rc = 0; 3552 3553 switch (value) { 3554 case SLI4_READ_CFG_TOPO_FCOE: 3555 case SLI4_READ_CFG_TOPO_FC: 3556 case SLI4_READ_CFG_TOPO_FC_DA: 3557 case SLI4_READ_CFG_TOPO_FC_AL: 3558 sli4->config.topology = value; 3559 break; 3560 default: 3561 ocs_log_test(sli4->os, "unsupported topology %#x\n", value); 3562 rc = -1; 3563 } 3564 3565 return rc; 3566 } 3567 3568 static inline uint16_t 3569 sli_get_link_module_type(sli4_t *sli4) 3570 { 3571 return sli4->config.link_module_type; 3572 } 3573 3574 static inline char * 3575 sli_get_portnum(sli4_t *sli4) 3576 { 3577 return sli4->config.port_name; 3578 } 3579 3580 static inline char * 3581 sli_get_bios_version_string(sli4_t *sli4) 3582 { 3583 return sli4->config.bios_version_string; 3584 } 3585 3586 static inline uint32_t 3587 sli_convert_mask_to_count(uint32_t method, uint32_t mask) 3588 { 3589 uint32_t count = 0; 3590 3591 if (method) { 3592 count = 1 << ocs_lg2(mask); 3593 count *= 16; 3594 } else { 3595 count = mask; 3596 } 3597 3598 return count; 3599 } 3600 3601 /** 3602 * @brief Common Create Queue function prototype 3603 */ 3604 typedef int32_t (*sli4_create_q_fn_t)(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t); 3605 3606 /** 3607 * @brief Common Destroy Queue function prototype 3608 */ 3609 typedef int32_t (*sli4_destroy_q_fn_t)(sli4_t *, void *, size_t, uint16_t); 3610 3611 /**************************************************************************** 3612 * Function prototypes 3613 */ 3614 extern int32_t sli_cmd_config_auto_xfer_rdy(sli4_t *, void *, size_t, uint32_t); 3615 extern int32_t sli_cmd_config_auto_xfer_rdy_hp(sli4_t *, void *, size_t, uint32_t, uint32_t, uint32_t); 3616 extern int32_t sli_cmd_config_link(sli4_t *, void *, size_t); 3617 extern int32_t sli_cmd_down_link(sli4_t *, void *, size_t); 3618 extern int32_t sli_cmd_dump_type4(sli4_t *, void *, size_t, uint16_t); 3619 extern int32_t sli_cmd_common_read_transceiver_data(sli4_t *, void *, size_t, uint32_t, ocs_dma_t *); 3620 extern int32_t sli_cmd_read_link_stats(sli4_t *, void *, size_t,uint8_t, uint8_t, uint8_t); 3621 extern int32_t sli_cmd_read_status(sli4_t *sli4, void *buf, size_t size, uint8_t clear_counters); 3622 extern int32_t sli_cmd_init_link(sli4_t *, void *, size_t, uint32_t, uint8_t); 3623 extern int32_t sli_cmd_init_vfi(sli4_t *, void *, size_t, uint16_t, uint16_t, uint16_t); 3624 extern int32_t sli_cmd_init_vpi(sli4_t *, void *, size_t, uint16_t, uint16_t); 3625 extern int32_t sli_cmd_post_xri(sli4_t *, void *, size_t, uint16_t, uint16_t); 3626 extern int32_t sli_cmd_release_xri(sli4_t *, void *, size_t, uint8_t); 3627 extern int32_t sli_cmd_read_sparm64(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t); 3628 extern int32_t sli_cmd_read_topology(sli4_t *, void *, size_t, ocs_dma_t *); 3629 extern int32_t sli_cmd_read_nvparms(sli4_t *, void *, size_t); 3630 extern int32_t sli_cmd_write_nvparms(sli4_t *, void *, size_t, uint8_t *, uint8_t *, uint8_t, uint32_t); 3631 typedef struct { 3632 uint16_t rq_id; 3633 uint8_t r_ctl_mask; 3634 uint8_t r_ctl_match; 3635 uint8_t type_mask; 3636 uint8_t type_match; 3637 } sli4_cmd_rq_cfg_t; 3638 extern int32_t sli_cmd_reg_fcfi(sli4_t *, void *, size_t, uint16_t, 3639 sli4_cmd_rq_cfg_t rq_cfg[SLI4_CMD_REG_FCFI_NUM_RQ_CFG], uint16_t); 3640 extern int32_t sli_cmd_reg_fcfi_mrq(sli4_t *, void *, size_t, uint8_t, uint16_t, uint16_t, uint8_t, uint8_t , uint16_t, sli4_cmd_rq_cfg_t *); 3641 3642 extern int32_t sli_cmd_reg_rpi(sli4_t *, void *, size_t, uint32_t, uint16_t, uint16_t, ocs_dma_t *, uint8_t, uint8_t); 3643 extern int32_t sli_cmd_reg_vfi(sli4_t *, void *, size_t, ocs_domain_t *); 3644 extern int32_t sli_cmd_reg_vpi(sli4_t *, void *, size_t, ocs_sli_port_t *, uint8_t); 3645 extern int32_t sli_cmd_sli_config(sli4_t *, void *, size_t, uint32_t, ocs_dma_t *); 3646 extern int32_t sli_cmd_unreg_fcfi(sli4_t *, void *, size_t, uint16_t); 3647 extern int32_t sli_cmd_unreg_rpi(sli4_t *, void *, size_t, uint16_t, sli4_resource_e, uint32_t); 3648 extern int32_t sli_cmd_unreg_vfi(sli4_t *, void *, size_t, ocs_domain_t *, uint32_t); 3649 extern int32_t sli_cmd_unreg_vpi(sli4_t *, void *, size_t, uint16_t, uint32_t); 3650 extern int32_t sli_cmd_common_nop(sli4_t *, void *, size_t, uint64_t); 3651 extern int32_t sli_cmd_common_get_resource_extent_info(sli4_t *, void *, size_t, uint16_t); 3652 extern int32_t sli_cmd_common_get_sli4_parameters(sli4_t *, void *, size_t); 3653 extern int32_t sli_cmd_common_write_object(sli4_t *, void *, size_t, 3654 uint16_t, uint16_t, uint32_t, uint32_t, char *, ocs_dma_t *); 3655 extern int32_t sli_cmd_common_delete_object(sli4_t *, void *, size_t, char *); 3656 extern int32_t sli_cmd_common_read_object(sli4_t *, void *, size_t, uint32_t, 3657 uint32_t, char *, ocs_dma_t *); 3658 extern int32_t sli_cmd_dmtf_exec_clp_cmd(sli4_t *sli4, void *buf, size_t size, 3659 ocs_dma_t *cmd, 3660 ocs_dma_t *resp); 3661 extern int32_t sli_cmd_common_set_dump_location(sli4_t *sli4, void *buf, size_t size, 3662 uint8_t query, uint8_t is_buffer_list, 3663 ocs_dma_t *buffer, uint8_t fdb); 3664 extern int32_t sli_cmd_common_set_features(sli4_t *, void *, size_t, uint32_t, uint32_t, void*); 3665 extern int32_t sli_cmd_common_get_profile_list(sli4_t *sli4, void *buf, 3666 size_t size, uint32_t start_profile_index, ocs_dma_t *dma); 3667 extern int32_t sli_cmd_common_get_active_profile(sli4_t *sli4, void *buf, 3668 size_t size); 3669 extern int32_t sli_cmd_common_set_active_profile(sli4_t *sli4, void *buf, 3670 size_t size, 3671 uint32_t fd, 3672 uint32_t active_profile_id); 3673 extern int32_t sli_cmd_common_get_reconfig_link_info(sli4_t *sli4, void *buf, 3674 size_t size, ocs_dma_t *dma); 3675 extern int32_t sli_cmd_common_set_reconfig_link_id(sli4_t *sli4, void *buf, 3676 size_t size, ocs_dma_t *dma, 3677 uint32_t fd, uint32_t active_link_config_id); 3678 extern int32_t sli_cmd_common_get_function_config(sli4_t *sli4, void *buf, 3679 size_t size); 3680 extern int32_t sli_cmd_common_get_profile_config(sli4_t *sli4, void *buf, 3681 size_t size, ocs_dma_t *dma); 3682 extern int32_t sli_cmd_common_set_profile_config(sli4_t *sli4, void *buf, 3683 size_t size, ocs_dma_t *dma, 3684 uint8_t profile_id, uint32_t descriptor_count, 3685 uint8_t isap); 3686 3687 extern int32_t sli_cqe_mq(void *); 3688 extern int32_t sli_cqe_async(sli4_t *, void *); 3689 3690 extern int32_t sli_setup(sli4_t *, ocs_os_handle_t, sli4_port_type_e); 3691 extern void sli_calc_max_qentries(sli4_t *sli4); 3692 extern int32_t sli_init(sli4_t *); 3693 extern int32_t sli_reset(sli4_t *); 3694 extern int32_t sli_fw_reset(sli4_t *); 3695 extern int32_t sli_teardown(sli4_t *); 3696 extern int32_t sli_callback(sli4_t *, sli4_callback_e, void *, void *); 3697 extern int32_t sli_bmbx_command(sli4_t *); 3698 extern int32_t __sli_queue_init(sli4_t *, sli4_queue_t *, uint32_t, size_t, uint32_t, uint32_t); 3699 extern int32_t __sli_create_queue(sli4_t *, sli4_queue_t *); 3700 extern int32_t sli_eq_modify_delay(sli4_t *sli4, sli4_queue_t *eq, uint32_t num_eq, uint32_t shift, uint32_t delay_mult); 3701 extern int32_t sli_queue_alloc(sli4_t *, uint32_t, sli4_queue_t *, uint32_t, sli4_queue_t *, uint16_t); 3702 extern int32_t sli_cq_alloc_set(sli4_t *, sli4_queue_t *qs[], uint32_t, uint32_t, sli4_queue_t *eqs[]); 3703 extern int32_t sli_get_queue_entry_size(sli4_t *, uint32_t); 3704 extern int32_t sli_queue_free(sli4_t *, sli4_queue_t *, uint32_t, uint32_t); 3705 extern int32_t sli_queue_reset(sli4_t *, sli4_queue_t *); 3706 extern int32_t sli_queue_is_empty(sli4_t *, sli4_queue_t *); 3707 extern int32_t sli_queue_eq_arm(sli4_t *, sli4_queue_t *, uint8_t); 3708 extern int32_t sli_queue_arm(sli4_t *, sli4_queue_t *, uint8_t); 3709 extern int32_t _sli_queue_write(sli4_t *, sli4_queue_t *, uint8_t *); 3710 extern int32_t sli_queue_write(sli4_t *, sli4_queue_t *, uint8_t *); 3711 extern int32_t sli_queue_read(sli4_t *, sli4_queue_t *, uint8_t *); 3712 extern int32_t sli_queue_index(sli4_t *, sli4_queue_t *); 3713 extern int32_t _sli_queue_poke(sli4_t *, sli4_queue_t *, uint32_t, uint8_t *); 3714 extern int32_t sli_queue_poke(sli4_t *, sli4_queue_t *, uint32_t, uint8_t *); 3715 extern int32_t sli_resource_alloc(sli4_t *, sli4_resource_e, uint32_t *, uint32_t *); 3716 extern int32_t sli_resource_free(sli4_t *, sli4_resource_e, uint32_t); 3717 extern int32_t sli_resource_reset(sli4_t *, sli4_resource_e); 3718 extern int32_t sli_eq_parse(sli4_t *, uint8_t *, uint16_t *); 3719 extern int32_t sli_cq_parse(sli4_t *, sli4_queue_t *, uint8_t *, sli4_qentry_e *, uint16_t *); 3720 3721 extern int32_t sli_raise_ue(sli4_t *, uint8_t); 3722 extern int32_t sli_dump_is_ready(sli4_t *); 3723 extern int32_t sli_dump_is_present(sli4_t *); 3724 extern int32_t sli_reset_required(sli4_t *); 3725 extern int32_t sli_fw_error_status(sli4_t *); 3726 extern int32_t sli_fw_ready(sli4_t *); 3727 extern uint32_t sli_reg_read(sli4_t *, sli4_regname_e); 3728 extern void sli_reg_write(sli4_t *, sli4_regname_e, uint32_t); 3729 extern int32_t sli_link_is_configurable(sli4_t *); 3730 3731 #include "ocs_fcp.h" 3732 3733 /** 3734 * @brief Maximum value for a FCFI 3735 * 3736 * Note that although most commands provide a 16 bit field for the FCFI, 3737 * the FC/FCoE Asynchronous Recived CQE format only provides 6 bits for 3738 * the returned FCFI. Then effectively, the FCFI cannot be larger than 3739 * 1 << 6 or 64. 3740 */ 3741 #define SLI4_MAX_FCFI 64 3742 3743 /** 3744 * @brief Maximum value for FCF index 3745 * 3746 * The SLI-4 specification uses a 16 bit field in most places for the FCF 3747 * index, but practically, this value will be much smaller. Arbitrarily 3748 * limit the max FCF index to match the max FCFI value. 3749 */ 3750 #define SLI4_MAX_FCF_INDEX SLI4_MAX_FCFI 3751 3752 /************************************************************************* 3753 * SLI-4 FC/FCoE mailbox command formats and definitions. 3754 */ 3755 3756 /** 3757 * FC/FCoE opcode (OPC) values. 3758 */ 3759 #define SLI4_OPC_FCOE_WQ_CREATE 0x1 3760 #define SLI4_OPC_FCOE_WQ_DESTROY 0x2 3761 #define SLI4_OPC_FCOE_POST_SGL_PAGES 0x3 3762 #define SLI4_OPC_FCOE_RQ_CREATE 0x5 3763 #define SLI4_OPC_FCOE_RQ_DESTROY 0x6 3764 #define SLI4_OPC_FCOE_READ_FCF_TABLE 0x8 3765 #define SLI4_OPC_FCOE_POST_HDR_TEMPLATES 0xb 3766 #define SLI4_OPC_FCOE_REDISCOVER_FCF 0x10 3767 3768 /* Use the default CQ associated with the WQ */ 3769 #define SLI4_CQ_DEFAULT 0xffff 3770 3771 typedef struct sli4_physical_page_descriptor_s { 3772 uint32_t low; 3773 uint32_t high; 3774 } sli4_physical_page_descriptor_t; 3775 3776 /** 3777 * @brief FCOE_WQ_CREATE 3778 * 3779 * Create a Work Queue for FC/FCoE use. 3780 */ 3781 #define SLI4_FCOE_WQ_CREATE_V0_MAX_PAGES 4 3782 3783 typedef struct sli4_req_fcoe_wq_create_s { 3784 sli4_req_hdr_t hdr; 3785 #if BYTE_ORDER == LITTLE_ENDIAN 3786 uint32_t num_pages:8, 3787 dua:1, 3788 :7, 3789 cq_id:16; 3790 sli4_physical_page_descriptor_t page_physical_address[SLI4_FCOE_WQ_CREATE_V0_MAX_PAGES]; 3791 uint32_t bqu:1, 3792 :7, 3793 ulp:8, 3794 :16; 3795 #else 3796 #error big endian version not defined 3797 #endif 3798 } sli4_req_fcoe_wq_create_t; 3799 3800 /** 3801 * @brief FCOE_WQ_CREATE_V1 3802 * 3803 * Create a version 1 Work Queue for FC/FCoE use. 3804 */ 3805 typedef struct sli4_req_fcoe_wq_create_v1_s { 3806 sli4_req_hdr_t hdr; 3807 #if BYTE_ORDER == LITTLE_ENDIAN 3808 uint32_t num_pages:16, 3809 cq_id:16; 3810 uint32_t page_size:8, 3811 wqe_size:4, 3812 :4, 3813 wqe_count:16; 3814 uint32_t rsvd6; 3815 sli4_physical_page_descriptor_t page_physical_address[8]; 3816 #else 3817 #error big endian version not defined 3818 #endif 3819 } sli4_req_fcoe_wq_create_v1_t; 3820 3821 #define SLI4_FCOE_WQ_CREATE_V1_MAX_PAGES 8 3822 3823 /** 3824 * @brief FCOE_WQ_DESTROY 3825 * 3826 * Destroy an FC/FCoE Work Queue. 3827 */ 3828 typedef struct sli4_req_fcoe_wq_destroy_s { 3829 sli4_req_hdr_t hdr; 3830 #if BYTE_ORDER == LITTLE_ENDIAN 3831 uint32_t wq_id:16, 3832 :16; 3833 #else 3834 #error big endian version not defined 3835 #endif 3836 } sli4_req_fcoe_wq_destroy_t; 3837 3838 /** 3839 * @brief FCOE_POST_SGL_PAGES 3840 * 3841 * Register the scatter gather list (SGL) memory and associate it with an XRI. 3842 */ 3843 typedef struct sli4_req_fcoe_post_sgl_pages_s { 3844 sli4_req_hdr_t hdr; 3845 #if BYTE_ORDER == LITTLE_ENDIAN 3846 uint32_t xri_start:16, 3847 xri_count:16; 3848 struct { 3849 uint32_t page0_low; 3850 uint32_t page0_high; 3851 uint32_t page1_low; 3852 uint32_t page1_high; 3853 } page_set[10]; 3854 #else 3855 #error big endian version not defined 3856 #endif 3857 } sli4_req_fcoe_post_sgl_pages_t; 3858 3859 /** 3860 * @brief FCOE_RQ_CREATE 3861 * 3862 * Create a Receive Queue for FC/FCoE use. 3863 */ 3864 typedef struct sli4_req_fcoe_rq_create_s { 3865 sli4_req_hdr_t hdr; 3866 #if BYTE_ORDER == LITTLE_ENDIAN 3867 uint32_t num_pages:16, 3868 dua:1, 3869 bqu:1, 3870 :6, 3871 ulp:8; 3872 uint32_t :16, 3873 rqe_count:4, 3874 :12; 3875 uint32_t rsvd6; 3876 uint32_t buffer_size:16, 3877 cq_id:16; 3878 uint32_t rsvd8; 3879 sli4_physical_page_descriptor_t page_physical_address[8]; 3880 #else 3881 #error big endian version not defined 3882 #endif 3883 } sli4_req_fcoe_rq_create_t; 3884 3885 #define SLI4_FCOE_RQ_CREATE_V0_MAX_PAGES 8 3886 #define SLI4_FCOE_RQ_CREATE_V0_MIN_BUF_SIZE 128 3887 #define SLI4_FCOE_RQ_CREATE_V0_MAX_BUF_SIZE 2048 3888 3889 /** 3890 * @brief FCOE_RQ_CREATE_V1 3891 * 3892 * Create a version 1 Receive Queue for FC/FCoE use. 3893 */ 3894 typedef struct sli4_req_fcoe_rq_create_v1_s { 3895 sli4_req_hdr_t hdr; 3896 #if BYTE_ORDER == LITTLE_ENDIAN 3897 uint32_t num_pages:16, 3898 :13, 3899 dim:1, 3900 dfd:1, 3901 dnb:1; 3902 uint32_t page_size:8, 3903 rqe_size:4, 3904 :4, 3905 rqe_count:16; 3906 uint32_t rsvd6; 3907 uint32_t :16, 3908 cq_id:16; 3909 uint32_t buffer_size; 3910 sli4_physical_page_descriptor_t page_physical_address[8]; 3911 #else 3912 #error big endian version not defined 3913 #endif 3914 } sli4_req_fcoe_rq_create_v1_t; 3915 3916 /** 3917 * @brief FCOE_RQ_CREATE_V2 3918 * 3919 * Create a version 2 Receive Queue for FC/FCoE use. 3920 */ 3921 typedef struct sli4_req_fcoe_rq_create_v2_s { 3922 sli4_req_hdr_t hdr; 3923 #if BYTE_ORDER == LITTLE_ENDIAN 3924 uint32_t num_pages:16, 3925 rq_count:8, 3926 :5, 3927 dim:1, 3928 dfd:1, 3929 dnb:1; 3930 uint32_t page_size:8, 3931 rqe_size:4, 3932 :4, 3933 rqe_count:16; 3934 uint32_t hdr_buffer_size:16, 3935 payload_buffer_size:16; 3936 uint32_t base_cq_id:16, 3937 :16; 3938 uint32_t rsvd; 3939 sli4_physical_page_descriptor_t page_physical_address[0]; 3940 #else 3941 #error big endian version not defined 3942 #endif 3943 } sli4_req_fcoe_rq_create_v2_t; 3944 3945 #define SLI4_FCOE_RQ_CREATE_V1_MAX_PAGES 8 3946 #define SLI4_FCOE_RQ_CREATE_V1_MIN_BUF_SIZE 64 3947 #define SLI4_FCOE_RQ_CREATE_V1_MAX_BUF_SIZE 2048 3948 3949 #define SLI4_FCOE_RQE_SIZE_8 0x2 3950 #define SLI4_FCOE_RQE_SIZE_16 0x3 3951 #define SLI4_FCOE_RQE_SIZE_32 0x4 3952 #define SLI4_FCOE_RQE_SIZE_64 0x5 3953 #define SLI4_FCOE_RQE_SIZE_128 0x6 3954 3955 #define SLI4_FCOE_RQ_PAGE_SIZE_4096 0x1 3956 #define SLI4_FCOE_RQ_PAGE_SIZE_8192 0x2 3957 #define SLI4_FCOE_RQ_PAGE_SIZE_16384 0x4 3958 #define SLI4_FCOE_RQ_PAGE_SIZE_32768 0x8 3959 #define SLI4_FCOE_RQ_PAGE_SIZE_64536 0x10 3960 3961 #define SLI4_FCOE_RQE_SIZE 8 3962 3963 /** 3964 * @brief FCOE_RQ_DESTROY 3965 * 3966 * Destroy an FC/FCoE Receive Queue. 3967 */ 3968 typedef struct sli4_req_fcoe_rq_destroy_s { 3969 sli4_req_hdr_t hdr; 3970 #if BYTE_ORDER == LITTLE_ENDIAN 3971 uint32_t rq_id:16, 3972 :16; 3973 #else 3974 #error big endian version not defined 3975 #endif 3976 } sli4_req_fcoe_rq_destroy_t; 3977 3978 /** 3979 * @brief FCOE_READ_FCF_TABLE 3980 * 3981 * Retrieve a FCF database (also known as a table) entry created by the SLI Port 3982 * during FIP discovery. 3983 */ 3984 typedef struct sli4_req_fcoe_read_fcf_table_s { 3985 sli4_req_hdr_t hdr; 3986 #if BYTE_ORDER == LITTLE_ENDIAN 3987 uint32_t fcf_index:16, 3988 :16; 3989 #else 3990 #error big endian version not defined 3991 #endif 3992 } sli4_req_fcoe_read_fcf_table_t; 3993 3994 /* A FCF index of -1 on the request means return the first valid entry */ 3995 #define SLI4_FCOE_FCF_TABLE_FIRST (UINT16_MAX) 3996 3997 /** 3998 * @brief FCF table entry 3999 * 4000 * This is the information returned by the FCOE_READ_FCF_TABLE command. 4001 */ 4002 typedef struct sli4_fcf_entry_s { 4003 #if BYTE_ORDER == LITTLE_ENDIAN 4004 uint32_t max_receive_size; 4005 uint32_t fip_keep_alive; 4006 uint32_t fip_priority; 4007 uint8_t fcf_mac_address[6]; 4008 uint8_t fcf_available; 4009 uint8_t mac_address_provider; 4010 uint8_t fabric_name_id[8]; 4011 uint8_t fc_map[3]; 4012 uint8_t val:1, 4013 fc:1, 4014 :5, 4015 sol:1; 4016 uint32_t fcf_index:16, 4017 fcf_state:16; 4018 uint8_t vlan_bitmap[512]; 4019 uint8_t switch_name[8]; 4020 #else 4021 #error big endian version not defined 4022 #endif 4023 } sli4_fcf_entry_t; 4024 4025 /** 4026 * @brief FCOE_READ_FCF_TABLE response. 4027 */ 4028 typedef struct sli4_res_fcoe_read_fcf_table_s { 4029 sli4_res_hdr_t hdr; 4030 #if BYTE_ORDER == LITTLE_ENDIAN 4031 uint32_t event_tag; 4032 uint32_t next_index:16, 4033 :16; 4034 sli4_fcf_entry_t fcf_entry; 4035 #else 4036 #error big endian version not defined 4037 #endif 4038 } sli4_res_fcoe_read_fcf_table_t; 4039 4040 /* A next FCF index of -1 in the response means this is the last valid entry */ 4041 #define SLI4_FCOE_FCF_TABLE_LAST (UINT16_MAX) 4042 4043 /** 4044 * @brief FCOE_POST_HDR_TEMPLATES 4045 */ 4046 typedef struct sli4_req_fcoe_post_hdr_templates_s { 4047 sli4_req_hdr_t hdr; 4048 #if BYTE_ORDER == LITTLE_ENDIAN 4049 uint32_t rpi_offset:16, 4050 page_count:16; 4051 sli4_physical_page_descriptor_t page_descriptor[0]; 4052 #else 4053 #error big endian version not defined 4054 #endif 4055 } sli4_req_fcoe_post_hdr_templates_t; 4056 4057 #define SLI4_FCOE_HDR_TEMPLATE_SIZE 64 4058 4059 /** 4060 * @brief FCOE_REDISCOVER_FCF 4061 */ 4062 typedef struct sli4_req_fcoe_rediscover_fcf_s { 4063 sli4_req_hdr_t hdr; 4064 #if BYTE_ORDER == LITTLE_ENDIAN 4065 uint32_t fcf_count:16, 4066 :16; 4067 uint32_t rsvd5; 4068 uint16_t fcf_index[16]; 4069 #else 4070 #error big endian version not defined 4071 #endif 4072 } sli4_req_fcoe_rediscover_fcf_t; 4073 4074 /** 4075 * Work Queue Entry (WQE) types. 4076 */ 4077 #define SLI4_WQE_ABORT 0x0f 4078 #define SLI4_WQE_ELS_REQUEST64 0x8a 4079 #define SLI4_WQE_FCP_IBIDIR64 0xac 4080 #define SLI4_WQE_FCP_IREAD64 0x9a 4081 #define SLI4_WQE_FCP_IWRITE64 0x98 4082 #define SLI4_WQE_FCP_ICMND64 0x9c 4083 #define SLI4_WQE_FCP_TRECEIVE64 0xa1 4084 #define SLI4_WQE_FCP_CONT_TRECEIVE64 0xe5 4085 #define SLI4_WQE_FCP_TRSP64 0xa3 4086 #define SLI4_WQE_FCP_TSEND64 0x9f 4087 #define SLI4_WQE_GEN_REQUEST64 0xc2 4088 #define SLI4_WQE_SEND_FRAME 0xe1 4089 #define SLI4_WQE_XMIT_BCAST64 0X84 4090 #define SLI4_WQE_XMIT_BLS_RSP 0x97 4091 #define SLI4_WQE_ELS_RSP64 0x95 4092 #define SLI4_WQE_XMIT_SEQUENCE64 0x82 4093 #define SLI4_WQE_REQUEUE_XRI 0x93 4094 4095 /** 4096 * WQE command types. 4097 */ 4098 #define SLI4_CMD_FCP_IREAD64_WQE 0x00 4099 #define SLI4_CMD_FCP_ICMND64_WQE 0x00 4100 #define SLI4_CMD_FCP_IWRITE64_WQE 0x01 4101 #define SLI4_CMD_FCP_TRECEIVE64_WQE 0x02 4102 #define SLI4_CMD_FCP_TRSP64_WQE 0x03 4103 #define SLI4_CMD_FCP_TSEND64_WQE 0x07 4104 #define SLI4_CMD_GEN_REQUEST64_WQE 0x08 4105 #define SLI4_CMD_XMIT_BCAST64_WQE 0x08 4106 #define SLI4_CMD_XMIT_BLS_RSP64_WQE 0x08 4107 #define SLI4_CMD_ABORT_WQE 0x08 4108 #define SLI4_CMD_XMIT_SEQUENCE64_WQE 0x08 4109 #define SLI4_CMD_REQUEUE_XRI_WQE 0x0A 4110 #define SLI4_CMD_SEND_FRAME_WQE 0x0a 4111 4112 #define SLI4_WQE_SIZE 0x05 4113 #define SLI4_WQE_EXT_SIZE 0x06 4114 4115 #define SLI4_WQE_BYTES (16 * sizeof(uint32_t)) 4116 #define SLI4_WQE_EXT_BYTES (32 * sizeof(uint32_t)) 4117 4118 /* Mask for ccp (CS_CTL) */ 4119 #define SLI4_MASK_CCP 0xfe /* Upper 7 bits of CS_CTL is priority */ 4120 4121 /** 4122 * @brief Generic WQE 4123 */ 4124 typedef struct sli4_generic_wqe_s { 4125 #if BYTE_ORDER == LITTLE_ENDIAN 4126 uint32_t cmd_spec0_5[6]; 4127 uint32_t xri_tag:16, 4128 context_tag:16; 4129 uint32_t :2, 4130 ct:2, 4131 :4, 4132 command:8, 4133 class:3, 4134 :1, 4135 pu:2, 4136 :2, 4137 timer:8; 4138 uint32_t abort_tag; 4139 uint32_t request_tag:16, 4140 :16; 4141 uint32_t ebde_cnt:4, 4142 :3, 4143 len_loc:2, 4144 qosd:1, 4145 :1, 4146 xbl:1, 4147 hlm:1, 4148 iod:1, 4149 dbde:1, 4150 wqes:1, 4151 pri:3, 4152 pv:1, 4153 eat:1, 4154 xc:1, 4155 :1, 4156 ccpe:1, 4157 ccp:8; 4158 uint32_t cmd_type:4, 4159 :3, 4160 wqec:1, 4161 :8, 4162 cq_id:16; 4163 #else 4164 #error big endian version not defined 4165 #endif 4166 } sli4_generic_wqe_t; 4167 4168 /** 4169 * @brief WQE used to abort exchanges. 4170 */ 4171 typedef struct sli4_abort_wqe_s { 4172 #if BYTE_ORDER == LITTLE_ENDIAN 4173 uint32_t rsvd0; 4174 uint32_t rsvd1; 4175 uint32_t ext_t_tag; 4176 uint32_t ia:1, 4177 ir:1, 4178 :6, 4179 criteria:8, 4180 :16; 4181 uint32_t ext_t_mask; 4182 uint32_t t_mask; 4183 uint32_t xri_tag:16, 4184 context_tag:16; 4185 uint32_t :2, 4186 ct:2, 4187 :4, 4188 command:8, 4189 class:3, 4190 :1, 4191 pu:2, 4192 :2, 4193 timer:8; 4194 uint32_t t_tag; 4195 uint32_t request_tag:16, 4196 :16; 4197 uint32_t ebde_cnt:4, 4198 :3, 4199 len_loc:2, 4200 qosd:1, 4201 :1, 4202 xbl:1, 4203 :1, 4204 iod:1, 4205 dbde:1, 4206 wqes:1, 4207 pri:3, 4208 pv:1, 4209 eat:1, 4210 xc:1, 4211 :1, 4212 ccpe:1, 4213 ccp:8; 4214 uint32_t cmd_type:4, 4215 :3, 4216 wqec:1, 4217 :8, 4218 cq_id:16; 4219 #else 4220 #error big endian version not defined 4221 #endif 4222 } sli4_abort_wqe_t; 4223 4224 #define SLI4_ABORT_CRITERIA_XRI_TAG 0x01 4225 #define SLI4_ABORT_CRITERIA_ABORT_TAG 0x02 4226 #define SLI4_ABORT_CRITERIA_REQUEST_TAG 0x03 4227 #define SLI4_ABORT_CRITERIA_EXT_ABORT_TAG 0x04 4228 4229 typedef enum { 4230 SLI_ABORT_XRI, 4231 SLI_ABORT_ABORT_ID, 4232 SLI_ABORT_REQUEST_ID, 4233 SLI_ABORT_MAX, /* must be last */ 4234 } sli4_abort_type_e; 4235 4236 /** 4237 * @brief WQE used to create an ELS request. 4238 */ 4239 typedef struct sli4_els_request64_wqe_s { 4240 sli4_bde_t els_request_payload; 4241 #if BYTE_ORDER == LITTLE_ENDIAN 4242 uint32_t els_request_payload_length; 4243 uint32_t sid:24, 4244 sp:1, 4245 :7; 4246 uint32_t remote_id:24, 4247 :8; 4248 uint32_t xri_tag:16, 4249 context_tag:16; 4250 uint32_t :2, 4251 ct:2, 4252 :4, 4253 command:8, 4254 class:3, 4255 ar:1, 4256 pu:2, 4257 :2, 4258 timer:8; 4259 uint32_t abort_tag; 4260 uint32_t request_tag:16, 4261 temporary_rpi:16; 4262 uint32_t ebde_cnt:4, 4263 :3, 4264 len_loc:2, 4265 qosd:1, 4266 :1, 4267 xbl:1, 4268 hlm:1, 4269 iod:1, 4270 dbde:1, 4271 wqes:1, 4272 pri:3, 4273 pv:1, 4274 eat:1, 4275 xc:1, 4276 :1, 4277 ccpe:1, 4278 ccp:8; 4279 uint32_t cmd_type:4, 4280 els_id:3, 4281 wqec:1, 4282 :8, 4283 cq_id:16; 4284 sli4_bde_t els_response_payload_bde; 4285 uint32_t max_response_payload_length; 4286 #else 4287 #error big endian version not defined 4288 #endif 4289 } sli4_els_request64_wqe_t; 4290 4291 #define SLI4_ELS_REQUEST64_CONTEXT_RPI 0x0 4292 #define SLI4_ELS_REQUEST64_CONTEXT_VPI 0x1 4293 #define SLI4_ELS_REQUEST64_CONTEXT_VFI 0x2 4294 #define SLI4_ELS_REQUEST64_CONTEXT_FCFI 0x3 4295 4296 #define SLI4_ELS_REQUEST64_CLASS_2 0x1 4297 #define SLI4_ELS_REQUEST64_CLASS_3 0x2 4298 4299 #define SLI4_ELS_REQUEST64_DIR_WRITE 0x0 4300 #define SLI4_ELS_REQUEST64_DIR_READ 0x1 4301 4302 #define SLI4_ELS_REQUEST64_OTHER 0x0 4303 #define SLI4_ELS_REQUEST64_LOGO 0x1 4304 #define SLI4_ELS_REQUEST64_FDISC 0x2 4305 #define SLI4_ELS_REQUEST64_FLOGIN 0x3 4306 #define SLI4_ELS_REQUEST64_PLOGI 0x4 4307 4308 #define SLI4_ELS_REQUEST64_CMD_GEN 0x08 4309 #define SLI4_ELS_REQUEST64_CMD_NON_FABRIC 0x0c 4310 #define SLI4_ELS_REQUEST64_CMD_FABRIC 0x0d 4311 4312 /** 4313 * @brief WQE used to create an FCP initiator no data command. 4314 */ 4315 typedef struct sli4_fcp_icmnd64_wqe_s { 4316 sli4_bde_t bde; 4317 #if BYTE_ORDER == LITTLE_ENDIAN 4318 uint32_t payload_offset_length:16, 4319 fcp_cmd_buffer_length:16; 4320 uint32_t rsvd4; 4321 uint32_t remote_n_port_id:24, 4322 :8; 4323 uint32_t xri_tag:16, 4324 context_tag:16; 4325 uint32_t dif:2, 4326 ct:2, 4327 bs:3, 4328 :1, 4329 command:8, 4330 class:3, 4331 :1, 4332 pu:2, 4333 erp:1, 4334 lnk:1, 4335 timer:8; 4336 uint32_t abort_tag; 4337 uint32_t request_tag:16, 4338 :16; 4339 uint32_t ebde_cnt:4, 4340 :3, 4341 len_loc:2, 4342 qosd:1, 4343 :1, 4344 xbl:1, 4345 hlm:1, 4346 iod:1, 4347 dbde:1, 4348 wqes:1, 4349 pri:3, 4350 pv:1, 4351 eat:1, 4352 xc:1, 4353 :1, 4354 ccpe:1, 4355 ccp:8; 4356 uint32_t cmd_type:4, 4357 :3, 4358 wqec:1, 4359 :8, 4360 cq_id:16; 4361 uint32_t rsvd12; 4362 uint32_t rsvd13; 4363 uint32_t rsvd14; 4364 uint32_t rsvd15; 4365 #else 4366 #error big endian version not defined 4367 #endif 4368 } sli4_fcp_icmnd64_wqe_t; 4369 4370 /** 4371 * @brief WQE used to create an FCP initiator read. 4372 */ 4373 typedef struct sli4_fcp_iread64_wqe_s { 4374 sli4_bde_t bde; 4375 #if BYTE_ORDER == LITTLE_ENDIAN 4376 uint32_t payload_offset_length:16, 4377 fcp_cmd_buffer_length:16; 4378 uint32_t total_transfer_length; 4379 uint32_t remote_n_port_id:24, 4380 :8; 4381 uint32_t xri_tag:16, 4382 context_tag:16; 4383 uint32_t dif:2, 4384 ct:2, 4385 bs:3, 4386 :1, 4387 command:8, 4388 class:3, 4389 :1, 4390 pu:2, 4391 erp:1, 4392 lnk:1, 4393 timer:8; 4394 uint32_t abort_tag; 4395 uint32_t request_tag:16, 4396 :16; 4397 uint32_t ebde_cnt:4, 4398 :3, 4399 len_loc:2, 4400 qosd:1, 4401 :1, 4402 xbl:1, 4403 hlm:1, 4404 iod:1, 4405 dbde:1, 4406 wqes:1, 4407 pri:3, 4408 pv:1, 4409 eat:1, 4410 xc:1, 4411 :1, 4412 ccpe:1, 4413 ccp:8; 4414 uint32_t cmd_type:4, 4415 :3, 4416 wqec:1, 4417 :8, 4418 cq_id:16; 4419 uint32_t rsvd12; 4420 #else 4421 #error big endian version not defined 4422 #endif 4423 sli4_bde_t first_data_bde; /* reserved if performance hints disabled */ 4424 } sli4_fcp_iread64_wqe_t; 4425 4426 /** 4427 * @brief WQE used to create an FCP initiator write. 4428 */ 4429 typedef struct sli4_fcp_iwrite64_wqe_s { 4430 sli4_bde_t bde; 4431 #if BYTE_ORDER == LITTLE_ENDIAN 4432 uint32_t payload_offset_length:16, 4433 fcp_cmd_buffer_length:16; 4434 uint32_t total_transfer_length; 4435 uint32_t initial_transfer_length; 4436 uint32_t xri_tag:16, 4437 context_tag:16; 4438 uint32_t dif:2, 4439 ct:2, 4440 bs:3, 4441 :1, 4442 command:8, 4443 class:3, 4444 :1, 4445 pu:2, 4446 erp:1, 4447 lnk:1, 4448 timer:8; 4449 uint32_t abort_tag; 4450 uint32_t request_tag:16, 4451 :16; 4452 uint32_t ebde_cnt:4, 4453 :3, 4454 len_loc:2, 4455 qosd:1, 4456 :1, 4457 xbl:1, 4458 hlm:1, 4459 iod:1, 4460 dbde:1, 4461 wqes:1, 4462 pri:3, 4463 pv:1, 4464 eat:1, 4465 xc:1, 4466 :1, 4467 ccpe:1, 4468 ccp:8; 4469 uint32_t cmd_type:4, 4470 :3, 4471 wqec:1, 4472 :8, 4473 cq_id:16; 4474 uint32_t remote_n_port_id:24, 4475 :8; 4476 #else 4477 #error big endian version not defined 4478 #endif 4479 sli4_bde_t first_data_bde; 4480 } sli4_fcp_iwrite64_wqe_t; 4481 4482 typedef struct sli4_fcp_128byte_wqe_s { 4483 uint32_t dw[32]; 4484 } sli4_fcp_128byte_wqe_t; 4485 4486 /** 4487 * @brief WQE used to create an FCP target receive, and FCP target 4488 * receive continue. 4489 */ 4490 typedef struct sli4_fcp_treceive64_wqe_s { 4491 sli4_bde_t bde; 4492 #if BYTE_ORDER == LITTLE_ENDIAN 4493 uint32_t payload_offset_length; 4494 uint32_t relative_offset; 4495 /** 4496 * DWord 5 can either be the task retry identifier (HLM=0) or 4497 * the remote N_Port ID (HLM=1), or if implementing the Skyhawk 4498 * T10-PI workaround, the secondary xri tag 4499 */ 4500 union { 4501 uint32_t sec_xri_tag:16, 4502 :16; 4503 uint32_t dword; 4504 } dword5; 4505 uint32_t xri_tag:16, 4506 context_tag:16; 4507 uint32_t dif:2, 4508 ct:2, 4509 bs:3, 4510 :1, 4511 command:8, 4512 class:3, 4513 ar:1, 4514 pu:2, 4515 conf:1, 4516 lnk:1, 4517 timer:8; 4518 uint32_t abort_tag; 4519 uint32_t request_tag:16, 4520 remote_xid:16; 4521 uint32_t ebde_cnt:4, 4522 :1, 4523 app_id_valid:1, 4524 :1, 4525 len_loc:2, 4526 qosd:1, 4527 wchn:1, 4528 xbl:1, 4529 hlm:1, 4530 iod:1, 4531 dbde:1, 4532 wqes:1, 4533 pri:3, 4534 pv:1, 4535 eat:1, 4536 xc:1, 4537 sr:1, 4538 ccpe:1, 4539 ccp:8; 4540 uint32_t cmd_type:4, 4541 :3, 4542 wqec:1, 4543 :8, 4544 cq_id:16; 4545 uint32_t fcp_data_receive_length; 4546 4547 #else 4548 #error big endian version not defined 4549 #endif 4550 sli4_bde_t first_data_bde; /* For performance hints */ 4551 4552 } sli4_fcp_treceive64_wqe_t; 4553 4554 /** 4555 * @brief WQE used to create an FCP target response. 4556 */ 4557 typedef struct sli4_fcp_trsp64_wqe_s { 4558 sli4_bde_t bde; 4559 #if BYTE_ORDER == LITTLE_ENDIAN 4560 uint32_t fcp_response_length; 4561 uint32_t rsvd4; 4562 /** 4563 * DWord 5 can either be the task retry identifier (HLM=0) or 4564 * the remote N_Port ID (HLM=1) 4565 */ 4566 uint32_t dword5; 4567 uint32_t xri_tag:16, 4568 rpi:16; 4569 uint32_t :2, 4570 ct:2, 4571 dnrx:1, 4572 :3, 4573 command:8, 4574 class:3, 4575 ag:1, 4576 pu:2, 4577 conf:1, 4578 lnk:1, 4579 timer:8; 4580 uint32_t abort_tag; 4581 uint32_t request_tag:16, 4582 remote_xid:16; 4583 uint32_t ebde_cnt:4, 4584 :1, 4585 app_id_valid:1, 4586 :1, 4587 len_loc:2, 4588 qosd:1, 4589 wchn:1, 4590 xbl:1, 4591 hlm:1, 4592 iod:1, 4593 dbde:1, 4594 wqes:1, 4595 pri:3, 4596 pv:1, 4597 eat:1, 4598 xc:1, 4599 sr:1, 4600 ccpe:1, 4601 ccp:8; 4602 uint32_t cmd_type:4, 4603 :3, 4604 wqec:1, 4605 :8, 4606 cq_id:16; 4607 uint32_t rsvd12; 4608 uint32_t rsvd13; 4609 uint32_t rsvd14; 4610 uint32_t rsvd15; 4611 #else 4612 #error big endian version not defined 4613 #endif 4614 } sli4_fcp_trsp64_wqe_t; 4615 4616 /** 4617 * @brief WQE used to create an FCP target send (DATA IN). 4618 */ 4619 typedef struct sli4_fcp_tsend64_wqe_s { 4620 sli4_bde_t bde; 4621 #if BYTE_ORDER == LITTLE_ENDIAN 4622 uint32_t payload_offset_length; 4623 uint32_t relative_offset; 4624 /** 4625 * DWord 5 can either be the task retry identifier (HLM=0) or 4626 * the remote N_Port ID (HLM=1) 4627 */ 4628 uint32_t dword5; 4629 uint32_t xri_tag:16, 4630 rpi:16; 4631 uint32_t dif:2, 4632 ct:2, 4633 bs:3, 4634 :1, 4635 command:8, 4636 class:3, 4637 ar:1, 4638 pu:2, 4639 conf:1, 4640 lnk:1, 4641 timer:8; 4642 uint32_t abort_tag; 4643 uint32_t request_tag:16, 4644 remote_xid:16; 4645 uint32_t ebde_cnt:4, 4646 :1, 4647 app_id_valid:1, 4648 :1, 4649 len_loc:2, 4650 qosd:1, 4651 wchn:1, 4652 xbl:1, 4653 hlm:1, 4654 iod:1, 4655 dbde:1, 4656 wqes:1, 4657 pri:3, 4658 pv:1, 4659 eat:1, 4660 xc:1, 4661 sr:1, 4662 ccpe:1, 4663 ccp:8; 4664 uint32_t cmd_type:4, 4665 :3, 4666 wqec:1, 4667 :8, 4668 cq_id:16; 4669 uint32_t fcp_data_transmit_length; 4670 4671 #else 4672 #error big endian version not defined 4673 #endif 4674 sli4_bde_t first_data_bde; /* For performance hints */ 4675 } sli4_fcp_tsend64_wqe_t; 4676 4677 #define SLI4_IO_CONTINUATION BIT(0) /** The XRI associated with this IO is already active */ 4678 #define SLI4_IO_AUTO_GOOD_RESPONSE BIT(1) /** Automatically generate a good RSP frame */ 4679 #define SLI4_IO_NO_ABORT BIT(2) 4680 #define SLI4_IO_DNRX BIT(3) /** Set the DNRX bit because no auto xref rdy buffer is posted */ 4681 4682 /* WQE DIF field contents */ 4683 #define SLI4_DIF_DISABLED 0 4684 #define SLI4_DIF_PASS_THROUGH 1 4685 #define SLI4_DIF_STRIP 2 4686 #define SLI4_DIF_INSERT 3 4687 4688 /** 4689 * @brief WQE used to create a general request. 4690 */ 4691 typedef struct sli4_gen_request64_wqe_s { 4692 sli4_bde_t bde; 4693 #if BYTE_ORDER == LITTLE_ENDIAN 4694 uint32_t request_payload_length; 4695 uint32_t relative_offset; 4696 uint32_t :8, 4697 df_ctl:8, 4698 type:8, 4699 r_ctl:8; 4700 uint32_t xri_tag:16, 4701 context_tag:16; 4702 uint32_t :2, 4703 ct:2, 4704 :4, 4705 command:8, 4706 class:3, 4707 :1, 4708 pu:2, 4709 :2, 4710 timer:8; 4711 uint32_t abort_tag; 4712 uint32_t request_tag:16, 4713 :16; 4714 uint32_t ebde_cnt:4, 4715 :3, 4716 len_loc:2, 4717 qosd:1, 4718 :1, 4719 xbl:1, 4720 hlm:1, 4721 iod:1, 4722 dbde:1, 4723 wqes:1, 4724 pri:3, 4725 pv:1, 4726 eat:1, 4727 xc:1, 4728 :1, 4729 ccpe:1, 4730 ccp:8; 4731 uint32_t cmd_type:4, 4732 :3, 4733 wqec:1, 4734 :8, 4735 cq_id:16; 4736 uint32_t remote_n_port_id:24, 4737 :8; 4738 uint32_t rsvd13; 4739 uint32_t rsvd14; 4740 uint32_t max_response_payload_length; 4741 #else 4742 #error big endian version not defined 4743 #endif 4744 } sli4_gen_request64_wqe_t; 4745 4746 /** 4747 * @brief WQE used to create a send frame request. 4748 */ 4749 typedef struct sli4_send_frame_wqe_s { 4750 sli4_bde_t bde; 4751 #if BYTE_ORDER == LITTLE_ENDIAN 4752 uint32_t frame_length; 4753 uint32_t fc_header_0_1[2]; 4754 uint32_t xri_tag:16, 4755 context_tag:16; 4756 uint32_t :2, 4757 ct:2, 4758 :4, 4759 command:8, 4760 class:3, 4761 :1, 4762 pu:2, 4763 :2, 4764 timer:8; 4765 uint32_t abort_tag; 4766 uint32_t request_tag:16, 4767 eof:8, 4768 sof:8; 4769 uint32_t ebde_cnt:4, 4770 :3, 4771 lenloc:2, 4772 qosd:1, 4773 wchn:1, 4774 xbl:1, 4775 hlm:1, 4776 iod:1, 4777 dbde:1, 4778 wqes:1, 4779 pri:3, 4780 pv:1, 4781 eat:1, 4782 xc:1, 4783 :1, 4784 ccpe:1, 4785 ccp:8; 4786 uint32_t cmd_type:4, 4787 :3, 4788 wqec:1, 4789 :8, 4790 cq_id:16; 4791 uint32_t fc_header_2_5[4]; 4792 #else 4793 #error big endian version not defined 4794 #endif 4795 } sli4_send_frame_wqe_t; 4796 4797 /** 4798 * @brief WQE used to create a transmit sequence. 4799 */ 4800 typedef struct sli4_xmit_sequence64_wqe_s { 4801 sli4_bde_t bde; 4802 #if BYTE_ORDER == LITTLE_ENDIAN 4803 uint32_t remote_n_port_id:24, 4804 :8; 4805 uint32_t relative_offset; 4806 uint32_t :2, 4807 si:1, 4808 ft:1, 4809 :2, 4810 xo:1, 4811 ls:1, 4812 df_ctl:8, 4813 type:8, 4814 r_ctl:8; 4815 uint32_t xri_tag:16, 4816 context_tag:16; 4817 uint32_t dif:2, 4818 ct:2, 4819 bs:3, 4820 :1, 4821 command:8, 4822 class:3, 4823 :1, 4824 pu:2, 4825 :2, 4826 timer:8; 4827 uint32_t abort_tag; 4828 uint32_t request_tag:16, 4829 remote_xid:16; 4830 uint32_t ebde_cnt:4, 4831 :3, 4832 len_loc:2, 4833 qosd:1, 4834 :1, 4835 xbl:1, 4836 hlm:1, 4837 iod:1, 4838 dbde:1, 4839 wqes:1, 4840 pri:3, 4841 pv:1, 4842 eat:1, 4843 xc:1, 4844 sr:1, 4845 ccpe:1, 4846 ccp:8; 4847 uint32_t cmd_type:4, 4848 :3, 4849 wqec:1, 4850 :8, 4851 cq_id:16; 4852 uint32_t sequence_payload_len; 4853 uint32_t rsvd13; 4854 uint32_t rsvd14; 4855 uint32_t rsvd15; 4856 #else 4857 #error big endian version not defined 4858 #endif 4859 } sli4_xmit_sequence64_wqe_t; 4860 4861 /** 4862 * @brief WQE used unblock the specified XRI and to release it to the SLI Port's free pool. 4863 */ 4864 typedef struct sli4_requeue_xri_wqe_s { 4865 uint32_t rsvd0; 4866 uint32_t rsvd1; 4867 uint32_t rsvd2; 4868 uint32_t rsvd3; 4869 uint32_t rsvd4; 4870 uint32_t rsvd5; 4871 #if BYTE_ORDER == LITTLE_ENDIAN 4872 uint32_t xri_tag:16, 4873 context_tag:16; 4874 uint32_t :2, 4875 ct:2, 4876 :4, 4877 command:8, 4878 class:3, 4879 :1, 4880 pu:2, 4881 :2, 4882 timer:8; 4883 uint32_t rsvd8; 4884 uint32_t request_tag:16, 4885 :16; 4886 uint32_t ebde_cnt:4, 4887 :3, 4888 len_loc:2, 4889 qosd:1, 4890 wchn:1, 4891 xbl:1, 4892 hlm:1, 4893 iod:1, 4894 dbde:1, 4895 wqes:1, 4896 pri:3, 4897 pv:1, 4898 eat:1, 4899 xc:1, 4900 :1, 4901 ccpe:1, 4902 ccp:8; 4903 uint32_t cmd_type:4, 4904 :3, 4905 wqec:1, 4906 :8, 4907 cq_id:16; 4908 uint32_t rsvd12; 4909 uint32_t rsvd13; 4910 uint32_t rsvd14; 4911 uint32_t rsvd15; 4912 #else 4913 #error big endian version not defined 4914 #endif 4915 } sli4_requeue_xri_wqe_t; 4916 4917 /** 4918 * @brief WQE used to send a single frame sequence to broadcast address 4919 */ 4920 typedef struct sli4_xmit_bcast64_wqe_s { 4921 sli4_bde_t sequence_payload; 4922 #if BYTE_ORDER == LITTLE_ENDIAN 4923 uint32_t sequence_payload_length; 4924 uint32_t rsvd4; 4925 uint32_t :8, 4926 df_ctl:8, 4927 type:8, 4928 r_ctl:8; 4929 uint32_t xri_tag:16, 4930 context_tag:16; 4931 uint32_t :2, 4932 ct:2, 4933 :4, 4934 command:8, 4935 class:3, 4936 :1, 4937 pu:2, 4938 :2, 4939 timer:8; 4940 uint32_t abort_tag; 4941 uint32_t request_tag:16, 4942 temporary_rpi:16; 4943 uint32_t ebde_cnt:4, 4944 :3, 4945 len_loc:2, 4946 qosd:1, 4947 :1, 4948 xbl:1, 4949 hlm:1, 4950 iod:1, 4951 dbde:1, 4952 wqes:1, 4953 pri:3, 4954 pv:1, 4955 eat:1, 4956 xc:1, 4957 :1, 4958 ccpe:1, 4959 ccp:8; 4960 uint32_t cmd_type:4, 4961 :3, 4962 wqec:1, 4963 :8, 4964 cq_id:16; 4965 uint32_t rsvd12; 4966 uint32_t rsvd13; 4967 uint32_t rsvd14; 4968 uint32_t rsvd15; 4969 #else 4970 #error big endian version not defined 4971 #endif 4972 } sli4_xmit_bcast64_wqe_t; 4973 4974 /** 4975 * @brief WQE used to create a BLS response. 4976 */ 4977 typedef struct sli4_xmit_bls_rsp_wqe_s { 4978 #if BYTE_ORDER == LITTLE_ENDIAN 4979 uint32_t payload_word0; 4980 uint32_t rx_id:16, 4981 ox_id:16; 4982 uint32_t high_seq_cnt:16, 4983 low_seq_cnt:16; 4984 uint32_t rsvd3; 4985 uint32_t local_n_port_id:24, 4986 :8; 4987 uint32_t remote_id:24, 4988 :6, 4989 ar:1, 4990 xo:1; 4991 uint32_t xri_tag:16, 4992 context_tag:16; 4993 uint32_t :2, 4994 ct:2, 4995 :4, 4996 command:8, 4997 class:3, 4998 :1, 4999 pu:2, 5000 :2, 5001 timer:8; 5002 uint32_t abort_tag; 5003 uint32_t request_tag:16, 5004 :16; 5005 uint32_t ebde_cnt:4, 5006 :3, 5007 len_loc:2, 5008 qosd:1, 5009 :1, 5010 xbl:1, 5011 hlm:1, 5012 iod:1, 5013 dbde:1, 5014 wqes:1, 5015 pri:3, 5016 pv:1, 5017 eat:1, 5018 xc:1, 5019 :1, 5020 ccpe:1, 5021 ccp:8; 5022 uint32_t cmd_type:4, 5023 :3, 5024 wqec:1, 5025 :8, 5026 cq_id:16; 5027 uint32_t temporary_rpi:16, 5028 :16; 5029 uint32_t rsvd13; 5030 uint32_t rsvd14; 5031 uint32_t rsvd15; 5032 #else 5033 #error big endian version not defined 5034 #endif 5035 } sli4_xmit_bls_rsp_wqe_t; 5036 5037 typedef enum { 5038 SLI_BLS_ACC, 5039 SLI_BLS_RJT, 5040 SLI_BLS_MAX 5041 } sli_bls_type_e; 5042 5043 typedef struct sli_bls_payload_s { 5044 sli_bls_type_e type; 5045 uint16_t ox_id; 5046 uint16_t rx_id; 5047 union { 5048 struct { 5049 uint32_t seq_id_validity:8, 5050 seq_id_last:8, 5051 :16; 5052 uint16_t ox_id; 5053 uint16_t rx_id; 5054 uint16_t low_seq_cnt; 5055 uint16_t high_seq_cnt; 5056 } acc; 5057 struct { 5058 uint32_t vendor_unique:8, 5059 reason_explanation:8, 5060 reason_code:8, 5061 :8; 5062 } rjt; 5063 } u; 5064 } sli_bls_payload_t; 5065 5066 /** 5067 * @brief WQE used to create an ELS response. 5068 */ 5069 typedef struct sli4_xmit_els_rsp64_wqe_s { 5070 sli4_bde_t els_response_payload; 5071 #if BYTE_ORDER == LITTLE_ENDIAN 5072 uint32_t els_response_payload_length; 5073 uint32_t s_id:24, 5074 sp:1, 5075 :7; 5076 uint32_t remote_id:24, 5077 :8; 5078 uint32_t xri_tag:16, 5079 context_tag:16; 5080 uint32_t :2, 5081 ct:2, 5082 :4, 5083 command:8, 5084 class:3, 5085 :1, 5086 pu:2, 5087 :2, 5088 timer:8; 5089 uint32_t abort_tag; 5090 uint32_t request_tag:16, 5091 ox_id:16; 5092 uint32_t ebde_cnt:4, 5093 :3, 5094 len_loc:2, 5095 qosd:1, 5096 :1, 5097 xbl:1, 5098 hlm:1, 5099 iod:1, 5100 dbde:1, 5101 wqes:1, 5102 pri:3, 5103 pv:1, 5104 eat:1, 5105 xc:1, 5106 :1, 5107 ccpe:1, 5108 ccp:8; 5109 uint32_t cmd_type:4, 5110 :3, 5111 wqec:1, 5112 :8, 5113 cq_id:16; 5114 uint32_t temporary_rpi:16, 5115 :16; 5116 uint32_t rsvd13; 5117 uint32_t rsvd14; 5118 uint32_t rsvd15; 5119 #else 5120 #error big endian version not defined 5121 #endif 5122 } sli4_xmit_els_rsp64_wqe_t; 5123 5124 /** 5125 * @brief Asynchronouse Event: Link State ACQE. 5126 */ 5127 typedef struct sli4_link_state_s { 5128 #if BYTE_ORDER == LITTLE_ENDIAN 5129 uint32_t link_number:6, 5130 link_type:2, 5131 port_link_status:8, 5132 port_duplex:8, 5133 port_speed:8; 5134 uint32_t port_fault:8, 5135 :8, 5136 logical_link_speed:16; 5137 uint32_t event_tag; 5138 uint32_t :8, 5139 event_code:8, 5140 event_type:8, /** values are protocol specific */ 5141 :6, 5142 ae:1, /** async event - this is an ACQE */ 5143 val:1; /** valid - contents of CQE are valid */ 5144 #else 5145 #error big endian version not defined 5146 #endif 5147 } sli4_link_state_t; 5148 5149 #define SLI4_LINK_ATTN_TYPE_LINK_UP 0x01 5150 #define SLI4_LINK_ATTN_TYPE_LINK_DOWN 0x02 5151 #define SLI4_LINK_ATTN_TYPE_NO_HARD_ALPA 0x03 5152 5153 #define SLI4_LINK_ATTN_P2P 0x01 5154 #define SLI4_LINK_ATTN_FC_AL 0x02 5155 #define SLI4_LINK_ATTN_INTERNAL_LOOPBACK 0x03 5156 #define SLI4_LINK_ATTN_SERDES_LOOPBACK 0x04 5157 5158 #define SLI4_LINK_ATTN_1G 0x01 5159 #define SLI4_LINK_ATTN_2G 0x02 5160 #define SLI4_LINK_ATTN_4G 0x04 5161 #define SLI4_LINK_ATTN_8G 0x08 5162 #define SLI4_LINK_ATTN_10G 0x0a 5163 #define SLI4_LINK_ATTN_16G 0x10 5164 5165 #define SLI4_LINK_TYPE_ETHERNET 0x0 5166 #define SLI4_LINK_TYPE_FC 0x1 5167 5168 /** 5169 * @brief Asynchronouse Event: FC Link Attention Event. 5170 */ 5171 typedef struct sli4_link_attention_s { 5172 #if BYTE_ORDER == LITTLE_ENDIAN 5173 uint32_t link_number:8, 5174 attn_type:8, 5175 topology:8, 5176 port_speed:8; 5177 uint32_t port_fault:8, 5178 shared_link_status:8, 5179 logical_link_speed:16; 5180 uint32_t event_tag; 5181 uint32_t :8, 5182 event_code:8, 5183 event_type:8, /** values are protocol specific */ 5184 :6, 5185 ae:1, /** async event - this is an ACQE */ 5186 val:1; /** valid - contents of CQE are valid */ 5187 #else 5188 #error big endian version not defined 5189 #endif 5190 } sli4_link_attention_t; 5191 5192 /** 5193 * @brief FC/FCoE event types. 5194 */ 5195 #define SLI4_LINK_STATE_PHYSICAL 0x00 5196 #define SLI4_LINK_STATE_LOGICAL 0x01 5197 5198 #define SLI4_FCOE_FIP_FCF_DISCOVERED 0x01 5199 #define SLI4_FCOE_FIP_FCF_TABLE_FULL 0x02 5200 #define SLI4_FCOE_FIP_FCF_DEAD 0x03 5201 #define SLI4_FCOE_FIP_FCF_CLEAR_VLINK 0x04 5202 #define SLI4_FCOE_FIP_FCF_MODIFIED 0x05 5203 5204 #define SLI4_GRP5_QOS_SPEED 0x01 5205 5206 #define SLI4_FC_EVENT_LINK_ATTENTION 0x01 5207 #define SLI4_FC_EVENT_SHARED_LINK_ATTENTION 0x02 5208 5209 #define SLI4_PORT_SPEED_NO_LINK 0x0 5210 #define SLI4_PORT_SPEED_10_MBPS 0x1 5211 #define SLI4_PORT_SPEED_100_MBPS 0x2 5212 #define SLI4_PORT_SPEED_1_GBPS 0x3 5213 #define SLI4_PORT_SPEED_10_GBPS 0x4 5214 5215 #define SLI4_PORT_DUPLEX_NONE 0x0 5216 #define SLI4_PORT_DUPLEX_HWF 0x1 5217 #define SLI4_PORT_DUPLEX_FULL 0x2 5218 5219 #define SLI4_PORT_LINK_STATUS_PHYSICAL_DOWN 0x0 5220 #define SLI4_PORT_LINK_STATUS_PHYSICAL_UP 0x1 5221 #define SLI4_PORT_LINK_STATUS_LOGICAL_DOWN 0x2 5222 #define SLI4_PORT_LINK_STATUS_LOGICAL_UP 0x3 5223 5224 /** 5225 * @brief Asynchronouse Event: FCoE/FIP ACQE. 5226 */ 5227 typedef struct sli4_fcoe_fip_s { 5228 #if BYTE_ORDER == LITTLE_ENDIAN 5229 uint32_t event_information; 5230 uint32_t fcf_count:16, 5231 fcoe_event_type:16; 5232 uint32_t event_tag; 5233 uint32_t :8, 5234 event_code:8, 5235 event_type:8, /** values are protocol specific */ 5236 :6, 5237 ae:1, /** async event - this is an ACQE */ 5238 val:1; /** valid - contents of CQE are valid */ 5239 #else 5240 #error big endian version not defined 5241 #endif 5242 } sli4_fcoe_fip_t; 5243 5244 /** 5245 * @brief FC/FCoE WQ completion queue entry. 5246 */ 5247 typedef struct sli4_fc_wcqe_s { 5248 #if BYTE_ORDER == LITTLE_ENDIAN 5249 uint32_t hw_status:8, 5250 status:8, 5251 request_tag:16; 5252 uint32_t wqe_specific_1; 5253 uint32_t wqe_specific_2; 5254 uint32_t :15, 5255 qx:1, 5256 code:8, 5257 pri:3, 5258 pv:1, 5259 xb:1, 5260 :2, 5261 vld:1; 5262 #else 5263 #error big endian version not defined 5264 #endif 5265 } sli4_fc_wcqe_t; 5266 5267 /** 5268 * @brief FC/FCoE WQ consumed CQ queue entry. 5269 */ 5270 typedef struct sli4_fc_wqec_s { 5271 #if BYTE_ORDER == LITTLE_ENDIAN 5272 uint32_t :32; 5273 uint32_t :32; 5274 uint32_t wqe_index:16, 5275 wq_id:16; 5276 uint32_t :16, 5277 code:8, 5278 :7, 5279 vld:1; 5280 #else 5281 #error big endian version not defined 5282 #endif 5283 } sli4_fc_wqec_t; 5284 5285 /** 5286 * @brief FC/FCoE Completion Status Codes. 5287 */ 5288 #define SLI4_FC_WCQE_STATUS_SUCCESS 0x00 5289 #define SLI4_FC_WCQE_STATUS_FCP_RSP_FAILURE 0x01 5290 #define SLI4_FC_WCQE_STATUS_REMOTE_STOP 0x02 5291 #define SLI4_FC_WCQE_STATUS_LOCAL_REJECT 0x03 5292 #define SLI4_FC_WCQE_STATUS_NPORT_RJT 0x04 5293 #define SLI4_FC_WCQE_STATUS_FABRIC_RJT 0x05 5294 #define SLI4_FC_WCQE_STATUS_NPORT_BSY 0x06 5295 #define SLI4_FC_WCQE_STATUS_FABRIC_BSY 0x07 5296 #define SLI4_FC_WCQE_STATUS_LS_RJT 0x09 5297 #define SLI4_FC_WCQE_STATUS_CMD_REJECT 0x0b 5298 #define SLI4_FC_WCQE_STATUS_FCP_TGT_LENCHECK 0x0c 5299 #define SLI4_FC_WCQE_STATUS_RQ_BUF_LEN_EXCEEDED 0x11 5300 #define SLI4_FC_WCQE_STATUS_RQ_INSUFF_BUF_NEEDED 0x12 5301 #define SLI4_FC_WCQE_STATUS_RQ_INSUFF_FRM_DISC 0x13 5302 #define SLI4_FC_WCQE_STATUS_RQ_DMA_FAILURE 0x14 5303 #define SLI4_FC_WCQE_STATUS_FCP_RSP_TRUNCATE 0x15 5304 #define SLI4_FC_WCQE_STATUS_DI_ERROR 0x16 5305 #define SLI4_FC_WCQE_STATUS_BA_RJT 0x17 5306 #define SLI4_FC_WCQE_STATUS_RQ_INSUFF_XRI_NEEDED 0x18 5307 #define SLI4_FC_WCQE_STATUS_RQ_INSUFF_XRI_DISC 0x19 5308 #define SLI4_FC_WCQE_STATUS_RX_ERROR_DETECT 0x1a 5309 #define SLI4_FC_WCQE_STATUS_RX_ABORT_REQUEST 0x1b 5310 5311 /* driver generated status codes; better not overlap with chip's status codes! */ 5312 #define SLI4_FC_WCQE_STATUS_TARGET_WQE_TIMEOUT 0xff 5313 #define SLI4_FC_WCQE_STATUS_SHUTDOWN 0xfe 5314 #define SLI4_FC_WCQE_STATUS_DISPATCH_ERROR 0xfd 5315 5316 /** 5317 * @brief DI_ERROR Extended Status 5318 */ 5319 #define SLI4_FC_DI_ERROR_GE (1 << 0) /* Guard Error */ 5320 #define SLI4_FC_DI_ERROR_AE (1 << 1) /* Application Tag Error */ 5321 #define SLI4_FC_DI_ERROR_RE (1 << 2) /* Reference Tag Error */ 5322 #define SLI4_FC_DI_ERROR_TDPV (1 << 3) /* Total Data Placed Valid */ 5323 #define SLI4_FC_DI_ERROR_UDB (1 << 4) /* Uninitialized DIF Block */ 5324 #define SLI4_FC_DI_ERROR_EDIR (1 << 5) /* Error direction */ 5325 5326 /** 5327 * @brief Local Reject Reason Codes. 5328 */ 5329 #define SLI4_FC_LOCAL_REJECT_MISSING_CONTINUE 0x01 5330 #define SLI4_FC_LOCAL_REJECT_SEQUENCE_TIMEOUT 0x02 5331 #define SLI4_FC_LOCAL_REJECT_INTERNAL_ERROR 0x03 5332 #define SLI4_FC_LOCAL_REJECT_INVALID_RPI 0x04 5333 #define SLI4_FC_LOCAL_REJECT_NO_XRI 0x05 5334 #define SLI4_FC_LOCAL_REJECT_ILLEGAL_COMMAND 0x06 5335 #define SLI4_FC_LOCAL_REJECT_XCHG_DROPPED 0x07 5336 #define SLI4_FC_LOCAL_REJECT_ILLEGAL_FIELD 0x08 5337 #define SLI4_FC_LOCAL_REJECT_NO_ABORT_MATCH 0x0c 5338 #define SLI4_FC_LOCAL_REJECT_TX_DMA_FAILED 0x0d 5339 #define SLI4_FC_LOCAL_REJECT_RX_DMA_FAILED 0x0e 5340 #define SLI4_FC_LOCAL_REJECT_ILLEGAL_FRAME 0x0f 5341 #define SLI4_FC_LOCAL_REJECT_NO_RESOURCES 0x11 5342 #define SLI4_FC_LOCAL_REJECT_FCP_CONF_FAILURE 0x12 5343 #define SLI4_FC_LOCAL_REJECT_ILLEGAL_LENGTH 0x13 5344 #define SLI4_FC_LOCAL_REJECT_UNSUPPORTED_FEATURE 0x14 5345 #define SLI4_FC_LOCAL_REJECT_ABORT_IN_PROGRESS 0x15 5346 #define SLI4_FC_LOCAL_REJECT_ABORT_REQUESTED 0x16 5347 #define SLI4_FC_LOCAL_REJECT_RCV_BUFFER_TIMEOUT 0x17 5348 #define SLI4_FC_LOCAL_REJECT_LOOP_OPEN_FAILURE 0x18 5349 #define SLI4_FC_LOCAL_REJECT_LINK_DOWN 0x1a 5350 #define SLI4_FC_LOCAL_REJECT_CORRUPTED_DATA 0x1b 5351 #define SLI4_FC_LOCAL_REJECT_CORRUPTED_RPI 0x1c 5352 #define SLI4_FC_LOCAL_REJECT_OUT_OF_ORDER_DATA 0x1d 5353 #define SLI4_FC_LOCAL_REJECT_OUT_OF_ORDER_ACK 0x1e 5354 #define SLI4_FC_LOCAL_REJECT_DUP_FRAME 0x1f 5355 #define SLI4_FC_LOCAL_REJECT_LINK_CONTROL_FRAME 0x20 5356 #define SLI4_FC_LOCAL_REJECT_BAD_HOST_ADDRESS 0x21 5357 #define SLI4_FC_LOCAL_REJECT_MISSING_HDR_BUFFER 0x23 5358 #define SLI4_FC_LOCAL_REJECT_MSEQ_CHAIN_CORRUPTED 0x24 5359 #define SLI4_FC_LOCAL_REJECT_ABORTMULT_REQUESTED 0x25 5360 #define SLI4_FC_LOCAL_REJECT_BUFFER_SHORTAGE 0x28 5361 #define SLI4_FC_LOCAL_REJECT_RCV_XRIBUF_WAITING 0x29 5362 #define SLI4_FC_LOCAL_REJECT_INVALID_VPI 0x2e 5363 #define SLI4_FC_LOCAL_REJECT_MISSING_XRIBUF 0x30 5364 #define SLI4_FC_LOCAL_REJECT_INVALID_RELOFFSET 0x40 5365 #define SLI4_FC_LOCAL_REJECT_MISSING_RELOFFSET 0x41 5366 #define SLI4_FC_LOCAL_REJECT_INSUFF_BUFFERSPACE 0x42 5367 #define SLI4_FC_LOCAL_REJECT_MISSING_SI 0x43 5368 #define SLI4_FC_LOCAL_REJECT_MISSING_ES 0x44 5369 #define SLI4_FC_LOCAL_REJECT_INCOMPLETE_XFER 0x45 5370 #define SLI4_FC_LOCAL_REJECT_SLER_FAILURE 0x46 5371 #define SLI4_FC_LOCAL_REJECT_SLER_CMD_RCV_FAILURE 0x47 5372 #define SLI4_FC_LOCAL_REJECT_SLER_REC_RJT_ERR 0x48 5373 #define SLI4_FC_LOCAL_REJECT_SLER_REC_SRR_RETRY_ERR 0x49 5374 #define SLI4_FC_LOCAL_REJECT_SLER_SRR_RJT_ERR 0x4a 5375 #define SLI4_FC_LOCAL_REJECT_SLER_RRQ_RJT_ERR 0x4c 5376 #define SLI4_FC_LOCAL_REJECT_SLER_RRQ_RETRY_ERR 0x4d 5377 #define SLI4_FC_LOCAL_REJECT_SLER_ABTS_ERR 0x4e 5378 5379 typedef struct sli4_fc_async_rcqe_s { 5380 #if BYTE_ORDER == LITTLE_ENDIAN 5381 uint32_t :8, 5382 status:8, 5383 rq_element_index:12, 5384 :4; 5385 uint32_t rsvd1; 5386 uint32_t fcfi:6, 5387 rq_id:10, 5388 payload_data_placement_length:16; 5389 uint32_t sof_byte:8, 5390 eof_byte:8, 5391 code:8, 5392 header_data_placement_length:6, 5393 :1, 5394 vld:1; 5395 #else 5396 #error big endian version not defined 5397 #endif 5398 } sli4_fc_async_rcqe_t; 5399 5400 typedef struct sli4_fc_async_rcqe_v1_s { 5401 #if BYTE_ORDER == LITTLE_ENDIAN 5402 uint32_t :8, 5403 status:8, 5404 rq_element_index:12, 5405 :4; 5406 uint32_t fcfi:6, 5407 :26; 5408 uint32_t rq_id:16, 5409 payload_data_placement_length:16; 5410 uint32_t sof_byte:8, 5411 eof_byte:8, 5412 code:8, 5413 header_data_placement_length:6, 5414 :1, 5415 vld:1; 5416 #else 5417 #error big endian version not defined 5418 #endif 5419 } sli4_fc_async_rcqe_v1_t; 5420 5421 #define SLI4_FC_ASYNC_RQ_SUCCESS 0x10 5422 #define SLI4_FC_ASYNC_RQ_BUF_LEN_EXCEEDED 0x11 5423 #define SLI4_FC_ASYNC_RQ_INSUFF_BUF_NEEDED 0x12 5424 #define SLI4_FC_ASYNC_RQ_INSUFF_BUF_FRM_DISC 0x13 5425 #define SLI4_FC_ASYNC_RQ_DMA_FAILURE 0x14 5426 5427 typedef struct sli4_fc_coalescing_rcqe_s { 5428 #if BYTE_ORDER == LITTLE_ENDIAN 5429 uint32_t :8, 5430 status:8, 5431 rq_element_index:12, 5432 :4; 5433 uint32_t rsvd1; 5434 uint32_t rq_id:16, 5435 sequence_reporting_placement_length:16; 5436 uint32_t :16, 5437 code:8, 5438 :7, 5439 vld:1; 5440 #else 5441 #error big endian version not defined 5442 #endif 5443 } sli4_fc_coalescing_rcqe_t; 5444 5445 #define SLI4_FC_COALESCE_RQ_SUCCESS 0x10 5446 #define SLI4_FC_COALESCE_RQ_INSUFF_XRI_NEEDED 0x18 5447 5448 typedef struct sli4_fc_optimized_write_cmd_cqe_s { 5449 #if BYTE_ORDER == LITTLE_ENDIAN 5450 uint32_t :8, 5451 status:8, 5452 rq_element_index:15, 5453 iv:1; 5454 uint32_t fcfi:6, 5455 :8, 5456 oox:1, 5457 agxr:1, 5458 xri:16; 5459 uint32_t rq_id:16, 5460 payload_data_placement_length:16; 5461 uint32_t rpi:16, 5462 code:8, 5463 header_data_placement_length:6, 5464 :1, 5465 vld:1; 5466 #else 5467 #error big endian version not defined 5468 #endif 5469 } sli4_fc_optimized_write_cmd_cqe_t; 5470 5471 typedef struct sli4_fc_optimized_write_data_cqe_s { 5472 #if BYTE_ORDER == LITTLE_ENDIAN 5473 uint32_t hw_status:8, 5474 status:8, 5475 xri:16; 5476 uint32_t total_data_placed; 5477 uint32_t extended_status; 5478 uint32_t :16, 5479 code:8, 5480 pri:3, 5481 pv:1, 5482 xb:1, 5483 rha:1, 5484 :1, 5485 vld:1; 5486 #else 5487 #error big endian version not defined 5488 #endif 5489 } sli4_fc_optimized_write_data_cqe_t; 5490 5491 typedef struct sli4_fc_xri_aborted_cqe_s { 5492 #if BYTE_ORDER == LITTLE_ENDIAN 5493 uint32_t :8, 5494 status:8, 5495 :16; 5496 uint32_t extended_status; 5497 uint32_t xri:16, 5498 remote_xid:16; 5499 uint32_t :16, 5500 code:8, 5501 xr:1, 5502 :3, 5503 eo:1, 5504 br:1, 5505 ia:1, 5506 vld:1; 5507 #else 5508 #error big endian version not defined 5509 #endif 5510 } sli4_fc_xri_aborted_cqe_t; 5511 5512 /** 5513 * Code definitions applicable to all FC/FCoE CQE types. 5514 */ 5515 #define SLI4_CQE_CODE_OFFSET 14 5516 5517 #define SLI4_CQE_CODE_WORK_REQUEST_COMPLETION 0x01 5518 #define SLI4_CQE_CODE_RELEASE_WQE 0x02 5519 #define SLI4_CQE_CODE_RQ_ASYNC 0x04 5520 #define SLI4_CQE_CODE_XRI_ABORTED 0x05 5521 #define SLI4_CQE_CODE_RQ_COALESCING 0x06 5522 #define SLI4_CQE_CODE_RQ_CONSUMPTION 0x07 5523 #define SLI4_CQE_CODE_MEASUREMENT_REPORTING 0x08 5524 #define SLI4_CQE_CODE_RQ_ASYNC_V1 0x09 5525 #define SLI4_CQE_CODE_OPTIMIZED_WRITE_CMD 0x0B 5526 #define SLI4_CQE_CODE_OPTIMIZED_WRITE_DATA 0x0C 5527 5528 extern int32_t sli_fc_process_link_state(sli4_t *, void *); 5529 extern int32_t sli_fc_process_link_attention(sli4_t *, void *); 5530 extern int32_t sli_fc_cqe_parse(sli4_t *, sli4_queue_t *, uint8_t *, sli4_qentry_e *, uint16_t *); 5531 extern uint32_t sli_fc_response_length(sli4_t *, uint8_t *); 5532 extern uint32_t sli_fc_io_length(sli4_t *, uint8_t *); 5533 extern int32_t sli_fc_els_did(sli4_t *, uint8_t *, uint32_t *); 5534 extern uint32_t sli_fc_ext_status(sli4_t *, uint8_t *); 5535 extern int32_t sli_fc_rqe_rqid_and_index(sli4_t *, uint8_t *, uint16_t *, uint32_t *); 5536 extern int32_t sli_fc_process_fcoe(sli4_t *, void *); 5537 extern int32_t sli_cmd_fcoe_wq_create(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t); 5538 extern int32_t sli_cmd_fcoe_wq_create_v1(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t); 5539 extern int32_t sli_cmd_fcoe_wq_destroy(sli4_t *, void *, size_t, uint16_t); 5540 extern int32_t sli_cmd_fcoe_post_sgl_pages(sli4_t *, void *, size_t, uint16_t, uint32_t, ocs_dma_t **, ocs_dma_t **, 5541 ocs_dma_t *); 5542 extern int32_t sli_cmd_fcoe_rq_create(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t, uint16_t); 5543 extern int32_t sli_cmd_fcoe_rq_create_v1(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t, uint16_t); 5544 extern int32_t sli_cmd_fcoe_rq_destroy(sli4_t *, void *, size_t, uint16_t); 5545 extern int32_t sli_cmd_fcoe_read_fcf_table(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t); 5546 extern int32_t sli_cmd_fcoe_post_hdr_templates(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, ocs_dma_t *); 5547 extern int32_t sli_cmd_fcoe_rediscover_fcf(sli4_t *, void *, size_t, uint16_t); 5548 extern int32_t sli_fc_rq_alloc(sli4_t *, sli4_queue_t *, uint32_t, uint32_t, sli4_queue_t *, uint16_t, uint8_t); 5549 extern int32_t sli_fc_rq_set_alloc(sli4_t *, uint32_t, sli4_queue_t *[], uint32_t, uint32_t, uint32_t, uint32_t, uint16_t); 5550 extern uint32_t sli_fc_get_rpi_requirements(sli4_t *, uint32_t); 5551 extern int32_t sli_abort_wqe(sli4_t *, void *, size_t, sli4_abort_type_e, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t); 5552 5553 extern int32_t sli_els_request64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint8_t, uint32_t, uint32_t, uint8_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *); 5554 extern int32_t sli_fcp_iread64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t); 5555 extern int32_t sli_fcp_iwrite64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t); 5556 extern int32_t sli_fcp_icmnd64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint8_t); 5557 5558 extern int32_t sli_fcp_treceive64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint32_t, uint8_t, uint8_t, uint8_t, uint32_t); 5559 extern int32_t sli_fcp_trsp64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint32_t, uint8_t, uint8_t, uint32_t); 5560 extern int32_t sli_fcp_tsend64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint32_t, uint8_t, uint8_t, uint8_t, uint32_t); 5561 extern int32_t sli_fcp_cont_treceive64_wqe(sli4_t *, void*, size_t, ocs_dma_t *, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint32_t, uint8_t, uint8_t, uint8_t, uint32_t); 5562 extern int32_t sli_gen_request64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t,uint8_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t); 5563 extern int32_t sli_send_frame_wqe(sli4_t *sli4, void *buf, size_t size, uint8_t sof, uint8_t eof, uint32_t *hdr, 5564 ocs_dma_t *payload, uint32_t req_len, uint8_t timeout, 5565 uint16_t xri, uint16_t req_tag); 5566 extern int32_t sli_xmit_sequence64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint8_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t); 5567 extern int32_t sli_xmit_bcast64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint8_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t); 5568 extern int32_t sli_xmit_bls_rsp64_wqe(sli4_t *, void *, size_t, sli_bls_payload_t *, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint32_t); 5569 extern int32_t sli_xmit_els_rsp64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint32_t, uint32_t); 5570 extern int32_t sli_requeue_xri_wqe(sli4_t *, void *, size_t, uint16_t, uint16_t, uint16_t); 5571 extern void sli4_cmd_lowlevel_set_watchdog(sli4_t *sli4, void *buf, size_t size, uint16_t timeout); 5572 5573 /** 5574 * @ingroup sli_fc 5575 * @brief Retrieve the received header and payload length. 5576 * 5577 * @param sli4 SLI context. 5578 * @param cqe Pointer to the CQ entry. 5579 * @param len_hdr Pointer where the header length is written. 5580 * @param len_data Pointer where the payload length is written. 5581 * 5582 * @return Returns 0 on success, or a non-zero value on failure. 5583 */ 5584 static inline int32_t 5585 sli_fc_rqe_length(sli4_t *sli4, void *cqe, uint32_t *len_hdr, uint32_t *len_data) 5586 { 5587 sli4_fc_async_rcqe_t *rcqe = cqe; 5588 5589 *len_hdr = *len_data = 0; 5590 5591 if (SLI4_FC_ASYNC_RQ_SUCCESS == rcqe->status) { 5592 *len_hdr = rcqe->header_data_placement_length; 5593 *len_data = rcqe->payload_data_placement_length; 5594 return 0; 5595 } else { 5596 return -1; 5597 } 5598 } 5599 5600 /** 5601 * @ingroup sli_fc 5602 * @brief Retrieve the received FCFI. 5603 * 5604 * @param sli4 SLI context. 5605 * @param cqe Pointer to the CQ entry. 5606 * 5607 * @return Returns the FCFI in the CQE. or UINT8_MAX if invalid CQE code. 5608 */ 5609 static inline uint8_t 5610 sli_fc_rqe_fcfi(sli4_t *sli4, void *cqe) 5611 { 5612 uint8_t code = ((uint8_t*)cqe)[SLI4_CQE_CODE_OFFSET]; 5613 uint8_t fcfi = UINT8_MAX; 5614 5615 switch(code) { 5616 case SLI4_CQE_CODE_RQ_ASYNC: { 5617 sli4_fc_async_rcqe_t *rcqe = cqe; 5618 fcfi = rcqe->fcfi; 5619 break; 5620 } 5621 case SLI4_CQE_CODE_RQ_ASYNC_V1: { 5622 sli4_fc_async_rcqe_v1_t *rcqev1 = cqe; 5623 fcfi = rcqev1->fcfi; 5624 break; 5625 } 5626 case SLI4_CQE_CODE_OPTIMIZED_WRITE_CMD: { 5627 sli4_fc_optimized_write_cmd_cqe_t *opt_wr = cqe; 5628 fcfi = opt_wr->fcfi; 5629 break; 5630 } 5631 } 5632 5633 return fcfi; 5634 } 5635 5636 extern const char *sli_fc_get_status_string(uint32_t status); 5637 5638 #endif /* !_SLI4_H */ 5639